Level conversion circuit, data voltage generation circuit, driving method of data voltage generation circuit and display module

Abstract

The invention discloses a level conversion circuit, a data voltage generation circuit, a driving method thereof and a display module. The level conversion circuit is electrically connected with a first reference potential end and a second reference potential end; the first reference potential end is configured to output a first reference potential; the second reference potential end is configured to output a second reference potential; the level conversion circuit comprises a first part, a second part and a third part, the first part is electrically connected with the second part, the second part is electrically connected with the third part, and the third part is configured to receive a first level and provide a logic control signal for the second part when the first level is normal; the first part is configured to be switched off when the first level is normal and switched on when the first level is abnormal; the second part is configured to be switched to output a first reference potential and a second reference potential under the control of the logic control signal when the first part is closed; and when the first part is opened, the first reference potential and the second reference potential are switched to be output under the cooperative control of the first part.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a level conversion circuit, a data voltage generation circuit and a driving method thereof, and a display module. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays have attracted widespread attention due to their advantages such as self-luminescence, low power consumption, lightness, flexibility, brilliant colors, high contrast, and fast response rate. Summary of the Invention

[0003] Embodiments of the present disclosure provide a level conversion circuit, a data voltage generation circuit, a driving method thereof, and a display module.

[0004] In a first aspect, an embodiment of the present disclosure provides a level conversion circuit, wherein a first reference potential terminal and a second reference potential terminal are electrically connected;

[0005] The first reference potential terminal is configured to output a first reference potential; the second reference potential terminal is configured to output a second reference potential;

[0006] The level conversion circuit includes a first part, a second part and a third part, the first part is electrically connected to the second part, and the second part is electrically connected to the third part.

[0007] The third part is configured to receive the first level and provide a logic control signal to the second part when the first level is normal;

[0008] The first part is configured to be closed when the first level is normal, and to be opened when the first level is abnormal;

[0009] The second part is configured to switch to output the first reference potential and the second reference potential under the control of the logic control signal when the first part is closed; and to switch to output the first reference potential and the second reference potential under the coordinated control of the first part when the first part is opened.

[0010] In some embodiments, a control subcircuit is further included, which is electrically connected to the first part and configured to receive the first level and control the first part to be closed when the first level is normal; and control the first part to be opened when the first level is abnormal.

[0011] In some embodiments, the first portion includes a first transistor and a second transistor;

[0012] The second part includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first inverter;

[0013] The control electrode of the first transistor is electrically connected to the first output terminal of the control sub - circuit; the first electrode of the first transistor is electrically connected to the first electrode of the third transistor, the first electrode of the fourth transistor, the first electrode of the ninth transistor, and the second reference potential terminal; the second electrode of the first transistor is electrically connected to the second electrode of the fourth transistor, the control electrode and the first electrode of the sixth transistor, the control electrode of the seventh transistor, and the control electrode of the ninth transistor;

[0014] The control electrode of the second transistor is electrically connected to the second output terminal of the control sub - circuit; the first electrode of the second transistor is electrically connected to the second electrode of the third transistor, the control electrode and the first electrode of the fifth transistor, and the control electrode of the eighth transistor; the second electrode of the second transistor is electrically connected to the second electrode of the seventh transistor, the second electrode of the eighth transistor, the second electrode of the tenth transistor, and the first reference potential terminal;

[0015] The control electrode of the third transistor is electrically connected to the first output terminal of the third part;

[0016] The control electrode of the fourth transistor is electrically connected to the second output terminal of the third part;

[0017] A second inverter is electrically connected between the first output terminal of the third part and the second output terminal of the third part;

[0018] The second electrode of the fifth transistor is electrically connected to the first electrode of the seventh transistor;

[0019] The second electrode of the sixth transistor is electrically connected to the first electrode of the eighth transistor and the control electrode of the tenth transistor;

[0020] The second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor and the input terminal of the first inverter;

[0021] The first inverter is electrically connected to the first reference potential terminal and the second reference potential terminal;

[0022] The input terminal of the first inverter is the first output terminal of the level conversion circuit, and the output terminal of the first inverter is the second output terminal of the level conversion circuit.

[0023] In some embodiments, the control sub - circuit includes an eleventh transistor, three third inverters, and a resistor;

[0024] The control electrode of the eleventh transistor is electrically connected to the output terminal of the first level; the first pole of the eleventh transistor is electrically connected to the second reference potential terminal; the second pole of the eleventh transistor is electrically connected to one end of the resistor and the input terminal of the first third inverter; the other end of the resistor is electrically connected to the first reference potential terminal;

[0025] The first third inverter, the second third inverter, and the third third inverter are connected in series in sequence; and the first third inverter, the second third inverter, and the third third inverter are respectively electrically connected to the first reference potential terminal and the second reference potential terminal;

[0026] The first output terminal of the control sub - circuit is the connection position of the output terminal of the second third inverter and the input terminal of the third third inverter;

[0027] The second output terminal of the control sub - circuit is the output terminal of the third third inverter.

[0028] In some embodiments, the first transistor includes an N - type transistor, and the second transistor includes a P - type transistor;

[0029] Alternatively, the first transistor includes a P - type transistor, and the second transistor includes an N - type transistor.

[0030] In some embodiments, the third transistor, the fourth transistor, the ninth transistor, and the eleventh transistor include N - type transistors;

[0031] The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P - type transistors.

[0032] In a second aspect, an embodiment of the present disclosure further provides a data voltage generation circuit, which includes an initial level generation sub - circuit configured to generate a first level;

[0033] Two of the above - mentioned level conversion circuits are respectively electrically connected to the initial level generation sub - circuit;

[0034] A data driving sub - circuit is respectively electrically connected to the two level conversion circuits and is configured to prevent a short - circuit under the control of the first reference potential and the second reference potential output by the level conversion circuits.

[0035] In some embodiments, the first output terminal of one level conversion circuit is electrically connected to the data driving sub - circuit, and the second output terminal of the other level conversion circuit is electrically connected to the data driving sub - circuit.

[0036] In some embodiments, the data driving sub - circuit includes a grayscale signal generating part, a voltage conversion part, and an output control part; the grayscale signal generating part, the voltage conversion part, and the output control part are connected in series in sequence;

[0037] The output control part includes an amplifier, a switching element, a twelfth transistor, and a thirteenth transistor;

[0038] The input end of the amplifier is electrically connected to the output end of the voltage conversion part; the output end of the amplifier is electrically connected to one end of the switching element; the amplifier is also electrically connected to the first reference potential terminal and the second reference potential terminal;

[0039] The other end of the switching element is electrically connected to the second pole of the twelfth transistor and the first pole of the thirteenth transistor;

[0040] The control pole of the twelfth transistor is electrically connected to the first output end of one of the level conversion circuits; the first pole of the twelfth transistor is electrically connected to the first reference potential terminal;

[0041] The control pole of the thirteenth transistor is electrically connected to the second output end of the other level conversion circuit; the second pole of the thirteenth transistor is electrically connected to the second reference potential terminal;

[0042] The connection position of the second pole of the twelfth transistor and the first pole of the thirteenth transistor is the output end of the data driving sub - circuit.

[0043] In some embodiments, the twelfth transistor includes a P - type transistor, and the thirteenth transistor includes an N - type transistor.

[0044] In a third aspect, an embodiment of the present disclosure further provides a display module, which includes the above - mentioned data voltage generation circuit.

[0045] In a fourth aspect, an embodiment of the present disclosure further provides a driving method for a data voltage generation circuit, where the data voltage generation circuit includes an initial level generation sub - circuit;

[0046] Two level conversion circuits, which are respectively electrically connected to a first reference potential terminal and a second reference potential terminal, and are respectively electrically connected to the initial level generation sub - circuit;

[0047] The level conversion circuit includes a first part, a second part, and a third part, the first part and the second part are electrically connected, and the second part and the third part are electrically connected;

[0048] A data driving sub - circuit, which is respectively electrically connected to the two level conversion circuits;

[0049] The driving method includes:

[0050] The initial level generating sub - circuit generates a first level;

[0051] The first reference potential terminal outputs a first reference potential; the second reference potential terminal outputs a second reference potential;

[0052] The third part receives the first level and provides a logic control signal to the second part when the first level is normal; the logic control signal includes a first control signal and a second control signal;

[0053] The first part is turned off when the first level is normal and is turned on when the first level is abnormal;

[0054] When the first part is turned off, the second part switches to output the first reference potential and the second reference potential under the control of the logic control signal; when the first part is turned on, the second part switches to output the first reference potential and the second reference potential under the cooperative control of the first part;

[0055] The data driving sub - circuit will not be short - circuited under the control of the first reference potential and the second reference potential.

[0056] In some embodiments, the level conversion circuit further includes a control sub - circuit, electrically connected to the initial level generating sub - circuit and the first part;

[0057] The driving method further includes:

[0058] The control sub - circuit receives the first level and controls the first part to be turned off when the first level is normal; controls the first part to be turned on when the first level is abnormal.

[0059] In some embodiments, the first transistor includes an N - type transistor, and the second transistor includes a P - type transistor;

[0060] The third transistor, the fourth transistor, and the ninth transistor include N - type transistors;

[0061] The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P - type transistors;

[0062] The first output terminal of the third part outputs the first control signal, and the second output terminal of the third part outputs the second control signal;

[0063] The driving method includes:

[0064] When the first level is normal, the first transistor and the second transistor are turned off under the control of the control sub - circuit;

[0065] The operation processes of the two level conversion circuits are as follows:

[0066] When the first control signal is at the second level and the second control signal is at the third level; the first control signal controls the third transistor to turn off, and at the same time the second control signal controls the fourth transistor to turn on;

[0067] The second reference potential controls the sixth transistor, the seventh transistor and the tenth transistor to turn on, and at the same time controls the ninth transistor to turn off;

[0068] A first output terminal of one of the level conversion circuits outputs the first reference potential, and the first reference potential controls the twelfth transistor in the data driving sub - circuit to turn off; a second output terminal of the other level conversion circuit outputs the second reference potential, and the second reference potential controls the thirteenth transistor in the data driving sub - circuit to turn off;

[0069] At this time, if the switching element in the data driving sub - circuit is closed, the output terminal of the data driving sub - circuit outputs a data signal; the data signal can light up the pixel.

[0070] In some embodiments, the first transistor includes an N - type transistor, and the second transistor includes a P - type transistor;

[0071] The third transistor, the fourth transistor and the ninth transistor include N - type transistors;

[0072] The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the tenth transistor include P - type transistors;

[0073] The first output terminal of the third part outputs the first control signal, and the second output terminal of the third part outputs the second control signal;

[0074] The driving method includes:

[0075] When the first level is normal, the first transistor and the second transistor are turned off under the control of the control sub - circuit;

[0076] The operation process of one of the level conversion circuits is as follows:

[0077] The first control signal is at the second level, and the second control signal is at the third level; the first control signal controls the third transistor to turn off, and at the same time the second control signal controls the fourth transistor to turn on;

[0078] The second reference potential turns on the sixth transistor, the seventh transistor, and the tenth transistor, and simultaneously turns off the ninth transistor;

[0079] A first output terminal of the level conversion circuit outputs the first reference potential, and the first reference potential turns off a twelfth transistor in the data driving sub - circuit;

[0080] The operation process of the other level conversion circuit is as follows:

[0081] The first control signal is at the third level, and the second control signal is at the second level; the first control signal turns on the third transistor, the second control signal turns off the fourth transistor, and simultaneously the ninth transistor is turned off;

[0082] The second reference potential turns on the fifth transistor and the eighth transistor, and simultaneously the first reference potential turns off the tenth transistor;

[0083] A second output terminal of the level conversion circuit outputs the first reference potential, and the first reference potential turns on a thirteenth transistor in the data driving sub - circuit;

[0084] At this time, the output terminal of the data driving sub - circuit outputs the second reference potential.

[0085] In some embodiments, the first transistor includes an N - type transistor, and the second transistor includes a P - type transistor;

[0086] The third transistor, the fourth transistor, and the ninth transistor include N - type transistors;

[0087] The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P - type transistors;

[0088] A first output terminal of the third part outputs the first control signal, and a second output terminal of the third part outputs the second control signal;

[0089] The driving method includes:

[0090] When the first level is normal, the first transistor and the second transistor are turned off under the control of the control sub - circuit;

[0091] The operation process of one of the level conversion circuits is as follows:

[0092] The first control signal is at a second level, and the second control signal is at a third level; the first control signal controls the third transistor to turn off, and at the same time, the second control signal controls the fourth transistor to turn on;

[0093] The second reference potential controls the sixth transistor, the seventh transistor, and the tenth transistor to turn on, and at the same time controls the ninth transistor to turn off;

[0094] The second output terminal of the level conversion circuit outputs the second reference potential, and the second reference potential controls the twelfth transistor in the data driving sub - circuit to turn on;

[0095] The operation process of the other level conversion circuit is as follows:

[0096] The first control signal is at the third level, and the second control signal is at the second level; the first control signal controls the third transistor to turn on, the second control signal controls the fourth transistor to turn off, and at the same time the ninth transistor turns off;

[0097] The second reference potential controls the fifth transistor and the eighth transistor to turn on, and at the same time the first reference potential controls the tenth transistor to turn off;

[0098] The first output terminal of the level conversion circuit outputs the second reference potential, and the second reference potential controls the thirteenth transistor in the data driving sub - circuit to turn off;

[0099] At this time, the output terminal of the data driving sub - circuit outputs the first reference potential.

[0100] In some embodiments, the first transistor includes an N - type transistor, and the second transistor includes a P - type transistor;

[0101] The third transistor, the fourth transistor, and the ninth transistor include N - type transistors;

[0102] The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P - type transistors;

[0103] The driving method includes:

[0104] When the first level is abnormal, the first transistor and the second transistor are turned on under the control of the control sub - circuit;

[0105] The operation processes of the two level conversion circuits are as follows:

[0106] The first output terminal of the third part does not output a signal, the switching state of the third transistor is unknown, and at the same time, the second output terminal of the third part does not output a signal, and the switching state of the fourth transistor is unknown;

[0107] The second reference potential controls the sixth transistor and the seventh transistor to turn on; the first reference potential controls the fifth transistor and the eighth transistor to turn off; at the same time, the second pole of the sixth transistor controls the tenth transistor to turn on, and the first pole of the sixth transistor controls the ninth transistor to turn off;

[0108] The first output terminal of one of the level conversion circuits outputs the first reference potential, and the first reference potential controls the twelfth transistor in the data driving sub - circuit to turn off; the second output terminal of the other level conversion circuit outputs the second reference potential, and the second reference potential controls the thirteenth transistor in the data driving sub - circuit to turn off;

[0109] At this time, the output terminal of the data driving sub - circuit does not output a signal.

[0110] In some embodiments, the eleventh transistor in the control sub - circuit includes an N - type transistor;

[0111] The driving method further includes:

[0112] When the first level is normal, the eleventh transistor turns on, the first of the three inverters in the control sub - circuit inputs the second reference potential, and the second reference potential is inverted through the first and the second of the three inverters, and the second reference potential is output at the first output terminal of the control sub - circuit; at the same time, the second reference potential is inverted through the first, the second, and the third of the three inverters, and the first reference potential is output at the second output terminal of the control sub - circuit;

[0113] When the first level is abnormal, the eleventh transistor turns off, the first of the three inverters in the control sub - circuit inputs the first reference potential, and the first reference potential is inverted through the first and the second of the three inverters, and the first reference potential is output at the first output terminal of the control sub - circuit; at the same time, the first reference potential is inverted through the first, the second, and the third of the three inverters, and the second reference potential is output at the second output terminal of the control sub - circuit.

[0114] In some embodiments, the first reference potential is higher than the first level;

[0115] The first level is higher than the second reference potential.

[0116] The level conversion circuit provided in this embodiment can be turned on when the first level is abnormal by setting a first part in the level conversion circuit, so as to cooperate with the second part to switch the level conversion circuit to output a first reference potential and a second reference potential, and further prevent the data voltage generation circuit in the display module from generating a short-circuit large current under the control of the first reference potential and the second reference potential, thereby avoiding damage to the display module caused by the large current.

[0117] The data voltage generation circuit provided in this embodiment can be turned on when the first level is abnormal by adopting the above-mentioned level conversion circuit, so as to cooperate with the second part of the level conversion circuit to switch the level conversion circuit to output a first reference potential and a second reference potential, and further prevent the data driving sub-circuit from generating a short-circuit large current under the control of the first reference potential and the second reference potential, thereby avoiding damage to the display module caused by the large current.

[0118] The display module provided in this embodiment can prevent the data driving sub-circuit in the display module from generating a short-circuit large current by adopting the above-mentioned data voltage generation circuit, thereby avoiding damage to the display module caused by the large current. Description of the Drawings

[0119] The drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. They are used together with the embodiments of the present disclosure to explain the present disclosure, and do not constitute a limitation to the present disclosure. By describing the detailed exemplary embodiments with reference to the drawings, the above and other features and advantages will become more obvious to those skilled in the art. In the drawings:

[0120] Figure 1 It is a circuit diagram of a data voltage generation circuit in the related art.

[0121] Figure 2a It is a circuit diagram of a level conversion circuit in an embodiment of the present disclosure.

[0122] Figure 2b It is a circuit diagram of another level conversion circuit in an embodiment of the present disclosure.

[0123] Figure 2c It is a circuit diagram of a control sub-circuit in an embodiment of the present disclosure.

[0124] Figure 3a It is a circuit diagram of a data voltage generation circuit in an embodiment of the present disclosure.

[0125] Figure 3b It is a circuit diagram of another data voltage generation circuit in an embodiment of the present disclosure. Detailed Embodiments

[0126] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a level conversion circuit, a data voltage generation circuit, its driving method, and a display module provided by the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0127] In the following, the embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. However, the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0128] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications to the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shape examples of the regions shown in the drawings illustrate the specific shapes of the regions, but are not intended to be restrictive.

[0129] In the related art, referring to [[ID=IO]] Figure 1 is a circuit diagram of a data voltage generation circuit in the related art; the data voltage generation circuit of the OLED display module includes an initial level generation sub-circuit 1, a level conversion circuit 2, and a data driving sub-circuit 3. The initial level generation sub-circuit 1 and the level conversion circuit 2 are electrically connected; the level conversion circuit 2 and the data driving sub-circuit 3 are electrically connected. The level conversion circuit 2 is a circuit formed by connecting a plurality of transistors to the first reference potential AVDD and the second reference potential GND, and capable of switching to output the first reference potential AVDD and the second reference potential GND. The output signal of the level conversion circuit 2 is used to control the on and off of the PMOS transistor M1 and the NMOS transistor M2 connected to the output terminal Sout of the data driving sub-circuit 3, so that the data driving sub-circuit 3 outputs a data voltage signal for display.

[0130] In the OLED display module, abnormal power-off of the VCI and DVDD voltage signals often occurs due to human or external environmental reasons. The most direct impact of the abnormal power-off of these two voltages is that the display module cannot be lit. However, in more cases, it directly causes a large current in the transistors connected to the output terminal of the data driving sub-circuit 3, resulting in damage to the display module, such as burning out the display panel, flexible circuit board, and main control chip in the display module. This causes a huge waste to the display module.

[0131] It should be noted that there may be a typo in "referring to and ", which is assumed to be a minor error in the original text. The translation is made based on the overall context.Analysis shows that the reason for the large current in the transistor connected to the output terminal of the data driving sub - circuit 3 in the display module is mainly caused by the internal short - circuit of the main control chip. The analysis of the internal short - circuit of the main control chip is mainly because the VCI or DVDD voltage signals inside the initial level generation sub - circuit 1 are unstable. When the VCI or DVDD voltage signals drop abnormally, the input voltage and bias current of the operational amplifier AMP in the initial level generation sub - circuit 1 are not generated. Therefore, the output voltage (VDD) of the initial level generation sub - circuit 1 is not correctly generated, which leads to abnormal digital logic power supply at the front - end input of the internal level conversion circuit 2 of the main control chip (i.e., the display driver IC), resulting in an uncertain state of the output of the level conversion circuit 2. The level conversion circuit 2 cannot work properly. At the same time, the PMOS transistor M1 and NMOS transistor M2 electrically connected to the output terminal Sout of the data driving sub - circuit 3 are turned on, resulting in a short - circuit large current I formed between the first reference potential AVDD and the second reference potential GND.

[0132] The current practice is that the fixture sets a current threshold. When the current exceeds a certain current threshold, the fixture will take power - off protection measures. However, this method is only effective in the short term, wasting a lot of time and being inefficient.

[0133] To solve the above problems in the related art, on the one hand, the embodiments of the present disclosure provide a level conversion circuit. Referring to Figure 2a , it is the circuit diagram of a level conversion circuit in the embodiments of the present disclosure; Figure 2b It is the circuit diagram of another level conversion circuit in the embodiments of the present disclosure; wherein, the level conversion circuit is electrically connected to the first reference potential terminal AVDD and the second reference potential terminal GND, and is configured to receive the first level VDD; the first reference potential terminal AVDD is configured to output the first reference potential; the second reference potential terminal GND is configured to output the second reference potential; the level conversion circuit includes a first part 21, a second part 22 and a third part 24. The first part 21 and the second part 22 are electrically connected, and the second part 22 and the third part 24 are electrically connected. The third part is configured to receive the first level VDD and provide a logic control signal to the second part 22 when the first level VDD is normal; the first part 21 is configured to be turned off when the first level VDD is normal and turned on when the first level VDD is abnormal; the second part 22 is configured to switch to output the first reference potential and the second reference potential under the control of the logic control signal when the first part 21 is turned off; when the first part 21 is turned on, it switches to output the first reference potential and the second reference potential under the cooperative control of the first part 21.

[0134] In this embodiment, by providing the first part 21 in the level conversion circuit, it can be turned on when the first level VDD has an abnormal power failure, so as to cooperate with the second part 22 to switch the level conversion circuit to output the first reference potential and the second reference potential, and further prevent the data voltage generation circuit in the display module from having a short-circuit large current under the control of the first reference potential and the second reference potential, thereby avoiding damage to the display module caused by the large current.

[0135] In some embodiments, referring to Figure 2b , the level conversion circuit further includes a control sub-circuit 23, electrically connected to the first part 21, configured to receive the first level VDD, and when the first level VDD is normal, control the first part 21 to turn off; when the first level VDD is abnormal, control the first part 21 to turn on. The control sub-circuit 23 is used to provide control signals for the turn-off and turn-on of the first part 21.

[0136] In some embodiments, referring to Figure 2a and Figure 2b , the first part 21 includes a first transistor T1 and a second transistor T2; the second part 22 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a first inverter F1.

[0137] The control electrode of the first transistor T1 is electrically connected to the first output terminal of the control sub-circuit 23; the first electrode of the first transistor T1 is electrically connected to the first electrode of the third transistor T3, the first electrode of the fourth transistor T4, the first electrode of the ninth transistor T9, and the second reference potential terminal GND; the second electrode of the first transistor T1 is electrically connected to the second electrode of the fourth transistor T4, the control electrode and the first electrode of the sixth transistor T6, the control electrode and the first electrode of the seventh transistor T7, and the control electrode of the ninth transistor T9.

[0138] The control electrode of the second transistor T2 is electrically connected to the second output terminal of the control sub-circuit 23; the first electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, the control electrode and the first electrode of the fifth transistor T5, and the control electrode of the eighth transistor T8; the second electrode of the second transistor T2 is electrically connected to the second electrode of the seventh transistor T7, the second electrode of the eighth transistor T8, the second electrode of the tenth transistor T10, and the first reference potential terminal AVDD.

[0139] The control electrode of the third transistor T3 is electrically connected to the first output terminal of the third part 24; the control electrode of the fourth transistor T4 is electrically connected to the second output terminal of the third part 24; a second inverter F2 is electrically connected between the first output terminal of the third part 24 and the second output terminal of the third part 24; the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the seventh transistor T7; the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the eighth transistor T8 and the control electrode of the tenth transistor T10; the second electrode of the ninth transistor T9 is electrically connected to the first electrode of the tenth transistor T10 and the input terminal of the first inverter F1; the first inverter F1 is electrically connected to the first reference potential terminal AVDD and the second reference potential terminal GND.

[0140] The input terminal of the first inverter F1 is the first output terminal OutB of the level conversion circuit, and the output terminal of the first inverter F1 is the second output terminal Out of the level conversion circuit.

[0141] In some embodiments, referring to Figure 2c , is the circuit diagram of the control sub-circuit in the embodiment of the present disclosure; the control sub-circuit 23 includes an eleventh transistor T11, three third inverters F3, and a resistor R.

[0142] The control electrode of the eleventh transistor T11 is electrically connected to the output terminal of the first level VDD; the first electrode of the eleventh transistor T11 is electrically connected to the second reference potential terminal GND; the second electrode of the eleventh transistor T11 is electrically connected to one end of the resistor R and the input terminal of the first third inverter F3; the other end of the resistor R is electrically connected to the first reference potential terminal AVDD.

[0143] The first third inverter F3, the second third inverter F3, and the third third inverter F3 are connected in series in sequence; and the first third inverter F3, the second third inverter F3, and the third third inverter F3 are respectively electrically connected to the first reference potential terminal AVDD and the second reference potential terminal GND; the first output terminal LS_ENB of the control sub-circuit 23 is the connection position between the output terminal of the second third inverter F3 and the input terminal of the third third inverter F3; the second output terminal LS_EN of the control sub-circuit 23 is the output terminal of the third third inverter F3.

[0144] In some embodiments, the first transistor T1 includes an N-type transistor, and the second transistor T2 includes a P-type transistor; alternatively, the first transistor T1 includes a P-type transistor, and the second transistor T2 includes an N-type transistor.

[0145] In some embodiments, the third transistor 3, the fourth transistor T4, the ninth transistor T9, and the eleventh transistor T11 include N-type transistors; the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 include P-type transistors.

[0146] In some embodiments, the first transistor T1, the second transistor T2, the third transistor 3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 may be MOS transistors (i.e., field effect transistors) or triodes.

[0147] In a second aspect, embodiments of the present disclosure further provide a data voltage generation circuit. Refer to Figure 3a a circuit diagram of a data voltage generation circuit in an embodiment of the present disclosure; Figure 3b a circuit diagram of another data voltage generation circuit in an embodiment of the present disclosure; wherein, it includes an initial level generation sub-circuit 1 configured to generate a first level VDD; two level conversion circuits 2 in the above two embodiments, electrically connected to the initial level generation sub-circuit 1 respectively; and a data driving sub-circuit 3, electrically connected to the two level conversion circuits 2 respectively, and configured to prevent a short circuit under the control of the first reference potential AVDD and the second reference potential GND output by the level conversion circuit 2.

[0148] Among them, the data driving sub-circuit 3 is used to generate and output a data signal, and the data signal can be provided to the data line in the display module to drive the pixels for display. The pixels in the display module may be OLED devices or liquid crystal pixels. The initial level generation sub-circuit 1 is used to receive the VCI voltage input and output the first level VDD. The initial level generation sub-circuit 1 includes a processing circuit 11, an operational amplifier 12, and two first resistors R1. The processing circuit 11 is electrically connected to the non-inverting input terminal of the operational amplifier 12. The inverting input terminal of the operational amplifier 12 is electrically connected to one first resistor R1 and grounded. The inverting input terminal of the operational amplifier 12 is also electrically connected to the other first resistor R1 and the output terminal; the DVDD voltage terminal provides power for the operational amplifier 12. The VCI voltage, the DVDD voltage, and the first level VDD are all DC voltages, and the DVDD voltage is higher than the first level VDD. The initial level generation sub-circuit 1 adopts a traditional circuit and will not be elaborated here.

[0149] In the data voltage generation circuit of this embodiment, by providing two level conversion circuits 2 in the above embodiment, one level conversion circuit 2 can independently provide the first reference potential AVDD or the second reference potential GND, and the other level conversion circuit 2 can independently provide the first reference potential AVDD or the second reference potential GND, so as to control two transistors (the twelfth transistor T12 and the thirteenth transistor T13) connected to the output end of the data driving sub-circuit 3 to achieve two switching states, that is, one switching state is that one transistor is turned on and the other transistor is turned off; the other switching state is that both transistors are turned off; furthermore, it is prevented that a short-circuit large current occurs when the first level VDD is abnormal in the data driving sub-circuit 3, and then the damage to the display module caused by the large current is avoided.

[0150] In some embodiments, the first output terminal OutB of one level conversion circuit 2 is electrically connected to the data driving sub-circuit 3, and the second output terminal Out of the other level conversion circuit 2 is electrically connected to the data driving sub-circuit 3.

[0151] In some embodiments, the data driving sub-circuit 3 includes a grayscale signal generating part 31, a voltage conversion part 32 and an output control part 33; the grayscale signal generating part 31, the voltage conversion part 32 and the output control part 33 are connected in series in sequence; the output control part 33 includes an amplifier Amp, a switching element OUT_EN, a twelfth transistor T12 and a thirteenth transistor T13; the input terminal of the amplifier Amp is electrically connected to the output terminal of the voltage conversion part 32; the output terminal of the amplifier Amp is electrically connected to one end of the switching element OUT_EN; the amplifier Amp is also electrically connected to the first reference potential terminal AVDD and the second reference potential terminal GND; the other end of the switching element OUT_EN is electrically connected to the second pole of the twelfth transistor T12 and the first pole of the thirteenth transistor T13; the control pole AVDD_OUT of the twelfth transistor T12 is electrically connected to the first output terminal OutB of one level conversion circuit 2; the first pole of the twelfth transistor T12 is electrically connected to the first reference potential terminal AVDD; the control pole AVSS_OUT of the thirteenth transistor T13 is electrically connected to the second output terminal Out of the other level conversion circuit 2; the second pole of the thirteenth transistor T13 is electrically connected to the second reference potential terminal GND; the connection position of the second pole of the twelfth transistor T12 and the first pole of the thirteenth transistor T13 is the output terminal Sout of the data driving sub-circuit 3.

[0152] In some embodiments, the grayscale signal generating part 31 adopts a traditional Gamma circuit, and the traditional Gamma circuit is a relatively mature circuit, which will not be elaborated here. The voltage conversion part 32 adopts a decoder, and the decoder circuit is a relatively mature circuit, which will not be elaborated here.

[0153] In some embodiments, the twelfth transistor T12 includes a P-type transistor, and the thirteenth transistor T13 includes an N-type transistor.

[0154] In some embodiments, the twelfth transistor T12 and the thirteenth transistor T13 may be MOS transistors (i.e., field effect transistors) or triodes.

[0155] In some embodiments, referring to Figure 3a and Figure 3b , the number of control sub-circuits 23 in the entire data voltage generation circuit may be one or two. If one control sub-circuit 23 is provided, the first output terminal LS_ENB and the second output terminal LS_EN of the control sub-circuit 23 simultaneously provide control signals for the two first parts 21. If two control sub-circuits 23 are provided, the first output terminal LS_ENB and the second output terminal LS_EN of one control sub-circuit 23 provide control signals for one first part 21; the first output terminal LS_ENB and the second output terminal LS_EN of the other control sub-circuit 23 provide control signals for the other first part 21.

[0156] In some embodiments, the first reference potential AVDD is higher than the first level VDD; the first level VDD is higher than the second reference potential GND.

[0157] Based on the above circuit of the data voltage generation circuit, in a third aspect, an embodiment of the present disclosure further provides a driving method for the data voltage generation circuit, where the data voltage generation circuit includes an initial level generation sub-circuit; two level conversion circuits, respectively electrically connected to the first reference potential terminal and the second reference potential terminal, and respectively electrically connected to the initial level generation sub-circuit; the level conversion circuit includes a first part, a second part, and a third part, the first part and the second part are electrically connected, and the second part and the third part are electrically connected; a data driving sub-circuit, respectively electrically connected to the two level conversion circuits.

[0158] The driving method includes: the initial level generation sub-circuit generates a first level; the first reference potential terminal outputs a first reference potential; the second reference potential terminal outputs a second reference potential; the third part receives the first level and provides a logic control signal to the second part when the first level is normal; the logic control signal includes a first control signal and a second control signal; the first part is turned off when the first level is normal and turned on when the first level is abnormal; the second part switches to output the first reference potential and the second reference potential under the control of the logic control signal when the first part is turned off; when the first part is turned on, it switches to output the first reference potential and the second reference potential under the cooperative control of the first part; the data driving sub-circuit does not short-circuit under the control of the first reference potential and the second reference potential.

[0159] In some embodiments, the level conversion circuit further includes a control sub-circuit, electrically connected to the initial level generation sub-circuit and the first part; the driving method further includes: the control sub-circuit receives a first level, and when the first level is normal, controls the first part to turn off; when the first level is abnormal, controls the first part to turn on.

[0160] In some embodiments, referring to Figure 3a and Figure 3b , the data voltage generation circuit is the data voltage generation circuit in the above embodiments; the first transistor T1 includes an N-type transistor, the second transistor T2 includes a P-type transistor; the third transistor T3, the fourth transistor T4, and the ninth transistor T9 include N-type transistors; the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 include P-type transistors; the first reference potential (AVDD) is higher than the second reference potential (GND); the third part 24 of the level conversion circuit 2 receives the first level VDD, its first output terminal outputs a first control signal In, and its second output terminal outputs a second control signal

[0161] The driving method includes: as shown in Table 1 below: when the first level VDD is normal, the first transistor T1 and the second transistor T2 are turned off (OFF) under the control of the control sub-circuit 23; the operation process of the two level conversion circuits 2 is: when the first control signal In is a second level, the second control signal is a third level, and the third level is higher than the second level; the second level is a low level, and the third level is a high level; the first control signal In controls the third transistor T3 to turn off, and at the same time the second control signal controls the fourth transistor T4 to turn on.

[0162] The second reference potential (GND) controls the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 to turn on, and at the same time controls the ninth transistor T9 to turn off.

[0163] As shown in Table 1': the first output terminal OutB of a level conversion circuit 2 outputs the first reference potential (AVDD), and the first reference potential (AVDD) controls the twelfth transistor T12 in the data driving sub-circuit 3 to turn off; the second output terminal Out of the other level conversion circuit 2 outputs the second reference potential (GND), and the second reference potential (GND) controls the thirteenth transistor T13 in the data driving sub-circuit 3 to turn off.

[0164] Among them, as shown in Table 1, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on, the third transistor T3 is turned off, the first pole of the sixth transistor T6 is at the second reference potential (GND), the ninth transistor T9 is turned off, the second pole of the sixth transistor T6 is at the second reference potential (GND), the tenth transistor T10 is turned on, the first output terminal OutB of each level conversion circuit 2 outputs the first reference potential (AVDD), and the second output terminal Out of each level conversion circuit 2 outputs the second reference potential (GND); the fifth transistor T5 is turned off, the control pole and the first pole of the fifth transistor T5 are connected together, the fifth transistor T5 is equivalent to a resistor, at this time the potential of the control pole of the fifth transistor T5 is pulled up by the potential of the first pole of the seventh transistor T7, and the control pole of the eighth transistor T8 is at a high potential, and the eighth transistor T8 is turned off.

[0165] At this time, as shown in Table 1', if the switching element OUT_EN in the data driving sub-circuit 3 is closed, the output terminal Sout of the data driving sub-circuit 3 outputs a data signal; the data signal can light up the pixel.

[0166] Table 1

[0167]

[0168] Table 1'

[0169] VDD Operating State Out OutB T12 T13 OUT_EN Sout Remarks VDD Normal Operation GND AVDD Off Off Closed Data Signal Data Signal Normal Operation State

[0170] In some embodiments, the driving method includes: when the first level VDD is normal, the first transistor T1 and the second transistor T2 are turned off under the control of the control sub-circuit 23; the operation process of one of the level conversion circuits 2 is: as shown in Table 2, the first control signal In is at the second level, the second control signal is at the third level, and the third level is higher than the second level; the second level is a low level, and the third level is a high level; the first control signal In controls the third transistor T3 to be turned off, and at the same time the second control signal controls the fourth transistor T4 to be turned on.

[0171] The second reference potential (GND) controls the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 to be turned on, and at the same time controls the ninth transistor T9 to be turned off.

[0172] As shown in Table 2', the first output terminal OutB of the level conversion circuit 2 outputs the first reference potential (AVDD), and the first reference potential (AVDD) controls the twelfth transistor T12 in the data driving sub-circuit 3 to be turned off.

[0173] Among them, as shown in Table 2, the fifth transistor T5 is turned off, the control electrode and the first electrode of the fifth transistor T5 are connected together, and the fifth transistor T5 is equivalent to a resistor. At this time, the potential of the control electrode of the fifth transistor T5 is pulled up by the potential of the first electrode of the seventh transistor T7, the control electrode of the eighth transistor T8 is at a high potential, and the eighth transistor T8 is turned off.

[0174] Table 2

[0175]

[0176] The operation process of another level conversion circuit 2 is as follows: as shown in Table 3, the first control signal In is at the third level, the second control signal is at the second level, and the third level is higher than the second level; the second level is at a low level, and the third level is at a high level; the first control signal In controls the third transistor T3 to turn on, and the second control signal controls the fourth transistor T4 to turn off, and at the same time the ninth transistor T9 turns off.

[0177] The second reference potential (GND) controls the fifth transistor T5 and the eighth transistor T8 to turn on, and at the same time the first reference potential (AVDD) controls the tenth transistor T10 to turn off.

[0178] As shown in Table 2', the second output terminal Out of the level conversion circuit 2 outputs the first reference potential (AVDD), and the first reference potential (AVDD) controls the thirteenth transistor T13 in the data driving sub-circuit 3 to turn on.

[0179] Among them, as shown in Table 3, the third transistor T3, the fifth transistor T5 and the eighth transistor T8 are turned on, the fourth transistor T4 is turned off, the first electrode of the sixth transistor T6 is at the first reference potential (AVDD), and the tenth transistor T10 is turned off; the sixth transistor T6 is turned off, the control electrode of the sixth transistor T6 is connected to the second electrode, and the sixth transistor T6 is equivalent to a resistor. At this time, the potential of the second electrode of the sixth transistor T6 will be pulled up by the potential of the first electrode of the sixth transistor T6, then the ninth transistor T9 is turned on, the first output terminal OutB of the level conversion circuit 2 outputs the second reference potential (GND), and the second output terminal Out of the level conversion circuit 2 outputs the first reference potential (AVDD); synchronously, because the seventh transistor T7 is a PMOS type, the control electrode of the seventh transistor T7 is at a high potential, and the seventh transistor T7 is turned off.

[0180] At this time, as shown in Table 2', if the switching element OUT_EN in the data driving sub-circuit 3 is turned on, the output terminal Sout of the data driving sub-circuit 3 outputs the second reference potential (GND). The output terminal Sout of the data driving sub-circuit 3 outputs the second reference potential (GND), which can achieve power consumption saving and prevent the output terminal Sout of the data driving sub-circuit 3 from outputting an unknown signal.

[0181] Table 3

[0182]

[0183] Table 2'

[0184] VDD Operating State Out OutB T12 T13 OUT_EN Sout Remarks VDD Normal Operation AVDD AVDD Off On Turned On GND Power consumption is saved and unknown output signals are prevented

[0185] In some embodiments, the driving method includes: when the first level VDD is normal, the first transistor T1 and the second transistor T2 are turned off under the control of the control sub-circuit 23; the operation process of one of the level conversion circuits 2 is as follows: as shown in Table 4, the first control signal In is at the second level, the second control signal is at the third level, and the third level is higher than the second level; the second level is a low level, and the third level is a high level; the first control signal In controls the third transistor T3 to turn off, and at the same time the second control signal controls the fourth transistor T4 to turn on.

[0186] The second reference potential (GND) controls the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 to turn on, and at the same time controls the ninth transistor T9 to turn off.

[0187] As shown in Table 3', the second output terminal Out of the level conversion circuit 2 outputs the second reference potential (GND), and the second reference potential (GND) controls the twelfth transistor T12 in the data driving sub-circuit 3 to turn on.

[0188] Among them, as shown in Table 4, the fifth transistor T5 is turned off, the control electrode and the first electrode of the fifth transistor T5 are connected together, the fifth transistor T5 is equivalent to a resistor, and at this time the potential of the control electrode of the fifth transistor T5 is pulled up by the potential of the first electrode of the seventh transistor T7, the control electrode of the eighth transistor T8 is at a high level, and the eighth transistor T8 is turned off.

[0189] Table 4

[0190]

[0191] The operation process of another level conversion circuit 2 is as follows: as shown in Table 5, the first control signal In is at the third level, the second control signal is at the second level, and the third level is higher than the second level; the second level is a low level, and the third level is a high level; the first control signal In controls the third transistor T3 to turn on, the second control signal controls the fourth transistor T4 to turn off, and at the same time the ninth transistor T9 is turned off.

[0192] The second reference potential (GND) controls the fifth transistor T5 and the eighth transistor T8 to turn on, while the first reference potential (AVDD) controls the tenth transistor T10 to turn off.

[0193] As shown in Table 3', the first output terminal OutB of the level conversion circuit 2 outputs the second reference potential (GND), and the second reference potential (GND) controls the thirteenth transistor T13 in the data driving sub-circuit 3 to turn off.

[0194] Among them, as shown in Table 5, the sixth transistor T6 is turned off. The control electrode and the second electrode of the sixth transistor T6 are connected together. The sixth transistor T6 is equivalent to a resistor. At this time, the potential of the second electrode of the sixth transistor T6 will be pulled up by the potential of the first electrode of the sixth transistor T6, so the ninth transistor T9 is turned on. The first output terminal OutB of the level conversion circuit 2 outputs the second reference potential (GND), and the second output terminal Out of the level conversion circuit 2 outputs the first reference potential (AVDD); synchronously, since the seventh transistor T7 is a PMOS type and the control electrode of the seventh transistor T7 is at a high potential, the seventh transistor T7 is turned off.

[0195] At this time, as shown in Table 3', if the switching element OUT_EN in the data driving sub-circuit 3 is turned on, the output terminal Sout of the data driving sub-circuit 3 outputs the first reference potential (AVDD). In this way, when the display module needs to display a black state, the output terminal Sout of the data driving sub-circuit 3 directly outputs the first reference potential (AVDD) to ensure full black display.

[0196] Table 5

[0197]

[0198] Table 3'

[0199] VDD Operating State Out OutB T12 T13 OUT_EN Sout Remarks VDD Normal Operation GND GND On Off Turned On AVDD When black state display is required, directly output AVDD to ensure full black

[0200] In some embodiments, the driving method includes: when the first level VDD is abnormal, the first transistor T1 and the second transistor T2 are turned on under the control of the control sub-circuit 23; the operation processes of the two level conversion circuits 2 are as follows: as shown in Table 6, the first output terminal of the third part 24 of the level conversion circuit 2 does not output a signal, and the switching state of the third transistor T3 is unknown. At the same time, the second output terminal of the third part 24 of the level conversion circuit 2 does not output a signal, and the switching state of the fourth transistor T4 is unknown.

[0201] The first transistor T1 is turned on, and the second reference potential (GND) controls the sixth transistor T6 and the seventh transistor T7 to be turned on; the second transistor T2 is turned on, and the first reference potential (AVDD) controls the fifth transistor T5 and the eighth transistor T8 to be turned off; at the same time, the second pole of the sixth transistor T6 controls the tenth transistor T10 to be turned on, and the first pole of the sixth transistor T6 controls the ninth transistor T9 to be turned off.

[0202] As shown in Table 4', a first output terminal OutB of a level conversion circuit 2 outputs a first reference potential (AVDD), and the first reference potential (AVDD) controls the twelfth transistor T12 in the data driving sub-circuit 3 to be turned off; another second output terminal Out of the level conversion circuit 2 outputs a second reference potential (GND), and the second reference potential (GND) controls the thirteenth transistor T13 in the data driving sub-circuit 3 to be turned off.

[0203] Among them, by providing the first transistor T1 and the second transistor T2 in the level conversion circuit 2, it can be turned on when the first level VDD has an abnormal power failure, so as to cooperate with the second part 22 in the level conversion circuit 2 to switch the level conversion circuit 2 to output the first reference potential (AVDD) and the second reference potential (GND), and further enable the data voltage generation circuit to prevent a short-circuit large current under the control of the first reference potential (AVDD) and the second reference potential (GND), thereby avoiding damage to the display module caused by the large current.

[0204] At this time, as shown in Table 4' below, the state of the switching element OUT_EN in the data driving sub-circuit 3 is unknown, that is, the switching element OUT_EN can be closed or opened, and the output terminal Sout of the data driving sub-circuit 3 does not output a signal. The twelfth transistor T12 and the thirteenth transistor T13 are both turned off, and there is no risk of large current, thereby avoiding a short-circuit large current in the data driving sub-circuit 3.

[0205] Table 6

[0206]

[0207] Table 4'

[0208] VDD Operating State Out OutB T12 T13 OUT_EN Sout Remarks VDD Abnormal GND AVDD Off Off Unknown State No Signal Output Both T12 and T13 are off, no risk of large current

[0209] In some embodiments, refer to Figure 2c, the eleventh transistor T11 in the control sub - circuit 23 is an N - type transistor; the driving method further includes: when the first level VDD is normal, the eleventh transistor T11 is turned on, the first third inverter F3 in the control sub - circuit 23 inputs the second reference potential (GND), and after the second reference potential (GND) is inverted by the first third inverter F3 and the second third inverter F3, the second reference potential (GND) is output at the first output terminal LS_ENB of the control sub - circuit 23; at the same time, after the second reference potential (GND) is inverted by the first third inverter F3, the second third inverter F3 and the third third inverter F3, the first reference potential (AVDD) is output at the second output terminal LS_EN of the control sub - circuit 23.

[0210] When the first level VDD is abnormal, the eleventh transistor T11 is turned off, the first third inverter F3 in the control sub - circuit 23 inputs the first reference potential (AVDD), and after the first reference potential (AVDD) is inverted by the first third inverter F3 and the second third inverter F3, the first reference potential (AVDD) is output at the first output terminal LS_ENB of the control sub - circuit 23; at the same time, after the first reference potential (AVDD) is inverted by the first third inverter F3, the second third inverter F3 and the third third inverter F3, the second reference potential (GND) is output at the second output terminal LS_EN of the control sub - circuit 23.

[0211] In some embodiments, the first reference potential (AVDD) is higher than the first level VDD; the first level VDD is higher than the second reference potential (GND).

[0212] In the data voltage generation circuit of this embodiment, by adopting the level conversion circuit in the above - mentioned embodiment, it can be turned on when the first level is abnormal, so as to cooperate with the second part of the level conversion circuit to switch the level conversion circuit to output the first reference potential and the second reference potential, and further prevent the data driving sub - circuit from generating short - circuit large current under the control of the first reference potential and the second reference potential, thereby avoiding damage to the display module caused by the large current.

[0213] In a fourth aspect, an embodiment of the present disclosure further provides a display module, including the data voltage generation circuit in the above - mentioned embodiment.

[0214] By adopting the data voltage generation circuit in the above - mentioned embodiment, it can prevent the data driving sub - circuit in the display module from generating short - circuit large current, thereby avoiding damage to the display module caused by the large current.

[0215] The display module provided by the embodiment of the present disclosure can be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, a navigator, etc.

[0216] It is understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A level conversion circuit, characterized in that, Electrically connect the first reference potential terminal and the second reference potential terminal; The first reference potential terminal is configured to output a first reference potential; The second reference potential terminal is configured to output a second reference potential; The level conversion circuit includes a first part, a second part, and a third part. The first part and the second part are electrically connected, and the second part and the third part are electrically connected. The third part is configured to receive a first level and provide a logic control signal to the second part when the first level is normal; The first part is configured to turn off when the first level is normal and turn on when the first level is abnormal; The second part is configured to switch to output the first reference potential and the second reference potential under the control of the logic control signal when the first part is turned off; When the first part is turned on, it switches to output the first reference potential and the second reference potential under the cooperative control of the first part.

2. The level conversion circuit according to claim 1, wherein It further includes a control sub-circuit, electrically connected to the first part, configured to receive the first level, and control the first part to turn off when the first level is normal; control the first part to turn on when the first level is abnormal.

3. The level conversion circuit according to claim 2, wherein The first part includes a first transistor and a second transistor; The second part includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first inverter; The control electrode of the first transistor is electrically connected to the first output terminal of the control sub-circuit; the first electrode of the first transistor is electrically connected to the first electrode of the third transistor, the first electrode of the fourth transistor, the first electrode of the ninth transistor, and the second reference potential terminal; The second electrode of the first transistor is electrically connected to the second electrode of the fourth transistor, the control electrode and the first electrode of the sixth transistor, the control electrode of the seventh transistor, and the control electrode of the ninth transistor; The control electrode of the second transistor is electrically connected to the second output terminal of the control sub-circuit; the first electrode of the second transistor is electrically connected to the second electrode of the third transistor, the control electrode and the first electrode of the fifth transistor, and the control electrode of the eighth transistor; the second electrode of the second transistor is electrically connected to the second electrode of the seventh transistor, the second electrode of the eighth transistor, the second electrode of the tenth transistor, and the first reference potential terminal; The control electrode of the third transistor is electrically connected to the first output terminal of the third part; The control electrode of the fourth transistor is electrically connected to the second output terminal of the third part; A second inverter is electrically connected between the first output terminal of the third part and the second output terminal of the third part; The second electrode of the fifth transistor is electrically connected to the first electrode of the seventh transistor; The second electrode of the sixth transistor is electrically connected to the first electrode of the eighth transistor and the control electrode of the tenth transistor; The second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor and the input terminal of the first inverter; The first inverter is electrically connected to the first reference potential terminal and the second reference potential terminal; The input terminal of the first inverter is the first output terminal of the level conversion circuit, and the output terminal of the first inverter is the second output terminal of the level conversion circuit.

4. The level conversion circuit according to claim 3, wherein The control sub-circuit includes an eleventh transistor, three third inverters, and a resistor; The control electrode of the eleventh transistor is electrically connected to the output terminal of the first level; the first electrode of the eleventh transistor is electrically connected to the second reference potential terminal; the second electrode of the eleventh transistor is electrically connected to one end of the resistor and the input terminal of the first of the third inverters; the other end of the resistor is electrically connected to the first reference potential terminal; The first of the third inverters, the second of the third inverters, and the third of the third inverters are connected in series in sequence; and the first of the third inverters, the second of the third inverters, and the third of the third inverters are respectively electrically connected to the first reference potential terminal and the second reference potential terminal; The first output terminal of the control sub-circuit is the connection position of the output terminal of the second of the third inverters and the input terminal of the third of the third inverters; The second output terminal of the control sub-circuit is the output terminal of the third of the third inverters.

5. The level conversion circuit according to claim 3, wherein The first transistor includes an N-type transistor, and the second transistor includes a P-type transistor; Alternatively, the first transistor includes a P-type transistor, and the second transistor includes an N-type transistor.

6. The level conversion circuit according to claim 4, wherein The third transistor, the fourth transistor, the ninth transistor, and the eleventh transistor include N-type transistors; The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P-type transistors.

7. A data voltage generating circuit, characterized in that, An initial level generation sub-circuit is included, configured to generate a first level; Two level conversion circuits according to any one of claims 1-6 are respectively electrically connected to the initial level generation sub-circuit; A data driving sub-circuit is electrically connected to the two level conversion circuits respectively, and is configured to prevent short circuit under the control of the first reference potential and the second reference potential output by the level conversion circuit.

8. The data voltage generation circuit according to claim 7, wherein The first output terminal of one of the level conversion circuits is electrically connected to the data driving sub-circuit, and the second output terminal of the other level conversion circuit is electrically connected to the data driving sub-circuit.

9. The data voltage generation circuit according to claim 8, wherein The data driving sub-circuit includes a grayscale signal generation part, a voltage conversion part, and an output control part; the grayscale signal generation part, the voltage conversion part, and the output control part are connected in series in sequence; The output control part includes an amplifier, a switching element, a twelfth transistor, and a thirteenth transistor; The input terminal of the amplifier is electrically connected to the output terminal of the voltage conversion part; the output terminal of the amplifier is electrically connected to one end of the switching element; the amplifier is also electrically connected to the first reference potential terminal and the second reference potential terminal; The other end of the switching element is electrically connected to the second electrode of the twelfth transistor and the first electrode of the thirteenth transistor; The control electrode of the twelfth transistor is electrically connected to the first output terminal of one of the level conversion circuits; the first electrode of the twelfth transistor is electrically connected to the first reference potential terminal; The control electrode of the thirteenth transistor is electrically connected to the second output terminal of the other level conversion circuit; the second electrode of the thirteenth transistor is electrically connected to the second reference potential terminal; The connection position of the second electrode of the twelfth transistor and the first electrode of the thirteenth transistor is the output terminal of the data driving sub-circuit.

10. The data voltage generation circuit according to claim 9, wherein The twelfth transistor includes a P-type transistor, and the thirteenth transistor includes an N-type transistor.

11. A display module, characterized in that, It includes the data voltage generation circuit according to any one of claims 7-10.

12. A driving method for a data voltage generation circuit, characterized in that, The data voltage generation circuit includes an initial level generation sub-circuit; Two level conversion circuits, which are respectively electrically connected to the first reference potential terminal and the second reference potential terminal, and are respectively electrically connected to the initial level generation sub-circuit; The level conversion circuit includes a first part, a second part, and a third part. The first part and the second part are electrically connected, and the second part and the third part are electrically connected; A data driving sub-circuit, which is respectively electrically connected to the two level conversion circuits; The driving method includes: The initial level generation sub-circuit generates a first level; The first reference potential terminal outputs a first reference potential; the second reference potential terminal outputs a second reference potential; The third part receives the first level and provides a logic control signal to the second part when the first level is normal; the logic control signal includes a first control signal and a second control signal; The first part is turned off when the first level is normal and is turned on when the first level is abnormal; When the first part is turned off, the second part switches to output the first reference potential and the second reference potential under the control of the logic control signal; when the first part is turned on, the second part switches to output the first reference potential and the second reference potential under the cooperative control of the first part; The data driving sub-circuit will not be short-circuited under the control of the first reference potential and the second reference potential.

13. The driving method according to claim 12, wherein The level conversion circuit further includes a control sub-circuit, which is electrically connected to the initial level generation sub-circuit and the first part; The driving method further includes: The control sub-circuit receives the first level and controls the first part to be turned off when the first level is normal; controls the first part to be turned on when the first level is abnormal.

14. The driving method according to claim 13, characterized in that, The data voltage generation circuit is the data voltage generation circuit in claim 10; The first transistor includes an N-type transistor, and the second transistor includes a P-type transistor; The third transistor, the fourth transistor, and the ninth transistor include N-type transistors; The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P-type transistors; The first output terminal of the third part outputs the first control signal, and the second output terminal of the third part outputs the second control signal; The driving method includes: When the first level is normal, the first transistor and the second transistor are turned off under the control of the control sub-circuit; The operation processes of the two level conversion circuits are: When the first control signal is at the second level and the second control signal is at the third level, the first control signal controls the third transistor to turn off, and at the same time, the second control signal controls the fourth transistor to turn on; The second reference potential controls the sixth transistor, the seventh transistor, and the tenth transistor to turn on, and at the same time controls the ninth transistor to turn off; A first output terminal of one of the level conversion circuits outputs the first reference potential, and the first reference potential controls the twelfth transistor in the data driving sub-circuit to turn off; a second output terminal of the other level conversion circuit outputs the second reference potential, and the second reference potential controls the thirteenth transistor in the data driving sub-circuit to turn off; At this time, if the switching element in the data driving sub-circuit is closed, the output terminal of the data driving sub-circuit outputs a data signal; the data signal can light up the pixel.

15. The driving method according to claim 13, characterized in that, The data voltage generating circuit is the data voltage generating circuit in claim 10; The first transistor includes an N-type transistor, and the second transistor includes a P-type transistor; The third transistor, the fourth transistor, and the ninth transistor include N-type transistors; The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P-type transistors; A first output terminal of the third part outputs the first control signal, and a second output terminal of the third part outputs the second control signal; The driving method includes: When the first level is normal, the first transistor and the second transistor are controlled by the control sub-circuit to turn off; The operation process of one of the level conversion circuits is as follows: The first control signal is at the second level, and the second control signal is at the third level; the first control signal controls the third transistor to turn off, and at the same time, the second control signal controls the fourth transistor to turn on; The second reference potential controls the sixth transistor, the seventh transistor, and the tenth transistor to turn on, and at the same time controls the ninth transistor to turn off; The first output terminal of the level conversion circuit outputs the first reference potential, and the first reference potential controls the twelfth transistor in the data driving sub-circuit to turn off; The operation process of the other level conversion circuit is as follows: The first control signal is at the third level, and the second control signal is at the second level; the first control signal controls the third transistor to turn on, the second control signal controls the fourth transistor to turn off, and at the same time the ninth transistor turns off; The second reference potential controls the fifth transistor and the eighth transistor to turn on, and at the same time the first reference potential controls the tenth transistor to turn off; The second output terminal of the level conversion circuit outputs the first reference potential, and the first reference potential controls the thirteenth transistor in the data driving sub-circuit to turn on; At this time, the output terminal of the data driving sub-circuit outputs the second reference potential.

16. The driving method according to claim 13, wherein The data voltage generating circuit is the data voltage generating circuit in claim 10; The first transistor includes an N-type transistor, and the second transistor includes a P-type transistor; The third transistor, the fourth transistor, and the ninth transistor include N-type transistors; The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P-type transistors; The first output terminal of the third part outputs the first control signal, and the second output terminal of the third part outputs the second control signal; The driving method includes: When the first level is normal, the first transistor and the second transistor are turned off under the control of the control sub-circuit; The operation process of one of the level conversion circuits is as follows: The first control signal is at a second level, and the second control signal is at a third level; the first control signal controls the third transistor to turn off, and at the same time the second control signal controls the fourth transistor to turn on; The second reference potential controls the sixth transistor, the seventh transistor, and the tenth transistor to turn on, and at the same time controls the ninth transistor to turn off; The second output terminal of the level conversion circuit outputs the second reference potential, and the second reference potential controls the twelfth transistor in the data driving sub-circuit to turn on; The operation process of the other level conversion circuit is as follows: The first control signal is at the third level, and the second control signal is at the second level; the first control signal controls the third transistor to turn on, the second control signal controls the fourth transistor to turn off, and at the same time the ninth transistor turns off; The second reference potential controls the fifth transistor and the eighth transistor to turn on, and at the same time the first reference potential controls the tenth transistor to turn off; The first output terminal of the level conversion circuit outputs the second reference potential, and the second reference potential controls the thirteenth transistor in the data driving sub-circuit to turn off; At this time, the output terminal of the data driving sub-circuit outputs the first reference potential.

17. The driving method according to claim 13, characterized in that, The data voltage generation circuit is the data voltage generation circuit in claim 10; The first transistor includes an N-type transistor, and the second transistor includes a P-type transistor; The third transistor, the fourth transistor, and the ninth transistor include N-type transistors; The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor include P-type transistors; The driving method includes: When the first level is abnormal, the first transistor and the second transistor are turned on under the control of the control sub-circuit; The operation processes of the two level conversion circuits are as follows: The first output terminal of the third part does not output a signal, the switching state of the third transistor is unknown, and at the same time the second output terminal of the third part does not output a signal, and the switching state of the fourth transistor is unknown; The second reference potential controls the sixth transistor and the seventh transistor to turn on; the first reference potential controls the fifth transistor and the eighth transistor to turn off; meanwhile, the second pole of the sixth transistor controls the tenth transistor to turn on, and the first pole of the sixth transistor controls the ninth transistor to turn off; A first output terminal of one of the level conversion circuits outputs the first reference potential, and the first reference potential controls the twelfth transistor in the data driving sub - circuit to turn off; a second output terminal of the other level conversion circuit outputs the second reference potential, and the second reference potential controls the thirteenth transistor in the data driving sub - circuit to turn off; At this time, no signal is output from the output terminal of the data driving sub - circuit.

18. The driving method according to any one of claims 14-17, characterized in that, The eleventh transistor in the control sub - circuit includes an N - type transistor; The driving method further includes: When the first level is normal, the eleventh transistor turns on, the first third inverter in the control sub - circuit inputs the second reference potential, and the second reference potential is inverted by the first third inverter and the second third inverter, and the second reference potential is output at the first output terminal of the control sub - circuit; meanwhile, the second reference potential is inverted by the first third inverter, the second third inverter and the third third inverter, and the first reference potential is output at the second output terminal of the control sub - circuit; When the first level is abnormal, the eleventh transistor turns off, the first third inverter in the control sub - circuit inputs the first reference potential, and the first reference potential is inverted by the first third inverter and the second third inverter, and the first reference potential is output at the first output terminal of the control sub - circuit; meanwhile, the first reference potential is inverted by the first third inverter, the second third inverter and the third third inverter, and the second reference potential is output at the second output terminal of the control sub - circuit.

19. The driving method according to any one of claims 14-17, characterized in that, The first reference potential is higher than the first level; The first level is higher than the second reference potential.

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