Offset calibration method and device

Abstract

The invention provides an offset calibration method and device, and the method comprises the steps: detecting at least one time period in which a DDR controller forbids to access SDRAM particles, and then carrying out the offset calibration operation on the data transmission delay on a whole data transmission link in the at least one time period, thereby not needing to independently occupy the bandwidth resources of a system, and improving the data transmission efficiency. The bandwidth utilization rate can be improved, and the stability of data transmission is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to an offset calibration method and device. Background Art

[0002] In complementary metal-oxide-semiconductor (CMOS) integrated circuits or granular circuits, due to design differences in data / clock paths, when Process / Voltage / Temperature (PVT) changes, data transmission delays on the data transmission path may change. And the data transmission delays on the data transmission path may cause offset problems, such as sampling point offset, etc., which may further lead to abnormal data transmission. Therefore, how to ensure the stability of data transmission is an urgent problem to be solved. Summary of the Invention

[0003] This application provides an offset calibration method and device for calibrating the data transmission delay on the data transmission path and improving the stability of data transmission.

[0004] In a first aspect, this application provides an offset calibration method, which includes: a Double Data Rate Physical Layer (DDRPHY) detects at least one time period during which a DDR controller prohibits access to a Synchronous Dynamic Random Access Memory (SDRAM) granular; the DDRPHY performs an offset calibration operation on the data transmission delay of the data transmission link during the at least one time period. Wherein, the data transmission link is the transmission link between the DDR controller and the SDRAM granular.

[0005] Through the above technical solution, the DDR PHY can use the time period when the DDR controller cannot access the SDRAM granular to perform the offset calibration operation, and the offset calibration can be achieved without occupying the system bandwidth, thereby improving the stability of data transmission.

[0006] In a possible implementation, the time period during which the DDR controller prohibits access to the Synchronous Dynamic Random Access Memory (SDRAM) granular includes the following time periods: the time period when the SDRAM granular performs a refresh operation or the time period that can identify that the DDR controller prohibits access to the SDRAM granular within at least one set time period.

[0007] Through the above technical solution, the DDR PHY can perform offset calibration during the time period when the granular performs a refresh operation or other time periods that can identify that the DDR controller prohibits access to the SDRAM granular.

[0008] In a possible implementation, the DDR PHY detects the time period during which the DDR controller is prohibited from accessing the SDRAM die, including:

[0009] Receiving an auto - refresh instruction sent by the DDR controller and sending the auto - refresh instruction to the SDRAM die, where the auto - refresh instruction is used to instruct the SDRAM die to perform a refresh operation. Among them, the time period during which the SDRAM die performs the refresh operation is the time period during which the DDR controller cannot access the SDRAM die.

[0010] In a possible implementation, the DDR PHY detects the time period during which the DDR controller is prohibited from accessing the SDRAM die, including:

[0011] Receiving an auto - refresh instruction sent by the DDR controller and sending the auto - refresh instruction to the SDRAM die, the auto - refresh instruction instructs the SDRAM die to perform a refresh operation within a time period; the time period indicated by the auto - refresh instruction is the time period during which the SDRAM die performs the refresh operation. Among them, M of the N consecutive time periods during which the SDRAM die performs the refresh operation are the time periods during which the DDR controller cannot access the SDRAM die, where both N and M are positive integers, and M is less than or equal to N.

[0012] Through the above technical solution, the DDR PHY can perform offset calibration operations during the die auto - refresh, so it does not need to occupy system bandwidth resources, can improve bandwidth utilization, and improve the stability of data transmission.

[0013] In a possible implementation, the DDR PHY detects the time period during which the DDR controller is prohibited from accessing the SDRAM die, including:

[0014] Receiving an instruction to enter self - refresh sent by the DDR controller and sending the instruction to enter self - refresh to the SDRAM die, the instruction to enter self - refresh is used to instruct the SDRAM die to start performing a refresh operation; receiving an instruction to exit self - refresh sent by the DDR controller and sending the instruction to exit self - refresh to the SDRAM die, the instruction to exit self - refresh is used to instruct the SDRAM die to exit the refresh operation. Among them, the time period during which the DDR controller is prohibited from accessing the SDRAM die is the time period between the first time point when the DDR controller receives the instruction to enter self - refresh and the second time point when it receives the instruction to exit self - refresh.

[0015] In a possible implementation, the DDR PHY detects the time period during which the DDR controller is prohibited from accessing the SDRAM die, including:

[0016] Receive the instruction to enter self - refresh sent by the DDR controller and send the instruction to enter self - refresh to the SDRAM die. The instruction to enter self - refresh is used to indicate that the SDRAM die starts to perform a refresh operation; receive the instruction to exit self - refresh sent by the DDR controller and send the instruction to exit self - refresh to the SDRAM die. The instruction to exit self - refresh is used to indicate that the SDRAM die exits the refresh operation. Among them, the time period during which the SDRAM die performs the refresh operation is the time period between the first time point when the DDR controller receives the instruction to enter self - refresh and the second time point when it receives the instruction to exit self - refresh; M of the N consecutive time periods during which the SDRAM die performs the refresh operation are time periods when the DDR controller cannot access the SDRAM die. Both N and M are positive integers, and M is less than or equal to N.

[0017] Through the above - mentioned technical solution, the DDR PHY can complete the offset calibration operation during the self - refresh time period of the die, without separately occupying the system bandwidth, which can improve the bandwidth utilization rate and at the same time improve the stability of data transmission.

[0018] In a possible implementation manner, the SDRAM die includes a memory array and a non - memory array, and at least one time period during which the DDR controller prohibits access to the SDRAM die is at least one time period during which the DDR controller prohibits access to the memory array of the SDRAM die.

[0019] In a possible implementation manner, the method further includes:

[0020] Receive the read operation instruction sent by the DDR controller when performing the offset calibration operation. The read operation instruction is used to indicate performing a read operation on the non - memory array of the SDRAM die.

[0021] In a possible implementation manner, the method further includes:

[0022] Receive the write operation instruction sent by the DDR controller when performing the offset calibration operation. The write operation instruction is used to indicate performing a write operation on the non - memory array of the SDRAM die.

[0023] Through the above - mentioned technical solution, during the process of performing the offset calibration operation, a read operation instruction and / or a write operation instruction can be simultaneously performed on the non - memory array of the SDRAM die.

[0024] In a possible implementation manner, the method further includes:

[0025] The DDR PHY performs background calibration operations during the at least one time period, and the background calibration operations at least include the following calibration operations: time-to-digital conversion (TDC) calibration, conversion relationship calibration of delay logic, pull-up impedance calibration of high-speed I / O, and pull-down impedance calibration of high-speed I / O.

[0026] Through the above technical solutions, calibration of multiple other parameters except for data transmission delay calibration can be achieved, and the calibration of these parameters can be completed through background calibration operations.

[0027] In a second aspect, the present application provides an offset calibration device, which includes a processor; a memory and one or more computer programs; wherein the one or more computer programs are stored in the one or more memories, and the one or more computer programs include instructions, when the instructions are called and executed by the one or more processors, the offset calibration device is caused to execute the method according to the first aspect and any possible design of the first aspect above.

[0028] In a third aspect, the present application further provides an offset calibration device, which includes modules / units that execute the method according to the first aspect or any possible design of the first aspect; these modules / units can be implemented by hardware or by hardware executing corresponding software.

[0029] In a fourth aspect, the present application further provides a computer-readable storage medium, in which instructions are stored, when the instructions run on an offset calibration device, the offset calibration device is caused to execute the method according to the first aspect and any possible design of the first aspect.

[0030] In a fifth aspect, the present application further provides a computer program product, when the computer program product runs on an offset calibration device, the offset calibration device is caused to execute the method according to the first aspect and any possible design of the first aspect of the embodiments of the present application.

[0031] For the various aspects in the second aspect to the fifth aspect above and the possible technical effects that each aspect may achieve, please refer to the description of the possible technical effects that can be achieved by the various possible solutions in the first aspect above, and details will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1A It is a schematic block diagram of a DDR system provided by an embodiment of the present application;

[0033] Figure 1B It is a schematic diagram of a system architecture provided by an embodiment of the present application;

[0034] Figure 2ASchematic diagram of a refresh cycle time tRFC provided by an embodiment of the present application;

[0035] Figure 2B Schematic diagram of a self - refresh time provided by an embodiment of the present application;

[0036] Figure 3 Flowchart of an offset calibration method provided by an embodiment of the present application;

[0037] Figure 4 Flowchart of an offset calibration method provided by an embodiment of the present application;

[0038] Figure 5 Another flowchart of an offset calibration method provided by an embodiment of the present application;

[0039] Figure 6 Schematic structural diagram of an offset calibration device provided by an embodiment of the present application;

[0040] Figure 7 Schematic structural diagram of an offset calibration device provided by an embodiment of the present application. Detailed implementation manners

[0041] In the description of the embodiments of the present application, the term "including" and its similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0042] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: including the case where A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one of the following" or its similar expressions refer to any combination of these items, including any combination of single item(s) or plural item(s). For example, at least one of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c can be single or multiple.

[0043] Hereinafter, first, some terms in the embodiments of the present application will be explained to facilitate the understanding of those skilled in the art.

[0044] 1. DDR

[0045] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), simply referred to as DDR.

[0046] First, the architecture of the DDR system will be introduced. Exemplarily, as Figure 1A shown, it is a schematic block diagram of a DDR system provided by an embodiment of this application. Referring to Figure 1A shown, it may include a DDR controller 10, a Double Data Rate Physical Layer (DDR PHY) 20, and SDRAM chips 30.

[0047] In some embodiments, the DDR controller 10 is used to send auto - refresh instructions, self - refresh instructions, and read / write operation instructions to the SDRAM chips 30. The DDR PHY 20 is a bridge connecting the SDRAM chips 30 and the DDR controller 10. It is responsible for converting the data sent by the DDR controller 10 into signals compliant with the DDR protocol and sending them to the SDRAM chips 30. Conversely, the DDR PHY 20 is also responsible for converting the data sent by the SDRAM chips 30 into signals compliant with the DDR Physical Layer Interface (DFI) protocol and sending them to the DDR controller 10. The SDRAM chips 30 are used to perform a refresh operation when receiving the auto - refresh instruction or self - refresh instruction sent by the DDR controller 10 to ensure the security of the internal data of the DDR.

[0048] The SDRAM chips 30 may include a memory array and a non - memory array. In the embodiments of this application, when the SDRAM chips 30 perform a refresh operation, the DDR controller 10 cannot access the memory array of the SDRAM chips 30, while the DDR controller 10 can send read operation instructions and / or write operation instructions to the non - memory array of the SDRAM chips 30.

[0049] As Figure 1B shown, it is a schematic diagram of a system architecture provided by an embodiment of this application. Referring to Figure 1B shown, in this system architecture, the DDR PHY 20 may include a parsing component (also referred to as: DDR controller command parsing component) 201, an active calibration state machine 202, an active calibration data processing component 203, a background calibration module group 204, a DFI interface 205, a PHY / IO configuration parameter register 206, and a PHY / IO high - speed component 207. In addition, this system architecture also includes a DDR controller 10, SDRAM chips 30, a package, and a single - board 40.

[0050] Among them, the parsing component 201 is used to detect whether the DDR controller has issued a command to refresh all memory bank groups (refresh all bank, REFab), a self-refresh (SR) command for the die, and to determine whether the DDR controller 10 is in a state of non-access to the die and whether this state will last for a certain period of time; the active calibration state machine 202 is used to start the active calibration operation, update the calibration result, perform DFI interface switching, adjust the PHY delay, analyze the comparison results of reading and writing the die, and perform calibration operations; the active calibration data processing component 203 is controlled by the active calibration state machine 202, and can generate DFI interface data and timing for reading and writing the die, and perform data comparison on the data of the write operation and the data of the read operation to generate a comparison result; the background calibration module group 204 is used to perform background calibration operations; the DFI interface 205 is an interface between the DDR controller 10 and the DDR PHY 20; the PHY / IO configuration parameter register 206 includes a parameter register for calibration operations, a configuration parameter register during normal operation, and a parameter switching and updating circuit; the PHY / IO high-speed component 207 is used to receive the parameters configured by the PHY / IO configuration parameter register 206 and the interface information for DFI interface switching. The DDR PHY 20 and the SDRAM die 30 can be connected through a DDR interface. The package and the single board 40 are passive connection links between the DDR PHY 20 and the SDRAM die 30.

[0051] Regarding the refresh operation of the SDRAM die 30, the embodiments of the present application may include an auto-refresh operation and a self-refresh operation. The following introduces the two refresh operations.

[0052] The first type: Auto refresh

[0053] Due to the limitations of the storage cell design principle of the SDRAM die 30, the DDR controller 10 needs to regularly (or: at fixed time intervals) issue an auto-refresh instruction to the SDRAM die 30, so that the SDRAM die 30 performs a refresh operation to ensure the security of the internal data. After receiving the auto-refresh instruction, the SDRAM die 30 can start the refresh process inside the die. Specifically, when the SDRAM die 30 performs a refresh operation, it can read each row of data inside the die, and after the read data is amplified by an amplifier, the data is written back to the original position.

[0054] During the refresh of the SDRAM die 30, the DDR controller 10 cannot issue read and write operation instructions to the memory bank in the SDRAM die 30. This period of self-refresh time can be called: the refresh cycle time (ReFresh Cycle Time, tRFC). Exemplarily, such as Figure 2AAs shown, it is a schematic diagram of a refresh cycle time tRFC provided by an embodiment of the present application. In Figure 2A In the shown schematic diagram, it may include a particle working clock (clock, CK), a particle strobe signal (chip strobe, CS), an instruction (COMMAND), a refresh all storage array group (REF all bank), a multi-purpose (multi-purpose command, MPC) instruction, and other instructions (other command).

[0055] The second type: self-refresh

[0056] When the DDR controller 10 does not access the SDRAM particle 30 for more than a set duration, the DDR controller 10 can send an instruction to enter the self-refresh operation to the SDRAM particle 30 through the DDRPHY20, so that the SDRAM particle 30 enters the self-refresh state. Moreover, during the self-refresh of the SDRAM particle 30, the DDR controller 10 cannot issue read / write operation instructions to the storage array in the SDRAM particle 30. When the self-refresh ends, the DDR controller 10 can send an instruction to exit the self-refresh to the SDRAM particle 30 through the DDR PHY20. After the SDRAM particle 30 exits the self-refresh, the DDR controller 10 can issue read / write operation instructions. Exemplarily, as Figure 2B As shown, it is a schematic diagram of a self-refresh time provided by an embodiment of the present application. Among them, the particle enters self-refresh (self-refresh enter, SRE) indicates entering self-refresh, and the particle exits self-refresh (self-refresh exit, SRX) indicates exiting self-refresh. In Figure 2B In the shown schematic diagram, it may include a particle working clock CK, a particle strobe signal CS of a DDR memory (DDR memorycontroller, DMC), an instruction (COMMAND), a particle working clock enable (clock enable, CKE), and a status flag signal (DMC_STATUS_DISABLE), indicating that the DMC is in a non-enabled state.

[0057] Based on the introduction of the above two refresh operations, it can be known that when the SDRAM chip 30 performs a refresh operation, the DDR controller 10 cannot send an access instruction to the SDRAM chip 30. Therefore, in the embodiments of the present application, the time period when the DDR controller 10 is in the state of not accessing the SDRAM chip 30 can be identified, and then this time period is used to perform offset calibration operations to solve the offset problem caused by PVT variations. It should be understood that the time period when the DDR controller 10 is in the state of not accessing the SDRAM chip 30 may include the time period when the SDRAM chip 30 performs a refresh operation and other time periods that can indicate that the DDR controller 10 is in the state of not accessing the SDRAM chip 30.

[0058] As Figure 3 shown, it is a flowchart of an offset calibration method provided by an embodiment of the present application. Referring to Figure 3 shown, the method may include the following steps:

[0059] Step 301, the DDR PHY 20 detects at least one time period during which the DDR controller 10 is prohibited from accessing the SDRAM chip 30.

[0060] It should be understood that in the embodiments of the present application, the DDR controller 10 being prohibited from accessing the SDRAM chip 30 means that the DDR controller 10 cannot access the memory array of the SDRAM chip 30.

[0061] In some embodiments, taking the structure of the DDR PHY 20 shown in Figure 1B as an example. The parsing component 201 in the DDR PHY 20 can detect the status information of the DDR controller 10, such as whether the DDR controller 10 is in the state of accessing the SDRAM chip 30. When the DDR PHY 20 detects that the DDR controller 10 is in the state of not accessing the SDRAM chip 30 and the duration of this state is greater than the set duration, an offset calibration operation is performed within the time period of this state to improve the stability of data transmission. Or, it can also be understood that: the DDR PHY 20 can detect the time period during which the DDR controller 10 is prohibited from accessing the SDRAM chip 30.

[0062] It should be understood that in the embodiments of the present application, the time period during which the DDR controller 10 is in the state of not accessing the SDRAM chip 30 and the duration of this state is greater than the set duration (or the time period during which the DDR controller 10 is prohibited from accessing the SDRAM chip 30) may include at least one time period.

[0063] In the embodiments of the present application, the time period during which the DDR controller 10 is prohibited from accessing the SDRAM chip 30 may include one or several of the following possible time periods:

[0064] The first type: The time period during which the SDRAM chip 30 performs a refresh operation.

[0065] Specifically, the time period during which the SDRAM chip 30 performs a refresh operation may include the following two types:

[0066] (1) When the DDR controller 10 triggers an auto - refresh command, the corresponding refresh time period. The DDR controller 10 sends an auto - refresh command to the SDRAM chip 30 through the DDR PHY20 at a fixed time interval. Correspondingly, after receiving the auto - refresh command, the SDRAM chip 30 starts the refresh process. The auto - refresh command instructs the SDRAM chip 30 to perform a refresh operation during a time period. This time period can be understood as tRFC described above. It should be understood that Figure 4 The illustrated embodiment is introduced by taking this first possible time period as an example.

[0067] (2) When the DDR controller 10 triggers a command to enter self - refresh, the corresponding refresh time period. When the DDR controller 10 has not accessed the SDRAM chip 30 for more than a preset duration, the DDR controller 10 can send a command to enter self - refresh to the SDRAM chip 30 through the DDR PHY20. When the SDRAM chip 30 receives the command to enter self - refresh, it can perform a self - refresh operation. When the SDRAM chip 30 receives the command to exit self - refresh sent by the DDR controller 10 through the DDR PHY20, it can exit the self - refresh operation. Therefore, the time period during which the SDRAM chip 30 performs a refresh operation can be understood as: the time period between the first time point when the DDR controller 10 receives the command to enter self - refresh and the second time point when it receives the command to exit self - refresh. This time period can be understood as SelfRefresh described above. It should be understood that the following Figure 5 The illustrated embodiment is introduced by taking this second possible time period as an example.

[0068] The second type: Other time periods that can identify that the DDR controller 10 will not access the SDRAM chip 30.

[0069] In some embodiments, set identification information can be configured. When the set identification information is detected, it can be determined that the DDR controller 10 is in a time period when accessing the SDRAM chip 30 is prohibited.

[0070] Step 302, the DDR PHY20 performs offset calibration on the data transmission delay of the data transmission link during at least one time period.

[0071] In some embodiments, the DDR PHY 20 may perform offset calibration of data transfer delay during the period when the DDR controller 10 prohibits access to the SDRAM die 30. For example, the offset calibration of data transfer delay may be performed during a period when the DDR controller 10 prohibits access to the SDRAM die 30, or alternatively, the offset calibration of data transfer delay may also be performed during multiple periods when the DDR controller 10 prohibits access to the SDRAM die 30. The present application does not make specific limitations in this regard.

[0072] Exemplarily, taking the auto refresh command as an example. The DDR PHY 20 receives the auto refresh command sent by the DDR controller 10, and this auto refresh command instructs the SDRAM die 30 to perform a refresh operation during a period. Then, the DDR PHY 20 may send this auto refresh command to the SDRAM die 30, and the period indicated by this auto refresh command can be understood as the period when the SDRAM die 30 performs the refresh operation.

[0073] For example, the DDR PHY 20 may perform offset calibration of data transfer latency during a period when the SDRAM die 30 performs the refresh operation. For another example, the DDR PHY 20 may determine M (where M and N are both positive integers and M is less than or equal to N) of the consecutive N periods when the SDRAM die 30 performs the refresh operation as the periods when the DDR controller 10 prohibits access to the SDRAM die 30, then the DDR PHY 20 may perform offset calibration operations during the M periods when the SDRAM die 30 performs the refresh operation.

[0074] Another example, taking the command to enter self-refresh as an example. The DDR PHY 20 may receive the command to enter self-refresh sent by the DDR controller 10, and then the DDR PHY 20 sends the command to enter self-refresh to the SDRAM die 30. Correspondingly, the SDRAM die 30 performs the refresh operation, and the DDR PHY 20 may perform offset calibration operations while the SDRAM die 30 performs the refresh operation. After the DDR PHY 20 receives the command to exit self-refresh sent by the DDR controller 10, the SDRAM die 30 may exit the self-refresh operation, and at the same time, the DDR PHY 20 may stop performing offset calibration operations.

[0075] For example, the DDR PHY 20 can complete an offset calibration operation for the data transmission delay within the time period when the SDRAM die 30 performs a self-refresh operation. Among them, the time period for the SDRAM die 30 to perform the self-refresh operation is the time period between the first time point when the DDR controller 10 receives the instruction to enter the self-refresh and the second time point when it receives the instruction to exit the self-refresh. For another example, the DDR PHY 20 can also complete an offset calibration operation for the data transmission delay within M time periods among the time periods when the SDRAM die 30 continuously performs N self-refresh operations. In this case, the M time periods among the time periods when the SDRAM die 30 continuously performs N refresh operations can be understood as the time periods when the DDR controller 10 cannot access the SDRAM die 30.

[0076] In the embodiments of the present application, the offset calibration operation may include the following operations: Calibration of the path transmission delays in both the read and write directions requires steps such as switching the path delay configuration, sending read and write data to the die, comparing the read operation results, determining the delay adjustment direction and adjustment amplitude, and adjusting the delay. For details, please refer to the introduction in the embodiments shown below. Figure 4 and Figure 5 the introduction in the embodiments shown below.

[0077] In addition, in the embodiments of the present application, in addition to calibrating the data transmission delay on the data transmission path, the DDR PHY 20 can also perform a background calibration operation. Exemplarily, the background calibration may include: calibration of the driving ability of the interface signal (such as calibration of the pull-up impedance of the high-speed IO and calibration of the pull-down impedance of the high-speed IO), calibration of the delay value represented by the unit delay of the delay chain (such as calibration of the time-to-digital conversion TDC and calibration of the conversion relationship of the delay logic), calibration of the path delay in the receiving direction, calibration of the signal duty cycle in the receiving direction, and other steps.

[0078] Next, the offset calibration method of the embodiments of the present application will be introduced by taking two types of refreshes as examples. First, an example of auto-refresh will be introduced. As Figure 4 shown, it is a flowchart of an offset calibration method provided by the embodiments of the present application. Referring to Figure 4 shown, the method may include the following steps:

[0079] It should be understood that Figure 4 the execution subject of the embodiments shown Figure 1A may be the DDR PHY 20 in the system shown.

[0080] Step 401: Receive the auto-refresh instruction sent by the DDR controller 10.

[0081] In some embodiments, the DDR PHY 20 may receive an auto-refresh instruction sent by the DDR controller 10, and this auto-refresh instruction is used to instruct the SDRAM die 30 to perform a refresh operation. After the DDR PHY 20 receives the auto-refresh instruction sent by the DDR controller 10, it may send the auto-refresh instruction to the SDRAM die 30, so that the SDRAM die 30 starts to perform a refresh operation after receiving the auto-refresh instruction.

[0082] Step 402: Determine whether the background calibration is completed. If the background calibration has been completed, update the background calibration result to the PHY / IO high-speed component 207; if the background calibration has not been completed, continue to execute step 403.

[0083] Among them, the background calibration may include Time-Digital-Conversion (TDC) calibration, conversion relationship calibration of the delay logic, pull-up impedance calibration of the high-speed IO, pull-down impedance calibration of the high-speed IO, etc.

[0084] In some embodiments, the active calibration state machine 202 may detect whether the background calibration is completed. When the background calibration has been completed, update the background calibration result to the PHY / IO high-speed component 207, so that the PHY / IO high-speed component 207 can perform offset calibration according to the background calibration result subsequently.

[0085] Step 403: Determine whether the previous offset calibration has completed window boundary detection. If the previous offset calibration has completed window boundary detection, calculate the average value according to the window boundary and use the average value as the new delay configuration parameter. If the previous active calibration has not completed window boundary detection, continue to execute step 404.

[0086] It should be understood that the window boundary refers to the left boundary and the right boundary of the path delay value, and the path delay value can be a numerical range.

[0087] In some embodiments, it may be determined whether the left and right boundaries of the path delay value have been calculated in the previous offset calibration. If the left and right boundaries of the path delay value have been calculated, calculate the average value based on the left boundary and the right boundary. Exemplarily, for example, if the path delay value takes the value of [X1, X2], then calculate Y = (X1 + X2) / 2 and use the Y value as the new delay configuration parameter.

[0088] In the embodiments of the present application, the window boundary detection may need to be calculated through multiple calibration processes. After the window boundary detection is calculated, the average value of the currently calculated window boundary can be used as a new delay configuration parameter to update the PHY / IO high-speed component 207. Then, after the window boundary detection is completed next time, the average value of the window boundary calculated next time can be used as a new delay configuration parameter to update the PHY / IO high-speed component 207.

[0089] Step 404: Perform an offset calibration operation on the data transmission delay of the data transmission link during at least one time period when the DDR controller 10 is not accessing the SDRAM particle 30.

[0090] In the embodiments of the present application, the offset calibration operation may not be completed within one time period. Therefore, the offset calibration operation can be performed multiple times within multiple time periods. It can also be understood that one offset calibration operation can be completed within multiple time periods, and partial offset calibration operations are performed within each time period.

[0091] Specifically, the offset calibration process may include the following steps:

[0092] Step 4041: Switch the DFI interface from the interface corresponding to the DDR controller path to the interface corresponding to the calibration path, and switch the delay parameter of the PHY / IO high-speed component 207 from the configuration parameter to the operation parameter.

[0093] In some embodiments, the DFI interface may include interfaces corresponding to two paths, specifically including the interface corresponding to the DDR controller path and the interface corresponding to the calibration path. When performing the offset calibration operation, the active calibration state machine 202 can switch the DFI interface from the interface corresponding to the DDR controller path to the interface corresponding to the calibration path, and switch the delay parameter of the PHY / IO high-speed component 207 from the configuration parameter to the operation parameter.

[0094] Step 4042: Perform a write operation on the SDRAM particle 30.

[0095] The active calibration state machine 202 controls the active calibration data processing component 203 to perform a write operation on the SDRAM particle 30.

[0096] Step 4043: Perform a read operation on the SDRAM particle 30, and compare the result of the read operation with a preset result to obtain a comparison result.

[0097] In some embodiments, the active calibration state machine 202 can control the active calibration data processing component 203 to perform a read operation on the SDRAM die 30, and compare the result of the read operation with a preset result to obtain a comparison result. That is to say, the result of the write operation in step 4042 is read back from the SDRAM die 30, and then the read-back result of the write operation is compared with the preset result.

[0098] Step 4044: Switch the DFI interface from the interface corresponding to the calibration path to the interface corresponding to the DDR controller path, and switch the delay parameter of the PHY / IO high-speed component 207 from the operation parameter to the configuration parameter.

[0099] In some embodiments, after the read and write operations are completed, the DFI interface can be switched back from the interface corresponding to the calibration path to the interface corresponding to the DDR controller path, and the delay parameter of the PHY / IO high-speed component 207 can be switched back from the operation parameter to the configuration parameter.

[0100] Step 4045: Analyze the comparison result in step 4043.

[0101] In some embodiments, the comparison result of the read and write operation results and the preset result can be obtained in step 4043, and the comparison result can be analyzed in step 4045.

[0102] Step 4046: Determine whether the offset is greater than the set threshold. If it is greater than the set threshold, continue to execute step 4047; if the offset is not greater than the set threshold, return to step 401.

[0103] After the active calibration data processing component 203 obtains the comparison result in step 4043, the active calibration state machine 202 can analyze and calculate the comparison result. Determine whether the offset in the calculation result is greater than the set threshold. If it is greater than the set threshold, perform offset calibration on the offset.

[0104] Step 4047: Perform offset calibration on the offset.

[0105] In some embodiments, after the read operation is completed, the result of the read operation can be compared with the preset result to determine whether the offset in the comparison result is greater than the set threshold. If the offset is greater than the set threshold, perform offset calibration, and then return to step 401.

[0106] So far, steps 4041 to 4047 can be understood as a fragmented offset calibration operation. When it is detected next time that the DDR controller is in a state of not accessing the SDRAM die, the offset calibration operation can continue to be performed according to the above process.

[0107] In addition, in the embodiments of the present application, when the DDR PHY 20 performs the offset calibration operation, the DDR controller 10 may also send read operation instructions and / or write operation instructions to the non-storage array of the SDRAM chip 30, such as a first in first out (FIFO) array. That is to say, during the execution of the offset calibration operation, the read and write operations can still be performed.

[0108] It should be understood that in the embodiments of the present application, since the chip reading and writing can be performed during the refresh, through the read and write operations between the DDR controller 10 and the SDRAM chip 30, the read and write delay calibration of the entire link including the on-chip clock tree, on-chip delay line, on-chip IO, off-chip package, off-chip single board, and off-chip chip is realized. That is to say, the offset calibration operation may include the offset calibration of the entire transmission link from the DDR controller to the SDRAM chip.

[0109] The following takes self-refresh as an example for introduction. As Figure 5 shown, it is a flowchart of an offset calibration method provided by an embodiment of the present application. Referring to Figure 5 shown, the method may include the following steps:

[0110] It should be understood that Figure 5 the execution subject of the embodiment shown may be Figure 1A the DDR PHY 20 in the system shown.

[0111] Step 501: Receive an instruction from the DDR controller 10 to enter self-refresh.

[0112] In some embodiments, the parsing component 201 in the DDR PHY 20 may detect at least one time period when the DDR controller 10 is not accessing the SDRAM chip 30. When it is detected that the DDR controller sends an instruction to enter self-refresh to the SDRANM chip 30 through the DDR PHY 20, it can be determined that the at least one detected time period is the time period when the SDRAM chip 30 is in self-refresh. When the SDRAM chip 30 receives the instruction to enter self-refresh, it enters the self-refresh operation. At the same time, the DDR PHY 20 may perform the offset calibration operation during this self-refresh time period.

[0113] Step 502: Determine whether the background calibration is completed. If the background calibration has been completed, update the background calibration result to the PHY / IO high-speed component 207; if the background calibration has not been completed, continue to execute step 503.

[0114] Step 503: Determine whether the window boundary detection was completed in the previous offset calibration. If the window boundary detection was completed in the previous offset calibration, calculate the average value based on the window boundary and use the average value as the new delay configuration parameter. If the window boundary detection was not completed in the previous active calibration, continue to execute Step 504.

[0115] Step 504: Perform an offset calibration operation on the data transfer delay of the data transfer link during at least one time period when the DDR controller 10 is not accessing the SDRAM particle 30.

[0116] Specifically, in the self-refresh scenario, Step 504 may include the following steps:

[0117] Step 5041: Switch the DFI interface from the interface corresponding to the DDR controller path to the interface corresponding to the calibration path, and switch the delay parameter of the PHY / IO high-speed component 207 from the configuration parameter to the operation parameter.

[0118] Step 5042: Perform a write operation on the SDRAM particle 30.

[0119] Step 5043: Perform a read operation on the SDRAM particle 30, and compare the result of the read operation with a preset result to obtain a comparison result.

[0120] Step 5044: Switch the DFI interface from the interface corresponding to the calibration path to the interface corresponding to the DDR controller path, and switch the delay parameter of the PHY / IO high-speed component 207 from the operation parameter to the configuration parameter.

[0121] Step 5045: Analyze the comparison result in Step 5043.

[0122] Step 5046: Determine whether the offset is greater than a set threshold. If it is greater than the set threshold, continue to execute Step 5047; if the offset is not greater than the set threshold, return to Step 501.

[0123] Step 5047: Perform an offset calibration on the offset.

[0124] Step 5048: Receive an instruction to exit self-refresh sent by the DDR controller 10.

[0125] In some embodiments, the DDR controller 10 may send an instruction to exit self-refresh to the SDRANM particle 30 through the DDR PHY20. When the SDRAM particle 30 receives the instruction to exit self-refresh, it exits the self-refresh operation and also stops the offset calibration operation. That is to say, Steps 5041 to 5048 can be a fragmented offset calibration operation.

[0126] In other embodiments, a timer may be added to the self-refresh scenario. When the DDR controller 10 does not send an instruction to exit the self-refresh, the offset calibration operation may be controlled by the timer. For example, the offset calibration operation may enter a pause state after executing for a period of time, at which time the timer is started. When the timer times out, the offset calibration operation may be restarted. This can avoid the offset calibration operation from being continuously executed, thereby achieving the purpose of saving power consumption.

[0127] It should be understood that Figure 5 The embodiment shown and Figure 4 Compared with the embodiment shown in the figure, the calibration process is slightly different in different refresh scenarios. Figure 4 In the automatic refresh scenario shown, the DDR controller 10 only needs to send an automatic refresh instruction to the SDRAM particle 30, and the SDRAM particle 30 can automatically exit the refresh after the refresh is completed. Figure 5 In the self-refresh scenario of the illustrated embodiment, the DDR controller 10 may send an enter self-refresh instruction and an exit self-refresh instruction to the SDRAM particles 30 . Figure 5 The specific implementation of steps 501 to 503 and steps 5041 to 5047 in the embodiment shown can be referred to. Figure 4 The detailed description in the illustrated embodiments will not be repeated here.

[0128] It should be noted that all or part of the above embodiments provided in this application can be freely and arbitrarily combined with each other, and the combined technical solutions are also within the scope of protection of this application.

[0129] like Figure 6 As shown, an offset calibration device provided in an embodiment of the present application is provided. The device 600 may include a detection module 601 and a calibration module 602.

[0130] The detection module 601 is used to detect at least one time period during which the DDR controller prohibits access to the SDRAM particles; the calibration module 602 is used to perform an offset calibration operation on the data transmission delay of the data transmission link within the at least one time period detected by the detection module 601.

[0131] In one possible design, the time period during which the DDR controller prohibits access to the synchronous dynamic random access memory SDRAM particles includes the following time period: the time period during which the SDRAM particles perform refresh operations or the time period that can identify the DDR controller prohibiting access to the SDRAM particles within at least one set time period.

[0132] In one possible design, the detection module 601 is specifically configured to detect the time period during which the DDR controller prohibits access to the SDRAM particles in the following manner:

[0133] Receive the auto-refresh instruction sent by the DDR controller, and send the auto-refresh instruction to the SDRAM die. The auto-refresh instruction is used to instruct the SDRAM die to perform a refresh operation. Wherein, the time period during which the SDRAM die performs the refresh operation is the time period during which the DDR controller cannot access the SDRAM die.

[0134] In a possible design, the detection module 601 is specifically configured to detect at least one time period during which the DDR controller prohibits access to the SDRAM die in the following manner:

[0135] Receive the auto-refresh instruction sent by the DDR controller, and send the auto-refresh instruction to the SDRAM die. The auto-refresh instruction instructs the SDRAM die to perform a refresh operation within a time period. The time period indicated by the auto-refresh instruction is the time period during which the SDRAM die performs the refresh operation. Wherein, M of the N consecutive time periods during which the SDRAM die performs the refresh operation are the time periods during which the DDR controller cannot access the SDRAM die. Both N and M are positive integers, and M is less than or equal to N.

[0136] In a possible design, the detection module 601 is specifically configured to detect the time period during which the DDR controller prohibits access to the SDRAM die in the following manner:

[0137] Receive the enter self-refresh instruction sent by the DDR controller, and send the enter self-refresh instruction to the SDRAM die. The enter self-refresh instruction is used to instruct the SDRAM die to start performing a refresh operation.

[0138] Receive the exit self-refresh instruction sent by the DDR controller, and send the exit self-refresh instruction to the SDRAM die. The exit self-refresh instruction is used to instruct the SDRAM die to exit the refresh operation.

[0139] Wherein, the time period between the first time point when the DDR controller receives the enter self-refresh instruction and the second time point when the DDR controller receives the exit self-refresh instruction is the time period during which the DDR controller prohibits access to the SDRAM die.

[0140] In a possible design, the detection module 601 is specifically configured to detect the time period during which the DDR controller prohibits access to the SDRAM die in the following manner:

[0141] Receive the instruction to enter self - refresh sent by the DDR controller and send the instruction to enter self - refresh to the SDRAM die. The instruction to enter self - refresh is used to instruct the SDRAM die to start performing a refresh operation; receive the instruction to exit self - refresh sent by the DDR controller and send the instruction to exit self - refresh to the SDRAM die. The instruction to exit self - refresh is respectively used to instruct the SDRAM die to exit the refresh operation;

[0142] Among them, the time period between the first time point when the DDR controller receives the instruction to enter self - refresh and the second time point when it receives the instruction to exit self - refresh is the time period for the SDRAM die to perform the refresh operation; M of the N consecutive time periods for the SDRAM die to perform the refresh operation are the time periods when the DDR controller cannot access the SDRAM die. Both N and M are positive integers, and M is less than or equal to N.

[0143] In a possible design, the SDRAM die includes a storage array and a non - storage array, and at least one time period when the DDR controller prohibits accessing the SDRAM die is at least one time period when the DDR controller prohibits accessing the storage array of the SDRAM die.

[0144] In a possible design, the device 600 may further include a transceiver module 603. The transceiver module 603 is used to receive a read operation instruction sent by the DDR controller during the execution of the offset calibration operation. The read operation instruction is used to instruct to perform a read operation on the non - storage array of the SDRAM die.

[0145] In a possible design, the device 600 may further include a transceiver module 603. The transceiver module 603 is used to receive a write operation instruction sent by the DDR controller during the execution of the offset calibration operation. The write operation instruction is used to instruct to perform a write operation on the non - storage array of the SDRAM die.

[0146] In a possible design, the calibration module 602 is further used to perform a background calibration operation within at least one time period. The background calibration operation at least includes the following calibration operations: time - to - digital converter (TDC) calibration, conversion relationship calibration of delay logic, pull - up impedance calibration of high - speed I / O, and pull - down impedance calibration of high - speed I / O.

[0147] In the embodiments of the present application, the division of modules is illustrative, merely a logical function division. In actual implementation, there may be other division methods. Additionally, in each embodiment of the present application, the various functional modules can be integrated in a processor, can exist independently physically, or two or more modules can be integrated in one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0148] As Figure 7 shown, some other embodiments of the present application provide an offset calibration device. Referring to Figure 7 shown, the offset calibration device 700 includes: a processor 701; a memory 702; a communication interface 703; and one or more computer programs 704 (not shown in the figure). The above components can be connected through one or more communication buses 705.

[0149] Among them, the memory 702 stores one or more computer programs. When the instructions are called and executed by the processor 701, the offset calibration device 700 is caused to execute the method steps in the above embodiments. Exemplarily, when the instructions are called and executed by the processor 701, the offset calibration device 700 is caused to execute the following steps:

[0150] Detect at least one time period during which the DDR controller prohibits access to the SDRAM particles, and perform offset calibration on the data transmission delay of the data transmission link within at least one time period detected by the detection module 601.

[0151] It should be understood that Figure 7 the processor 701 in the shown embodiment is used to execute Figure 6 the functions of the detection module 601 and the calibration module 602 in the shown embodiment, and the communication interface 703 is used to execute Figure 6 the function of the transceiver module 603 in the shown embodiment. For specific details, reference can be made to the introduction in the embodiment shown in Figure 6 shown, and details will not be repeated here.

[0152] In the embodiments of the present application, the processor 701 can be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application can be directly implemented by the hardware processor, or can be implemented by a combination of hardware and software modules in the processor. The software module can be located in the memory 702, and the processor 701 reads the program instructions in the memory 702 and combines its hardware to complete the steps of the above method.

[0153] In the embodiments of the present application, the memory 702 may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., or may also be a volatile memory, such as RAM. The memory may also be any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in the embodiments of the present application may also be a circuit or any other device capable of implementing a storage function, for storing instructions and / or data.

[0154] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0155] Based on the above embodiments, the present application also provides a computer storage medium, in which a computer program is stored. When the computer program is executed by a computer, the computer is caused to execute the offset calibration method provided in the above embodiments.

[0156] Based on the above embodiments of the present application, the present application also provides a computer program product, including instructions, which when running on a computer, cause the computer to execute the offset calibration method provided in the above embodiments.

[0157] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and the combination of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by instructions. These instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0158] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0159] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are executed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing steps for implementing the functions specified in one flow or more flows of the flowchart and / or one block or more blocks of the block diagram on the computer or other programmable apparatus.

Claims

1. An offset calibration method, characterized in that, including: The double data rate physical layer (DDR PHY) detects at least one time period during which the DDR controller is prohibited from accessing the synchronous dynamic random access memory (SDRAM) chip; During the at least one time period, the DDR PHY performs offset calibration on the data transmission delay of the data transmission link, where the data transmission link is the transmission link between the DDR controller and the SDRAM chip.

2. The method according to claim 1, characterized in that, The time period during which the DDR controller is prohibited from accessing the synchronous dynamic random access memory (SDRAM) chip includes the following time periods: The time period during which the SDRAM chip performs a refresh operation or the time period that can identify that the DDR controller is prohibited from accessing the SDRAM chip within at least one set time period.

3. The method according to claim 1 or 2, characterized in that, The time period during which the DDR PHY detects that the DDR controller is prohibited from accessing the synchronous dynamic random access memory (SDRAM) chip includes: Receiving an auto-refresh instruction sent by the DDR controller and sending the auto-refresh instruction to the SDRAM chip, where the auto-refresh instruction is used to instruct the SDRAM chip to perform a refresh operation; Among them, the time period during which the SDRAM chip performs a refresh operation is the time period during which the DDR controller cannot access the SDRAM chip.

4. The method according to claim 1 or 2, characterized in that, The time period during which the DDR PHY detects that the DDR controller is prohibited from accessing the synchronous dynamic random access memory (SDRAM) chip includes: Receiving an auto-refresh instruction sent by the DDR controller and sending the auto-refresh instruction to the SDRAM chip, where the auto-refresh instruction instructs the SDRAM chip to perform a refresh operation within a time period; the time period indicated by the auto-refresh instruction is the time period during which the SDRAM chip performs a refresh operation; Among them, M time periods out of the N consecutive time periods during which the SDRAM chip performs a refresh operation are the time periods during which the DDR controller cannot access the SDRAM chip, where both N and M are positive integers, and M is less than or equal to N.

5. The method according to claim 1 or 2, characterized in that, The time period during which the DDR PHY detects that the DDR controller is prohibited from accessing the synchronous dynamic random access memory (SDRAM) chip includes: Receiving an enter self-refresh instruction sent by the DDR controller and sending the enter self-refresh instruction to the SDRAM chip, where the enter self-refresh instruction is used to instruct the SDRAM chip to start performing a refresh operation; Receiving an exit self-refresh instruction sent by the DDR controller and sending the exit self-refresh instruction to the SDRAM chip, where the exit self-refresh instruction is used to instruct the SDRAM chip to exit the refresh operation; Among them, the time period between the first time point when the DDR controller receives the enter self-refresh instruction and the second time point when it receives the exit self-refresh instruction is the time period during which the DDR controller is prohibited from accessing the SDRAM chip.

6. The method according to claim 1 or 2, characterized in that, The time period during which the DDR PHY detects that the DDR controller is prohibited from accessing the synchronous dynamic random access memory (SDRAM) chip includes: Receives the instruction to enter self-refresh sent by the DDR controller and sends the instruction to enter self-refresh to the SDRAM die, where the instruction to enter self-refresh is used to instruct the SDRAM die to start performing the refresh operation; Receives the instruction to exit self-refresh sent by the DDR controller and sends the instruction to exit self-refresh to the SDRAM die, where the instruction to exit self-refresh is respectively used to instruct the SDRAM die to exit the refresh operation; Wherein, the time period between the first time point when the DDR controller receives the instruction to enter self-refresh and the second time point when it receives the instruction to exit self-refresh is the time period for the SDRAM die to perform the refresh operation; M of the N consecutive time periods for the SDRAM die to perform the refresh operation are the time periods during which the DDR controller cannot access the SDRAM die, where N and M are both positive integers, and M is less than or equal to N.

7. The method according to any one of claims 1-6, characterized in that, The SDRAM die includes a memory array and a non-memory array, and at least one time period during which the DDR controller prohibits access to the SDRAM die is at least one time period during which the DDR controller prohibits access to the memory array of the SDRAM die.

8. The method according to claim 7, wherein The method further includes: Receiving a read operation instruction sent by the DDR controller during the execution of the offset calibration operation, where the read operation instruction is used to instruct a read operation on the non-memory array of the SDRAM die.

9. The method according to claim 7 or 8, characterized in that, The method further includes: Receiving a write operation instruction sent by the DDR controller during the execution of the offset calibration operation, where the write operation instruction is used to instruct a write operation on the non-memory array of the SDRAM die.

10. The method according to any one of claims 1 to 9, characterized in that, The method further includes: The DDR PHY performs a background calibration operation during the at least one time period, and the background calibration operation at least includes the following calibration operations: time-to-digital converter (TDC) calibration, conversion relationship calibration of the delay logic, pull-up impedance calibration of the high-speed I / O, and pull-down impedance calibration of the high-speed I / O.

11. An offset calibration device, characterized in that, Includes: A memory and a processor; The memory is used to store computer instructions; The processor is used to execute the computer instructions stored in the memory, so that the offset calibration device executes the method according to any one of claims 1-10.

12. A computer-readable storage medium, characterized in that, The storage medium stores computer instructions, and when the computer instructions are executed by the offset calibration device, the offset calibration device is caused to execute the method according to any one of claims 1-10.

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