Memory, operation method thereof and memory system

Abstract

The embodiment of the invention provides a memory, an operation method thereof and a memory system. The memory comprises a memory cell array, the memory cell array comprises a plurality of memory strings, each memory string comprises a plurality of upper selection tubes and a plurality of memory cells, and the plurality of upper selection tubes are located on one side of the plurality of memory cells; the plurality of upper selection grid lines are coupled to the plurality of upper selection tubes, and the plurality of word lines are coupled to the plurality of storage units; the peripheral circuit is coupled to the plurality of upper selection grid lines and the plurality of word lines, and the peripheral circuit is configured to apply a first pulse to a first word line in the plurality of word lines, so that the voltage of the first word line reaches a first target voltage at a first moment; applying a second pulse to a first upper selection grid line adjacent to the first word line in the plurality of upper selection grid lines, so that the voltage of the first upper selection grid line reaches a second target voltage at a second moment; wherein the second moment is later than the first moment.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and particularly to a memory, an operation method thereof, and a memory system. Background Art

[0002] With the continuous development of current science and technology, semiconductor devices are widely used in various electronic devices and products. For example, as a non-volatile memory, a NAND memory is a commonly used semiconductor storage device in a computer. How to improve the programming crosstalk problem of the NAND memory has always been a key research topic for those skilled in the art. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory, an operation method thereof, and a memory system.

[0004] According to a first aspect of the present disclosure, there is provided a memory, the memory comprising:

[0005] a memory cell array including a plurality of memory strings, the memory strings including a plurality of upper selection transistors and a plurality of memory cells, the plurality of upper selection transistors being located on one side of the plurality of memory cells;

[0006] a plurality of upper selection gate lines coupled to the plurality of upper selection transistors;

[0007] a plurality of word lines coupled to the plurality of memory cells;

[0008] a peripheral circuit coupled to the plurality of upper selection gate lines and the plurality of word lines, configured to:

[0009] apply a first pulse to a first word line among the plurality of word lines, so that the voltage of the first word line reaches a first target voltage at a first moment;

[0010] apply a second pulse to a first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines, so that the voltage of the first upper selection gate line reaches a second target voltage at a second moment; wherein, the second moment is later than the first moment.

[0011] According to a second aspect of the present disclosure, there is provided a memory system, comprising:

[0012] a memory as described in any one of the first aspects of the present disclosure; and

[0013] a memory controller coupled to the memory and configured to control the memory.

[0014] According to a third aspect of the present disclosure, there is provided a method for operating a memory, the memory including a memory cell array and a peripheral circuit coupled to the memory cell array, the memory cell array including a plurality of memory strings, the memory strings including a plurality of memory cells and a plurality of upper selection transistors located on one side of the plurality of memory cells; a plurality of word lines are coupled to the plurality of memory cells, and a plurality of upper selection gate lines are coupled to the plurality of upper selection transistors;

[0015] The operation method includes:

[0016] Applying a first pulse to a first word line among the plurality of word lines to cause the voltage of the first word line to reach a first target voltage at a first moment;

[0017] Applying a second pulse to a first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines to cause the voltage of the first upper selection gate line to reach a second target voltage at a second moment; wherein, the second moment is later than the first moment.

[0018] When the memory provided by the embodiment of the present disclosure executes a programming operation, a first pulse is applied to a first word line among the plurality of word lines, and a second pulse is applied to a first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines. Among them, the second moment when the first upper selection gate line reaches the second target voltage is later than the first moment when the first word line reaches the first target voltage. In other words, when the first word line reaches the first target voltage at the first moment, the first upper selection gate line may not have been applied with the second pulse yet, or the voltage of the first upper selection gate line is still in the rising edge stage of the second pulse and has not reached the second target voltage. At this time, due to the coupling effect of the voltage of the first word line, a voltage spike may occur on the first upper selection gate line before or during the rising edge of the second pulse. Compared with the voltage spike coupled out when the first upper selection gate line is at the second target voltage, the voltage value of the voltage spike that appears at this time is smaller. Therefore, the probability of leakage of unselected memory strings can be reduced, and further the programming crosstalk problem caused by leakage of unselected memory strings can be improved. Description of the Drawings

[0019] Figure 1 It is a block diagram of an exemplary system including a memory provided by an embodiment of the present disclosure;

[0020] Figure 2a It is a schematic diagram of a memory card including a memory provided by an embodiment of the present disclosure;

[0021] Figure 2b It is a schematic diagram of a solid-state drive including a memory provided by an embodiment of the present disclosure;

[0022] Figure 3 It is a schematic diagram of a memory including a peripheral circuit provided by an embodiment of the present disclosure;

[0023] Figure 4 Schematic diagram of a memory cell array including a memory string provided by an embodiment of the present disclosure;

[0024] Figure 5 Schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure;

[0025] Figure 6 Schematic diagram of a memory cell array provided by an embodiment of the present disclosure;

[0026] Figure 7 Schematic diagram of another memory cell array provided by an embodiment of the present disclosure;

[0027] Figure 8 Schematic circuit diagram of a memory cell array provided by an embodiment of the present disclosure;

[0028] Figure 9 Timing diagram of multiple signals during a programming operation of a memory provided by an embodiment of the present disclosure;

[0029] Figure 10 Schematic diagram of a memory provided by an embodiment of the present disclosure;

[0030] Figure 11 Timing diagram of voltages of a first word line and a first upper select gate line during a programming operation provided by an embodiment of the present disclosure;

[0031] Figure 12 Another timing diagram of voltages of a first word line and a first upper select gate line during a programming operation provided by an embodiment of the present disclosure;

[0032] Figure 13 Another timing diagram of voltages of a first word line and a first upper select gate line during a programming operation provided by an embodiment of the present disclosure;

[0033] Figure 14 Timing diagram of multiple signals during a programming operation provided by an embodiment of the present disclosure;

[0034] Figure 15 Another timing diagram of multiple signals during a programming operation provided by an embodiment of the present disclosure;

[0035] Figure 16 Another timing diagram of multiple signals during a programming operation provided by an embodiment of the present disclosure;

[0036] Figure 17 Another timing diagram of multiple signals during a programming operation provided by an embodiment of the present disclosure;

[0037] Figure 18 Flow chart of an operation method of a memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be construed as limiting the present disclosure. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0039] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0040] In the following description, the terms "first", "second", and "third" are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first", "second", and "third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] It should be noted that, in this document, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising such element.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0043] Figure 1Block diagram of an exemplary system including a memory provided by an embodiment of the present disclosure. The exemplary system 100 may include a host 110 and a memory system 120. Among them, the exemplary system 100 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 122 therein; the host 110 may be a processor of the electronic device (for example, a central processing unit (CPU) or a system on chip (SoC) (for example, an application processor (AP))).

[0044] In an embodiment of the present disclosure, the host 110 may be configured to send data to the memory system 120 or receive data from the memory system 120. Here, the memory system 120 may include a memory controller 121 and one or more memories 122. Among them, the memory 122 may include, but is not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0045] In one embodiment of the present disclosure, a Memory Controller 121 may be coupled to a Memory 122 and a Host 110, and is configured to control the Memory 122. Exemplarily, the Memory Controller 121 may be designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the Memory Controller 121 may also be designed to operate in a high-duty-cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0046] Furthermore, the Memory Controller 121 may manage data in the Memory 122 and communicate with the Host 110. The Memory Controller 121 may be configured to control operations such as reading, erasing, and programming of the Memory 122; may also be configured to manage various functions regarding data stored in or to be stored in the Memory 122, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; may also be configured to process Error Checking and Correction (ECC) for data read from or written to the Memory 122. In addition, the Memory Controller 121 may also perform any other suitable functions, such as formatting the Memory 122, or communicating with external devices according to a specific communication protocol (e.g., Figure 1communicate with the external host 110. Exemplarily, the memory controller 121 may communicate with the external host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc.

[0047] In an embodiment of the present disclosure, the memory controller 121 and one or more memories 122 may be integrated into various types of storage devices. For example, they may be included in the same package (such as Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 120 may be implemented and packaged into different types of terminal electronic products. As Figure 2a shown, the memory controller 121 and a single memory 122 may be integrated together to form a memory card 210. The memory card 210 may include a PC card (Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, Memory Stick, Multi-Media Card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), SD card (SD, miniSD, microSD, Secure Digital High Capacity (SDHC)), UFS, etc. The memory card 210 may also include a memory card connector 211 that couples the memory card 210 to a host (such as Figure 1 the host 110 in Figure 2bIn another embodiment shown in the figure, the memory controller 121 and the plurality of memories 122 may be integrated together to form an SSD 220. The SSD 220 may also include an SSD connector 221 that couples the SSD 220 to a host (e.g., Figure 1 the host 110 in). In some embodiments, the storage capacity and / or operating speed of the SSD 220 is greater than the storage capacity and / or operating speed of the memory card 210.

[0048] It should be noted that the memory related to an embodiment of the present disclosure may be a semiconductor memory, which is a solid-state electronic device for storing data information made by semiconductor integrated circuit processes. Figure 3 FIG. is a schematic diagram of a memory including a peripheral circuit provided by an embodiment of the present disclosure. Among them, the memory 300 may be Figures 1 to 2b the memory 122 in. As Figure 3 shown, the memory 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301, etc. Here, the memory cell array may be a NAND flash memory cell array, where the memory cell array is arranged in the form of a string of memory strings 308 array, and each memory string 308 extends vertically above the substrate. In some embodiments, each memory string 308 may include a plurality of memory cells 306 coupled in series and vertically stacked. Among them, each memory cell 306 may hold a continuous analog value, such as voltage or charge, which depends on the number of electrons captured in the memory cell region. In addition, each memory cell 306 in the above memory cell array 301 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0049] As Figure 3 shown, each memory string 308 may include a lower select transistor 310 at its source extreme and an upper select transistor 312 at its drain extreme. The lower select transistor 310 and the upper select transistor 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations.

[0050] In some embodiments, the sources of the NAND memory strings 308 in the same memory block (simply referred to as "block") 304 are coupled through the same source line (SL) 314 (e.g., a common source line). In other words, according to some embodiments, all the memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the upper select transistor 312 of each memory string 308 is coupled to a corresponding bit line 316, and data can be read or written from the bit line 316 via an output bus (not shown).

[0051] In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the top select transistor 312) or a deselected voltage (e.g., 0V) to the gate of the corresponding top select transistor 312 via one or more top select gates (TSG) 313; and / or, by applying a select voltage (e.g., higher than the threshold voltage of the bottom select transistor 310) or a deselected voltage (e.g., 0V) to the gate of the corresponding bottom select transistor 310 via one or more bottom select gates (BSG) 315. The memory string 308 can thus be classified into a selected memory string or an unselected memory string.

[0052] As Figure 3 shown, the memory strings 308 can be organized into a plurality of blocks 304, and each of the plurality of blocks 304 can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all the memory cells 306 on the same block 304 are erased simultaneously. To erase the memory cells 306 in a selected block, the source line 314 coupled to the selected block and the unselected blocks in the same plane as the selected block can be biased with an erase voltage (Vers), e.g., a high positive voltage (e.g., 20V or higher). It should be understood that in some examples, the erase operation can be performed at a half-block level, at a quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of a block.

[0053] The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, and the word lines 318 select which row of the memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of the memory cells 306, and the page 320 is a basic data unit for a program operation. The size of a page 320 in bits can be related to the number of memory strings 308 coupled by the word lines 318 in a block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in the corresponding page 320 and a gate line coupling the control gates.

[0054] Figure 4 Schematic diagram of a memory cell array including memory strings provided by an embodiment of the present disclosure. As Figure 4 shown, the memory strings 308 can extend vertically above the substrate 402 through the stacked layer 404. The substrate 402 can include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0055] The stacked layer 404 may include alternating gate conductive layers 406 and dielectric layers 408, where the number of pairs of gate conductive layers 406 and dielectric layers 408 may determine the number of memory cells 306 in the memory cell array 301. The gate conductive layer 406 may include a conductive material, which includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. The gate conductive layer 406 may extend laterally at the top of the memory stacked layer 404 as Figure 3 the upper select gate line 313 in Figure 3 or extend laterally at the bottom of the stacked layer 404 as Figure 3 the lower select gate line 315 in Figure 3 or extend laterally between the upper select gate line 313 and the lower select gate line 315 as

[0056] As Figure 4 shown, the memory string 308 includes a channel structure 412 that extends vertically through the stacked layer 404. In some embodiments, the channel structure 412 includes a channel hole filled with a semiconductor material (for example, as a semiconductor channel 420) and a dielectric material (for example, as a memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, for example, polysilicon. In some embodiments, the memory film 418 is a composite dielectric layer, including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping layer"), and a blocking layer 422. The channel structure 412 may have a column shape (for example, a cylindrical shape). According to some embodiments, the semiconductor channel 420, the tunneling layer 426, the storage layer 424, and the blocking layer 422 are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer 422 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 418 may include a composite layer composed of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0057] In some embodiments, as Figure 4As shown, a well 414 (e.g., a P-well and / or an N-well) is formed in a substrate 402, and a source extreme of the memory string 308 is in contact with the well 414. For example, Figure 3 the source line 314 in [reference] can be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the memory string 308) during an erase operation. In some embodiments, the memory string 308 further includes a channel plug 416 at a drain extreme of the memory string 308, e.g., as part of the drain of the memory string 308. It should be understood that Figure 4 the structure of the channel structure 412 depicted in [reference] is for illustrative purposes only and can be changed in other examples. It should be understood that although not shown in Figure 4 additional components of the memory cell array 301 can also be formed, including but not limited to gate line slots / source contacts, local contacts, interconnect layers, etc.

[0058] Returning to Figure 3 , the peripheral circuit 302 can be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, lower select gate lines 315, and upper select gate lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed-signal circuits for implementing write and read operations of the memory cell array 301 by applying voltage signals and / or current signals to each target memory cell 306 and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, lower select gate lines 315, and upper select gate lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 is a schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure. The peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / BL driver 506, a row decoder / WL driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface (I / F) 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in Figure 5 can also be included.

[0059] In combination with Figure 5 and Figure 3, the page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bits stored in the memory cells 306 and amplify the small voltage swing to a recognizable logic level during a read operation.

[0060] The column decoder / BL driver 506 can be configured to be controlled by the control logic unit 512 and select one or more memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0061] The row decoder / WL driver 508 can be configured to be controlled by the control logic unit 512 and select / deselect the blocks 304 of the memory cell array 301 and select / deselect the word lines 318 in the blocks 304 according to control signals generated by the control logic unit 512. The row decoder / WL driver 508 can also be configured to drive the word lines 318 with different word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / WL driver 508 can also select / deselect the lower select gate line 315 and the upper select gate line 313. The row decoder / WL driver 508 is configured to drive the lower select gate line 315 with different lower select gate line voltages generated from the voltage generator 510, and / or drive the upper select gate line 313 with different upper select gate line voltages generated from the voltage generator 510.

[0062] The voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate various word line voltages (e.g., read voltage, program voltage, pass voltage, verify voltage, etc.), bit line voltages, ground voltage, various lower select gate line voltages (e.g., select voltage, deselect voltage), and various upper select gate line voltages (e.g., select voltage, deselect voltage) to be supplied to the memory cell array 301.

[0063] The control logic unit 512 can be coupled to each of the peripheral circuit portions described above and is configured to control the operation of each peripheral circuit portion. The register 514 can be coupled to the control logic unit 512 and includes a status register, a command register, and an address register to store status information, command operation codes, and command addresses for controlling the operation of the peripheral circuits. In some embodiments, the control logic unit 512 can receive programming commands issued by a memory controller (e.g., the memory controller 121 in Figure 1 ) and send control signals to various peripheral circuit portions, such as the row decoder / word line driver 508, the column decoder / bit line driver 506, and the voltage generator 510, to perform a programming operation on the select transistors coupled to the lower select gate lines.

[0064] The interface 516 can be coupled to the control logic unit 512 and acts as a control buffer to buffer control commands (e.g., programming commands) received from the memory controller or the host and relay them to the control logic unit 512, and buffer status information received from the control logic unit 512 and relay it to the memory controller or the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and acts as a data input / output (I / O) interface and a data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0065] Figure 6 A schematic structural diagram of a memory cell array provided by an embodiment of the present disclosure. As Figure 6 shown, the memory cell array includes a stacked layer 610 and a channel structure 620. The structures of the stacked layer 610 and the channel structure 620 are the same as those of the stacked layer 404 and the channel structure 412 described above. Specifically, the stacked layer 610 includes gate conductive layers 611 and dielectric layers 612 stacked alternately in the vertical direction, and the channel structure 620 is located in the stacked layer and extends in the vertical direction. The channel structure 620 includes a semiconductor channel 621 and a memory film 622 surrounding the semiconductor channel 621. Exemplarily, the semiconductor channel 621 includes silicon, such as polysilicon. Exemplarily, the memory film 622 includes a tunneling layer 601, a storage layer 602, and a blocking layer 603 arranged in sequence outward from the center of the channel. Exemplarily, the tunneling layer 601 can include silicon oxide, silicon oxynitride, or any combination thereof. The charge trapping layer 602 can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer 603 can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 622 can be a composite layer composed of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0066] The gate conductive layer 611 at the top of the stacked layer 610 is used to form the upper select gate line 630. The number of gate conductive layers used to form the upper select gate line can be one or more. In this embodiment, as Figure 6 shown, the three gate conductive layers 611 at the topmost of the stacked layer 610 are used to form the upper select gate line 630. The memory cell array further includes upper select gate cut lines 640 that vertically extend through a plurality of gate conductive layers 611 at the topmost of the stacked layer 610. The upper select gate cut lines 640 can extend in the Y direction to cut each of the plurality of gate conductive layers 611 into a plurality of regions, and each region forms an upper select gate line 630. Figure 6 In [reference], the three gate conductive layers 611 at the topmost of the stacked layer 610 are divided by the upper select gate cut lines 640 such that each memory string is coupled to three upper select gate lines 630.

[0067] In some embodiments, in order to increase the layout density of the memory cell array, a process structure in which the stacked layer of the upper select transistors is independent of the stacked layer of the memory cells can be adopted. Figure 7 This is a schematic structural diagram of another memory cell array provided by an embodiment of the present disclosure. As Figure 7 shown, the stacked layer includes a first sub-stacked layer 710 and a second sub-stacked layer 720 located on the first sub-stacked layer 710. Among them, the first sub-stacked layer 710 includes a first gate conductive layer 711 and a first dielectric layer 712 alternately stacked in the vertical direction, and the second sub-stacked layer 720 includes a second gate conductive layer 721 and a second dielectric layer 722 sequentially stacked in the vertical direction. The materials of the second gate conductive layer 721 and the first gate conductive layer 711 can be the same or different. The materials of the first gate conductive layer 711 and the second gate conductive layer 721 are the same as those of the gate conductive layer 611 described above, so details are not described here. The materials of the second dielectric layer 722 and the first dielectric layer 712 can be the same or different.

[0068] As Figure 7 shown, the channel structure includes: a first sub-channel structure 730 and a second sub-channel structure 740. The first sub-channel structure 730 is disposed in the first sub-stacked layer 710 and extends in the vertical direction, and the second sub-channel structure 740 is disposed in the second sub-stacked layer 720 and extends in the vertical direction. The bottom of the second sub-channel structure 740 is in contact with the top of the first sub-channel structure 730, and the second sub-channel structure 740 is different from the first sub-channel structure 730.

[0069] Exemplarily, the first sub-channel structure 730 includes a first channel 731 and a memory film 732 surrounding the first channel 731. Exemplarily, the material of the first channel 731 includes silicon, such as polysilicon. The memory film 732 includes a tunneling layer 701, a charge trapping layer 702, and a blocking layer 703 sequentially arranged outward along the center of the first channel 731. Exemplarily, the memory film 732 may be a composite layer composed of silicon oxide / silicon oxynitride / silicon oxide (ONO). The second sub-channel structure 740 includes a second channel 741 and a gate oxide layer 742 surrounding the second channel 741. Exemplarily, the material of the second channel 741 includes silicon, such as polysilicon. The material of the gate oxide layer 742 includes silicon oxide, silicon oxynitride, high-k (high dielectric constant) dielectric, or any combination thereof.

[0070] The second sub-stack layer 720 and the second sub-channel structure 740 are used to form an upper select transistor and an upper select gate line. In some embodiments, a memory string may include multiple upper select transistors, and the multiple upper select transistors include: a coarse control upper select transistor (Coarse TSG), a buffer upper select transistor (Buffer TSG), and a fine control upper select transistor (Fine TSG). Among them, the coarse control upper select transistor is located in the second sub-stack layer 720, and the buffer upper select transistor and the fine control upper select transistor are located in the first sub-stack layer 710.

[0071] The memory cell array further includes an upper select gate cut line 750. The upper select gate cut line 750 extends vertically to cut the second gate conductive layer 721 into multiple regions. Each region is used to form a coarse control upper select gate line 761, and the coarse control upper select gate line 761 is coupled to the coarse control upper select transistor. The upper select gate cut line 750 may further extend to the first gate conductive layer 711 at the topmost of the first sub-stack layer 710 and cut it into multiple regions. Each region is used to form a buffer upper select gate line 762, and the buffer upper select gate line 762 is coupled to the buffer upper select transistor. The first gate conductive layer 711 at the second topmost of the first sub-stack layer 710 is used to form a fine control upper select gate line 763, and the fine control upper select gate line 763 is coupled to the fine control upper select transistor. The fine control upper select gate line 763 is not cut by the upper select gate cut line 750, and the fine control upper select gate line 763 is coupled to the fine control upper select transistors of all memory strings in an entire memory block.

[0072] Figure 6 In the shown memory cell array, the overlapping area of each upper select gate line 630 and word line 650 is a region of a memory block, that is Figure 6 the region circled by each dashed box. And Figure 7 in the shown memory cell array, the overlapping area of the fine control upper select gate line 763 and the word line 770 is the area of an entire memory block. Compared with Figure 6The positive area between the fine control upper select gate line 763 and the word line 770 is increased in precise control, so that the coupling capacitance between them is increased.

[0073] Figure 8 A circuit schematic diagram of a memory cell array provided by an embodiment of the present disclosure. Figure 9 A timing diagram of multiple signals in a programming operation of a memory provided by an embodiment of the present disclosure. The following will be combined with Figure 8 and Figure 9 to illustrate the process of the programming operation.

[0074] As Figure 8 shown, the memory cell array includes a plurality of memory strings 810. The upper end of each memory string 810 is connected to a bit line (BL) 820. Each memory string 810 includes a plurality of upper select transistors and a plurality of memory cells. In this embodiment, the plurality of upper select transistors include a coarse control upper select transistor 811, a buffer upper select transistor 812, and a fine control upper select transistor 813. Among them, the coarse control upper select transistor 811 is coupled to the coarse control upper select gate line 761, the buffer upper select transistor 812 is coupled to the buffer upper select gate line 762, and the fine control upper select transistor 813 is coupled to the fine control upper select gate line 763. The memory cells include dummy memory cells 814 and normal memory cells 815. The dummy memory cells 814 are coupled to a dummy word line (DMY WL) 771, and the normal memory cells 815 are coupled to a normal word line 772. The dummy word line 771 is located between the fine control upper select gate line 763 and the normal word line 772, and the dummy word line 771 is adjacent to the fine control upper select gate line 763.

[0075] In the programming operation, the row decoder / WL driver selects a normal word line according to the row address. The selected normal word line is called the selected word line (Sel WL); the column decoder / BL driver selects one or more bit lines according to the column address. The selected bit lines are called the selected bit lines. In the programming operation, the selected coarse control upper select gate line is called the selected coarse control gate select gate line. The fine control upper select gate line is coupled to all the fine control upper select transistors in an entire memory block, and a selection voltage is applied thereto in the programming operation to turn on the fine control upper select transistors.

[0076] As Figure 9 shown, during the programming process, a programming voltage (Vpgm) is applied to the selected word line (Sel WL). At the same time when the programming voltage is applied to the selected word line, a dummy voltage is applied to the dummy word line (DMY WL), a first selection voltage is applied to the selected coarse control upper select gate line (Coarse TSG), a second selection voltage is applied to the buffer upper select gate line (buffer TSG), and a third selection voltage is applied to the fine control upper select gate line (Fine TSG).

[0077] Exemplarily, as Figure 8As shown, the first selection voltage applied to the selection gate line of the selected coarse control during programming is 5V. The selected bit line is applied with a programming enable voltage, which is, for example, a ground voltage (0V). The memory string commonly coupled to the selection gate line of the selected coarse control and the selected bit line is the selected memory string. During programming, the unselected bit line is applied with a programming inhibit voltage, which is, for example, 2.2V. The memory string commonly coupled to the selection gate line of the unselected bit line and the selected coarse control is the unselected memory string. Since the first selection voltage applied to the selection gate line of the selected coarse control is relatively large, the difference between the first selection voltage and the programming inhibit voltage applied to the unselected bit line may be greater than the threshold voltage of the selection transistor on the coarse control, thus turning on the selection transistor on the coarse control of the unselected memory string and causing leakage of the unselected memory string. During programming, the third selection voltage applied to the selection gate line of the fine control is 3V, and the difference from the programming inhibit voltage applied to the unselected bit line is relatively small, which cannot turn on the selection transistor on the fine control. Therefore, the probability of leakage of the unselected memory string can be reduced.

[0078] Since the coupling capacitance between the selection gate line of the fine control and the dummy word line increases, the coupling effect of the dummy voltage applied to the dummy word line on the selection gate line of the fine control during the programming process increases, resulting in an instantaneous high voltage being coupled out on the selection gate line of the fine control. As Figure 8 shown, a voltage spike appears on the voltage of the selection gate line of the fine control after reaching the third selection voltage. Especially for the memory string far from the row decoder / WL driver, due to the influence of RC delay (resistance - capacitance delay), the voltage value of the voltage spike is larger.

[0079] During programming, since a voltage spike appears on the voltage of the selection gate line of the fine control, it may cause the voltage difference between the selection gate line of the fine control and the voltage of the unselected bit line at the moment of the voltage spike to be greater than the threshold voltage of the selection transistor on the fine control, causing leakage of the unselected memory string and making the programming crosstalk problem more serious.

[0080] To reduce the coupling effect of the dummy word line on the selection gate line of the fine control during programming and reduce programming crosstalk, an embodiment of the present disclosure also provides a memory, Figure 10 which is a schematic diagram of a memory provided by an embodiment of the present disclosure. As Figure 10 shown, the memory includes: a memory cell array 910, a plurality of upper selection gate lines 920, a plurality of word lines 930, and a peripheral circuit 940, where:

[0081] The memory cell array 910 includes a plurality of memory strings 911. The memory string 911 includes a plurality of upper selection transistors 912 and a plurality of memory cells 913. The plurality of upper selection transistors 912 are located on one side of the plurality of memory cells 913;

[0082] Multiple upper selection gate lines 920 are coupled to multiple upper selection transistors 912, and multiple word lines 930 are coupled to multiple memory cells 913;

[0083] An peripheral circuit 940, coupled to the upper selection gate lines 920 and the word lines 930, is configured to:

[0084] Apply a first pulse to a first word line 931 among the multiple word lines 930 to make the voltage of the first word line 931 reach a first target voltage at a first moment;

[0085] Apply a second pulse to a first upper selection gate line 921 adjacent to the first word line 931 among the multiple upper selection gate lines 920 to make the voltage of the first upper selection gate line 921 reach a second target voltage at a second moment; wherein, the second moment is later than the first moment.

[0086] As Figure 10 As shown, the memory cell array 910 includes multiple memory strings 911. The upper end of each memory string 911 is coupled to a bit line (BL) 950, and the lower end is coupled to an array common source (ACS) 960. The memory string 911 includes multiple upper selection transistors 912, multiple memory cells 913, and lower selection transistors 914 connected in series in sequence. The multiple memory strings 911 are arranged in an array along intersecting first and second directions, and the first and second directions intersect and are both perpendicular to the extending direction of the memory string. Exemplarily, the first direction is the X direction, the second direction is the Y direction, and the extending direction of the memory string 911 is the Z direction.

[0087] The multiple upper selection transistors of the memory string 911 include a first upper selection transistor 9121. The first upper selection transistor 9121 is adjacent to the memory cell 913, and the upper selection gate line coupled to the first upper selection transistor 9121 is a first upper selection gate line (TSG1) 921, and the first upper selection gate line 921 is adjacent to the word line 930. Here, the first upper selection transistor 9121 can be the above-mentioned precisely controlled upper selection transistor. The multiple upper selection transistors further include a second upper selection transistor 9122. The second upper selection transistor 9122 is far from the memory cell, and the multiple upper selection gate lines coupled to the second upper selection transistor 9122 are second upper selection gate lines (TSG21, TSG22... TSG2n) 922, and the second upper selection gate lines 922 are far from the word line 930. The second upper selection transistor 9122 can be the above-mentioned coarsely controlled upper selection transistor.

[0088] As Figure 10As shown, the second upper selection gate line 922 can extend along the first direction (X direction) and is coupled to the gates of the second upper selection transistors 9122 of multiple memory strings arranged in parallel along the first direction. The bit line 950 extends along the second direction (Y direction) and is coupled to the upper ends of multiple memory strings arranged in parallel along the second direction. By controlling the voltages applied to the bit line 950 and the second upper selection gate line 922, a certain memory string can be selected to perform a programming operation and a read operation on any memory cell in the selected memory string. The first upper selection gate line 921 extends in the plane where the first direction and the second direction are located, and is coupled to the first upper selection transistor 9121 in each memory string. The word line 930 also extends in the plane where the first direction and the second direction are located, and is coupled to the gate of a memory cell 913 in each memory string. Multiple word lines 930 are arranged in parallel along the extending direction (Z direction) of the memory string 911 to be coupled to multiple memory cells 913 in the memory string 911 in a one-to-one correspondence.

[0089] The multiple word lines 930 include a first word line 931 adjacent to the upper selection gate line. The first word line 931 is adjacent to the first upper selection gate line 921. Figure 11 This is a voltage timing diagram of the first word line and the first upper selection gate line in the programming operation provided by the embodiments of the present disclosure. As Figure 11 shown, during the programming process, a first pulse is applied to the first word line, and the voltage of the first word line reaches a first target voltage V1 at a first moment t1. Here, the first target voltage V1 is the peak voltage of the first pulse. A second pulse is applied to the first upper selection gate line adjacent to the first word line, and the voltage of the first upper selection gate line reaches a second target voltage V2 at a second moment t2. Here, the second target voltage V2 is the peak voltage of the second pulse. The second moment t2 is later than the first moment t1, so that when the voltage of the first word line reaches the first target voltage V1, the voltage of the first upper selection gate line is still a low voltage or on the rising edge from the low voltage to the second target voltage V2. The coupling effect of the voltage of the first word line on the first upper selection gate line will cause a voltage spike to appear in the voltage of the first upper selection gate line when it is at a low voltage or on the rising edge, rather than when the first upper selection gate line is at the second target voltage V2, reducing the voltage value of the voltage spike. The difference between the voltage value of the voltage spike and the voltage value of the bit line is not sufficient to turn on the first upper selection transistor, thereby reducing the probability that an unselected memory string is turned on, and further reducing the probability of programming crosstalk occurring.

[0090] To make the second moment t2 later than the first moment t1, in some embodiments, as Figure 11 shown, the peripheral circuit is configured as:

[0091] At a third moment t3, a first pulse is applied to the first word line;

[0092] At a fourth time t4, a second pulse is applied to the first upper selection gate line; wherein, the fourth time t4 is later than the third time t3.

[0093] As Figure 11 shown, the third time t3 is the starting time of the first pulse, the first time t1 is the time when the first pulse reaches its peak voltage. The process of the first pulse rising from the start to its peak voltage is called the rising edge of the first pulse. The time period between the third time t3 and the first time t1 is the duration of the rising edge of the first pulse, which can also be called the rise time of the first pulse. Starting from the third time t3, the voltage of the first word line changes from a low voltage to a first target voltage V1. After a period of time, at the first time t1, the voltage of the first word line reaches the first target voltage V1.

[0094] The fourth time t4 is the starting time of the second pulse, the second time t2 is the time when the second pulse reaches its peak voltage. The process of the second pulse rising from the start to its peak voltage is called the rising edge of the second pulse. The time period between the fourth time t4 and the second time t2 is the duration of the rising edge of the second pulse, which can also be called the rise time of the second pulse. Starting from the fourth time t4, the voltage of the first upper selection gate line changes from a low voltage to a second target voltage V2. After a period of time, at the second time t2, the voltage of the first upper selection gate line reaches the second target voltage V2.

[0095] In this embodiment, the fourth time t4 is later than the third time t3, and the duration of the rising edge of the second pulse can be less than or equal to the duration of the rising edge of the first pulse, so as to ensure that the second time t2 when the first upper selection gate line reaches the second target voltage V2 is later than the first time t1 when the first word line reaches the first target voltage V1, thereby improving the programming crosstalk caused by the leakage of unselected memory strings.

[0096] To make the second time t2 later than the first time t1, in another embodiment, the peripheral circuit is configured to:

[0097] At the same time when the first pulse is applied to the first word line, a second pulse is applied to the first upper selection gate line; the duration of the rising edge of the second pulse is greater than the duration of the rising edge of the first pulse.

[0098] As Figure 12As shown, at the same moment, for example, the third moment t3, a first pulse is applied to the first word line, and a second pulse is applied to the first upper select gate line. Since the duration of the rising edge of the second pulse is greater than that of the rising edge of the first pulse, when the first word line reaches the first target voltage V1 at the first moment t1, the voltage of the first upper select gate line is still in the rising edge stage and has not reached the second target voltage V2. At this time, due to the coupling effect of the voltage of the first word line, a voltage spike may occur on the first upper select gate line during the rising edge stage, reducing the voltage value of the voltage spike of the first upper select gate line, thereby reducing the probability of leakage in the unselected memory string, and further improving the programming crosstalk problem caused by the leakage of the unselected memory string. The voltage of the first upper select gate line reaches the second target voltage V2 at the second moment t2 after the first moment t1.

[0099] To make the duration of the rising edge of the second pulse greater than that of the rising edge of the first pulse, in some embodiments, as Figure 12 shown, the rising edge of the first pulse has a first slope K1, and the rising edge of the second pulse has a second slope K2, where the second slope K2 is less than the first slope K1.

[0100] The rising edge of the first pulse has a first slope K1, that is, the voltage of the first word line linearly changes with time to the first target voltage V1. The rising edge of the second pulse has a second slope K2, that is, the voltage of the first upper select gate line linearly changes with time to the second target voltage V2. In this embodiment, since the second slope K2 is less than the first slope K1, it means that the voltage of the first upper select gate line changes more slowly, which can make the time required for the first upper select gate line to reach the second target voltage V2 longer. Therefore, the second moment t2 when the second upper select gate line reaches the second target voltage V2 is later than the first moment t1 when the first word line reaches the first target voltage V1. Exemplarily, the second target voltage V2 can be greater than, equal to, or slightly less than the first target voltage V1.

[0101] In some embodiments, as Figure 13 shown, the rising edge of the first pulse corresponding to the first word line has a first slope K1, and the second pulse corresponding to the first upper select gate line is in a stepped waveform, where the rising edge of the second pulse includes multiple steps.

[0102] The second pulse being in a stepped waveform means that the voltage of the second pulse rises to the second target voltage V2 in multiple steps. In each step, the voltage of the second pulse first increases to a stage voltage and stays at the stage voltage for a period of time before continuing to increase, making the rising edge of the second pulse in a stepped shape. Exemplarily, as Figure 13 shown, the rising edge of the second pulse includes two steps, and the voltage of the second pulse can first increase to the stage voltage V ST, after staying at the stage target voltage for a period of time, it continues to increase to the second target voltage V2. The voltage of the second pulse is the voltage of the first upper selection gate line. In this embodiment, by increasing the voltage of the first upper selection gate line step by step in multiple steps, the voltage of the first upper selection gate line can be increased to the second target voltage V2, which can extend the duration of the rising edge of the second upper selection gate line, so that the voltage of the first upper selection gate line reaches the second target voltage V2 later, and further makes the second moment t2 when the first upper selection gate line reaches the second target voltage V2 later than the first moment t1 when the first word line reaches the first target voltage V1. Exemplarily, the slope of the sub-rising edge of each step of the second pulse is equal to or less than the first slope K1. It should be understood that the slope of the sub-rising edge of at least one step of the second pulse can also be greater than the first slope K1, and the voltage of the first upper selection gate line can reach the second target voltage V2 later by extending the residence time at the stage voltage.

[0103] It should be understood that in some embodiments, Figure 11 and Figure 12 the methods adopted can also be combined, or Figure 11 and Figure 13 the methods adopted can be combined. That is: both making the fourth moment t4 when applying the second pulse to the first upper selection gate line later than the third moment t3 when applying the first pulse to the first word line, and making the duration of the rising edge of the second pulse longer than the duration of the rising edge of the first pulse, so that the second moment t2 when the first upper selection gate line reaches the second target voltage V2 is later than the first moment t1 when the first word line reaches the first target voltage V1, and further improving the programming crosstalk problem caused by the leakage of unselected memory strings.

[0104] Return to refer to Figure 9 , in some embodiments, the multiple word lines 930 include dummy word lines DMY WL and normal word lines WL, and the dummy word lines DMY WL are located between the normal word lines WL and the first upper selection gate line 921. The number of dummy word lines DMY WL can be one or multiple. Among them, the first word line 931 is a dummy word line DMY WL adjacent to the upper selection gate line 920. The multiple memory cells 913 include dummy memory cells 9131 and normal memory cells 9132, the dummy word lines DMY WL are coupled to the dummy memory cells 9131, and the normal word lines WL are coupled to the normal memory cells 9132.

[0105] One of the functions of the dummy memory cells coupled to the dummy word lines 9131 is to protect the normal memory cells 9132 coupled to the normal word lines at the edge, so that the normal memory cells at the edge have the same surrounding environment as other normal memory cells, so as to improve the accuracy of accessing data by the normal memory cells at the edge. The dummy memory cells are not used for storing data, and the data is stored in the normal memory cells.

[0106] In some embodiments, as Figure 10 and Figure 14 shown, during a programming operation, the peripheral circuit is further configured to:

[0107] Apply a third pulse to a second word line 932 among multiple normal word lines, so that the second word line reaches a third target voltage at a fifth moment t5; wherein, the fifth moment t5 is not earlier than the second moment t2.

[0108] Here, the fifth moment t5 is not earlier than the second moment t2, including that the fifth moment t5 is simultaneous with the second moment t2, or the fifth moment t5 is later than the second moment t2.

[0109] The second word line 932 is a selected word line (Sel WL) among multiple normal word lines, and the normal memory cell coupled to the second word line 932 is used to store data during a programming operation. The second word line is applied with the third pulse and reaches the third target voltage at the fifth moment t5. Here, the third target voltage is the peak voltage of the third pulse, that is, the programming voltage V pgm . The voltage of the second word line reaches the programming voltage V pgm . After that, electrons can be trapped into the charge trapping layer, thereby performing data storage.

[0110] The voltage of the second word line 932 reaches the programming voltage V pgm at the fifth moment t5. The fifth moment t5 is not earlier than the second moment t2, that is, at the same time as or after the voltage of the first word line 931 reaches the first target voltage V1 and the voltage of the first upper select gate line 921 reaches the second target voltage V2, the voltage of the second word line 932 reaches the programming voltage V pgm . This is because the voltage of the first upper select gate line 921 determines which memory strings are selected and which are not. After determining the selected memory strings, the voltage of the second word line 932 reaches the programming voltage V pgm , which can avoid programming crosstalk caused by unselected memory strings being programmed.

[0111] In some embodiments, the peripheral circuit is configured to:

[0112] Apply the third pulse to the second word line at the same moment as applying the first pulse to the first word line, or at the same moment as applying the second pulse to the first upper select gate line; wherein, the duration of the rising edge of the third pulse is greater than the duration of the rising edge of the second pulse.

[0113] In an example, as Figure 14As shown, at the third moment t3, a first pulse is applied to the first word line, and at the same time, a third pulse is applied to the second word line. At the fourth moment t4 after the third moment t3, a second pulse is applied to the first upper selection gate line. Here, the process in which the third pulse rises from the start to its peak voltage (i.e., the programming voltage V pgm ) is called the rising edge of the third pulse. The time period between the third moment t3 and the fifth moment t5 is the duration of the rising edge of the third pulse, which can also be referred to as the rise time of the third pulse. Exemplarily, as Figure 14 shown, the third pulse can be in a stepped waveform.

[0114] Since the duration of the rising edge of the third pulse is much greater than the duration of the rising edge of the second pulse, although the moment when the third pulse is applied to the second word line is earlier than the moment when the second pulse is applied to the first upper selection gate line, the fifth moment t5 when the second word line reaches the third target voltage (i.e., the programming voltage V pgm ) can be simultaneous with or later than the second moment t2 when the first upper selection gate line reaches the second target voltage V2.

[0115] In another example, as Figure 15 shown, at the third moment t3, a first pulse is applied to the first word line; at the fourth moment t4 after the third moment t3, a second pulse is applied to the first upper selection gate line, and at the same time, a third pulse is applied to the second word line. Since the duration of the rising edge of the third pulse is greater than the duration of the rising edge of the second pulse, the fifth moment t5 when the second word line reaches the third target voltage is later than the second moment t2 when the first upper selection gate line reaches the second target voltage V2. In yet another example, when the second pulse is applied to the first upper selection gate line and the third pulse is applied to the second word line simultaneously, if the duration of the rising edge of the third pulse is equal to the duration of the rising edge of the second pulse, the fifth moment t5 when the second word line reaches the third target voltage can be equal to the second moment t2 when the first upper selection gate line reaches the second target voltage V2.

[0116] In still other examples, as Figure 16 and Figure 17 shown, at the same moment, for example, the third moment t3, a first pulse is applied to the first word line, a second pulse is applied to the first upper selection gate line, and a third pulse is applied to the second word line, and the third pulse is in a stepped waveform. Since the duration of the rising edge of the second pulse is greater than the duration of the rising edge of the first pulse and less than the duration of the rising edge of the third pulse, the second moment t2 is later than the first moment t1, and the fifth moment t5 is later than the second moment t2. The specific form of the second pulse is not limited in this disclosure.

[0117] Exemplarily, as Figure 16As shown, the second slope K2 of the rising edge of the second pulse is less than the first slope K1 of the rising edge of the first pulse, such that the rising edge of the second pulse is staggered from the rising edge of the first pulse, and the rising edge of the second pulse changes more slowly, so that the second time t2 is later than the first time t1. The third pulse has a stepped waveform, and the rising edge of the third pulse includes multiple steps, which can extend the duration of the rising edge of the third pulse, and further make the fifth time t5 not earlier than the second time t2.

[0118] Also, by way of example, as Figure 17 shown, the second pulse applied to the first upper selection gate line and the third pulse applied to the second word line can both be stepped waveforms, but the duration of the rising edge of the third pulse can be equal to or greater than the duration of the rising edge of the second pulse, so that the fifth time t5 is not earlier than the second time t2.

[0119] Return to refer to Figure 10 , a plurality of upper selection transistors 912 in the memory string include a first upper selection transistor 9121 and a second upper selection transistor 9122. The first upper selection transistor 9121 is close to the dummy memory cell 9131, and the second upper selection transistor 9122 is far from the dummy memory cell 9131; wherein, the first upper selection gate line 921 extends along the first direction and the second direction and is coupled to the first upper selection transistor 9121 of each of the plurality of memory strings, in other words, the first upper selection gate line 921 is coupled to the first upper selection transistor 9121 of each of all the memory strings in an entire memory block. The second upper selection gate line 922 can extend along the first direction (X direction) and is coupled to the second upper selection transistors of a plurality of memory strings arranged side by side along the first direction; a plurality of second upper selection gate lines 922 are arranged side by side along the second direction (Y direction).

[0120] During the programming process, as Figures 14 to 17 shown, the peripheral circuit is further configured to:

[0121] Apply a fourth pulse to the selected second upper selection gate line among the plurality of second upper selection gate lines 922, so that the selected second upper selection gate line reaches the fourth target voltage V4 at the sixth time t6; wherein, the sixth time t6 is not later than the second time t2, and the fourth target voltage V4 is greater than the second target voltage V2.

[0122] Here, the fourth target voltage V4 is the peak voltage of the fourth pulse. In order to make the sixth time t6 not later than the second time t2, in some embodiments, as Figure 14 , Figure 16 and Figure 17As shown, at the same time when a first pulse is applied to the first word line, for example, at the third time t3, a fourth pulse is applied to the selected second upper selection gate line; wherein, the duration of the rising edge of the fourth pulse is equal to the duration of the rising edge of the first pulse, such that the sixth time t6 when the selected second upper selection gate line reaches the fourth target voltage V4 is the same as the first time t1 when the first word line reaches the first target voltage V1, and both are earlier than the second time t2.

[0123] In some other embodiments, as Figure 15 shown, at the same time when a second pulse is applied to the first upper selection gate line, a fourth pulse is applied to the selected second upper selection gate line; wherein, the duration of the rising edge of the fourth pulse is equal to the duration of the rising edge of the second pulse, such that the sixth time t6 when the selected second upper selection gate line reaches the fourth target voltage V4 is the same as the second time t2 when the first upper selection gate line reaches the second target voltage V2.

[0124] In this embodiment, the fourth target voltage V4 of the selected second upper selection gate line is greater than the second target voltage V2 of the first upper selection gate line. During programming, a larger fourth target voltage V4, for example 5V, is applied to the selected second upper selection gate line; a programming enable voltage, for example a ground voltage (0V), is applied to the selected bit line; and the memory string coupled to the selected second upper selection gate line and the selected bit line is the selected memory string. During programming, a programming inhibit voltage, for example 2.2V, is applied to the unselected bit line; and the memory string coupled to the selected second upper selection gate line and the unselected bit line is the unselected memory string.

[0125] During programming, since the fourth target voltage V4 of the selected second upper selection gate line is large, the difference between it and the programming inhibit voltage of the unselected bit line may be greater than the threshold voltage of the second upper selection transistor, resulting in possible leakage of the unselected memory string. And during programming, the second target voltage applied to the first upper selection gate line is small, for example 3V, and the difference between the second target voltage and the voltage of the unselected bit line is small, which cannot turn on the first upper selection transistor. Therefore, the probability of leakage of the unselected memory string can be reduced.

[0126] In addition, the cooperation of the first upper selection gate line and the second upper selection gate line can achieve selecting one-half page or one-quarter page from the selected page for programming, enriching the programming method.

[0127] In some embodiments, the multiple upper selection transistors further include a third upper selection transistor, which is located between the first upper selection transistor and the second upper selection transistor, and the third upper selection transistor is coupled to a third upper selection gate line. The third upper selection gate line can be [[ID= / / 18]] Figure 7The topmost first gate conductive layer in the first sub-stack layer, the third upper selection transistor is, for example, the above-mentioned buffer top selection transistor (buffer TSG), and the third upper selection gate line correspondingly is the buffer top selection gate line. The third upper selection gate line plays a buffering role in the process. Specifically, as Figure 7 shown, the upper selection gate cut line 750 may extend from the second sub-stack layer 720 to the first sub-stack layer 710 and may damage the first sub-channel structure 730. If the topmost first gate conductive layer 711 in the first sub-stack layer 710 is used to form the first upper selection gate line, then the damaged channel structure affects the performance of the first upper selection transistor. Therefore, a third upper selection gate line is provided on the first upper selection gate line to play a buffering role in the process to ensure the normal functions of the first upper selection gate line and the first upper selection transistor.

[0128] As Figures 14 to 17 shown, a fifth pulse is applied to the third upper selection gate line, and the moment when the fifth pulse is applied to the third upper selection gate line is the same as the moment when the fourth pulse is applied to the selected second upper selection gate line, and the moment when the third upper selection gate line reaches the fifth target voltage V5 is also the same as the sixth moment t6 when the selected second upper selection gate line reaches the fourth target voltage V4.

[0129] Exemplarily, the fifth target voltage V5 is equal to the second target voltage V2. For example, both the fifth target voltage V5 and the second target voltage V2 are 3V.

[0130] Exemplarily, the first target voltage is greater than 3V.

[0131] When the memory provided by the embodiment of the present disclosure performs a programming operation, a first pulse is applied to a first word line adjacent to the upper selection gate line among multiple word lines, and a second pulse is applied to a first upper selection gate line adjacent to the first word line among multiple upper selection gate lines. Among them, the second moment when the first upper selection gate line reaches the second target voltage is later than the first moment when the first word line reaches the first target voltage. In other words, when the first word line reaches the first target voltage at the first moment, the first upper selection gate line may not have been applied with the second pulse yet, or the voltage of the first upper selection gate line is still in the rising edge stage and has not reached the second target voltage. At this time, due to the coupling effect of the voltage of the first word line, the first upper selection gate line may have a voltage spike before or during the rising edge stage. Since the voltage value of the voltage spike that appears at this time is small, and may even be less than the second target voltage, the probability of leakage of unselected memory strings can be reduced, and thus the programming crosstalk problem caused by the leakage of unselected memory strings can be improved.

[0132] The embodiment of the present disclosure also provides a method for operating a memory, Figure 18Schematic flow diagram of the operation method of the memory provided by the embodiments of the present disclosure. The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory strings, and each memory string includes a plurality of memory cells and a plurality of upper selection transistors located on one side of the plurality of memory cells; a plurality of word lines are coupled to the plurality of memory cells, and a plurality of upper selection gate lines are coupled to the plurality of upper selection transistors;

[0133] As Figure 18 shown, the operation method includes:

[0134] Step S100: Apply a first pulse to a first word line adjacent to the upper selection gate line among the plurality of word lines, so that the voltage of the first word line reaches a first target voltage at a first moment;

[0135] Step S200: Apply a second pulse to a first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines, so that the voltage of the first upper selection gate line reaches a second target voltage at a second moment; wherein, the second moment is later than the first moment.

[0136] In some embodiments, step S100 includes: applying a first pulse to the first word line at a third moment;

[0137] Step S200 includes: applying a second pulse to the first upper selection gate line at a fourth moment; wherein, the fourth moment is later than the third moment to achieve that the second moment is later than the first moment.

[0138] In some embodiments, step S200 includes: applying a second pulse to the first upper selection gate line at the same moment when the first pulse is applied to the first word line; wherein, the duration of the rising edge of the second pulse is greater than the duration of the rising edge of the first pulse to achieve that the second moment is later than the first moment.

[0139] In some embodiments, in step S100, the rising edge of the first pulse applied to the first word line has a first slope;

[0140] Step S200 includes: applying a second pulse to the first upper selection gate line, and the rising edge of the second pulse has a second slope; wherein, the second slope is less than the first slope to achieve that the duration of the rising edge of the second pulse is greater than the duration of the rising edge of the first pulse, and further achieve that the second moment is later than the first moment.

[0141] In some embodiments, in step S100, the rising edge of the first pulse applied to the first word line has a first slope;

[0142] Step S200 includes: applying a second pulse with a stepped waveform to the first upper select gate line; wherein, the rising edge of the second pulse includes multiple levels of steps to enable the duration of the rising edge of the second pulse to be greater than the duration of the rising edge of the first pulse, thereby enabling the second moment to be later than the first moment.

[0143] In some embodiments, the word line includes a normal word line and a dummy word line located between the normal word line and the upper select gate line; the first word line is a dummy word line adjacent to the upper select gate line;

[0144] The operation method further includes: applying a third pulse to a second word line among multiple normal word lines to enable the second word line to reach a third target voltage at a fifth moment; wherein, the fifth moment is not earlier than the second moment.

[0145] In some embodiments, applying the third pulse to the second word line among multiple normal word lines includes:

[0146] Applying the third pulse to the second word line at the same moment as applying the first pulse to the first word line, or at the same moment as applying the second pulse to the first upper select gate line; wherein, the duration of the rising edge of the third pulse is greater than the duration of the rising edge of the second pulse to enable the fifth moment to be not earlier than the second moment.

[0147] In some embodiments, multiple upper select transistors in the memory string include a first upper select transistor and a second upper select transistor, the first upper select gate line is coupled to the first upper select transistor of each of the multiple memory strings; the upper select gate line further includes multiple second upper select gate lines, which are coupled to the second upper select transistors of the multiple memory strings, and different second upper select gate lines are coupled to the second upper select transistors of different memory strings;

[0148] The operation method further includes:

[0149] Applying a fourth pulse to a selected second upper select gate line among multiple second upper select gate lines to enable the selected second upper select gate line to reach a fourth target voltage at a sixth moment; wherein, the sixth moment is not later than the second moment, and the fourth target voltage is greater than the second target voltage.

[0150] In some embodiments, applying the fourth pulse to the selected second upper select gate line among multiple second upper select gate lines includes: applying the fourth pulse to the selected second upper select gate line at the same moment as applying the first pulse to the first word line; wherein, the duration of the rising edge of the fourth pulse is equal to the duration of the rising edge of the first pulse to enable the sixth moment to be earlier than the second moment.

[0151] In some embodiments, applying a fourth pulse to the selected second upper selection gate lines among multiple second upper selection gate lines may also include: applying the fourth pulse to the selected second upper selection gate lines at the same time as applying the second pulse to the first upper selection gate line; wherein, the duration of the rising edge of the fourth pulse is equal to or less than the duration of the rising edge of the second pulse, so as to achieve that the sixth moment is earlier than the second moment.

[0152] For the operation method of the memory provided by the embodiments of the present disclosure, a first pulse is applied to the first word line adjacent to the upper selection gate line among multiple word lines, and a second pulse is applied to the first upper selection gate line adjacent to the first word line among multiple upper selection gate lines. Among them, the second moment when the first upper selection gate line reaches the second target voltage is later than the first moment when the first word line reaches the first target voltage, which can avoid the voltage spike of the first upper selection gate line due to the coupling effect of the voltage of the first word line when it is at the second target voltage, thereby reducing the voltage value of the voltage spike and reducing the probability of leakage of non-selected memory strings, and further improving the programming crosstalk problem caused by the leakage of unselected memory strings.

[0153] Regarding the method in the above embodiments, its specific implementation method has been described in detail in the embodiments of the product corresponding to the method, and will not be elaborated here.

[0154] The embodiments of the present disclosure further provide a memory system, which includes a memory and a memory controller coupled to the memory and used to control the memory. The memory is any of the above memories and is used to implement the programming operation method provided by the embodiments of the present disclosure.

[0155] As mentioned above, it is only the implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory, characterized in that, The memory includes: A memory cell array including a plurality of memory strings, each memory string including a plurality of upper selection transistors and a plurality of memory cells, and the plurality of upper selection transistors being located on one side of the plurality of memory cells; A plurality of upper selection gate lines coupled to the plurality of upper selection transistors; A plurality of word lines coupled to the plurality of memory cells; A peripheral circuit coupled to the plurality of upper selection gate lines and the plurality of word lines, and configured to: Apply a first pulse to a first word line among the plurality of word lines to cause the voltage of the first word line to reach a first target voltage at a first moment; Apply a second pulse to a first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines to cause the voltage of the first upper selection gate line to reach a second target voltage at a second moment; wherein, the second moment is later than the first moment.

2. The memory according to claim 1, wherein The peripheral circuit is configured to: at a third moment, apply the first pulse to the first word line; At a fourth moment, apply the second pulse to the first upper selection gate line; wherein, the fourth moment is later than the third moment.

3. The memory according to claim 1, wherein The peripheral circuit is configured to: At the same moment when the first pulse is applied to the first word line, apply the second pulse to the first upper selection gate line; the duration of the rising edge of the second pulse is greater than the duration of the rising edge of the first pulse.

4. The memory according to claim 3, wherein The rising edge of the first pulse has a first slope, and the rising edge of the second pulse has a second slope; Wherein, the second slope is less than the first slope.

5. The memory according to claim 3, characterized in that, The second pulse has a stepped waveform, wherein the rising edge of the second pulse includes multiple steps.

6. The memory according to any one of claims 1 to 3, characterized in that, The word lines include dummy word lines and normal word lines, and the dummy word lines are located between the normal word lines and the upper selection gate lines; the first word line is the dummy word line adjacent to the upper selection gate line; The peripheral circuit is further configured to: Apply a third pulse to a second word line among the plurality of normal word lines to cause the second word line to reach a third target voltage at a fifth moment; wherein, the fifth moment is not earlier than the second moment.

7. The memory according to claim 6, wherein The peripheral circuit is configured to: At the same moment when the first pulse is applied to the first word line, or at the same moment when the second pulse is applied to the first upper selection gate line, apply the third pulse to the second word line; wherein, the duration of the rising edge of the third pulse is greater than the duration of the rising edge of the second pulse.

8. The memory according to any one of claims 1 to 3, characterized in that, The plurality of upper selection transistors in the memory string include a first upper selection transistor and a second upper selection transistor, and the first upper selection gate line is coupled to the first upper selection transistor of each of the plurality of memory strings; The upper selection gate lines further include a plurality of second upper selection gate lines, which are coupled to the second upper selection transistors in the plurality of memory strings, and different second upper selection gate lines are coupled to the second upper selection transistors of different memory strings; the peripheral circuit is further configured to: Apply a fourth pulse to a selected second upper selection gate line among the plurality of second upper selection gate lines to cause the selected second upper selection gate line to reach a fourth target voltage at a sixth moment; wherein, the sixth moment is not later than the second moment, and the fourth target voltage is greater than the second target voltage.

9. The memory according to claim 8, wherein, The peripheral circuit is configured to: At the same time as applying the first pulse to the first word line, a fourth pulse is applied to the selected second upper selection gate line; wherein, the duration of the rising edge of the fourth pulse is equal to the duration of the rising edge of the first pulse; or, At the same time as applying the second pulse to the first upper selection gate line, a fourth pulse is applied to the selected second upper selection gate line; wherein, the duration of the rising edge of the fourth pulse is equal to or less than the duration of the rising edge of the second pulse.

10. A memory system, characterized in that, The memory system includes: The memory according to any one of claims 1 to 9; and A memory controller coupled to the memory and configured to control the memory.

11. A method for operating a memory, characterized in that, The memory includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes a plurality of memory strings, and each memory string includes a plurality of memory cells and a plurality of upper selection transistors located on one side of the plurality of memory cells; A plurality of word lines are coupled to the plurality of memory cells, and a plurality of upper selection gate lines are coupled to the plurality of upper selection transistors; The operation method includes: Applying a first pulse to a first word line among the plurality of word lines to make the voltage of the first word line reach a first target voltage at a first moment; Applying a second pulse to a first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines to make the voltage of the first upper selection gate line reach a second target voltage at a second moment; wherein, the second moment is later than the first moment.

12. The operation method of the memory according to claim 11, wherein Applying the first pulse to the first word line adjacent to the first upper selection gate line among the plurality of word lines includes: applying the first pulse to the first word line at a third moment; Applying the second pulse to the first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines includes: applying the second pulse to the first upper selection gate line at a fourth moment; wherein, the fourth moment is later than the third moment.

13. The method for operating a memory according to claim 11, wherein Applying the second pulse to the first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines includes: Applying the second pulse to the first upper selection gate line at the same time as applying the first pulse to the first word line; wherein, the duration of the rising edge of the second pulse is greater than the duration of the rising edge of the first pulse.

14. The method for operating a memory according to claim 13, wherein, The rising edge of the first pulse has a first slope; Applying the second pulse to the first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines includes: Applying a second pulse with a rising edge having a second slope to the first upper selection gate line; wherein, the second slope is less than the first slope.

15. The method for operating a memory according to claim 13, wherein Applying the second pulse to the first upper selection gate line adjacent to the first word line among the plurality of upper selection gate lines includes: Applying a second pulse having a stepped waveform to the first upper selection gate line; wherein, the rising edge of the second pulse includes multiple steps.

16. The method for operating a memory according to claim 12 or 13, characterized in that, The word line includes a normal word line and a dummy word line located between the normal word line and the upper selection gate line; The first word line is the dummy word line adjacent to the upper selection gate line; The operation method further includes: Applying a third pulse to a second word line among the multiple normal word lines, so that the second word line reaches a third target voltage at a fifth moment; wherein, the fifth moment is not earlier than the second moment.

17. The method for operating a memory according to claim 16, characterized in that, The applying the third pulse to the second word line among the multiple normal word lines includes: Applying the third pulse to the second word line at the same moment when applying the first pulse to the first word line, or at the same moment when applying the second pulse to the first upper selection gate line; wherein, the duration of the rising edge of the third pulse is greater than the duration of the rising edge of the second pulse.

18. The method for operating a memory according to claim 12 or 13, characterized in that, The multiple upper selection transistors in the memory string include a first upper selection transistor and a second upper selection transistor. The first upper selection gate line is coupled to the first upper selection transistor of each of the multiple memory strings; the upper selection gate line further includes multiple second upper selection gate lines, which are coupled to the second upper selection transistors of the multiple memory strings, and different second upper selection gate lines are coupled to the second upper selection transistors of different memory strings; The operation method further includes: Applying a fourth pulse to a selected second upper selection gate line among the multiple second upper selection gate lines, so that the selected second upper selection gate line reaches a fourth target voltage at a sixth moment; wherein, the sixth moment is not later than the second moment, and the fourth target voltage is greater than the second target voltage.

19. The method for operating a memory according to claim 18, wherein The applying the fourth pulse to the selected second upper selection gate line among the multiple second upper selection gate lines includes: Applying the fourth pulse to the selected second upper selection gate line at the same moment when applying the first pulse to the first word line; wherein, the duration of the rising edge of the fourth pulse is equal to the duration of the rising edge of the first pulse; or, Applying the fourth pulse to the selected second upper selection gate line at the same moment when applying the second pulse to the first upper selection gate line; wherein, the duration of the rising edge of the fourth pulse is equal to or less than the duration of the rising edge of the second pulse.

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