Chip with alignment key and packaging structure using same
By using aligning keys in integrated circuit packaging, the problems of limited packaging density and inaccurate pattern alignment in lithography processes are solved, and efficient packaging density and bonding yield are achieved.
Patent Information
- Application Number
- CN202410223734.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-01
- Filing Date
- 2024-02-28
- Publication Date
- 2025-08-01
AI Technical Summary
The prior art has problems in integrated circuit packaging that the packaging density is limited by the area of the bonding region and the overall height, and inaccurate pattern alignment in the lithography process leads to a decrease in bonding yield.
Using a chip design with alignment keys, by setting alignment keys on the substrate, using infrared lenses for precision alignment, and retaining non-metallic areas on the chip and wafer to avoid lithography errors, metal alignment keys are used to penetrate the substrate to ensure accurate alignment and reduce space waste.
It improves the packaging density, reduces space waste, ensures accurate alignment of chips and wafers, avoids inaccurate pattern alignment in the lithography process, and improves bonding yield.
Smart Images
Figure CN120413461A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a chip having alignment keys and a packaging structure using the chip. Background Art
[0002] In order to meet the requirements of high efficiency and reduced production costs, how to simplify the number of components and achieve higher packaging density has become the goal of the electronics industry. In the field of integrated circuit packaging, the density of integrated circuit packaging is mainly limited by the area of the region used as the bonding area and the overall height of the integrated circuit packaging. Three-dimension package technology is one of the methods used to increase the density of integrated circuit packaging. Summary of the Invention
[0003] An embodiment of the present disclosure provides a chip, including a device area disposed on a substrate, a corner area disposed at a corner of the substrate, a sealing ring surrounding the device area, a dicing street area surrounding the sealing ring and the corner area, and alignment keys. The sealing ring includes a corner segment adjacent to the corner area. The alignment keys are disposed adjacent to the sealing ring.
[0004] In some embodiments, the sealing ring includes a plurality of edge segments connected by the corner segment, the angle between the corner segment and the edge segment is greater than 90 degrees, and the alignment keys are disposed in the corner area or the dicing street area.
[0005] In some embodiments, the chip further includes a stress relief area, wherein the stress relief area and the corner area are respectively located on opposite sides of the corner segment, and the alignment keys are disposed in the stress relief area.
[0006] In some embodiments, the chip further includes an inner spacer disposed between the device area and the sealing ring, wherein the alignment keys are disposed in the inner spacer.
[0007] In some embodiments, the chip further includes an outer spacer disposed between the sealing ring and the dicing street area, wherein the alignment keys are disposed in the outer spacer.
[0008] In some embodiments, the chip further includes an outer spacer disposed between the sealing ring and the dicing street area, wherein half of the alignment keys are disposed in the outer spacer and the other half are disposed in the dicing street area.
[0009] Another embodiment of the present disclosure provides a chip, including a substrate having an upper surface and a lower surface, and alignment keys disposed in the substrate. The alignment keys continuously extend from the upper surface to the lower surface in a single direction. The material of the alignment keys is metal, and the alignment keys are isolated from the inner connection metal layer.
[0010] In some embodiments, the alignment key includes a triangular pattern, a spiral pattern, or a stripe pattern.
[0011] In some embodiments, the alignment key includes a plurality of dot-shaped vias, and the dot-shaped vias form a triangular pattern, a spiral pattern, or a stripe pattern.
[0012] Another embodiment of the present disclosure provides a packaging structure, including a first device and a second device bonded to the first device. The first device includes a first alignment key disposed on the upper surface of the first device. The second device includes a second alignment key disposed on the lower surface of the second device, wherein in a plan view, a plurality of spacings between the first alignment key and the second alignment key are the same, and these spacings are measured in at least two directions.
[0013] In some embodiments, the second alignment key continuously extends from the lower surface of the second device to the upper surface of the second device in a single direction.
[0014] In some embodiments, the second device includes another second alignment key disposed on an upper surface of the second device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] To make the objectives, features, advantages, and embodiments of the present disclosure more obvious and understandable, the detailed description of the accompanying drawings is as follows:
[0016] Figure 1 A partial enlarged view of some embodiments of a chip with an alignment key according to the present disclosure.
[0017] Figure 2 A partial enlarged view of some embodiments of a chip with an alignment key according to the present disclosure.
[0018] Figure 3 A partial enlarged view of some embodiments of a chip with an alignment key according to the present disclosure.
[0019] Figure 4 A partial enlarged view of some embodiments of a wafer of a chip with an alignment key according to the present disclosure.
[0020] Figure 5 A partial enlarged view of some embodiments of a wafer of a chip with an alignment key according to the present disclosure.
[0021] Figure 6 A partial enlarged view of some embodiments of a wafer of a chip with an alignment key according to the present disclosure.
[0022] Figure 7 A cross-sectional schematic view of some embodiments of a chip with an alignment key according to the present disclosure.
[0023] Figure 8 AndFigure 9 Top views of different embodiments of the alignment keys in Figure 7 respectively.
[0024] Figure 10A Schematic cross-sectional views of some embodiments of the encapsulation structure of the present disclosure.
[0025] Figures 10B to 10D Top views of different embodiments of the alignment keys in Figure 10A respectively.
[0026] Figure 11A Schematic cross-sectional views of some embodiments of the encapsulation structure of the present disclosure.
[0027] Figures 11b to Figure 11D Top views of different embodiments of the alignment keys in Figure 11A respectively.
[0028] Figure 12A Schematic cross-sectional views of some embodiments of the encapsulation structure of the present disclosure.
[0029] Figures 12B to 12D Top views of different embodiments of the alignment keys in Figure 12A respectively.
[0030] Figure 13A Settings of traditional paired alignment keys and their corresponding detection signals.
[0031] Figure 13B Settings of traditional paired alignment keys that encounter inaccurate pattern alignment during lithography and their corresponding detection signals.
[0032] Figure 14A Settings of paired alignment keys of some embodiments of the present disclosure and their corresponding detection signals.
[0033] [[ID=4⑨]] Figure 14B Settings of paired alignment keys of some embodiments of the present disclosure that encounter inaccurate pattern alignment during lithography and their corresponding detection signals.
[0034] Explanation of reference numerals:
[0035] A 10: Wafer
[0036] 20: Scoring line
[0037] 100: Chip
[0038] 102: Substrate
[0039] 102t: Upper surface
[0040] 102b: Lower surface
[0041] 110: Device area
[0042] 120: Corner area
[0043] 130: Sealing ring
[0044] 132: Corner segment
[0045] 134: Edge segment
[0046] 140: Scribing lane area
[0047] 142: Scribing edge
[0048] 150: Stress relief area
[0049] 160: Inner spacer
[0050] 170: Outer spacer
[0051] 200, 200’, 200a, 200b, 200c, 200d, 200e, 200f, 200g, 200h, 200i, 200j, 200k, 200l, 200m: Alignment keys
[0052] 210: Dot-shaped via hole
[0053] 300: Encapsulation structure
[0054] 310: Wafer
[0055] 312: First alignment key
[0056] 320: First chip
[0057] 322: Second alignment key
[0058] 330: Second chip
[0059] 332: Third alignment key
[0060] 340: Third chip
[0061] 342: Fourth alignment key
[0062] 410: First alignment key
[0063] 420: Second alignment key
[0064] 430: First alignment key
[0065] 440: Second alignment key
[0066] θ: Angle
[0067] X, Y: Directions
[0068] P1, P2, P3, P4, P5, P6, P7, P8, P9: Spacing Detailed implementation manners
[0069] The spirit of the present disclosure will be clearly described below with reference to the drawings and detailed descriptions. After those skilled in the art understand the preferred embodiments of the present disclosure, they can make changes and modifications based on the techniques taught by the present disclosure, which do not depart from the spirit and scope of the present disclosure.
[0070] In a three-dimensional packaging structure, multiple chips and / or wafers are stacked in sequence. These chips and / or wafers are first initially aligned and then precisely aligned for positioning. The steps of initial alignment include inserting a visible light lens between the chips and / or wafers and using alignment keys on the chips and / or wafers for alignment. After the chips and / or wafers are temporarily positioned, an infrared light lens is used to precisely align the chips and / or wafers.
[0071] Since infrared light cannot penetrate metal, therefore, in each chip or wafer, areas need to be reserved near the alignment keys. According to the design rules, no metal is provided from the bottom surface to the top surface within this reserved area to prevent other metals from being too close to the alignment keys and affecting the accuracy of the image or the quality of bonding. However, the configuration of this reserved area will cause a large amount of space waste. One aspect of the present disclosure is to provide a chip with alignment keys, where the setting position of the alignment keys will not cause additional space waste and can improve the space utilization efficiency.
[0072] Refer to Figure 1 , which is a partial enlarged view of some embodiments of the chip with alignment keys of the present disclosure. Chip 100 includes a device area 110 in a substrate 102, a corner area 120 at a corner of the substrate 102, a sealing ring 130 surrounding the device area 110, and a scribe line area 140. The sealing ring 130 includes a corner segment 132 adjacent to the corner area 120, and the scribe line area 140 surrounds the sealing ring 130 and the corner area 120. Chip 100 includes an alignment key 200, and the alignment key 200 is disposed at a position adjacent to the sealing ring 130. Please note that the alignment key 200' represented by the dashed line in the following drawings is the alignment key 200' that matches the alignment key 200, and the alignment key 200' is disposed on another chip or wafer.
[0073] The sealing ring 130 is mostly disposed inside the cutting line, and the scribe line area 140 is the area cut during the cutting process. The sealing ring 130 is configured to protect the device area 110 from external environmental interference and to protect the integrated circuit in the device area 110 from deterioration due to moisture ingress.
[0074] The sealing ring 130 is mostly composed of metal wires and connected vias, and has a floating potential without providing any electrical connection function. The sealing ring 130 includes an edge segment 134, which is connected by a corner segment 132, and the angle θ between the corner segment 132 and the edge segment 134 is greater than 90 degrees. In other words, the shape of the corner region 120 adjacent to the corner segment 132 is triangular. The alignment key 200 in the present disclosure can be disposed in the corner region 120 to reduce space waste.
[0075] Although only one alignment key 200 is shown in Figure 1 , in practice, the number of alignment keys 200 is preferably multiple, for example, more than three, and these alignment keys 200 can be respectively disposed in multiple corner regions 120 of the chip 100. Figure 1 The alignment key 200 shown in
[0076] is a stripe pattern, but it is not limited thereto, as long as the alignment key 200 (or the whole of multiple alignment keys 200) can provide the function of preventing misalignment in the X and Y directions.
[0077] In some embodiments, the chip 100 further includes a stress relief region 150 disposed inside the sealing ring 130. The stress relief region 150 and the corner region 120 are respectively located on opposite sides of the corner segment 132. The stress relief region 150 is a region without circuit configuration to provide the function of stress relief at the corners of the chip.
[0078] The aforementioned stress relief region 150, inner spacer 160, and outer spacer 170 are regions without circuits. Therefore, one or more alignment keys 200 can be disposed in the corner region 120, scribe lane region 140, stress relief region 150, inner spacer 160, outer spacer 170, or a combination thereof, thereby reducing the space waste caused by setting the alignment keys 200.
[0079] Referring to Figure 2, which is a partial enlarged view of some embodiments of the chip with alignment keys according to the present disclosure. In some embodiments, the alignment keys 200 are disposed at positions adjacent to the sealing ring 130, such as in the inner spacer 160 and / or the outer spacer 170. The pattern of the alignment keys 200 may extend inward or outward from the sealing ring 130. In some embodiments, the alignment keys 200, such as alignment keys 200a and 200b, are connected to the edge segment 134 of the sealing ring 130. In some embodiments, the alignment keys 200, such as alignment keys 200c and 200d, are separated from the edge segment 134 of the sealing ring 130.
[0080] In some embodiments, the alignment keys 200 may be disposed at positions corresponding to at least two edge segments 134 of the sealing ring 130, and these alignment keys 200 as a whole provide the function of preventing misalignment on the X reference axis and the Y reference axis. In some embodiments, the alignment keys 200 may be disposed in the inner spacer 160 and the outer spacer 170, and the patterns of the alignment keys 200 in the inner spacer 160, such as alignment keys 200a and 200c, are symmetric to the patterns of the alignment keys 200 in the outer spacer 170, such as alignment keys 200b and 200d, to further improve the accuracy of alignment.
[0081] In some embodiments, the alignment keys 200, such as alignment keys 200e and 200f, are disposed in either the inner spacer 160 or the outer spacer 170. The pattern of the alignment key 200e is different from that of the alignment key 200f to provide more than one alignment rule, thereby improving the accuracy of alignment.
[0082] Referring to Figure 3 , which is a partial enlarged view of some embodiments of the chip with alignment keys according to the present disclosure. In some embodiments, the alignment keys 200 are disposed at positions adjacent to the sealing ring 130. The alignment keys 200, such as alignment keys 200g and 200h, are disposed in the corner region 120 and / or the stress relief region 150. The patterns of the alignment keys 200g and 200h may extend inward or outward from the corner segment 132 of the sealing ring 130.
[0083] Since the corner segment 132 has an angle of, for example, 45 degrees with the X reference axis and the Y reference axis, the alignment keys 200g and 200h having patterns extending inward or outward from the corner segment 132 of the sealing ring 130 can further provide the function of preventing rotation, for example, can avoid the problem of 45-degree rotational misalignment.
[0084] Referring to Figure 4, which is a partial enlarged view of some embodiments of a wafer of a chip with alignment keys according to the present disclosure. The wafer 10 includes a plurality of dicing lines 20, and after dicing along the dicing lines 20, the wafer 10 is divided into a plurality of chips 100. The saw street region 140 in the chip 100 is the region where the dicing operation is performed. In some embodiments, the alignment keys 200, such as alignment key 200i and alignment key 200j, are disposed in the saw street region 140 and are symmetric with respect to the dicing line 20, such that the remaining half patterns of the alignment keys 200i and 200j after dicing still maintain alignment.
[0085] In some embodiments, the alignment key 200, such as alignment key 200i, has a portion directly disposed on the dicing line 20. In this way, after the dicing process is performed, the saw street region 140 will have a dicing edge 142, and the alignment key 200i is connected to the dicing edge 142.
[0086] In some embodiments, the alignment key 200, such as alignment key 200j, is spaced apart from the dicing line 20 to avoid the situation where the alignment key 200j breaks or there are residues of the alignment key 200j during the dicing process. In this way, after the dicing process is performed, the saw street region 140 will have a dicing edge 142, and the alignment key 200j is separated from the dicing edge 142.
[0087] Refer to Figure 5 , which is a partial enlarged view of some embodiments of a wafer of a chip with alignment keys according to the present disclosure. In some embodiments, the alignment key 200 is disposed in the saw street region 140 of the chip 100, and the alignment key 200 is separated from the dicing edge 142 and is closer to the sealing ring 130 (see Figure 4 ) to avoid damage to the pattern of the alignment key 200 during the dicing process. In some embodiments, the number of alignment keys 200 in the saw street region 140 is multiple, and the patterns of the alignment keys 200 can be different. One of the alignment keys 200, such as alignment key 200k, has a triangular pattern, and the alignment key 200k is disposed at a corner of the saw street region 140 for identifying rotational misalignment.
[0088] Refer to Figure 6, which is a partial enlarged view of some embodiments of the wafer of the chip with alignment keys of the present disclosure. In some embodiments, the alignment keys 200 are disposed in the scribe lane region 140 and the outer spacer 170. For example, half of the alignment keys 200, such as half of the alignment keys 2001, are disposed in the scribe lane region 140, while the other half of the alignment keys 2001 are disposed in the outer spacer 170. Optionally, the alignment keys 200, such as the alignment keys 200m, are disposed in the scribe lane region 140, and the alignment keys 200' on another chip or wafer that match them are disposed in its outer spacer 170. In this way, the spatial configuration of the alignment keys 200 can be applied more efficiently.
[0089] The above-mentioned alignment keys 200 are configured to align the chips and / or wafers before chip and / or wafer bonding. The above-mentioned alignment keys 200 can be formed on the upper surface or the lower surface of the chip and / or wafer.
[0090] In addition, the alignment keys on the upper surface and the lower surface of each chip or wafer should also be accurately aligned to ensure the accuracy of bonding. However, the lithography process will inevitably encounter problems such as inaccurate alignment (overlay) of patterns in different layers and / or errors in the critical dimensions (CD) of patterns in different layers, which will cause blurring or misalignment between the alignment keys on the upper surface and the lower surface of the chip, resulting in a decrease in the bonding yield. Therefore, one aspect of the present disclosure is to provide a chip with alignment keys, and the alignment keys have a consistent shape and position.
[0091] Refer to Figure 7 , which is a cross-sectional schematic diagram of some embodiments of the chip with alignment keys of the present disclosure. In some embodiments, the chip 100 includes a substrate 102 having opposite upper surface 102t and lower surface 102b. The alignment keys 200 are formed in the substrate 102 and continuously extend from the upper surface 102t of the substrate 102 to the lower surface 102b in a single direction, so that the shape and position of the alignment keys 200 are continuously maintained between the upper surface 102t and the lower surface 102b of the substrate 102, allowing the alignment keys 200 to linearly penetrate the substrate 102 and having the same shape and position on both the upper surface 102t and the lower surface 102b. Since the alignment keys 200 are structures that linearly penetrate the substrate 102, only one exposure and development process is required, so problems such as inaccurate alignment of patterns in different layers in the lithography process will not be encountered, and at the same time, problems such as errors in the critical dimensions of patterns in different layers in the lithography process can be avoided.
[0092] The alignment key 200 is made of a material that blocks infrared rays, such as metal. The alignment key 200 has a floating potential and does not provide any electrical connection function. The alignment key 200 is isolated from other internal connection metal layers, that is, the alignment key 200 is electrically and physically isolated from other internal connection metal layers. The internal connection metal layers referred to here include but are not limited to metal layers and / or metal wires for connecting circuits and / or components of different layers, and vias for connecting these metal layers and / or metal wires. In addition, the alignment key 200 passing through the substrate 102 is also isolated from the pads used to connect to external components, so as to avoid affecting the image reading result of the alignment key 200 due to the shielding of the pads or the solder thereon. In some embodiments, the alignment key 200 passing through the substrate 102 not only provides the function of alignment, but also provides an additional heat dissipation path for the chip 100.
[0093] The setting position of the alignment key 200 continuously extending in a single direction between the upper surface 102t and the lower surface 102b can be the same as the position set in the previous Figures 1 to 6 embodiment. The substrate 102 can be a semiconductor substrate, and the corresponding alignment key 200 can be a through-silicon via (TSV). The substrate 102 can be a glass substrate, and the corresponding alignment key 200 can be a through glass-via (TGV). The substrate 102 can be a glass substrate, and the corresponding alignment key 200 can be a through glass-via (TGV). The substrate 102 can be an integrated fanout (InFO) substrate, and the corresponding alignment key 200 can be a through-InFO via (TIV). The substrate 102 can be a molded material substrate, and the corresponding alignment key 200 can be a though-molding via (TMV). The substrate 102 can be a dielectric material substrate, and the corresponding alignment key 200 can be a though-dielectric via (TDV).
[0094] Refer to Figure 8 and Figure 9 , which are respectively Figure 7 top views of different embodiments of the alignment key in Figure 8 . In some embodiments, the alignment key 200 can be a solid pattern, and the matching alignment key 200' is also a solid pattern, as shown in
[0095] In some other embodiments, the alignment key 200 includes a plurality of dot-shaped vias 210, and the dot-shaped vias 210 form a pattern. The matching alignment key 200' is also a pattern formed by the dot-shaped vias 210, as shown in Figure 9 . The pattern of the alignment key 200 is a triangular pattern, a spiral pattern, or a stripe pattern formed by the dot-shaped vias 210. The alignment key 200 having a pattern formed by the dot-shaped vias 210 can be easily integrated into the existing semiconductor process and has a high manufacturing precision. Through algorithms, the optical analysis results of the alignment key 200 as shown in Figure 9 can be equivalent to the optical analysis results of the alignment key 200 as shown in Figure 8 .
[0096] Referring to Figure 10A , which is a cross-sectional schematic diagram of some embodiments of the packaging structure of the present disclosure. The packaging structure 300 includes a wafer 310 and a first chip 320 bonded to the wafer 310. The wafer 310 and the first chip 320 can be bonded together by hybrid bonding, μ-bump bonding, or other suitable bonding methods.
[0097] The wafer 310 includes a first alignment key 312 disposed on the upper surface of the wafer 310, and the first chip 320 includes a second alignment key 322 disposed on the lower surface of the first chip 320. The setting position of the second alignment key 322 can be as shown in the embodiment of Figures 1 to 6 . In some embodiments, the second alignment key 322 can be disposed on the upper and lower surfaces of the first chip 320. In some embodiments, as shown in Figure 7 , the second alignment key 322 can continuously extend from the lower surface to the upper surface of the first chip 320 in a single direction. The second alignment key 322 can be a solid pattern or a pattern formed by dot-shaped vias. In some embodiments, in addition to providing the function of alignment, the first alignment key 312 and the second alignment key 322 can also serve as contact points for hybrid bonding between the wafer 310 and the first chip 320.
[0098] Referring to Figures 10B to 10D , which are respectively the plan views of different embodiments of the alignment keys in Figure 10A . In as shown in Figure 10BIn the shown plan view, the patterns of the first alignment key 312 and the second alignment key 322 are triangular patterns, and the spacings P1, P2, and P3 between the first alignment key 312 and the second alignment key 322 are the same. The spacings P1, P2, and P3 are measured in at least two directions. For example, the spacings P1 and P2 are measured along the X direction and the Y direction to avoid misalignment with respect to the X reference axis and the Y reference axis, while the spacing P3 is measured at a 45-degree angle with respect to the X direction and the Y direction to further avoid misalignment due to 45-degree rotation.
[0099] In the plan view as Figure 10C shown, the patterns of the first alignment key 312 and the second alignment key 322 are spiral patterns. The spiral pattern can be an arc-shaped spiral, a quadrilateral spiral, or a polygonal spiral. The spacings P1 and P2 between the first alignment key 312 and the second alignment key 322 are the same, and the spacings P1 and P2 are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment with respect to the X reference axis and the Y reference axis. In some embodiments, the centers of these alignment keys, such as the center of the second alignment key 322, can be a point (in the case of an arc-shaped spiral) or a rectangle (in the case of a quadrilateral spiral).
[0100] In the plan view as Figure 10D shown, the patterns of the first alignment key 312 and the second alignment key 322 are stripe patterns. The spacings P1 and P2 between the first alignment key 312 and the second alignment key 322 are the same, and the spacings P1 and P2 are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment between the wafer 310 and the first chip 320 (refer to Figure 10A ).) with respect to the X reference axis and the Y reference axis. In some embodiments, the stripes of the first alignment key 312 and the stripes of the second alignment key 322 are arranged alternately. The stripes of the first alignment key 312 and the stripes of the second alignment key 322 can be divided into four groups, where the stripes in two diagonal groups extend vertically, and the stripes in the other two diagonal groups extend horizontally to facilitate identification more conveniently.
[0101] Refer to Figure 11A , which is a schematic cross-sectional view of some embodiments of the packaging structure of the present disclosure. The packaging structure 300 includes a wafer 310, a first chip 320 bonded to the wafer 310, and a second chip 330 bonded to the first chip 320. The wafer 310, the first chip 320, and the second chip 330 can be bonded together by hybrid bonding, micro-bump bonding, or other suitable bonding methods.
[0102] In some embodiments, the wafer 310 includes first alignment keys 312 disposed on the upper surface of the wafer 310. The first chip 320 includes second alignment keys 322 disposed on both the upper and lower surfaces of the first chip 320, and the positions and shapes of the second alignment keys 322 on the upper and lower surfaces of the first chip 320 are substantially the same. The second chip 330 includes third alignment keys 332 disposed on the lower surface of the second chip 330. The positions of the second alignment keys 322 and the third alignment keys 332 can be as shown in the embodiments of FIGS. 1 to 6. In some other embodiments, as Figure 7 shown, the second alignment keys 322 can continuously extend from the lower surface to the upper surface of the first chip 320 in a single direction, so that the positions and shapes of the second alignment keys 322 on the upper and lower surfaces of the first chip 320 can be maintained consistent, avoiding problems such as inaccurate pattern alignment of different layers and / or errors in the critical dimensions of patterns of different layers in the lithography process. The second alignment keys 322 and the third alignment keys 332 can be solid patterns or patterns composed of dot vias. In some embodiments, in addition to providing alignment functions, the first alignment keys 312, the second alignment keys 322, and the third alignment keys 332 can also serve as contact points for hybrid bonding between the wafer 310 and the first chip 320 and the second chip 330.
[0103] Referring to Figures 11B to 11D , which are respectively Figure 11A plan views of different embodiments of the alignment keys in Figure 11B shown. In the plan view as Figure 11B shown, the patterns of the first alignment keys 312, the second alignment keys 322, and the third alignment keys 332 are triangular patterns, and the second alignment keys 322 are disposed between the first alignment keys 312 and the third alignment keys 332. The spacings P1, P2, P3 between the first alignment keys 312 and the second alignment keys 322 are the same. The spacings P4, P5, P6 between the second alignment keys 322 and the third alignment keys 332 are the same. The spacings P1, P2, P3 are measured in at least two directions, and P4, P5, P6 are measured in at least two directions. For example, the spacings P1, P2, P4, P5 are measured along the X direction and the Y direction to avoid misalignment with respect to the X reference axis and the Y reference axis, and the spacings P3, P6 are measured at a 45-degree angle with respect to the X direction and the Y direction to further avoid misalignment due to 45-degree rotation.
[0104] In the case of Figure 11CIn the shown plan view, the patterns of the first alignment key 312, the second alignment key 322, and the third alignment key 332 are spiral patterns. The spiral patterns can be arc-shaped spirals, quadrilateral spirals, or polygonal spirals. The distances P1 and P2 between the first alignment key 312 and the second alignment key 322 are the same, and the distances P4 and P5 between the second alignment key 322 and the third alignment key 332 are the same. The distances P1, P2, P4, and P5 are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment with respect to the X reference axis and the Y reference axis. In some embodiments, the centers of these alignment keys, such as the center of the third alignment key 332, can be a point (taking the arc-shaped spiral as an example) or a rectangle (taking the quadrilateral spiral as an example).
[0105] In, such as Figure 11D In the shown plan view, the patterns of the first alignment key 312, the second alignment key 322, and the third alignment key 332 are stripe patterns. The distances P1 and P2 between the first alignment key 312 and the second alignment key 322 are the same and are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment between the wafer 310 and the first chip 320 (refer to Figure 11A ) with respect to the X reference axis and the Y reference axis. The distances P4 and P5 between the second alignment key 322 and the third alignment key 332 are the same and are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment between the first chip 320 and the second chip 330 (refer to Figure 11A ) with respect to the X reference axis and the Y reference axis.
[0106] In some embodiments, the stripes of the first alignment key 312 and the stripes of the second alignment key 322 are arranged alternately. The stripes of the first alignment key 312 and the stripes of the second alignment key 322 can be divided into four groups, where the stripes of two groups on the diagonal extend vertically, and the stripes of the other two groups on the diagonal extend horizontally for easier identification. The stripes of the third alignment key 332 are in a cross shape and are arranged between the stripes of the first alignment key 312 and the stripes of the second alignment key 322 in these four groups.
[0107] Refer to Figure 12A , which is a schematic cross-sectional view of some embodiments of the packaging structure of the present disclosure. The packaging structure 300 includes a wafer 310, a first chip 320 bonded to the wafer 310, a second chip 330 bonded to the first chip 320, and a third chip 340 bonded to the second chip 330. The wafer 310, the first chip 320, the second chip 330, and the third chip 340 can be bonded together by hybrid bonding, micro-bump bonding, or other suitable bonding methods.
[0108] In some embodiments, the wafer 310 includes a first alignment key 312 disposed on the upper surface of the wafer 310. The first chip 320 includes a second alignment key 322 that continuously extends from the lower surface to the upper surface of the first chip 320 in a single direction. The second chip 330 includes a third alignment key 332 that continuously extends from the lower surface to the upper surface of the second chip 330 in a single direction. The third chip 340 includes a fourth alignment key 342 disposed on the lower surface of the third chip 340. The second alignment key 322 and the third alignment key 332 respectively penetrate through the first chip 320 and the second chip 330 in a single direction, so that the positions and shapes of the second alignment key 322 and the third alignment key 332 on the upper and lower surfaces of the first chip 320 and the second chip 330 are maintained consistent, avoiding problems such as inaccurate pattern alignment of different layers and / or errors in the critical dimensions of patterns of different layers in the lithography process. The second alignment key 322 and the third alignment key 332 can be solid patterns or patterns composed of dot vias. The setting positions of the second alignment key 322, the third alignment key 332, and the fourth alignment key 342 can be as shown in Figures 1 to 6 In some other embodiments, the second alignment key 322 and the third alignment key 332 can be respectively disposed on the upper and lower surfaces of the first chip 320 and the second chip 330.
[0109] Referring to Figures 12B to 12D which are respectively Figure 12A the plan views of different embodiments of the alignment keys in Figure 12B In the plan view as shown in Figure 12B , the patterns of the first alignment key 312, the second alignment key 322, the third alignment key 332, and the fourth alignment key 342 are triangular patterns. The second alignment key 322 is disposed between the first alignment key 312 and the third alignment key 332, and the third alignment key 332 is disposed between the second alignment key 322 and the fourth alignment key 342. The spacings P1, P2, P3 between the first alignment key 312 and the second alignment key 322 are the same. The spacings P4, P5, P6 between the second alignment key 322 and the third alignment key 332 are the same. The spacings P7, P8, P9 between the third alignment key 332 and the fourth alignment key 342 are the same. The spacings P1, P2, P3 are measured in at least two directions, P4, P5, P6 are measured in at least two directions, and P7, P8, P9 are measured in at least two directions. For example, the spacings P1, P2, P4, P5, P7, P8 are measured along the X direction and the Y direction to avoid misalignment relative to the X reference axis and the Y reference axis, while the spacings P3, P6, P9 are measured at a 45-degree angle relative to the X direction and the Y direction to further avoid misalignment of 45-degree rotation.
[0110] In the case of Figure 12CIn the shown plan view, the patterns of the first alignment key 312, the second alignment key 322, the third alignment key 332, and the fourth alignment key 342 are spiral patterns. The spiral patterns can be arc-shaped spirals, quadrilateral spirals, or polygonal spirals. The distances P1 and P2 between the first alignment key 312 and the second alignment key 322 are the same, the distances P4 and P5 between the second alignment key 322 and the third alignment key 332 are the same, and the distances P7 and P8 between the third alignment key 332 and the fourth alignment key 342 are the same. The distances P1, P2, P4, P5, P7, and P8 are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment with respect to the X reference axis and the Y reference axis. In some embodiments, the centers of these alignment keys, such as the center of the fourth alignment key 342, can be a point (taking the arc-shaped spiral as an example) or a rectangle (taking the quadrilateral spiral as an example).
[0111] In the plan view as shown in Figure 12D , the patterns of the first alignment key 312, the second alignment key 322, the third alignment key 332, and the fourth alignment key 342 are stripe patterns. The distances P1 and P2 between the first alignment key 312 and the second alignment key 322 are the same and are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment between the wafer 310 and the first chip 320 (refer to Figure 12A ) with respect to the X reference axis and the Y reference axis. The distances P4 and P5 between the second alignment key 322 and the third alignment key 332 are the same and are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment between the first chip 320 and the second chip 330 (refer to Figure 12A ) with respect to the X reference axis and the Y reference axis. The distances P7 and P8 between the third alignment key 332 and the fourth alignment key 342 are the same and are measured in at least two directions, such as along the X direction and the Y direction, to avoid misalignment between the first chip 320 and the second chip 330 (refer to Figure 12A ) with respect to the X reference axis and the Y reference axis.
[0112] In some embodiments, the stripes of the first alignment key 312, the second alignment key 322, the third alignment key 332, and the fourth alignment key 342 are arranged alternately, such that the overall stripes of the first alignment key 312, the second alignment key 322, the third alignment key 332, and the fourth alignment key 342 have a periodic distribution. The stripes of the first alignment key 312, the second alignment key 322, the third alignment key 332, and the fourth alignment key 342 can be divided into four groups, where the stripes of two groups on the diagonal extend vertically, and the stripes of the other two groups on the diagonal extend horizontally for easier identification. The stripes of the fourth alignment key 342 also include cross-shaped stripes and are arranged between the stripes of these four groups.
[0113] In some embodiments, the stripes in two sets of the diagonal are cross-shaped stripes symmetric to the fourth alignment key 342. In each set, the stripe of the third alignment key 332 is disposed between the stripe of the first alignment key 312 and the stripe of the second alignment key 322, the stripe of the second alignment key 322 is disposed between the stripe of the third alignment key 332 and the stripe of the fourth alignment key 342, and the stripe of the fourth alignment key 342 is disposed between the stripe of the second alignment key 322 and the stripe of the first alignment key 312.
[0114] Although the device of the packaging structure 300 disclosed in the above embodiments is a combination of a wafer and a chip, the packaging structure 300 is not limited to a wafer-chip packaging structure. In some other embodiments, the packaging structure of the present disclosure may also be a wafer-wafer packaging structure or a chip-chip packaging structure.
[0115] Such as Figures 10B to 10D 、 Figures 11B to 11D and Figures 12B to 12D The setting of the alignment keys as shown can not only provide good alignment effect, but also improve the efficiency of signal analysis during alignment.
[0116] Referring to Figure 13A and Figure 13B . Figure 13A are the settings of traditional paired alignment keys and their corresponding detection signals, where the first alignment key 410 is disposed on one side of the second alignment key 420. Figure 13B are the settings of traditional paired alignment keys and their corresponding detection signals, where the first alignment key 410 is disposed on one side of the second alignment key 420, and the first alignment key 410 suffers from the problem of critical dimension error of the pattern during lithography. Comparing Figure 13A and Figure 13B it can be known that Figure 13A the measured signals are periodic and have the same width. However, Figure 13B are periodic but have different widths, which will require additional work during signal analysis.
[0117] Referring to Figure 14A and Figure 14B . Figure 14A are the settings of paired alignment keys of some embodiments of the present disclosure and their corresponding detection signals, where the distance between the first alignment key 430 and the second alignment key 440 is the same. Figure 14B are the settings of paired alignment keys of some embodiments of the present disclosure and their corresponding detection signals, where the distance between the first alignment key 430 and the second alignment key 440 is the same, and the first alignment key 430 suffers from the problem of critical dimension error of the pattern during lithography. Comparing Figure 14A and Figure 14B it can be known thatFigure 14A The signals measured in Figure 14B are also periodic and still have the same width, even when the first alignment key 430 encounters problems with the critical dimension of the pattern during lithography.
[0118] This design with the same spacing between the first alignment key 430 and the second alignment key 440 can still operate smoothly when encountering problems with the critical dimension of the pattern during lithography, and no additional work is required during signal analysis. In this way, the signal analysis stage in the alignment process can be more efficient.
[0119] Although the present disclosure has been disclosed above by way of examples, it is not intended to limit the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the appended claims.
Claims
1. A chip, comprising: A device area disposed on a substrate; A corner area disposed at a corner of the substrate; A sealing ring surrounding the device area, the sealing ring including a corner segment adjacent to the corner area; A scribe lane area surrounding the sealing ring and the corner area; and A pair of alignment keys disposed adjacent to the sealing ring.
2. The chip according to claim 1, wherein the sealing ring includes a plurality of edge segments connected by the corner segment, the angle between the corner segment and the edge segments is greater than 90 degrees, and the alignment keys are disposed in the corner area or the scribe lane area.
3. The chip according to claim 1, further comprising a stress relief area, wherein the stress relief area and the corner area are respectively located on opposite sides of the corner segment, and the alignment keys are disposed in the stress relief area.
4. The chip according to claim 1, further comprising an inner spacer disposed between the device area and the sealing ring, wherein the alignment keys are disposed in the inner spacer.
5. The chip according to claim 1, further comprising an outer spacer disposed between the sealing ring and the scribe lane area, wherein the alignment keys are disposed in the outer spacer.
6. The chip according to claim 1, further comprising an outer spacer disposed between the sealing ring and the scribe lane area, wherein half of the alignment keys are disposed in the outer spacer and the other half of the alignment keys are disposed in the scribe lane area.
7. A chip, comprising: A substrate having an upper surface and a lower surface; and A pair of alignment keys disposed in the substrate and continuously extending from the upper surface to the lower surface in a single direction, wherein the material of the alignment keys is metal and the alignment keys are isolated from the inner connection metal layer.
8. The chip according to claim 7, wherein the alignment keys include a triangular pattern, a spiral pattern, or a stripe pattern.
9. The chip according to claim 7, wherein the alignment keys include a plurality of dot vias, and the dot vias form a triangular pattern, a spiral pattern, or a stripe pattern.
10. A packaging structure, comprising: A first device including a first alignment key disposed on an upper surface of the first device; and A second device bonded to the first device, including a second alignment key disposed on a lower surface of the second device, wherein in a plan view, the distances between the first alignment key and the second alignment key are the same, and the distances are measured in at least two directions.
11. The packaging structure according to claim 10, wherein the second alignment key continuously extends from the lower surface of the second device to an upper surface of the second device in a single direction.
12. The packaging structure according to claim 10, wherein the second device includes another second alignment key disposed on an upper surface of the second device.