Bootstrap drive circuit

Abstract

The bootstrap drive circuit comprises an H-bridge circuit, a switch tube Q1, a switch tube Q5, an MOS tube Q3, an MOS tube Q7, a resistor R1, a resistor R5, a capacitor C2 and a capacitor C4. The H-bridge circuit is composed of an upper tube composed of an MOS tube Q2 and an MOS tube Q4 and a lower tube composed of an MOS tube Q6 and an MOS tube Q8, the drain electrode of the MOS tube Q2 and the drain electrode of the MOS tube Q6 are connected to a VDC end, and the source electrode of the MOS tube Q4 and the source electrode of the MOS tube Q8 are connected with a GND end; through the circuit, independent driving control of four MOS tubes of an H bridge can be realized when the circuit is matched with low-voltage-withstanding master control, driving of a high-voltage H bridge by low-voltage PWM is realized, the circuit has the advantages of high switching speed, high driving capability and controllable dead time, the application limitation of low-voltage-withstanding master control is solved, the cost is reduced while high-efficiency and high-stability driving is realized, and the use requirements are met.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and particularly relates to a bootstrap drive circuit. Background Art

[0002] The working principle of a wireless charger is that the control unit drives the H-bridge MOS transistors to invert and convert the DC voltage into an AC voltage. The AC voltage drives the transmitting coil to generate a changing magnetic field. Placing the receiving coil within the range of this magnetic field can generate an induced electromotive force. After rectifying the AC induced electromotive force, a DC voltage is output, thereby realizing the wireless charging function.

[0003] However, the H-bridge MOS transistors need to be driven by a dedicated drive circuit. The drive circuit controls the upper and lower transistors of the H-bridge to quickly turn on and off through certain control logic to achieve high-frequency inversion. If the H-bridge is composed of 4 NMOS transistors, to drive the upper NMOS transistor, bootstrap boosting is required to turn on the upper NMOS transistor, which increases the complexity of the drive circuit; most of the existing H-bridge drive circuits composed of 4 NMOS transistors use dedicated drive chips or microcontroller integrated drive modules, and the costs of both are relatively high; therefore, there is an urgent need for a bootstrap drive circuit to solve the above problems. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. For this purpose, the present invention provides a bootstrap drive circuit.

[0005] An embodiment of the present invention adopts the following technical solution to solve its technical problems: A bootstrap drive circuit includes an H-bridge circuit, a switching transistor Q1, a switching transistor Q5, an MOS transistor Q3, an MOS transistor Q7, a resistor R1, a resistor R5, a capacitor C2, and a capacitor C4;

[0006] The H-bridge circuit is composed of an upper transistor formed by an MOS transistor Q2 and an MOS transistor Q4, and a lower transistor formed by an MOS transistor Q6 and an MOS transistor Q8. The drain of the MOS transistor Q2 and the drain of the MOS transistor Q6 are connected to the VDC terminal, and the source of the MOS transistor Q4 and the source of the MOS transistor Q8 are connected to the GND terminal;

[0007] The input terminal of the switching transistor Q1 is respectively connected to one end of the resistor R1 and one end of the capacitor C2 and connected to the HVCC terminal. The control terminal of the switching transistor Q1 is respectively connected to the other end of the resistor R1 and the gate of the MOS transistor Q3 and connected to the PWM1 H signal. The output terminal of the switching transistor Q1 is respectively connected to the gate of the MOS transistor Q2 and the drain of the MOS transistor Q3. The source of the MOS transistor Q2 is respectively connected to the other end of the capacitor C2 and the drain of the MOS transistor Q4. The gate of the MOS transistor Q4 is connected to the PWM 1L signal;

[0008] The input terminal of switching transistor Q5 is respectively connected to one end of resistor R5 and one end of capacitor C4 and is connected to the HVCC terminal. The control terminal of switching transistor Q5 is respectively connected to the other end of resistor R5 and the gate of MOS transistor Q7 and is connected to the PWM2H signal. The output terminal of switching transistor Q5 is respectively connected to the gate of MOS transistor Q6 and the drain of MOS transistor Q7. The source of MOS transistor Q6 is respectively connected to the other end of capacitor C5 and the drain of MOS transistor Q8. The gate of MOS transistor Q8 is connected to the PWM 1L signal;

[0009] The sources of MOS transistors Q3 and Q7 are connected to the GND terminal.

[0010] As one of the preferred embodiments of the present invention, a bootstrap drive circuit further includes capacitor C1 and resistor R2. One end of capacitor C1 is connected to the gate of MOS transistor Q3 and is connected to the PWM1 H signal. The other end of capacitor C1 is respectively connected to the other end of resistor R1 and the control terminal of switching transistor Q1 through resistor R2.

[0011] As one of the preferred embodiments of the present invention, a bootstrap drive circuit further includes capacitor C3 and resistor R6. One end of capacitor C3 is connected to the gate of MOS transistor Q7 and is connected to the PWM2H signal. The other end of capacitor C3 is respectively connected to the other end of resistor R5 and the control terminal of switching transistor Q5 through resistor R6.

[0012] As one of the preferred embodiments of the present invention, a bootstrap drive circuit further includes diode D1. The anode of diode D1 is connected to the HVCC terminal. The cathode of diode D1 is connected to one end of capacitor C2, the input terminal of switching transistor Q1, and one end of resistor R1.

[0013] As one of the preferred embodiments of the present invention, a bootstrap drive circuit further includes diode D2. The anode of diode D2 is connected to the HVCC terminal. The cathode of diode D2 is connected to one end of capacitor C4, the input terminal of switching transistor Q5, and one end of resistor R5.

[0014] As one of the preferred embodiments of the present invention, the PWM1 H signal and the PWM1 L signal are a pair of PWM signals with in-phase output and independently configured dead times for the rising edge and the falling edge. The PWM2H signal and the PWM2L signal are a pair of PWM signals with in-phase output and independently configured dead times for the rising edge and the falling edge.

[0015] As one of the preferred embodiments of the present invention, switching transistors Q1 and Q5 are configured as bipolar transistors.

[0016] As one of the preferred embodiments of the present invention, MOS transistors Q3 and Q7 are configured as NMOS transistors.

[0017] Advantages of the present invention: A bootstrap drive circuit includes an H-bridge circuit, a switching transistor Q1, a switching transistor Q5, an MOS transistor Q3, an MOS transistor Q7, a resistor R1, a resistor R5, a capacitor C2, and a capacitor C4; the H-bridge circuit consists of an upper tube composed of an MOS transistor Q2 and an MOS transistor Q4 and a lower tube composed of an MOS transistor Q6 and an MOS transistor Q8. The drain of the MOS transistor Q2 and the drain of the MOS transistor Q6 are connected to the VDC terminal, and the source of the MOS transistor Q4 and the source of the MOS transistor Q8 are connected to the GND terminal; through the above circuit, independent drive control of the four MOS transistors of the H-bridge can be achieved when cooperating with a low-voltage withstand main controller, realizing low-voltage PWM driving of a high-voltage H-bridge, having the advantages of fast switching speed, strong driving ability, and controllable dead time, solving the application limitations of low-voltage withstand main controllers, achieving high-efficiency and high-stability driving while reducing costs, and meeting the usage requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a circuit schematic diagram of a bootstrap drive circuit;

[0020] Figure 2 is a circuit schematic diagram of a bootstrap drive circuit when the PWM1 H signal is a rising-edge drive current;

[0021] Figure 3 is a circuit schematic diagram of a bootstrap drive circuit when the PWM1 L signal is a rising-edge drive current;

[0022] Figure 4 is a circuit schematic diagram of a bootstrap drive circuit when the PWM1 L signal is a falling-edge drive current;

[0023] Figure 5 is a circuit schematic diagram of a bootstrap drive circuit when the PWM1 H signal is a falling-edge drive current;

[0024] Figure 6 is a driving logic schematic diagram of the PWM1 L signal and the PWM1 H signal. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] This part will describe the specific embodiments of the present invention in detail. The preferred embodiments of the present invention are shown in the accompanying drawings. The role of the drawings is to supplement the description of the text part of the specification, enabling people to intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the protection scope of the present invention.

[0026] In the description of the present invention, the meaning of "a plurality of" is more than two. Understandings such as "greater than", "less than", "exceeding", etc. do not include the corresponding number, while understandings such as "above", "below", "within", etc. include the corresponding number. If there is a description of "first" and "second", it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0027] In the description of the present invention, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by "up", "down", "front", "back", "left", "right", etc., it is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation to the present invention.

[0028] In the present invention, unless otherwise clearly defined, terms such as "arrangement", "installation", "connection", etc. should be understood in a broad sense. For example, it can be directly connected, or indirectly connected through an intermediate medium; it can be fixedly connected, or detachably connected, or integrally formed; it can be mechanically connected; it can be the communication inside two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meaning of the above terms in the present invention in combination with the specific content of the technical solution.

[0029] Referring to Figures 1 to 6 , a bootstrap drive circuit includes an H-bridge circuit, a switching transistor Q1, a switching transistor Q5, an MOS transistor Q3, an MOS transistor Q7, a resistor R1, a resistor R5, a capacitor C2, and a capacitor C4;

[0030] The H-bridge circuit is composed of an upper tube formed by an MOS transistor Q2 and an MOS transistor Q4 and a lower tube formed by an MOS transistor Q6 and an MOS transistor Q8. The drain of the MOS transistor Q2 and the drain of the MOS transistor Q6 are connected to the VDC terminal, and the source of the MOS transistor Q4 and the source of the MOS transistor Q8 are connected to the GND terminal; in some embodiments, an inductor L1 and a capacitor C5 are further included. One end of the inductor L1 is respectively connected to the source of the MOS transistor Q2, the drain of the MOS transistor Q4, and the other end of the capacitor C2. The other end of the inductor L1 is respectively connected to the source of the MOS transistor Q6, the drain of the MOS transistor Q8, and the other end of the capacitor C4 through the capacitor C5. The inductor L1 is used as a wireless transmitting coil;

[0031] The input terminal of switching transistor Q1 is respectively connected to one end of resistor R1 and one end of capacitor C2 and is connected to the HVCC terminal. The control terminal of switching transistor Q1 is respectively connected to the other end of resistor R1 and the gate of MOS transistor Q3 and is connected to the PWM1 H signal. The output terminal of switching transistor Q1 is respectively connected to the gate of MOS transistor Q2 and the drain of MOS transistor Q3. The source of MOS transistor Q2 is respectively connected to the other end of capacitor C2 and the drain of MOS transistor Q4. The gate of MOS transistor Q4 is connected to the PWM 1L signal;

[0032] The input terminal of switching transistor Q5 is respectively connected to one end of resistor R5 and one end of capacitor C4 and is connected to the HVCC terminal. The control terminal of switching transistor Q5 is respectively connected to the other end of resistor R5 and the gate of MOS transistor Q7 and is connected to the PWM2H signal. The output terminal of switching transistor Q5 is respectively connected to the gate of MOS transistor Q6 and the drain of MOS transistor Q7. The source of MOS transistor Q6 is respectively connected to the other end of capacitor C5 and the drain of MOS transistor Q8. The gate of MOS transistor Q8 is connected to the PWM 1L signal;

[0033] The sources of MOS transistors Q3 and Q7 are connected to the GND terminal.

[0034] In the present invention, the PWM1 H signal and the PWM1 L signal are a pair of PWM signals with in-phase output and independently configured dead times for the rising edge and the falling edge. The PWM2H signal and the PWM2L signal are a pair of PWM signals with in-phase output and independently configured dead times for the rising edge and the falling edge. Here, taking the PWM1 L signal and the PWM 1H signal to drive the upper transistors composed of MOS transistors Q2 and Q4 as an example for illustration, the driving principle of the lower transistors composed of MOS transistors Q6 and Q8 is the same, and the present invention will not be elaborated further. Specifically:

[0035] ① The dead time for the rising edge is the time interval between turning off MOS transistor Q2 and turning on MOS transistor Q4. The dead time for the falling edge is the time interval between turning off MOS transistor Q4 and turning on MOS transistor Q2. The PWM1 L signal needs to have a strong driving ability (the larger the IO output current capacity, the shorter the charging and discharging time of the MOS transistor gate capacitance). According to the instantaneous current formula I = C iss *V / t for the charging and discharging of the MOS transistor gate, when the gate drive voltage of the MOS transistor is constant, the shorter the switching time t, the larger the drive current I, and MOS transistor Q4 can be directly driven faster. iss

[0036] Refer to Figures 1 - 5 ​(The arrow lines outside the circuit diagram in the attached drawings indicate the current flow direction). In some embodiments, a bootstrap drive circuit further includes a capacitor C1 and a resistor R2. One end of the capacitor C1 is connected to the gate of the MOS transistor Q3 and receives the PWM1 H signal, and the other end of the capacitor C1 is connected to the other end of the resistor R1 and the control terminal of the switching transistor Q1 through the resistor R2. A bootstrap drive circuit further includes a capacitor C3 and a resistor R6. One end of the capacitor C3 is connected to the gate of the MOS transistor Q7 and receives the PWM2H signal, and the other end of the capacitor C3 is connected to the other end of the resistor R5 and the control terminal of the switching transistor Q5 through the resistor R6. And the switching transistors Q1 and Q5 are configured as PNP triodes. Among them, the base of the switching transistor Q1 is connected in series with the resistor R2 and the capacitor C1 to isolate the PWM1 H signal from the high-voltage BST1, achieving the effect of driving high voltage with low voltage. In some embodiments, a bootstrap drive circuit further includes a diode D1. The anode of the diode D1 is connected to the HVCC terminal, and the cathode of the diode D1 is connected to one end of the capacitor C2, the input terminal of the switching transistor Q1, and one end of the resistor R1. In some other embodiments, a bootstrap drive circuit further includes a diode D2. The anode of the diode D2 is connected to the HVCC terminal, and the cathode of the diode D2 is connected to one end of the capacitor C4, the input terminal of the switching transistor Q5, and one end of the resistor R5. And the MOS transistors Q3 and Q7 are configured as NMOS transistors.

[0037] In the standby state, both the PWM1 L signal and the PWM1 H signal are low levels, and the HVCC terminal is a 5V DC voltage. At this time, the PNP triode Q1 is turned off, the NMOS transistor Q3 is turned off, and the NMOS transistors Q2 and Q4 are turned off.

[0038] ② Refer to Figures 1 - 2 and Figure 6 , the PWM startup sequence is as follows: The PWM1 H signal first outputs a high level. At this time, the NMOS transistor Q3 is turned on, the gate of the MOS transistor Q2 is pulled down to GND, and at the same time, the rising edge of the PWM1 H signal charges the base of the PNP triode Q1 through the path of the capacitor C1 and the resistor R2, turning off the PNP triode Q1 to prevent the PNP triode Q1 and the NMOS transistor Q3 from being turned on simultaneously.

[0039] ③ Refer to Figure 1 、 Figure 3 and Figure 6 , after a dead time has passed, the PWM1 L signal outputs a high level. At this time, the NMOS transistor Q4 is turned on, and the HVCC terminal charges the capacitor C2 through the path of the diode D1, the capacitor C2, the MOS transistor Q4, and GND.

[0040] ④ Refer to Figure 1 、 Figures 4 - 6After the PWM1 L signal lasts for a period of high level time, the PWM1 L signal outputs a low level to turn off the MOS transistor Q4.

[0041] 1) If the current direction of the inductor L1 is to the left at this time, then due to the turn-off of the MOS transistor Q4, the current of the inductor L1 will flow through the body diode of the MOS transistor Q2 and continue to flow towards VDC. At this time, the voltage of the SW1 node will quickly rise to VDC plus the voltage difference of the body diode of the MOS transistor Q2; at the same time, because the voltage across the capacitor C2 cannot change suddenly, the BST1 node will be raised to VDC + HVCC. The rise of the BST1 voltage makes the emitter voltage of the PNP transistor Q1 higher than the base voltage. The emitter of the PNP transistor Q1 discharges through the base of the PNP transistor, the resistor R2, the capacitor C1, and the PWM1 H signal path to generate a base current. Due to the existence of the resistor R2 and the capacitor C1, a certain delay is introduced for the turn-on of the PNP transistor Q1, and at the same time, the collector current of the PNP transistor Q1 is limited (I c = β * I b ). Because the PWM1 H signal is at a high level at this time and the NMOS transistor Q3 is in a conducting state, it is necessary to delay the turn-on of the PNP transistor Q1 and limit the collector current of the PNP transistor Q1.

[0042] After the PNP transistor Q1 conducts, the current discharges to GND through the NMOS transistor Q3. Therefore, after the PWM1 L signal outputs a low level, the PWM1 H signal needs to output a low level after a very short dead time. The dead time of this falling edge should meet certain requirements. If the dead time of the falling edges of the PWM1 L signal and the PWM1 H signal is too short, and because the time for the PWM1 H signal to turn off the NMOS transistor Q3 is faster than the time for the PWM1 L signal to turn off the MOS transistor Q4, during the process of the PWM1 L signal turning off the MOS transistor Q4, the NMOS transistor Q3 has already been turned off, and the BST1 voltage is boosted and raised. After the PNP transistor Q1 is turned on, it will drive the MOS transistor Q2 to conduct. The time interval between the turn-off of the MOS transistor Q4 and the turn-on of the MOS transistor Q2 is insufficient, which will have a direct conduction risk; if the dead time of the falling edges of the PWM1 L signal and the PWM1 H signal is too long, the longer the time for the PNP transistor Q1 and the NMOS transistor Q3 to conduct directly to GND, the lower the driving efficiency itself, and at the same time, the charge stored in the capacitor C2 will be discharged too much, resulting in a decrease in the driving voltage difference; when the present invention is applied, according to the measured actual time for the PWM1 L signal to drive and drop, a suitable dead time for the falling edge is set, while taking into account the driving efficiency and the driving delay of the MOS transistor Q2.

[0043] 2) If the current direction of inductor L1 is to the right at this time or the current of inductor L1 is 0, the voltage of node SW1 will be less than 0V at this time, and the voltage of node BST1 will not bootstrap and rise. After the dead time, when the PWM1 H signal outputs a low level, NMOS transistor Q3 turns off. At the same time, the base of PNP transistor Q1 discharges through resistor R2, capacitor C1, PWM1 H signal, and GND path, and PNP transistor Q1 turns on, driving MOS transistor Q2 to turn on.

[0044] ⑤ After the PWM1 H signal lasts for a period of low level time, since the BST1 node charges the base of the PNP transistor Q1 through resistor R1, the base voltage of the PNP transistor Q1 will gradually tend to the BST 1 voltage, causing the PNP transistor Q1 to turn off; it should be noted that the parameter selection of resistor R1, resistor R2, and capacitor C2 should enable the PNP transistor Q1 to quickly tend to cut-off. The base charging time constant (R1 + R2)*C2 of the PNP transistor Q1 should be less than the sum of the continuous low level time and the dead time, that is, turn off before the PWM1 H signal outputs a high level again; if the PNP transistor Q1 cannot turn off before the PWM1 H signal outputs a high level again, then when the PWM1 H signal outputs a high level, since there is no dead time between the turn-on of the NMOS transistor Q3 and the turn-off of the PNP transistor Q1, and the NMOS transistor Q3 is a MOS transistor with a faster turn-on speed than the turn-off speed of the PNP transistor Q1, the PNP transistor Q1 and the NMOS transistor Q3 will have a short time to conduct directly to GND, causing a short circuit.

[0045] ⑥ The present invention is tested on the IP6801 demo board and achieves the same driving effect as the integrated solution; the advantages of the present invention are: through the above circuit, independent driving control of the 4 MOS transistors of the H-bridge can be achieved when cooperating with a low-voltage withstand main control, realizing low-voltage PWM driving of a high-voltage H-bridge, having the advantages of fast switching speed, strong driving ability, and controllable dead time, solving the application limitations of low-voltage withstand main control, achieving high-efficiency and high-stability driving while reducing costs, and meeting the usage requirements.

[0046] Of course, the present invention is not limited to the above embodiments. Those skilled in the art can make equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations and substitutions are all included in the scope defined by the claims of this application.

Claims

1. A bootstrap drive circuit, characterized in that: It includes an H-bridge circuit, switching transistor Q1, switching transistor Q5, MOS transistor Q3, MOS transistor Q7, resistor R1, resistor R5, capacitor C2, and capacitor C4; The H-bridge circuit consists of an upper tube composed of MOS transistors Q2 and Q4 and a lower tube composed of MOS transistors Q6 and Q8. The drain of MOS transistor Q2 and the drain of MOS transistor Q6 are connected to the VDC terminal, and the source of MOS transistor Q4 and the source of MOS transistor Q8 are connected to the GND terminal; The input terminal of switching transistor Q1 is respectively connected to one end of resistor R1 and one end of capacitor C2 and is connected to the HVCC terminal. The control terminal of switching transistor Q1 is respectively connected to the other end of resistor R1 and the gate of MOS transistor Q3 and is connected to the PWM1 H signal. The output terminal of switching transistor Q1 is respectively connected to the gate of MOS transistor Q2 and the drain of MOS transistor Q3. The source of MOS transistor Q2 is respectively connected to the other end of capacitor C2 and the drain of MOS transistor Q4. The gate of MOS transistor Q4 is connected to the PWM 1L signal; The input terminal of switching transistor Q5 is respectively connected to one end of resistor R5 and one end of capacitor C4 and is connected to the HVCC terminal. The control terminal of switching transistor Q5 is respectively connected to the other end of resistor R5 and the gate of MOS transistor Q7 and is connected to the PWM2H signal. The output terminal of switching transistor Q5 is respectively connected to the gate of MOS transistor Q6 and the drain of MOS transistor Q7. The source of MOS transistor Q6 is respectively connected to the other end of capacitor C5 and the drain of MOS transistor Q8. The gate of MOS transistor Q8 is connected to the PWM 1L signal; The source of MOS transistor Q3 and the source of MOS transistor Q7 are connected to the GND terminal.

2. The bootstrap drive circuit according to claim 1, characterized in that: It further includes capacitor C1 and resistor R2. One end of capacitor C1 is connected to the gate of MOS transistor Q3 and is connected to the PWM1 H signal. The other end of capacitor C1 is respectively connected to the other end of resistor R1 and the control terminal of switching transistor Q1 through resistor R2.

3. The bootstrap drive circuit according to claim 1, characterized in that: It further includes capacitor C3 and resistor R6. One end of capacitor C3 is connected to the gate of MOS transistor Q7 and is connected to the PWM2H signal. The other end of capacitor C3 is respectively connected to the other end of resistor R5 and the control terminal of switching transistor Q5 through resistor R6.

4. A bootstrap drive circuit according to claim 1, characterized in that: It further includes diode D1. The anode of diode D1 is connected to the HVCC terminal, and the cathode of diode D1 is connected to one end of capacitor C2, the input terminal of switching transistor Q1, and one end of resistor R1.

5. The bootstrap driving circuit according to claim 1, wherein: It further includes diode D2. The anode of diode D2 is connected to the HVCC terminal, and the cathode of diode D2 is connected to one end of capacitor C4, the input terminal of switching transistor Q5, and one end of resistor R5.

6. The bootstrap drive circuit according to claim 1, wherein: The PWM1 H signal and the PWM1 L signal are a pair of PWM signals with in-phase output and independently configurable dead times for the rising edge and the falling edge. The PWM2H signal and the PWM2L signal are a pair of PWM signals with in-phase output and independently configurable dead times for the rising edge and the falling edge.

7. The bootstrap drive circuit according to claim 1, wherein: The switching transistors Q1 and Q5 are configured as triodes.

8. The bootstrap driving circuit according to claim 1, wherein: The MOS transistors Q3 and Q7 are configured as NMOS transistors.

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