A DSP-based motor control system and control method

Abstract

The application discloses a kind of motor control system and control method based on DSP, it is related to motor control technical field.The method includes the following steps: collecting armature voltage and current signal, and the voltage and current signal are pretreated;Motor position signal is collected, and position information is calculated according to motor position signal;According to position information, position loop is generated, current loop is generated according to current signal, and error calculation is carried out based on the double closed-loop control of current loop and position loop on two independent CPU kernels, wherein, CPU kernel 2 runs control algorithm to carry out error calculation, CPU kernel 1 carries out external communication and carries out the supervision and distribution of task based on dynamic task allocation method;According to the error generated by calculation, modulation signal is generated, and motor is controlled using modulation signal.The application combines control algorithm and external communication by separation, and fully improves the precision and rate of motor control.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of motor control, and in particular to a motor control system and control method based on DSP. BACKGROUND

[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.

[0003] With the development of electric vehicles, the algorithm of motor control needs to have the characteristics of fast response, small overshoot and good follow-up, so as to meet the requirements of high efficiency and high power density of motor control. The traditional DSP control scheme, represented by TMS320F28335 chip, only relies on the internal PWM, UART, ADC and other peripherals of DSP (digital signal processor) to realize the communication, sampling and control of the controller. The traditional TMS320F28335 control scheme needs to concentrate the external communication and control system in one kernel. The external communication is interrupted frequently, the data throughput load is heavy, and a large amount of memory and CPU (central processing unit) processing capacity is needed, which cannot realize higher computing speed. To solve this problem, the number of chips must be increased, and high-speed communication between chips must be established to realize real-time communication of the control level. However, the mainstream DSP has few high-speed data IO peripherals, which limits the expansion ability of multiple chips.

[0004] FPGA has the advantage of high-speed parallel hardware operation, can realize all high real-time control algorithms, control logic and communication functions, and can greatly meet the high-precision control strategy. Single FPGA control has good real-time performance, but the single FPGA architecture needs to design PWM modulation modules and other peripherals by itself. The difficulty of pre-development of FPGA development chip architecture is much higher than that of traditional DSP architecture, and the cost is also much higher.

[0005] In summary, how to obtain high-performance processing capability without introducing high-cost control chips such as FPGA, compressing development cost and shortening development cycle has become a technical problem to be solved in the prior art. SUMMARY

[0006] In view of the deficiencies in the prior art, the purpose of the present application is to provide a motor control system and control method based on DSP, which combines separate control algorithms and external communication, solves the problems of high difficulty and high cost of FPGA pre-development, and has higher performance processing capability than traditional DSP architecture, greatly improving the precision and speed of motor control.

[0007] In order to achieve the above purpose, the present application is realized by the following technical scheme:

[0008] The first aspect of the present application provides a DSP-based motor control method, comprising the following steps:

[0009] Collecting armature voltage and current signals, and pre-processing the voltage and current signals;

[0010] Collecting motor position signals, and calculating position information according to the motor position signals;

[0011] Generating a position loop according to the position information, generating a current loop according to the current signals, and performing error calculation based on the double closed-loop control of the current loop and the position loop on two independent CPU cores, wherein CPU core 2 runs a control algorithm to perform error calculation, and CPU core 1 performs external communication and supervises and allocates tasks based on the dynamic task allocation method;

[0012] Generating a modulation signal according to the calculated error, and controlling the motor using the modulation signal.

[0013] The second aspect of the present application provides a DSP-based motor control system, comprising:

[0014] An ADC module for collecting armature voltage and current signals, and pre-processing the voltage and current signals;

[0015] An EQEP module for collecting motor position signals, and calculating position information according to the motor position signals;

[0016] A CPU core 2 module for generating a position loop according to the position information, generating a current loop according to the current signals, and performing error calculation based on the double closed-loop control of the current loop and the position loop;

[0017] An ePWM module for generating a modulation signal according to the calculated error, and controlling the motor using the modulation signal.

[0018] The third aspect of the present application provides a medium having a program stored thereon, wherein the program is executed by a processor to implement the steps in the DSP-based motor control method according to the first aspect of the present application.

[0019] The fourth aspect of the present application provides a device comprising a memory, a processor, and a program stored on the memory and executable on the processor, wherein the processor executes the program to implement the steps in the DSP-based motor control method according to the first aspect of the present application.

[0020] The fifth aspect of the present application provides a computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the steps in the DSP-based motor control method according to the first aspect of the present application.

[0021] The one or more technical solutions have the following beneficial effects:

[0022] The application discloses a motor control system and a control method based on a DSP, aiming at improving the precision and efficiency of motor control.

[0023] The application has the characteristics of fast response, small overshoot and good follow-up performance.

[0024] The application has the characteristics of fast response, small overshoot and good follow-up performance.

[0025] The application has the characteristics of fast response, small overshoot and good follow-up performance.

[0026] Advantages of additional aspects of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which constitute a part of this specification, are included to provide a further understanding of the application, and are incorporated by reference in their entirety into the present disclosure.

[0028] Figure 1 Flow chart of the DSP-based motor control method in the embodiment one of the application;

[0029] Figure 2 Structural diagram of the DSP-based motor control system in the embodiment two of the application. DETAILED DESCRIPTION

[0030] It should be noted that the following detailed description is merely exemplary and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0031] It is to be understood that the terminology used herein is for the purpose of describing the particular embodiments only and is not intended to be limiting of the example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0032] Embodiment one:

[0033] The embodiment one of the application provides a DSP-based motor control method, as shown in the figure, comprising the following steps: Figure 1

[0034] Step 1: Collecting the armature voltage and current signals, and pre-processing the voltage and current signals.

[0035] The pre-processing step includes linear transformation and reduction of the collected signals.

[0036] In a specific embodiment, the on-chip 16-bit ADC module is used to collect the armature voltage and current signals of the motor. The ADC module provides high-precision sampling capability, ensuring the accuracy of the input data.

[0037] ​Since the ADC acquisition range of the DSP chip is only 0-3.3V, the collected analog signal is a signal processed by the AFE (Analog Front End), which is first linearly transformed and then sent to the current loop algorithm to obtain the PWM modulation signal. The PPB (Post-Processing Block) in the ADC module has an over-voltage and over-current protection function, which can directly shut off the PWM module output; at the same time, it supports fault output and shutdown input, which can directly shut off the PWM module output.

[0038] Step 2: Collect the motor position signal and calculate the position information according to the motor position signal. After comparison with the predetermined position, the position error is generated as the input signal of the current loop to generate the current loop control signal.

[0039] In a specific embodiment, the motor position signal is obtained through a motor encoder, and a three-wire incremental encoder is used. The motor rotation angle is obtained by counting the number of A and B phase pulses, and the Z phase is used to indicate the initial count. The Z phase high level pulse can clear the A and B phase pulse counters. The motor rotation direction is identified by the A and B phase phase relationship.

[0040] Step 3: Generate the position loop according to the position information, and generate the current loop according to the current signal. The dynamic task allocation method is used in two independent CPU cores to perform error calculation based on the double closed-loop control of the current loop and the position loop.

[0041] Among them, the tasks are allocated in two independent CPU cores, CPU core 2 runs the control algorithm to perform error calculation, and CPU core 1 completes human-computer interaction and data processing. Specifically, external communication and task supervision and allocation based on the dynamic task allocation method are performed.

[0042] In a specific embodiment, the CPU core 1 and the CPU core 2 of the dual-core DSP28377D are responsible for external communication and control algorithm respectively, and the cores communicate through the IPC communication protocol. This design supports real-time processing of large data, greatly improving the real-time performance, flexibility, computing power and computing accuracy of the controller. At the same time, the modulation of the PWM control signal is completed by a separate PWM peripheral, without the need for independent development, greatly reducing the development cycle and development cost.

[0043] In the control scheme, CPU core 2 (CORE2) focuses on executing the motor control algorithm. This includes double closed-loop control of the current loop and the position loop. The current loop is used to adjust the torque output of the motor, while the position loop is used to ensure that the motor operates according to the predetermined trajectory.

[0044] The initial motor speed is 0, and the soft start algorithm is started to be executed. The armature voltage and current are sampled cycle by cycle, the PWM output duty cycle is dynamically controlled, and the current, voltage and power during starting are controlled. After starting to the rated current and voltage, the soft start is ended, and the position loop and current loop double closed loop algorithm is started to be executed. According to the set current reference value and the actually collected current value, the CPU kernel 2 uses the PI or PID control algorithm to adjust the current error and generates the PWM modulation signal. The position loop compares the actual position of the motor with the target position, calculates the position error, and adjusts the output of the current loop according to the error. At the same time, when overcurrent, overvoltage and external fault inputs are detected, the PWM is immediately turned off. After the corresponding event occurs, the cycle-by-cycle overcurrent protection algorithm is started to be executed. Through the intermittent output of low frequency and positive narrow pulse by the PWM module, if the overcurrent and overvoltage events still exist, the PWM output is turned off; if the overcurrent and overvoltage events disappear, the soft start algorithm is started to be executed again until the motor works normally.

[0045] In the process of error calculation, a dynamic task allocation method with interrupt nesting mechanism is designed in the embodiment. Specifically, a real-time operating system is run in the CPU kernel 1 to monitor the load states of the double CPU kernels and the double CLAs. Interrupt service programs are preset in the CLAs to respectively complete tasks such as current loop, position loop, FOC and SVPWM modulation. The CPU kernel 1 monitors the occupation state of the CPU kernel 2. If the CPU kernel 2 is full, the task allocation of CLA1 and CLA2 is regulated by starting a specified interrupt. If the CPU kernel 2 is idle, the tasks are preferentially arranged to be executed by the CPU kernel 2. The CPU kernel 1 works in a low main frequency state without external communication. After the UART interrupt is started, the CPU kernel 1 is restored to the maximum main frequency to execute the communication data carrying and man-machine interaction functions and then returns to the low main frequency mode.

[0046] According to the corresponding rates of the algorithms and the real-time performance of the interrupt functions, the interrupt nesting mechanism is divided into three priorities: the hardware protection of the CMPSS is the highest priority to ensure the safety of the system; the current loop algorithm is the second priority; and the position loop algorithm is the third priority. The corresponding interrupt priorities are realized by dynamically controlling the interrupt vector table of the CPU kernel 1 to bind the interrupt priorities and the tasks and dynamically control the interrupt priorities. The CPU kernel 1 first queries the state of the CPU kernel 2 to determine whether to allocate tasks to CLA1 and CLA2. If tasks are allocated to CLA1 and CLA2, the allocation objects and specific allocation tasks are determined. After the allocation tasks are determined, the interrupt vectors of CLA1 or CLA2 in the interrupt vector table are assigned to the addresses of the corresponding processing functions, and then the interrupt is triggered by the CPU kernel 1 to execute the corresponding functions in CLA1 or CLA2.

[0047] Based on the above dynamic task allocation method, a low-delay three-level protection mechanism is designed in the embodiment. The first level is hardware protection based on the on-chip CMPSS (window comparator) of TMS320F28377D. The second level is fault diagnosis of the interrupt service program based on CLA (control law accelerator). The third level is lockstep operation, on-site protection and system recovery based on the CPU kernel.

[0048] Among them, CMPSS faces element-level faults, including overcurrent, overvoltage, and overtemperature of power devices. CLA faces device-level faults, including harmonic overlimiting and power device damage. The CPU kernel faces program protection, including lockstep operation, on-site protection, and backup cut-in. CMPSS monitors the current and voltage of the device. When part of the data exceeds the threshold, CMPSS applies for an interrupt to CLA and the CPU kernel, CLA starts fault diagnosis to determine the working state of the power device. For a burned-out power device, the PWM output is directly turned off. For a normal power device, the CPU kernel performs backup cut-in, continuously observes the output power, and if the overcurrent fault disappears, only the data is uploaded without turning off the PWM output. If the overcurrent state still exists, the PWM output is turned off and the fault state is uploaded. CLA performs a fixed-point FFT algorithm to monitor the current harmonic. If the harmonic exceeds 5%, CLA applies for an interrupt to the CPU kernel, uploads the fault state, and does not turn off the PWM output. Temperature control is completed by CMPSS and CLA. The main control temperature is monitored by CLA and the on-chip ADC, and the power device temperature is monitored by CMPSS. After the power device overheats, CMPSS applies for an interrupt to CLA, CLA determines the current state, and if the forced cooling is not turned on, the external cooling is turned on. If the overheating state still exists, the PWM output is turned off and the fault state is reported to the CPU kernel. The main control temperature is monitored by CLA. The on-chip ADC collects the temperature of the main control chip. After the main control overheating event occurs, the ADC applies for an interrupt to CLA, and CLA controls the forced cooling to be turned on first. After the forced cooling is turned on, if the overheating event still exists, the main control chip is gradually downclocked by 5% of the rated frequency. Program fault detection is completed by the dual-core CPU kernel. The hardware lockstep operation is performed in the CPU kernel. For the current loop and position loop control algorithms, the dual cores are synchronously executed, the output results are compared by CPU kernel 2, and the consistent comparison results are sent to the PWM module for modulation output. If the comparison results are inconsistent, the PWM output is turned off and the state register data in the CPU kernel is transferred to the external ROM. At the same time, under normal operation, the CPU kernel controls the external RAM to save the sampling data within 1s. After the CPU kernel receives the fault interrupt, the data is immediately transferred to the external ROM for saving and uploaded through the serial port, completing the on-site protection.

[0049] In combination with the above-mentioned dynamic task allocation method, the calculation tasks are evenly divided to the CPU kernel 2, CLA1 and CLA2, so that the algorithm is processed by three cores in parallel, further improving the algorithm execution rate and improving the control performance. At the same time, through the three-level fault protection mechanism, the influence of the fault state on the motor is reduced, and through the on-site protection function of the CPU kernel, the obstacle processing is simplified.

[0050] Step 4: generate a modulation signal according to the calculated error, and control the motor by using the modulation signal.

[0051] In a specific embodiment, as shown in Figure 2 The reference signal generated by the control algorithm is transmitted to the on-chip ePWM module. The module generates 24-way PWM output signals according to the input signals. The PWM signal is converted to a 5V square wave after level conversion. The PWM signal is directly used to control the power electronic devices in the inverter circuit. Through accurate PWM signal modulation, accurate control of motor speed, direction and torque is realized.

[0052] In this embodiment, the controller uses IIC, SPI and CAN communication protocols to exchange data with other controllers and devices, ensuring efficient communication within and outside the system. The equipped 2-way UART interface is used for data and instruction interaction with the host computer, facilitating system monitoring and parameter adjustment.

[0053] Example two:

[0054] Example two of the present application provides a DSP-based motor control system, as shown in Figure 2 A high-performance motor controller software architecture based on TI's DSP chip is developed, which aims to improve the accuracy and efficiency of motor control. The DSP (TMS320F2837xD, TMS320F2838xD, etc.) chip integrates two C2000 cores, and the cores communicate through IPC and shared RAM. CPU core 1 completes human-computer interaction and data processing, and CPU core 2 runs the control algorithm. Through the dual-core DSP architecture, combined with high-precision signal acquisition and diversified control signal output capabilities. Through this innovative design, the controller realizes high-speed data processing and flexible communication interface, which can effectively cope with complex control tasks. At the same time, its modular hardware design and powerful processing performance provide reliable technical support for industrial automation applications.

[0055] In the architecture, the dual-core processor works with a heterogeneous multi-processing (AMP) architecture. CPU core 1 (CORE1) is responsible for communication interaction and the running of the on-chip operating system, while the motor control algorithm is executed on CPU core 2 (CORE2). The two CPU cores communicate through an IPC (Inter-Processor Communication) peripheral, ensuring that communication functions and real-time processing tasks are independent of each other, improving the overall controller's processing capability.

[0056] The specific structure includes:

[0057] The ADC module is used to collect the armature voltage and current signals and preprocess the voltage and current signals. The on-chip 16-bit ADC module is used to collect the armature voltage and current signals of the motor. The ADC module provides high-precision sampling capability to ensure the accuracy of the input data. Since the ADC module is integrated inside the chip, CPU core 1 and CPU core 2 can directly access its registers, efficiently reading and processing signal data.

[0058] The peripheral module is used to collect the motor position signal and calculate the position information based on the motor position signal. In the control scheme, CPU core 2 (CORE2) focuses on executing the motor control algorithm. This includes double-loop control of the current loop and the position loop. The current loop is used to adjust the torque output of the motor, while the position loop is used to ensure that the motor runs according to the predetermined trajectory.

[0059] The enhanced quadrature encoder pulse (eQEP) peripheral is used. This module is designed specifically for incremental encoder signal processing, and CPU core 1 and CPU core 2 access the eQEP registers to obtain accurate position information.

[0060] The position signal of the motor is processed through the enhanced quadrature encoder pulse (eQEP) built into the DSP. The eQEP is designed specifically for incremental encoders and can accurately capture the position information of the motor, which is particularly important for the position control loop.

[0061] The CPU core 2 module is used to generate a position loop based on the position information and a current loop based on the current signal, and to perform error calculation using double-loop control based on the current loop and the position loop.

[0062] Based on the set current reference value and the actual collected current value, CPU core 2 uses a PI or PID control algorithm to adjust the current error and generate a PWM modulation signal. The position loop compares the actual position of the motor with the target position, calculates the position error, and adjusts the output of the current loop based on the error.

[0063] The ePWM module is used to generate a modulation signal based on the calculated error and control the motor using the modulation signal.

[0064] The reference signal generated by the control algorithm is transmitted to the ePWM module on the chip. The module generates 24-way PWM output signals according to the input signals. The PWM signals are output as 5V square waves after level conversion, which are suitable for driving the inverter circuit on the controller backplane. The PWM signals are directly used to control the power electronic devices in the inverter circuit. Through accurate PWM signal modulation, accurate control of the motor speed, direction and torque is realized.

[0065] The controller uses communication protocols such as IIC, SPI and CAN to exchange data with other controllers and devices, ensuring efficient communication within and outside the system. The 2-way UART interface is used for data and instruction interaction with the host computer, facilitating system monitoring and parameter adjustment.

[0066] The embodiment designs a new PWM control logic for devices with partial CLB (Configurable Logic Block) (such as TMS320F28379D), which supports instantaneous shutdown and error output, improves system scalability and safety. By designing a software AD CPPB (ADC post-processing block) module, the CPU core calculation overhead is reduced, and hardware overcurrent and overvoltage protection is realized. The PWM modulation signal output is directly turned off through the post-processing block, further improving system safety.

[0067] The embodiment makes CPU core 1 and CPU core 2 of dual-core DSP28377D responsible for external communication and control algorithm respectively, and communicates through IPC communication protocol. This design supports real-time processing of large data, greatly improving the real-time performance, flexibility, computing power and computing accuracy of the controller. At the same time, the modulation of the PWM control signal is completed by a separate PWM peripheral, without the need for independent development, greatly reducing the development cycle and development cost.

[0068] Embodiment three:

[0069] The embodiment three of the present application provides a medium having a program stored thereon, and the program is executed by a processor to realize the steps in the DSP-based motor control method of the embodiment one of the present application.

[0070] Embodiment four:

[0071] The embodiment four of the present application provides a device including a memory, a processor and a program stored in the memory and executable on the processor, and the processor executes the program to realize the steps in the DSP-based motor control method of the embodiment one of the present application.

[0072] Embodiment five:

[0073] The embodiment five of the present application provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the DSP-based motor control method according to the embodiment one of the present application.

[0074] The steps and methods involved in the above embodiments two, three, four and five correspond to the embodiment one, and the specific implementation can refer to the relevant description of the embodiment one. The term "computer readable storage medium" should be understood as including a single medium or multiple media of one or more instruction sets; it should also be understood as including any medium capable of storing, encoding or carrying the instruction set for execution by the processor and causing the processor to perform any of the methods of the present application.

[0075] Those skilled in the art should understand that the above-mentioned modules or steps of the present application can be realized by a general computer device, alternatively, they can be realized by program codes executable by a computing device, so that they can be stored in a storage device for execution by a computing device, or they can be respectively manufactured into individual integrated circuit modules, or a plurality of modules or steps among them can be manufactured into a single integrated circuit module to realize. The present application is not limited to any specific combination of hardware and software.

[0076] Although the specific embodiments of the present application are described above in combination with the accompanying drawings, it is not a limitation on the protection scope of the present application, and those skilled in the art should understand that various modifications or changes made by those skilled in the art on the basis of the technical solutions of the present application without creative labor are still within the protection scope of the present application.

Claims

1. A DSP-based motor control method, characterized in that, Includes the following steps: Armature voltage and current signals are acquired and preprocessed. Collect motor position signals and calculate position information based on the motor position signals; Error calculation is performed on two independent CPU cores using a dynamic task allocation method based on dual closed-loop control of the current loop and position loop. CPU core 2 runs the control algorithm for error calculation, while CPU core 1 handles external communication and task supervision and allocation based on the dynamic task allocation method. The specific steps are as follows: The CPU core 1 runs a real-time operating system that monitors the load status of the dual CPU cores and dual CLAs. Specifically, the CLA has a preset interrupt service routine that completes the current loop, position loop, FOC, and SVPWM modulation tasks respectively. The CPU core 1 monitors the occupancy status of the CPU core 2. If the CPU core 2 is fully loaded, the task allocation between CLA1 and CLA2 is adjusted by triggering a specified interrupt. If the CPU core 2 is idle, the processing tasks will be prioritized for execution on the CPU core 2. A modulation signal is generated based on the calculated error, and the motor is controlled using the modulation signal.

2. The DSP-based motor control method as described in claim 1, characterized in that, The voltage and current signals are preprocessed to perform linear transformation and restoration on the acquired signals.

3. The DSP-based motor control method as described in claim 1, characterized in that, The specific steps for calculating position information based on the motor position signal are as follows: The motor position signal is obtained through the motor encoder; The motor rotation angle is obtained by counting the number of pulses in phases A and B. The direction of motor rotation is determined by the phase relationship between phases A and B.

4. The DSP-based motor control method as described in claim 2, characterized in that, An interrupt nesting mechanism is introduced into the dynamic task allocation method, and the interrupt nesting mechanism is divided into three priorities: CMPSS hardware protection is the highest priority to ensure system security; the current loop algorithm is the second priority. The position loop algorithm is the third priority.

5. The DSP-based motor control method as described in claim 1, characterized in that, Based on the above dynamic task allocation method, a low-latency three-level protection mechanism is equipped. The first level is hardware protection based on the on-chip CMPSS of TMS320F28377D, the second level is fault diagnosis of interrupt service routine based on CLA, and the third level is lockstep operation, context protection and system recovery based on CPU core.

6. A DSP-based motor control system, characterized in that, include: The ADC module is used to acquire armature voltage and current signals and to preprocess the voltage and current signals. The peripheral module is used to acquire motor position signals and calculate position information based on the motor position signals; CPU Core 2 module is used to generate a position loop based on position information and a current loop based on current signals. Error calculation is performed using dual closed-loop control based on the current and position loops. Specifically, CPU Core 2 runs the control algorithm for error calculation, while CPU Core 1 handles external communication and task supervision and allocation based on a dynamic task allocation method. The specific steps are as follows: The CPU core 1 runs a real-time operating system that monitors the load status of the dual CPU cores and dual CLAs. Specifically, the CLA has a preset interrupt service routine that completes the current loop, position loop, FOC, and SVPWM modulation tasks respectively. The CPU core 1 monitors the occupancy status of the CPU core 2. If the CPU core 2 is fully loaded, the task allocation between CLA1 and CLA2 is adjusted by triggering a specified interrupt. If the CPU core 2 is idle, the processing tasks will be prioritized for execution on the CPU core 2. The ePWM module is used to generate a modulation signal based on the calculated error, and then use the modulation signal to control the motor.

7. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the DSP-based motor control method according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, It stores multiple instructions, which are adapted to be loaded by the processor of the terminal device and executed by the DSP-based motor control method according to any one of claims 1-5.

9. A terminal device, characterized in that, The method includes a processor and a computer-readable storage medium, wherein the processor implements various instructions; and the computer-readable storage medium stores multiple instructions adapted to be loaded by the processor and executed by the processor in any one of claims 1-5.

Images