Rail-to-rail operational amplifier and input stage circuit thereof

Abstract

The invention provides a rail-to-rail operational amplifier and an input stage circuit thereof. An input stage circuit for a rail-to-rail operational amplifier includes: a complementary differential pair to provide a differential input to the operational amplifier; the tail current sampling circuit is used for sampling tail current in the circuit; the upper end negative feedback current mirror is used for performing current adjustment based on the sampled tail current and feeding back the tail current to the complementary differential pair; the lower end negative feedback current mirror performs current adjustment based on the sampled tail current and feeds back the tail current to the complementary differential pair; the bidirectional current source is used for providing current for the upper end negative feedback current mirror and the lower end negative feedback current mirror; the upper end active load is used for receiving the output of the complementary differential pair and is connected to an output end; and the lower end active load receives the output of the complementary differential pair and is connected to the output end. An active device load with transconductance irrelevant to input voltage and a tail current negative feedback compensation technology are adopted, so that harmonic distortion is reduced or avoided.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a rail-to-rail operational amplifier and its input stage circuit. Background Art

[0002] With the development of semiconductor technology, most operational amplifiers (abbreviated as "op-amps") exist in the form of single chips. There are various types of op-amps, which are widely used in the electronics industry. In an actual circuit, it usually combines with a feedback network to form a certain functional module. In addition, it is an amplifier with a special coupling circuit and feedback. Its output signal can be the result of mathematical operations such as addition, subtraction, differentiation, or integration of the input signal. Since it was originally used in analog computers to perform mathematical operations, it got the name "operational amplifier".

[0003] Integrated operational amplifiers, especially high-precision operational amplifiers, often need to reduce harmonic distortion. Among them, for an operational amplifier, the change in the transconductance of the devices on the signal path is an important cause of harmonic distortion. Specifically, due to the different Early voltages of NPN and PNP transistors, as the input voltage changes, the input-stage transconductance changes proportionally, thus introducing distortion. Therefore, an operational amplifier that can effectively solve the distortion problem caused by a varying input voltage is needed. Summary of the Invention

[0004] Aiming at the deficiencies in the prior art, the present invention provides a rail-to-rail operational amplifier and its input stage circuit, which mainly solves the problem that there is a lack of an operational amplifier in the prior art that can effectively solve the distortion problem caused by a varying input voltage.

[0005] The object of the present invention is achieved through the following solutions:

[0006] In a first aspect, according to an embodiment of the present invention, there is provided an input stage circuit for a rail-to-rail operational amplifier, including: a complementary differential pair for providing a differential input to the operational amplifier; a tail current sampling circuit for sampling the tail current in the circuit; an upper-end negative feedback current mirror for adjusting the current based on the sampled tail current and feeding it back to the complementary differential pair; a lower-end negative feedback current mirror for adjusting the current based on the sampled tail current and feeding it back to the complementary differential pair; a bidirectional current source for providing current to the upper-end negative feedback current mirror and the lower-end negative feedback current mirror; an upper-end active load for receiving the output of the complementary differential pair and connecting it to the output terminal; a lower-end active load for receiving the output of the complementary differential pair and connecting it to the output terminal.

[0007] According to an embodiment of the present invention, the complementary differential pair includes: a first N-type transistor, whose base is connected to the positive input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the upper active load; a second N-type transistor, whose base is connected to the negative input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the upper active load; a first P-type transistor, whose base is connected to the positive input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the lower active load; a second P-type transistor, whose base is connected to the negative input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the lower active load.

[0008] According to an embodiment of the present invention, the input voltage sampling circuit includes: a seventh N-type transistor, whose base is connected to the complementary differential pair, whose emitter is connected to the emitter of a seventh P-type transistor, and whose collector is connected to the upper negative feedback current mirror; a seventh P-type transistor, whose base is connected to the complementary differential pair, and whose collector is connected to the lower negative feedback current mirror.

[0009] According to an embodiment of the present invention, the upper negative feedback current mirror includes: a third P-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the positive power supply, and whose collector is connected to the complementary differential pair; a fourth P-type transistor, whose base and collector are connected to the tail current sampling circuit, and whose emitter is connected to the positive power supply; a fifth P-type transistor, whose base is connected to the tail current sampling circuit, whose emitter is connected to the positive power supply, and whose collector is connected to the bidirectional current source; a sixth P-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the positive power supply.

[0010] According to an embodiment of the present invention, the lower negative feedback current mirror includes: a third N-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the negative power supply, and whose collector is connected to the complementary differential pair; a fourth N-type transistor, whose base and collector are connected to the tail current sampling circuit, and whose emitter is connected to the negative power supply; a fifth N-type transistor, whose base is connected to the tail current sampling circuit, whose emitter is connected to the negative power supply, and whose collector is connected to the bidirectional current source; a sixth N-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the negative power supply.

[0011] According to an embodiment of the present invention, the bidirectional current source includes: an eighth P-type transistor, whose base is connected to a reference voltage, whose emitter is connected to a positive power supply through a first resistor and a first current source, and whose collector is connected to a negative power supply; an eighth N-type transistor, whose base is connected to the reference voltage, whose emitter is connected to the negative power supply through a second resistor and a second current source, and whose collector is connected to the positive power supply; a ninth P-type transistor, whose base is connected between the second resistor and the second current source, whose emitter is connected to the emitter of a ninth N-type transistor through a third resistor, and whose collector is connected to a lower negative feedback current mirror; a ninth N-type transistor, whose base is connected between the first resistor and the first current source, and whose collector is connected to an upper negative feedback current mirror; a tenth P-type transistor, whose base is connected between the second resistor and the second current source, whose emitter is connected to the emitter of a tenth N-type transistor through a fourth resistor, and whose collector is connected to the lower active load; a tenth N-type transistor, whose base is connected between the first resistor and the first current source, and whose collector is connected to an upper active load.

[0012] According to an embodiment of the present invention, the upper active load includes: an eleventh P-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the positive power supply through a fifth resistor; a twelfth P-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the positive power supply through a sixth resistor, and whose collector is connected to the output terminal.

[0013] According to an embodiment of the present invention, the lower active load includes: an eleventh N-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the negative power supply through a seventh resistor; a twelfth N-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the negative power supply through the seventh resistor, and whose collector is connected to the output terminal.

[0014] Second aspect, according to another embodiment of the present invention, there is provided a rail-to-rail operational amplifier, including an input-stage circuit for a rail-to-rail operational amplifier as described in the first aspect, and further comprising: a fourteenth P-type transistor, whose base and collector are connected to the base and collector of a fourteenth N-type transistor, and whose emitter is connected to the positive power supply via a ninth resistor; a fourteenth N-type transistor, whose emitter is connected to the negative power supply via a tenth resistor; a fifteenth P-type transistor, whose base is connected between the upper active load and the lower active load, whose emitter is connected to the positive power supply via a third current source, and whose collector is connected to the negative power supply; a fifteenth N-type transistor, whose base is connected between the upper active load and the lower active load, whose emitter is connected to the negative power supply via a fourth current source, and whose collector is connected to the positive power supply; a sixteenth N-type transistor, whose base is connected to the emitter of the fifteenth P-type transistor, whose emitter is connected to the output terminal, and whose collector is connected to the positive power supply; a sixteenth P-type transistor, whose base is connected to the emitter of the fifteenth N-type transistor, whose emitter is connected to the output terminal, and whose collector is connected to the negative power supply.

[0015] Compared with the prior art, the present invention has the following beneficial effects: By using active device loads whose transconductances are independent of the input voltage, distortion introduced by changes in the input voltage can be avoided; in addition, after adopting the tail current negative feedback compensation technique, the change in the transconductance of the differential pair is greatly reduced, and the feedback coefficient can be adjusted by the ratio of the emitters of each transistor, thereby adjusting the harmonic distortion of the input stage. Description of the Drawings

[0016] The embodiments of the present invention will be further described with reference to the following drawings:

[0017] Figure 1 is the circuit schematic diagram of a rail-to-rail operational amplifier in the prior art;

[0018] Figure 2 is the circuit schematic diagram of the input-stage circuit of the embodiment of the present invention;

[0019] Figure 3 is the circuit schematic diagram of the rail-to-rail operational amplifier of the embodiment of the present invention. Detailed Embodiments

[0020] Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "coupled," "connected," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "comprise" and "include," and their derivatives, mean including but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with," and its derivatives, mean including, included within, interconnected, containing, contained within, connected or connected to, coupled or coupled to, communicating with, cooperating with, interlacing, juxtaposed, adjacent, bound or bound to, having, having an attribute, having a relationship or having a relationship with, etc. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller can be implemented in hardware, or in a combination of hardware and software and / or firmware. The functions associated with any particular controller can be centralized or distributed, whether local or remote. The phrase "at least one," when used in conjunction with a list of items, means that different combinations of one or more of the listed items can be used, and it may only be necessary to have one item from the list. For example, "at least one of A, B, C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0021] Definitions of other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that, in many cases, if not most cases, such definitions apply to the prior and future use of the words and phrases so defined.

[0022] In this patent document, the application combination of modules and the hierarchical division of sub-modules are only for illustration purposes. Without departing from the scope of this disclosure, the application combination of modules and the hierarchical division of sub-modules can have different forms.

[0023] In order to make the objectives, technical solutions, and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0024] To better understand the present invention, first review the rail-to-rail operational amplifier in the prior art.

[0025] As Figure 1As shown, it is a typical rail-to-rail operational amplifier circuit, in which N1, N2, P1, and P2 form a complementary differential pair of the input stage, P3 and N3 form the tail current, R1, R2, P4, and P5 form the upper active load, R3, R4, N4, and N5 form the lower active load, A is the post-stage drive circuit, and Vref is a fixed voltage.

[0026] In the present invention, PX represents a certain PNP device (such as, P1, P2, etc., that is, the first P-type transistor, the second P-type transistor, etc.), where P represents the PNP bipolar transistor symbol, and X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; NX represents a certain NPN device (such as, N1, N2, etc., that is, the first N-type transistor, the second N-type transistor, etc.), where N represents the NPN bipolar transistor symbol, and X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; RX represents a certain resistor element (such as, R1, R2, etc., that is, the first resistor, the second resistor, etc.), where R represents the resistor element symbol, and X represents the element number, which are Arabic numerals such as 1, 2, 3, etc.; VCC is the positive power supply of the chip, VEE is the negative power supply of the chip; IN+ is the positive input terminal of the operational amplifier, IN- is the negative input terminal of the operational amplifier, and OUT is the output terminal of the operational amplifier.

[0027] Such as Figure 1 As shown, the input stage of the typical rail-to-rail operational amplifier circuit provides high gain, so there is no need to add an additional separate gain stage.

[0028] Such as Figure 1 As shown, for matching considerations, generally, I P3C = I N3C , R1 = R2 = R3 = R4, K N1N2 = K P1P2 = K N4N5 = K P4P5 = 1, I P4C = I P5C = I N4C = I N5C .

[0029] In the present invention, I PXY represents the current of a certain port of a PNP device, where I represents the current symbol, and in the subscript PXY, P represents the PNP bipolar transistor symbol, X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; Y represents the port of the device, which are C (collector), B (base), and E (emitter) respectively. I NXYRepresents the current of a certain port of an NPN device, where I represents the current symbol, and in the subscript NXY, N represents the NPN bipolar transistor symbol, X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; Y represents the port of the device, which are C (collector), B (base), and E (emitter) respectively.

[0030] In the present invention, K XYXZ Represents the ratio of the emitter areas of bipolar transistor devices XY and XZ, where X represents the device type, which is P or N; X and Y respectively represent the numbers of two active devices, which are Arabic numerals such as 1, 2, 3, etc.

[0031] In the present invention, R X Represents the resistance value of the resistor element RX, where R represents the resistor element symbol, and X represents the resistor element number, which are Arabic numerals such as 1, 2, 3, etc.

[0032] For a bipolar transistor operating in the amplification region, its transconductance is equal to:

[0033]

[0034] Where I C Is the collector current; V T Is the thermal voltage, which is approximately 26 mV at room temperature.

[0035] As Figure 1 Shown, because it is designed that I P3C = I N3C And K N1N2 = K P1P2 = 1, so the transconductance of both NPN and PNP differential pairs is:

[0036]

[0037] In the present invention, g PX Represents the transconductance of a PNP device operating in the amplification region. Here, g represents the transconductance symbol, and in the subscript PX, P represents the PNP bipolar transistor symbol, and X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.; g NX Represents the transconductance of an NPN device operating in the amplification region. Here, g represents the transconductance symbol, and in the subscript NX, N represents the NPN bipolar transistor symbol, and X represents the device number, which are Arabic numerals such as 1, 2, 3, etc.

[0038] As Figure 1 Shown, because it is designed that I P4C = I P5C = I N4C = I N5C , so:

[0039]

[0040] As Figure 1 shown, let the output current of the input stage be:

[0041] I O = I P5C - I N5C .

[0042] As Figure 1 shown, the output current is:

[0043]

[0044] Therefore, the transconductance of the input stage is equal to:

[0045]

[0046] As Figure 1 shown, since the transconductance of the bipolar transistor is very large, so g P4 R1 > 1, thus:

[0047]

[0048] As Figure 1 shown, when the input voltage changes by ΔV IN , due to the effect of the Early effect, the collector current of N3 becomes:

[0049]

[0050] The collector current of P3 becomes:

[0051]

[0052] In the present invention, V EP represents the Early voltage of the PNP device; V EN represents the Early voltage of the NPN device.

[0053] As Figure 1 shown, when the input voltage changes by ΔV IN , the transconductance of N1 and N2 becomes:

[0054]

[0055] As Figure 1 shown, when the input voltage changes by ΔV IN , the transconductance of P1 and P2 becomes:

[0056]

[0057] As Figure 1 shown, when the input voltage changes by ΔVIN When it is, the collector currents of P4, P5, N4, and N5 become:

[0058]

[0059]

[0060] As Figure 1 shown, when the input voltage changes by ΔV IN the transconductances of P4, P5, N4, and N5 become:

[0061]

[0062] As Figure 1 shown, when the input voltage changes by ΔV IN the input-stage transconductance becomes:

[0063]

[0064] Wherein,

[0065]

[0066] Therefore,

[0067]

[0068] As Figure 1 shown, to ensure the same slew rate, it is generally designed that:

[0069]

[0070] Therefore,

[0071]

[0072] Thus:

[0073]

[0074] As Figure 1 shown, when the input voltage changes by ΔV IN the change in the input-stage transconductance is:

[0075]

[0076] As Figure 1 shown, due to the different Early voltages of NPN and PNP, as the input voltage changes, the input-stage transconductance will change proportionally, thus introducing distortion.

[0077] To address the above problems, as Figure 2As shown, according to an embodiment of the present invention, an input stage circuit for a rail-to-rail operational amplifier is provided, including: a complementary differential pair 100 for providing a differential input to the operational amplifier; a tail current sampling circuit 200 for sampling the tail current in the circuit; an upper negative feedback current mirror 300 for adjusting the current based on the sampled tail current and feeding it back to the complementary differential pair; a lower negative feedback current mirror 400 for adjusting the current based on the sampled tail current and feeding it back to the complementary differential pair; a bidirectional current source 500 for providing current to the upper negative feedback current mirror and the lower negative feedback current mirror; an upper active load 600 for receiving the output of the complementary differential pair and connecting to the output terminal; a lower active load 700 for receiving the output of the complementary differential pair and connecting to the output terminal. By using active device loads whose transconductances are independent of the input voltage, distortion introduced by changes in the input voltage can be avoided; in addition, after adopting the tail current negative feedback compensation technique, the change in the transconductance of the differential pair is greatly reduced, and the feedback coefficient can be adjusted by the ratio of the emitters of each transistor, thereby adjusting the harmonic distortion of the input stage.

[0078] As Figure 2 shown, according to an embodiment of the present invention, the complementary differential pair 100 includes: a first N-type transistor, whose base is connected to the positive input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the upper active load; a second N-type transistor, whose base is connected to the negative input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the upper active load; a first P-type transistor, whose base is connected to the positive input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the lower active load; a second P-type transistor, whose base is connected to the negative input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the lower active load.

[0079] In addition, in order to quickly track the change of the input signal and stabilize the value of the output signal during the hold stage, an input voltage sampling circuit is adopted. Referring again to Figure 2 , according to an embodiment of the present invention, the input voltage sampling circuit 200 includes: a seventh N-type transistor, whose base is connected to the complementary differential pair, whose emitter is connected to the emitter of a seventh P-type transistor, and whose collector is connected to the upper negative feedback current mirror; a seventh P-type transistor, whose base is connected to the complementary differential pair, and whose collector is connected to the lower negative feedback current mirror. The sampled input voltage is used for subsequent processing of the operational amplifier, for example, specifically fed back to the complementary differential pair.

[0080] Based on the sampled voltage, in order to adjust the feedback to the complementary differential pair, referring again to Figure 2, according to an embodiment of the present invention, the upper negative feedback current mirror 300 includes: a third P-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the positive power supply, and whose collector is connected to the complementary differential pair; a fourth P-type transistor, whose base and collector are connected to the tail current sampling circuit, and whose emitter is connected to the positive power supply; a fifth P-type transistor, whose base is connected to the tail current sampling circuit, whose emitter is connected to the positive power supply, and whose collector is connected to the bidirectional current source; a sixth P-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the positive power supply. Wherein, the feedback coefficient can be adjusted by the ratio of the emitters of each transistor, thereby adjusting the harmonic distortion of the input stage.

[0081] Similarly, also based on the sampled voltage, the feedback to the complementary differential pair is adjusted. Referring again to Figure 2 , according to an embodiment of the present invention, the lower negative feedback current mirror 400 includes: a third N-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the negative power supply, and whose collector is connected to the complementary differential pair; a fourth N-type transistor, whose base and collector are connected to the tail current sampling circuit, and whose emitter is connected to the negative power supply; a fifth N-type transistor, whose base is connected to the tail current sampling circuit, whose emitter is connected to the negative power supply, and whose collector is connected to the bidirectional current source; a sixth N-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the negative power supply. Similarly, the feedback coefficient can be adjusted by the ratio of the emitters of each transistor, thereby adjusting the harmonic distortion of the input stage.

[0082] To supply current to the above-mentioned upper negative feedback current mirror and lower negative feedback current mirror, referring again to Figure 2 , according to an embodiment of the present invention, the bidirectional current source 500 includes: an eighth P-type transistor, whose base is connected to the reference voltage, whose emitter is connected to the positive power supply through a first resistor and a first current source, and whose collector is connected to the negative power supply; an eighth N-type transistor, whose base is connected to the reference voltage, whose emitter is connected to the negative power supply through a second resistor and a second current source, and whose collector is connected to the positive power supply; a ninth P-type transistor, whose base is connected between the second resistor and the second current source, whose emitter is connected to the emitter of the ninth N-type transistor through a third resistor, and whose collector is connected to the lower negative feedback current mirror; a ninth N-type transistor, whose base is connected between the first resistor and the first current source, and whose collector is connected to the upper negative feedback current mirror; a tenth P-type transistor, whose base is connected between the second resistor and the second current source, whose emitter is connected to the emitter of the tenth N-type transistor through a fourth resistor, and whose collector is connected to the lower active load; a tenth N-type transistor, whose base is connected between the first resistor and the first current source, and whose collector is connected to the upper active load.

[0083] In addition, in order to ensure that its transconductance does not change with the change of the input voltage, referring again to Figure 2 , according to an embodiment of the present invention, the upper active load 600 includes: an eleventh P-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the positive power supply through a fifth resistor; a twelfth P-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the positive power supply through a sixth resistor, and whose collector is connected to the output terminal. Since the constant current technology of the load active device is adopted, distortion will not be introduced due to the change of the input voltage. In addition, the output resistance can also be increased by means of common-gate common-source and the like.

[0084] Similarly, in order to ensure that its transconductance does not change with the change of the input voltage, referring again to Figure 2 , according to an embodiment of the present invention, the lower active load 700 includes: an eleventh N-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the negative power supply through a seventh resistor; a twelfth N-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the negative power supply through an eighth resistor, and whose collector is connected to the output terminal. Similarly, since the constant current technology of the load active device is adopted, distortion will not be introduced due to the change of the input voltage. In addition, the output resistance can also be increased by means of common-gate common-source and the like.

[0085] The working principle of the operational amplifier of the present invention is as follows.

[0086] As Figure 2 shown, the reference voltage Vref is a fixed voltage.

[0087] As Figure 2 shown, for the consideration of matching, it is designed that I P3C = I N3C , K N1N2 = K P1P2 = K N11N12 = K P11P12 = 1.

[0088] As Figure 2 shown, for the consideration of matching, it is designed that I1 = I2, R1 = R2, K P8P9 = K N8N9 = 2K R3R1 , K P8P10 = K N8N10 = 2K R4R1 .

[0089] In the present invention, K RXRY represents the ratio of the resistance value R X to the resistance value R Y , where X and Y respectively represent two resistor element numbers, which are Arabic numerals such as 1, 2, 3, and so on.

[0090] like Figure 2 As shown in the figure, after matching design, we have:

[0091] I P10C =I N10C =I P11C =I N11C =I P12C =I N12C =K P10P8 I1,

[0092] I P9C =I N9C =K P9P8 I1,

[0093] therefore,

[0094]

[0095] As can be seen from the above equation, the transconductance of all active devices included in upper active load 600 and lower active load 700 is independent of the input voltage. Therefore, due to the constant current technology used for the load active devices, no distortion is introduced due to changes in the input voltage.

[0096] like Figure 2 As shown, considering the matching, K is designed P1P7 =K N1N7 , K P4P5 =K N4N5 , K P5P6 =K N5N6 , K P3P4 =K N3N4 .

[0097] like Figure 2 As shown,

[0098] I P4C =I N4C =I P7C =I N7C =2K P7P1 I P3C ,

[0099] I P5C =I N5C =K P5P4 I P4C ,

[0100] I P6C =I N6C =K P6P3 I P3C ,

[0101] I P5C +I P6C =IN5C +I N6C = I P9C = K P9P8 I1,

[0102] It can be calculated that

[0103]

[0104] By adjusting the emitter ratio of each triode, I can be made P3C = I N3C = I P11C .

[0105] As Figure 2 shown, when the input voltage changes by ΔV IN , the collector currents of P3 and N3 introduce a change amount

[0106]

[0107] At this time, the collector currents of P7 and N7 also introduce an equal-proportion change amount:

[0108]

[0109] Due to the mirror relationship between P4 and P5, and between N4 and N5, the collector currents of P5 and N5 also introduce an equal-proportion change amount:

[0110]

[0111] Since the collector currents of N9 and P9 are fixed, the collector currents of P6 and N6 introduce a change amount:

[0112]

[0113] Finally, due to the mirror relationship between P6 and P3, and between N6 and N3, the collector currents of P3 and N3 introduce a negative feedback change amount:

[0114]

[0115] Comparing the ΔI P3C , ΔI N3C expressions, it can be known that the feedback coefficient is:

[0116] H = 2K P3P6 K P5P4 K P7P1 ,

[0117] As Figure 2 shown, when negative feedback is not introduced, when the input voltage changes by ΔV IN , the transconductance change amounts of N1, N2, P1, and P2 are:

[0118]

[0119] When negative feedback is introduced, the transconductance change amounts of N1, N2, P1, and P2 are as follows:

[0120]

[0121] It can be seen that after adopting the tail current negative feedback compensation technology, the change in the transconductance of the differential pair is greatly reduced, and the feedback coefficient can be adjusted by the ratio of the emitters of each transistor, thereby adjusting the harmonic distortion of the input stage.

[0122] As Figure 3 shown, according to another embodiment of the present invention, a rail-to-rail operational amplifier is provided, including an input stage circuit for a rail-to-rail operational amplifier as described in the first aspect, and further comprising: a fourteenth P-type transistor, whose base and collector are connected to the base and collector of a fourteenth N-type transistor, and whose emitter is connected to the positive power supply via a ninth resistor; a fourteenth N-type transistor, whose emitter is connected to the negative power supply via a tenth resistor; a fifteenth P-type transistor, whose base is connected between the upper active load and the lower active load, and whose emitter is connected to the positive power supply via a third current source, and whose collector is connected to the negative power supply; a fifteenth N-type transistor, whose base is connected between the upper active load and the lower active load, and whose emitter is connected to the negative power supply via a fourth current source, and whose collector is connected to the positive power supply; a sixteenth N-type transistor, whose base is connected to the emitter of the fifteenth P-type transistor, and whose emitter is connected to the output terminal, and whose collector is connected to the positive power supply; a sixteenth P-type transistor, whose base is connected to the emitter of the fifteenth N-type transistor, and whose emitter is connected to the output terminal, and whose collector is connected to the negative power supply.

[0123] The present invention may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to implement various aspects of the present invention.

[0124] A computer-readable storage medium can be a tangible device that holds and stores instructions for use by an instruction execution device. A computer-readable storage medium may include, for example, but is not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing.

[0125] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. An input stage circuit for a rail-to-rail operational amplifier, characterized in that, Comprising: A complementary differential pair for providing a differential input to an operational amplifier; A tail current sampling circuit for sampling the tail current in the circuit; An upper negative feedback current mirror for adjusting the current based on the sampled tail current and feeding it back to the complementary differential pair; A lower negative feedback current mirror for adjusting the current based on the sampled tail current and feeding it back to the complementary differential pair; A bidirectional current source for providing current to the upper negative feedback current mirror and the lower negative feedback current mirror; An upper active load for receiving the output of the complementary differential pair and connecting to the output terminal; A lower active load for receiving the output of the complementary differential pair and connecting to the output terminal.

2. The input stage circuit for an operational amplifier according to claim 1, characterized in that, The complementary differential pair includes: A first N-type transistor, whose base is connected to the positive input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the upper active load; A second N-type transistor, whose base is connected to the negative input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the upper active load; A first P-type transistor, whose base is connected to the positive input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the lower active load; A second P-type transistor, whose base is connected to the negative input terminal, whose emitter is connected to the tail current sampling circuit, and whose collector is connected to the lower active load.

3. The input stage circuit for an operational amplifier according to claim 1, characterized in that, The input voltage sampling circuit includes: A seventh N-type transistor, whose base is connected to the complementary differential pair, whose emitter is connected to the emitter of a seventh P-type transistor, and whose collector is connected to the upper negative feedback current mirror; A seventh P-type transistor, whose base is connected to the complementary differential pair, and whose collector is connected to the lower negative feedback current mirror.

4. The input stage circuit for an operational amplifier according to claim 1, characterized in that, The upper negative feedback current mirror includes: A third P-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the positive power supply, and whose collector is connected to the complementary differential pair; A fourth P-type transistor, whose base and collector are connected to the tail current sampling circuit, and whose emitter is connected to the positive power supply; A fifth P-type transistor, whose base is connected to the tail current sampling circuit, whose emitter is connected to the positive power supply, and whose collector is connected to the bidirectional current source; A sixth P-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the positive power supply.

5. A input stage circuit for an operational amplifier according to claim 1, characterized in that, The lower negative feedback current mirror includes: A third N-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the negative power supply, and whose collector is connected to the complementary differential pair; A fourth N-type transistor, whose base and collector are connected to the tail current sampling circuit, and whose emitter is connected to the negative power supply; A fifth N-type transistor, whose base is connected to the tail current sampling circuit, whose emitter is connected to the negative power supply, and whose collector is connected to the bidirectional current source; A sixth N-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the negative power supply.

6. The input stage circuit for an operational amplifier according to claim 1, characterized in that, The bidirectional current source includes: An eighth P-type transistor, whose base is connected to the reference voltage, whose emitter is connected to the positive power supply through a first resistor and a first current source, and whose collector is connected to the negative power supply; An eighth N-type transistor, whose base is connected to a reference voltage, whose emitter is connected to a negative power supply via a second resistor and a second current source, and whose collector is connected to a positive power supply; A ninth P-type transistor, whose base is connected between the second resistor and the second current source, whose emitter is connected to the emitter of the ninth N-type transistor via a third resistor, and whose collector is connected to the lower negative feedback current mirror; A ninth N-type transistor, whose base is connected between the first resistor and the first current source, and whose collector is connected to the upper negative feedback current mirror; A tenth P-type transistor, whose base is connected between the second resistor and the second current source, whose emitter is connected to the emitter of the tenth N-type transistor via a fourth resistor, and whose collector is connected to the lower active load; A tenth N-type transistor, whose base is connected between the first resistor and the first current source, and whose collector is connected to the upper active load.

7. The input stage circuit for an operational amplifier according to claim 1, wherein: The upper active load includes: An eleventh P-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the positive power supply via a fifth resistor; A twelfth P-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the positive power supply via a sixth resistor, and whose collector is connected to the output terminal.

8. The input stage circuit for an operational amplifier according to claim 1, wherein The lower active load includes: An eleventh N-type transistor, whose base and collector are connected to the bidirectional current source, and whose emitter is connected to the negative power supply via a seventh resistor; A twelfth N-type transistor, whose base is connected to the bidirectional current source, whose emitter is connected to the negative power supply via the seventh resistor, and whose collector is connected to the output terminal.

9. A rail-to-rail operational amplifier, characterized in that, An input stage circuit for a rail-to-rail operational amplifier, comprising the one described in any one of claims 1-8, further comprising: A fourteenth P-type transistor, whose base and collector are connected to the base and collector of the fourteenth N-type transistor, and whose emitter is connected to the positive power supply via a ninth resistor; A fourteenth N-type transistor, whose emitter is connected to the negative power supply via a tenth resistor; A fifteenth P-type transistor, whose base is connected between the upper active load and the lower active load, whose emitter is connected to the positive power supply via a third current source, and whose collector is connected to the negative power supply; A fifteenth N-type transistor, whose base is connected between the upper active load and the lower active load, whose emitter is connected to the negative power supply via a fourth current source, and whose collector is connected to the positive power supply; A sixteenth N-type transistor, whose base is connected to the emitter of the fifteenth P-type transistor, whose emitter is connected to the output terminal, and whose collector is connected to the positive power supply; A sixteenth P-type transistor, whose base is connected to the emitter of the fifteenth N-type transistor, whose emitter is connected to the output terminal, and whose collector is connected to the negative power supply.

Images