Digital filters, controllers and vehicles

Abstract

This invention discloses a digital filter, controller, and vehicle, relating to the field of filtering technology. The digital filter includes: a filtering circuit configured to filter input data to output filtered data; an accumulation circuit connected to the filtering circuit, configured to accumulate or extract the filtered data to output an accumulation result; a peak hold circuit connected to the accumulation circuit, configured to hold the accumulated result at its peak value; and a trigger signal generation circuit adapted to connect to a trigger source generation module, configured to generate a trigger signal based on a trigger source output from the trigger source generation module, and provide the trigger signal to the filtering circuit, accumulation circuit, and peak hold circuit respectively, so that the filtering circuit, accumulation circuit, and peak hold circuit operate according to the trigger signal. This digital filter does not rely on real-time CPU intervention and can dynamically adapt to external events.

Description

Technical Field

[0001] This application relates to the field of filtering technology, and in particular to a digital filter, controller, and vehicle. Background Technology

[0002] With the development of the information age, digital signal processing technology has gradually replaced traditional analog signal processing systems in many application fields such as automatic control, aerospace, fault detection, and communications. Digital filters occupy an important position in the field of digital signal processing. By utilizing the difference in the spectrum between the desired signal and other signals, and through certain computational relationships, they can filter out noise in the input signal, achieving the purpose of extracting and strengthening the useful components of the signal while weakening interference components. However, digital filters in related technologies typically rely on CPU (Central Processing Unit) instructions for configuration and enabling; therefore, the triggering method is singular and inflexible. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, the first objective of this invention is to propose a digital filter in which the trigger signal generation circuit can flexibly generate trigger signals based on a trigger source, without relying on real-time CPU intervention. It can dynamically adapt to external events and supports autonomous transmission of digital filter output data to the GTM submodule in scenarios without CPU intervention, thereby improving the efficiency and response speed of the digital filter.

[0004] The second objective of this invention is to provide a controller.

[0005] The third objective of this invention is to provide a vehicle.

[0006] To achieve the above objectives, a digital filter is provided according to a first aspect embodiment of the present invention, comprising: a filtering circuit configured to filter input data to output filtered data; an accumulation circuit connected to the filtering circuit, configured to accumulate or extract the filtered data to output an accumulation result; a peak hold circuit connected to the accumulation circuit, configured to perform peak hold processing on the accumulation result; and a trigger signal generation circuit adapted to be connected to a trigger source generation module, configured to generate a trigger signal according to a trigger source output by the trigger source generation module, and provide the trigger signal to the filtering circuit, the accumulation circuit, and the peak hold circuit respectively, so that the filtering circuit, the accumulation circuit, and the peak hold circuit operate according to the trigger signal respectively.

[0007] A digital filter according to an embodiment of the present invention includes a filtering circuit, an accumulation circuit, a peak hold circuit, and a trigger signal generation circuit. The filtering circuit is configured to filter input data to output filtered data. The accumulation circuit is connected to the filtering circuit and is configured to accumulate or extract the filtered data to output an accumulation result. The peak hold circuit is connected to the accumulation circuit and is configured to hold the peak value of the accumulation result. The trigger signal generation circuit is adapted to be connected to a trigger source generation module and is configured to generate a trigger signal based on the trigger source output by the trigger source generation module, and provide the trigger signal to the filtering circuit, the accumulation circuit, and the peak hold circuit respectively, so that the filtering circuit, the accumulation circuit, and the peak hold circuit operate according to the trigger signal. Therefore, the trigger signal generation circuit can flexibly generate trigger signals according to the trigger source, without relying on real-time CPU intervention, and can dynamically adapt to external events. Furthermore, it supports autonomous transmission of digital filter output data to the GTM submodule in scenarios without CPU intervention, thereby improving the efficiency and response speed of the digital filter.

[0008] According to one embodiment of the present invention, the trigger source generation module is at least one of a PWM module, a timer, a general-purpose timer module, and a comparator module.

[0009] According to one embodiment of the present invention, there are multiple trigger sources, and the trigger signal generation circuit includes: a trigger edge selection unit adapted to be connected to a trigger source generation module, the trigger edge selection unit being configured to select the effective edge of each trigger source according to the trigger edge selection signal to obtain multiple trigger source signals; a trigger signal matching unit connected to the trigger edge selection unit, the trigger signal matching unit being configured to select a first signal source to a fifth signal source from the multiple trigger source signals; and a trigger signal generation unit connected to the trigger signal matching unit, the trigger signal generation unit being configured to generate a first initialization flag of the peak hold circuit, a second initialization flag of the accumulator circuit, a third initialization flag of the filter circuit, an end flag of the peak hold circuit, and a disable flag of the accumulator circuit according to the first signal source to the fifth signal source, wherein the trigger signal includes the first initialization flag, the second initialization flag, the third initialization flag, the end flag, and the disable flag.

[0010] According to one embodiment of the present invention, the trigger signal generation unit includes five trigger signal generation modules, each trigger signal generation module including: a first selection submodule, adapted to input a signal source, the first selection submodule being configured to select a first trigger signal from a corresponding signal source according to a signal source selection signal; and a second selection submodule, connected to the first selection submodule and adapted to input a second trigger signal, the second selection submodule being configured to select one of the first trigger signal and the second trigger signal as a corresponding flag according to a setting signal.

[0011] According to an embodiment of the present invention, when the trigger source generation module is a general-purpose timer module, the trigger source includes a plurality of first interrupt signals and a plurality of second interrupt signals. The trigger edge selection unit is further configured to select the effective edge of each first interrupt signal and the effective edge of each second interrupt signal according to the trigger edge selection signal to obtain a plurality of first trigger source signals and a plurality of second trigger source signals. The trigger signal matching unit is further configured to select a first signal source, a second signal source and a third signal source from the plurality of first trigger source signals, and to select a fourth signal source and a fifth signal source from the plurality of second trigger source signals.

[0012] According to one embodiment of the present invention, the number of the second interrupt signal corresponding to the fourth signal source is the same as the number of the first interrupt signal corresponding to the first signal source, and the number of the second interrupt signal corresponding to the fifth signal source is the same as the number of the first interrupt signal corresponding to the second signal source.

[0013] According to one embodiment of the present invention, the accumulation circuit is configured to, when a first initialization flag is enabled, accumulate or extract filtered data according to the first initialization flag to output an accumulation result and write the accumulation result into an output data register, and when a disable flag is enabled, stop accumulating or extracting filtered data.

[0014] According to one embodiment of the present invention, the peak hold circuit is further configured to update the value stored in the result register by using the larger value between the filtered data and the value stored in the result register when the second initialization flag is enabled, and to stop peak hold processing on the filtered data when the end flag is enabled.

[0015] According to one embodiment of the present invention, the digital filter further includes: an output circuit connected to an accumulation circuit, the output circuit being configured to perform format conversion on the accumulation result to output a conversion result, and to store the accumulation result or the conversion result; and an output signal selection circuit connected to the peak hold circuit and the output circuit respectively, and adapted to connect to at least one target module, the output signal selection circuit being configured to determine at least one output trigger signal based on the output interrupt signal of the output circuit and the update signal of the peak hold circuit, and to provide each output trigger signal to the corresponding target module.

[0016] According to an embodiment of the present invention, the output signal selection circuit includes: a first selection unit connected to a peak hold circuit and an output circuit respectively, the first selection unit being configured to select at least one output trigger signal from an output interrupt signal and an update signal; and a second selection unit connected to the first selection unit and adapted to connect to at least one target module, the second selection unit being configured to determine a corresponding target module based on each output trigger signal and to provide each output trigger signal to the corresponding target module.

[0017] According to one embodiment of the present invention, the target module is one of a PWM module, a timer module, a general-purpose timer module, a comparator module, and an analog-to-digital converter module.

[0018] According to one embodiment of the present invention, the output circuit is further adapted to connect to a general-purpose timer submodule, and the output circuit is further configured to send an updated value to the general-purpose timer submodule when the value in the output data register is updated, so as to determine whether the data transmission is successful through the general-purpose timer submodule.

[0019] To achieve the above objectives, a controller is provided according to a second aspect of the present invention, comprising the digital filter of any of the foregoing embodiments.

[0020] According to the controller of the present invention, by employing the above-described digital filter, the trigger signal generation circuit can flexibly generate a trigger signal based on the trigger source, without relying on real-time intervention of the CPU. It can dynamically adapt to external events and supports autonomous transmission of digital filter output data to the GTM submodule in scenarios without CPU intervention, thereby improving the efficiency and response speed of the digital filter.

[0021] To achieve the above objectives, a vehicle comprising the aforementioned controller is provided according to a third aspect of the present invention.

[0022] According to the vehicle of the present invention, by adopting the above-described controller, the trigger signal generation circuit can flexibly generate trigger signals according to the trigger source, without relying on real-time intervention of the CPU, and can dynamically adapt according to external events. It also supports the autonomous transmission of digital filter output data to the GTM submodule in scenarios without CPU intervention, thereby improving the efficiency and response speed of the digital filter.

[0023] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a digital filter in related technologies;

[0025] Figure 2 This is a flowchart illustrating the workflow of digital filters in related technologies;

[0026] Figure 3 This is a schematic diagram of the structure of a digital filter according to an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the trigger signal generation circuit according to an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of the structure of a trigger signal generation module according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram illustrating the generation of an end marker according to an embodiment of the present invention;

[0030] Figure 7 This is a timing diagram of the operation after the first initialization flag is triggered according to an embodiment of the present invention;

[0031] Figure 8 This is a timing diagram of the operation after the second initialization flag is triggered according to an embodiment of the present invention;

[0032] Figure 9 This is a schematic diagram of the structure of a digital filter according to another embodiment of the present invention;

[0033] Figure 10 This is a schematic diagram of the output signal selection circuit according to an embodiment of the present invention;

[0034] Figure 11 This is a schematic diagram of the controller according to an embodiment of the present invention;

[0035] Figure 12 This is a structural schematic diagram of a vehicle according to an embodiment of the present invention. Detailed Implementation

[0036] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0037] It should be noted that this application is based on the inventor's understanding and research into the following issues:

[0038] Figure 1 The structure of a digital filter in the related art is shown. The digital filter in the related art mainly consists of a filter circuit 10, an accumulation circuit 20, and a peak hold circuit 30. For example... Figure 1As shown, the filtering circuit 10 in the digital filter receives the data to be filtered from the AD (Analog-to-Digital) converter and the external bus, and supports optional FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filters. The orders of both FIR and IIR filters are configurable. FIR filter orders include, but are not limited to, 8, 16, 24, and 32, while IIR filter orders include, but are not limited to, 1, 2, and 3. FIR has a finite impulse response, enabling linear phase characteristics; IIR, on the other hand, has a feedback loop, resulting in an infinitely continuous response to pulsed input signals with a higher frequency. A similar frequency response effect can be achieved with a lower order compared to FIR. For different scenarios, the appropriate filtering method and filter order can be selected through software configuration, meeting the filtering needs of many scenarios. The accumulator circuit 20 includes an absolute value calculation circuit 21, a first selector 22, an accumulation / decimation circuit 23, and a second selector 24. It controls the filtering result through the absolute value calculation enable signal ABS_EN and the selection signal ACC_MODE_SEL processed by the accumulator circuit 20. When ABS_EN=0b and ACC_MODE_SEL=01b, the accumulator circuit 20 does not perform absolute value calculation on the filtering result but directly performs accumulation processing. When ABS_EN=1b and ACC_MODE_SEL=10b, the accumulator circuit 20 performs absolute value calculation on the filtering result and then decimates the result. The peak hold circuit 30 can perform peak hold processing or comparison calculation on the filtering result or the output result of the accumulator circuit 20. When the peak circuit mode selection signal PH_MODE_SEL=01b, peak hold processing is performed on the filtering result or the output result of the accumulator circuit 20. When the peak circuit mode selection signal PH_MODE_SEL=10b, the filtering result or the output result of the accumulator circuit 20 is compared and calculated. The comparison operator can be configured and selected through PHI_CPS_SEL (e.g., PHI_CPS_SEL=01b, i.e., selecting the equals (==) operator, which is true when the comparison target register and the input data of the peak hold circuit 30 are equal). When the value in the peak hold result register is updated, the peak hold circuit 30 outputs a peak update notification PH_update_trigger. The peak hold circuit 30 can also output a peak hold interrupt signal PH_interrupt_request. The output circuit 40 has a floating-point conversion circuit 41 and a third selector 42, and the output result can be controlled through the floating-point enable signal FP_EN. When FP_EN=1b, floating-point conversion processing is specified.Output circuit 40 performs IEEE 754 (this standard is used as an example only; floating-point conversion includes but is not limited to this standard) floating-point conversion on the fixed-point format of the input data. Output circuit 40 also has an output buffer for storing the output result or floating-point conversion result of accumulation circuit 20. When the calculation result with ACC_MODE_SEL=01b (accumulation) or ACC_MODE_SEL=10b (decimation) is written to the output register, and a valid data output signal is generated, output circuit 40 outputs a data interrupt signal output_interrupt_request (when ACC_MODE_SEL=00b, neither accumulation nor decimation is performed; the calculation result is written to the output data register, but no interrupt is output).

[0039] Figure 2 This diagram illustrates the workflow of a digital filter in related technologies, applied to a CPU. The frequency response characteristics of the digital filter can be determined by configuring the filter type (FIR / IIR) and filter coefficients. Different combinations of coefficients can achieve various filtering functions, such as low-pass, high-pass, and band-pass filtering. After enabling accumulation, the sampled signal (the data to be filtered from the peripheral bus) is sent to the accumulation circuit 20 after passing through the filter circuit 10. When the accumulation count is configured to 1 (accumulating once, the two processing results of the filter are added and output from the accumulation circuit 20), two consecutively input data passes through the filter circuit 10. The processing result (D1) of the filter circuit 10 is written to the accumulator, and the processing result (D2) of the filter circuit 10 is input to the accumulation circuit 20. The results of D1 and D2 are added and written to the output data register, issuing an output data interrupt request. After enabling the peak hold circuit 30, the initial peak hold value is configured. For the first input data, the initial peak hold value and the input data of the peak hold circuit 30 are used for peak hold processing, and the larger value is saved to the result register of the peak hold circuit 30. Then, the data input to the peak hold circuit 30 is compared with the value of the result register of the peak hold circuit 30, and the larger value is updated and written to the result register of the peak hold circuit 30 as the peak hold result. The peak hold circuit 30 can be used to capture and hold the maximum peak value of the input signal. It can stably record the highest point when the signal fluctuates, and is used to monitor and record the extreme values ​​of the signal.

[0040] Therefore, digital filters in related technologies require CPU configuration, have a single and inflexible triggering method, and lack interaction with other modules. Consequently, the interaction between different modules is limited, and it is impossible to achieve synchronous interconnection with other events at the system level.

[0041] Based on this, embodiments of the present invention provide a digital filter, a controller, and a vehicle. The trigger signal generation circuit can flexibly generate trigger signals according to the trigger source without the direct involvement of the CPU, thereby realizing fast data processing and transmission, and improving the efficiency and response speed of the digital filter.

[0042] The digital filter, controller, and vehicle according to embodiments of the present invention are described below with reference to the accompanying drawings.

[0043] Figure 3 This is a schematic diagram of the structure of a digital filter according to an embodiment of the present invention. Figure 3 As shown, the digital filter 100 includes: a filter circuit 10, an accumulation circuit 20, a peak hold circuit 30, and a trigger signal generation circuit 50.

[0044] The filter circuit 10 is configured to filter the input data to output filtered data; the accumulator circuit 20 is connected to the filter circuit 10 and is configured to accumulate or extract the filtered data to output the accumulation result; the peak hold circuit 30 is connected to the accumulator circuit 20 and is configured to perform peak hold processing on the accumulation result; the trigger signal generation circuit 50 is adapted to be connected to the trigger source generation module and is configured to generate a trigger signal according to the trigger source output by the trigger source generation module, and provide the trigger signal to the filter circuit 10, the accumulator circuit 20 and the peak hold circuit 30 respectively, so that the filter circuit 10, the accumulator circuit 20 and the peak hold circuit 30 can work according to the trigger signal respectively.

[0045] Specifically, the trigger signal generation circuit 50 generates a trigger signal based on the trigger source output by the trigger source generation module, and provides the trigger signal to the filter circuit 10, the accumulation circuit 20, and the peak hold circuit 30 respectively, without requiring the CPU to pre-configure the trigger signal. The filter circuit 10 is suitable for connection to a SARADC (Successive Approximation Register Analog-to-Digital Converter) or a DSADC (Delta-Sigma Analog-to-Digital Converter). When it receives the trigger signal, the filter circuit 10 filters the data output (i.e., the input data) of the SARADC or DSADC to generate filtered data. The trigger signal includes the mode selection signal of the accumulation circuit 20. When it receives the trigger signal, the accumulation circuit 20 accumulates or decrements the filtered data according to the trigger signal to generate an accumulation result. When the peak hold circuit 30 receives the trigger signal, it activates the peak hold function to perform peak hold processing on the accumulation result.

[0046] In an alternative implementation, the trigger signal generation circuit 50 can be a TRGMUX (Trigger Multiplexer). The main function of TRGMUX is to provide a flexible trigger source selection mechanism. It allows users to select different trigger sources through software configuration; for example, the trigger source of a peripheral can be set to a GPIO pin, a timer event, or other peripheral signals. As an event router, TRGMUX flexibly routes trigger signals to different circuits, ensuring the coordinated operation of the circuits in the digital filter 100.

[0047] In the above embodiments, the trigger signal generation circuit can flexibly generate trigger signals according to the trigger source to control the filter circuit, the accumulation circuit and the peak hold circuit. It does not rely on real-time intervention of the CPU, can dynamically adapt to external events, and supports autonomous transmission of digital filter output data to the GTM submodule in scenarios without CPU intervention, thereby improving the efficiency and response speed of the digital filter.

[0048] For example, in some embodiments, the trigger source generation module is at least one of a PWM (Pulse Width Modulation) module, a timer, a module-specific timer module, and a comparator module.

[0049] It is understood that there are multiple trigger source generation modules. Therefore, there are multiple trigger source sources in this embodiment. Furthermore, since the trigger signal generation circuit 50 of this embodiment can interact with different trigger source generation modules, the digital filter 100 can interact with different modules, realizing synchronous interconnection with other events at the system level.

[0050] In some embodiments, there are multiple trigger sources, such as Figure 4As shown, the trigger signal generation circuit 50 includes: a trigger edge selection unit 51, a trigger signal matching unit 52, and a trigger signal generation unit 53. The trigger edge selection unit 51 is adapted to connect to the trigger source generation module and is configured to select the effective edge of each trigger source according to the trigger edge selection signal to obtain multiple trigger source signals. The trigger signal matching unit 52 is connected to the trigger edge selection unit 51 and is configured to select a first signal source to a fifth signal source from the multiple trigger source signals. The trigger signal generation unit 53 is connected to the trigger signal matching unit 52 and is configured to generate a first initialization flag for the peak hold circuit 30, a second initialization flag for the accumulator circuit 20, a third initialization flag for the filter circuit 10, an end flag for the peak hold circuit 30, and a disable flag for the accumulator circuit 20 according to the first to fifth signal sources. The trigger signal includes the first initialization flag, the second initialization flag, the third initialization flag, the end flag, and the disable flag.

[0051] Specifically, the trigger source generation module can output multiple trigger sources. The trigger edge selection unit 51 selects the effective edge of each trigger source according to the trigger edge selection signal edge_sel to generate multiple trigger source signals. The effective edge includes, but is not limited to, rising and falling edges. The trigger signal matching unit 52 selects signal sources from the multiple trigger source signals for the first initialization flag, the second initialization flag, the third initialization flag, the end flag, and the disable flag, respectively, thereby obtaining the first to fifth signal sources. Each signal source corresponds to a different trigger source, that is, one trigger source belongs to one signal source. The trigger signal generation unit 53 generates the first initialization flag, the second initialization flag, the third initialization flag, the end flag, and the disable flag according to each signal source. The first initialization flag, the second initialization flag, and the third initialization flag are used to control the peak holding circuit 30, the accumulator circuit 20, and the filter circuit 10 to work, respectively. The end flag and the disable flag are used to control the peak holding circuit 30 and the accumulator circuit 20 to stop working, respectively.

[0052] In the above embodiments, the trigger signal generation circuit generates a first initialization flag, a second initialization flag, a third initialization flag, an end flag, and a disable flag based on multiple trigger sources output by the trigger source generation module, thereby enabling and disabling the trigger control accumulation circuit and the peak hold circuit.

[0053] In some embodiments, the trigger signal generation unit 53 includes five trigger signal generation modules, such as... Figure 5As shown, each trigger signal generation module includes: a first selection submodule 531 and a second selection submodule 532, wherein the first selection submodule 531 is adapted to input a signal source and is configured to select a first trigger signal from the corresponding signal source according to a signal source selection signal; the second selection submodule 532 is connected to the first selection submodule 531 and is adapted to input a second trigger signal, and is configured to select one of the first trigger signal and the second trigger signal as a corresponding flag according to a setting signal.

[0054] Specifically, each signal source includes at least one trigger source signal. The first selection submodule 531 selects a first trigger signal from the corresponding signal source according to the signal source selection signal. The second trigger signal is a software trigger signal. The second selection submodule 532 selects one of the first and second trigger signals as a corresponding flag according to the set signal. Therefore, the present invention supports both software triggering and trigger signal generation circuit 50 triggering. The first selection submodule 531 and the second selection submodule 532 can each be a selector.

[0055] It should be noted that the present invention can also utilize the trigger setting register to generate a trigger signal.

[0056] Taking the generation of the end marker as an example, such as Figure 6 As shown, the fourth signal source includes four timer trigger signals, namely the first timer trigger signal to the fourth timer trigger signal. The first selection submodule 531 selects one of the four end trigger signals as the first trigger signal according to the signal source selection signal PH_TRG_SEL. The signal source selection signal PH_TRG_SEL = 01b~11b, which corresponds to the four end trigger signals respectively. Then, the second selection submodule 532 selects whether the first trigger signal or the second trigger signal is used as the end flag according to the setting signal PH_SET. When PH_SET = 1b, the first trigger signal is selected.

[0057] In the above embodiments, the second selection submodule can select either a trigger signal generated by the trigger source or a software trigger signal as the corresponding flag. Therefore, it can support both software triggering and trigger signal generation circuit triggering, making the triggering method more flexible.

[0058] In some embodiments, such as Figure 4As shown, when the trigger source generation module is a general-purpose timer module, the trigger sources include first interrupt signal 0 (GTM_TRG_A0) to first interrupt signal 11 (GTM_TRG_A11) and second interrupt signal 0 (GTM_TRG_B0) to second interrupt signal 11 (GTM_TRG_B11). The trigger edge selection unit 51 is also configured to select the effective edge of each of the first interrupt signals GTM_TRG_A0 to GTM_TRG_A11 and each of the second interrupt signals GTM_TRG_B0 to GTM_TRG_A11 according to the trigger edge selection signal. The effective edge of GTM_TRG_B11 is used to obtain the first trigger source signal 0 (TRG_A0) ~ the first trigger source signal 11 (TRG_A11) and the second trigger source signal 0 (TRG_B0 ~) and the second trigger source signal 11 (TRG_B11). The trigger signal matching unit 52 is also configured to select a first signal source, a second signal source and a third signal source from a plurality of first trigger source signals TRG_A0 ~ TRG_A11 respectively, and to select a fourth signal source and a fifth signal source from a plurality of second trigger source signals TRG_B0 ~ TRG_B11 respectively.

[0059] The general-purpose timer module is used to generate precise time trigger signals and can be configured with the timer's period and trigger mode (such as periodic trigger, single-pulse trigger, etc.). Figure 4 As shown in the example, the comparison matching interrupts GTM_TRG_A0~GTM_TRG_A11 and GTM_TRG_B0~GTM_TRG_B11 output by the general timer module are used as timer triggers. GTM_TRG_A0~GTM_TRG_A11 are multiple first interrupt signals, and GTM_TRG_B0~GTM_TRG_B11 are multiple second interrupt signals. The trigger edge selection unit 51 is also configured to select the effective edges of each first interrupt signal GTM_TRG_A0~GTM_TRG_A11 and each second interrupt signal GTM_TRG_B0~GTM_TRG_B11 according to the trigger edge selection signal edge_sel. The trigger signal matching unit 52 selects four first interrupt signals for each of the three trigger flag functions (i.e., first initialization flag, second initialization flag, and third initialization flag) of the initialization timer trigger selection register of the peak circuit, the initialization timer trigger selection register of the accumulator circuit 20, and the initialization timer trigger selection register of the filter circuit 10, to obtain the first signal source, the second signal source, and the third signal source. It also selects four second interrupt signals for the end flag and the disable flag, respectively, to obtain the fourth signal source and the fifth signal source. Then, the selected signals are sequentially assigned to the timer trigger 0~3 of each flag.

[0060] In some embodiments, the number of the second interrupt signal corresponding to the fourth signal source is the same as the number of the first interrupt signal corresponding to the first signal source, and the number of the second interrupt signal corresponding to the fifth signal source is the same as the number of the first interrupt signal corresponding to the second signal source.

[0061] Specifically, after the first interrupt signal corresponding to the first signal source is selected, the second interrupt signal corresponding to the fourth signal source is also determined according to the number of the first interrupt signal; after the first interrupt signal corresponding to the second signal source is selected, the second interrupt signal corresponding to the fifth signal source is also determined according to the number of the first interrupt signal.

[0062] For example, with Figure 4 For example, the first interrupt signal corresponding to the first signal source is numbered 0~3. Therefore, the second interrupt signal corresponding to the fourth signal source is also numbered 0~3. The first interrupt signal corresponding to the second signal source is numbered 4~7. Therefore, the second interrupt signal corresponding to the fourth signal source is also numbered 4~7.

[0063] In some embodiments, the accumulation circuit 20 is configured to accumulate or extract the filtered data according to the first initialization flag when the first initialization flag is enabled, to output the accumulation result and write the accumulation result into the output data register, and to stop accumulating or extracting the filtered data when the disable flag is enabled.

[0064] by Figure 7For example, when the first initialization flag is triggered by a timer or software and accumulation is specified, the accumulator counter is initialized, and the data to be accumulated is used as the first data to be accumulated. When the first initialization flag is enabled and the accumulator count is set to 2, after the first initialization flag is triggered, the first input data is AD(3), and the input data AD(3) is used as the first data of the new accumulator count. First, AD(3) is filtered to obtain filtered data D(3). The filtered data D(3) is input into the accumulator circuit 20 for accumulation, and the accumulated result DADD(3) is written into the accumulator. At this time, the original accumulated result DADD(1) + DADD(2) is overwritten. The same operation is performed on the input data AD(4). After filtering, data D(4) is obtained. Then, it is accumulated with the previous accumulated result DADD(3), the accumulation count is set to 2, and a new accumulated result DADD(3) + DADD(4) is generated. Since the accumulation count is set to 2, D(5) is processed again. The system only retains the two accumulated results DADD(3) + DADD(4) + DADD(5), and writes them into the output data register after the first initialization flag is enabled, and triggers the output data interrupt request. When the timer trigger or software trigger is enabled or disabled, the subsequent input data is stopped from being accumulated or decremented. If the accumulation or extraction process needs to be restarted, the first initialization flag needs to be re-enabled.

[0065] In some embodiments, the peak hold circuit 30 is further configured to update the value stored in the result register using the larger value between the filtered data and the value stored in the result register when the second initialization flag is enabled, and to stop peak hold processing on the filtered data when the end flag is enabled.

[0066] by Figure 8 Taking the example shown, after the general-purpose timer module triggers the second initialization flag, it will perform peak hold processing on multiple input data. After the AD conversion data AD(1) ​​is filtered and accumulated, D(1) is generated. The second initialization flag pulls the peak hold enable signal low to enable the peak hold function. D(1) is compared with the preset initial value, and the larger value PH result(1) between D(1) and the preset initial value is updated to the result register. After that, after the AD conversion data AD(2) is filtered and accumulated, D(2) is generated. D(2) is compared with the value stored in the result register, and the larger value PH result(2) between D(2) and the value stored in the result register is updated to the result register.

[0067] In some embodiments, such as Figure 9As shown, the digital filter 100 further includes an output circuit 40 and an output signal selection circuit 60. The output circuit 40 is connected to the accumulation circuit 20 and is configured to perform format conversion on the accumulation result to output the conversion result and store the accumulation result or the conversion result. The output signal selection circuit 60 is connected to the peak hold circuit 30 and the output circuit 40 respectively, and is adapted to connect to at least one target module 200. The output signal selection circuit 60 is configured to determine at least one output trigger signal based on the output interrupt signal output_interrupt_request of the output circuit 40 and the update signal PH_update_trigger of the peak hold circuit 30, and provide each output trigger signal to the corresponding target module 200.

[0068] Specifically, when the accumulated result is written to the output register and a valid data output signal is generated, the output circuit 40 outputs a data interrupt signal output_interrupt_request. After the value in the result register is updated, the peak hold circuit 30 outputs an update signal PH_update_trigger. The output signal selection circuit 60 can select at least one of the output interrupt signal output_interrupt_request and the update signal PH_update_trigger and provide each output trigger signal to the corresponding target module 200 so that the corresponding target module 200 can work according to the corresponding output trigger signal.

[0069] In some embodiments, the target module 200 is one of a PWM module, a timer module, a general-purpose timer module, a comparator module, and an analog-to-digital converter module.

[0070] It should be noted that the target module 200 is not limited to the types mentioned above, and can also be of other types. The analog-to-digital converter module can be a SARADC module or a DSADC module, and there are no specific restrictions here.

[0071] In the above embodiments, the output signal selection circuit has multiple output sources, which can transmit the output signal to different modules at the system level, realizing the interaction between the digital filter and different modules.

[0072] In some embodiments, such as Figure 10As shown, the output signal selection circuit 60 includes a first selection unit 61 and a second selection unit 62. The first selection unit 61 is connected to the peak hold circuit 30 and the output circuit 40, respectively. The first selection unit 61 is configured to select at least one output trigger signal 0 (OUT0) - output trigger signal 7 (OUT7) from the output interrupt signal output_interrupt_request and the update signal PH_update_trigger. The second selection unit 62 is connected to the first selection unit 61 and is adapted to connect to at least one target module 200. The second selection unit 62 is configured to determine the corresponding target module 200 according to each output trigger signal and provide each output trigger signal to the corresponding target module 200.

[0073] Specifically, the first selection unit 61 includes at least one 2-to-1 selector, and the first selection unit 61 selects an output trigger signal from the output interrupt signal and the update signal; such as Figure 10 As shown, when the first selection unit 61 includes eight 2-to-1 selectors, each 2-to-1 selector selects an output trigger signal from the output interrupt signal output_interrupt_request and the update signal PH_update_trigger. Therefore, the first selection unit 61 outputs eight output trigger signals OUT0-UT7. The second selection unit 62 can be a TRGMUX. The basic principle of TRGMUX is to map multiple trigger input sources (i.e., eight output trigger signals) to any one trigger output by using selection signals. The selection signals are usually composed of multiple switches, each switch corresponding to a trigger output source (i.e., target module 200). By controlling the state of the switches, the input signal can be selected to be transmitted to different output signals.

[0074] In some embodiments, such as Figure 9 As shown, the output circuit 40 is also adapted to connect to the general-purpose timer submodule 300. The output circuit 40 is also configured to send the updated value output_data to the general-purpose timer submodule 300 when the value in the output data register is updated, so that the general-purpose timer submodule 300 can determine whether the data transmission was successful.

[0075] In other words, this invention can also transmit the output result `output_data` of the digital filter 100 to the general-purpose timer submodule 300. First, the general-purpose timer module's transmission is enabled, allowing data to be written to it. Once the value in the output data register is updated, the `output_data_valid` flag is set, and the corresponding value `output_data` can be written to the MCS_RAM of the general-purpose timer module (i.e., the general-purpose timer submodule 300). Therefore, by querying the MCS_RAM of the general-purpose timer module, one can check whether the value `output_data` in the output data register has been successfully transmitted. By storing the data `output_data` in the general-purpose timer submodule 300, the digital filter 100 becomes more flexible and modular. Furthermore, the functionality of the submodule can be adjusted or expanded according to requirements to adapt to different application scenarios.

[0076] In summary, the digital filter according to embodiments of the present invention includes a filtering circuit, an accumulation circuit, a peak hold circuit, and a trigger signal generation circuit. The filtering circuit is configured to filter input data to output filtered data. The accumulation circuit is connected to the filtering circuit and is configured to accumulate or extract the filtered data to output an accumulation result. The peak hold circuit is connected to the accumulation circuit and is configured to perform peak hold processing on the accumulation result. The trigger signal generation circuit is adapted to be connected to a trigger source generation module and is configured to generate a trigger signal based on the trigger source output by the trigger source generation module, and provide the trigger signal to the filtering circuit, the accumulation circuit, and the peak hold circuit respectively, so that the filtering circuit, the accumulation circuit, and the peak hold circuit operate according to the trigger signal. Therefore, the trigger signal generation circuit can flexibly generate trigger signals according to the trigger source, without relying on real-time CPU intervention, and can dynamically adapt to external events, thereby improving the efficiency and response speed of the digital filter. Furthermore, the trigger signal generation circuit can be connected to multiple trigger source generation modules, and the output signal selection circuit can be connected to multiple target modules, realizing the interaction between the digital filter and different modules.

[0077] Corresponding to the above embodiments, embodiments of the present invention also provide a controller. For example... Figure 11 As shown, the controller 400 includes the digital filter 100 of any of the foregoing embodiments.

[0078] According to the controller of the present invention, by employing the above-described digital filter, the trigger signal generation circuit can flexibly generate a trigger signal based on the trigger source, without relying on real-time intervention of the CPU, and can dynamically adapt to external events, thereby improving the efficiency and response speed of the digital filter.

[0079] Corresponding to the above embodiments, embodiments of the present invention also provide a vehicle. For example... Figure 12 As shown, vehicle 500 includes the aforementioned controller 400.

[0080] According to the vehicle of the present invention, by employing the controller described above, the trigger signal generation circuit can flexibly generate a trigger signal based on the trigger source, without relying on real-time intervention of the CPU, and can dynamically adapt to external events, thereby improving the efficiency and response speed of the digital filter.

[0081] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0082] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0083] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.

[0084] In this invention, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific implementation.

[0085] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A digital filter, characterized in that, include: The filtering circuit is configured to filter the input data to output filtered data. An accumulation circuit, connected to the filtering circuit, is configured to accumulate or extract the filtered data to output an accumulation result. A peak hold circuit, connected to the accumulation circuit, is configured to perform peak hold processing on the accumulation result; A trigger signal generation circuit is adapted to be connected to a trigger source generation module. The trigger signal generation circuit is configured to generate a trigger signal based on the trigger source output by the trigger source generation module, and to provide the trigger signal to the filtering circuit, the accumulating circuit, and the peak hold circuit respectively, so that the filtering circuit, the accumulating circuit, and the peak hold circuit operate according to the trigger signal respectively.

2. The digital filter according to claim 1, characterized in that, The trigger source generation module is at least one of a PWM module, a timer, a general-purpose timer module, and a comparator module.

3. The digital filter according to claim 2, characterized in that, There are multiple trigger sources, and the trigger signal generation circuit includes: A trigger edge selection unit is adapted to be connected to the trigger source generation module. The trigger edge selection unit is configured to select the effective edge of each trigger source according to the trigger edge selection signal to obtain multiple trigger source signals. A trigger signal matching unit is connected to the trigger edge selection unit, and the trigger signal matching unit is configured to select a first signal source to a fifth signal source from the plurality of trigger source signals, respectively. A trigger signal generation unit is connected to the trigger signal matching unit. The trigger signal generation unit is configured to generate a first initialization flag of the peak hold circuit, a second initialization flag of the accumulation circuit, a third initialization flag of the filter circuit, an end flag of the peak hold circuit, and a disable flag of the accumulation circuit based on the first signal source to the fifth signal source, respectively. The trigger signal includes the first initialization flag, the second initialization flag, the third initialization flag, the end flag, and the disable flag.

4. The digital filter according to claim 3, characterized in that, The trigger signal generation unit includes five trigger signal generation modules, each of which includes: A first selection submodule is adapted to input a signal source, and the first selection submodule is configured to select a first trigger signal from the corresponding signal source according to a signal source selection signal; The second selection submodule is connected to the first selection submodule and is adapted to input a second trigger signal. The second selection submodule is configured to select one of the first trigger signal and the second trigger signal as a corresponding flag according to the setting signal.

5. The digital filter according to claim 3, characterized in that, When the trigger source generation module is a general-purpose timer module, the trigger source includes multiple first interrupt signals and multiple second interrupt signals. The trigger edge selection unit is further configured to select the effective edge of each first interrupt signal and the effective edge of each second interrupt signal according to the trigger edge selection signal to obtain multiple first trigger source signals and multiple second trigger source signals. The trigger signal matching unit is further configured to select a first signal source, a second signal source, and a third signal source from the multiple first trigger source signals, and to select a fourth signal source and a fifth signal source from the multiple second trigger source signals.

6. The digital filter according to claim 5, characterized in that, The number of the second interrupt signal corresponding to the fourth signal source is the same as the number of the first interrupt signal corresponding to the first signal source, and the number of the second interrupt signal corresponding to the fifth signal source is the same as the number of the first interrupt signal corresponding to the second signal source.

7. The digital filter according to any one of claims 3-6, characterized in that, The accumulation circuit is configured to, when the first initialization flag is enabled, accumulate or extract the filtered data according to the first initialization flag to output the accumulation result and write the accumulation result into the output data register, and when the disable flag is enabled, stop accumulating or extracting the filtered data.

8. The digital filter according to any one of claims 3-6, characterized in that, The peak hold circuit is further configured to update the value stored in the result register using the larger value between the filtered data and the value stored in the result register when the second initialization flag is enabled, and to stop peak hold processing on the filtered data when the end flag is enabled.

9. The digital filter according to claim 1, characterized in that, Also includes: An output circuit is connected to the accumulation circuit, and the output circuit is configured to perform format conversion on the accumulation result to output the conversion result, and to store the accumulation result or the conversion result; An output signal selection circuit is connected to the peak hold circuit and the output circuit respectively, and is adapted to connect to at least one target module. The output signal selection circuit is configured to determine at least one output trigger signal based on the output interrupt signal of the output circuit and the update signal of the peak hold circuit, and to provide each of the output trigger signals to the corresponding target module.

10. The digital filter according to claim 9, characterized in that, The output signal selection circuit includes: A first selection unit is connected to the peak hold circuit and the output circuit respectively, and the first selection unit is configured to select at least one of the output trigger signals from the output interrupt signal and the update signal; A second selection unit is connected to the first selection unit and adapted to connect at least one of the target modules. The second selection unit is configured to determine a corresponding target module based on each of the output trigger signals and to provide each of the output trigger signals to the corresponding target module.

11. The digital filter according to claim 9, characterized in that, The target module is one of the following: PWM module, timer module, general-purpose timer module, comparator module, and analog-to-digital converter module.

12. The digital filter according to claim 9, characterized in that, The output circuit is also adapted to connect to a general-purpose timer submodule, and the output circuit is further configured to send an updated value to the general-purpose timer submodule when the value in the output data register is updated, so that the general-purpose timer submodule can determine whether the data transmission was successful.

13. A controller, characterized in that, Includes the digital filter according to any one of claims 1-12.

14. A vehicle, characterized in that, Includes the controller according to claim 13.

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