Column memory circuit, chip, image sensor and imaging device

Abstract

The present invention provides a column memory circuit, chip, image sensor, and imaging device. The column memory circuit includes M×N memory modules, N readout modules, and a data transmission module. The correlated double sampling module of the column memory circuit is disposed in the readout module. A first end of the memory module receives a first data signal, a second end of the memory module is coupled to the first end of its corresponding readout module, and a second end of the readout module is coupled to the data transmission module. The memory module converts the received first data signal into a second data signal. The readout module performs correlated double sampling on the second data signal via the correlated double sampling module to obtain a third data signal, and the data transmission module outputs the third data signal. The present invention can significantly reduce the area of ​​the column memory circuit while ensuring good circuit performance. Using the column memory circuit provided by the present invention can significantly reduce the cost of image sensors.

Description

Technical Field

[0001] The present invention relates to the field of image processing technology, and in particular to a column memory circuit, a chip, an image sensor and an imaging device. Background Art

[0002] An image sensor typically includes components such as a pixel array, an analog-to-digital converter, and a column memory circuit. An image sensor is a device that converts an optical image into an electrical signal. For example, see Figure 1 , which schematically shows the flow of data signals during the imaging process. Figure 1 It can be seen that the pixel array 110 ( Figure 1 Not shown, see below Figure 7 ) is responsible for converting the collected image light signal into a voltage signal and outputting the voltage signal to the analog-to-digital converter 120 (ADC). The ADC 120 is responsible for comparing the received voltage signal with the ramp signal and generating a pulse signal when the two signals are equal. The column memory circuit 130 latches the data of the counter upon receiving the pulse signal, processes the data in a certain manner, and then outputs the data serially to the image signal processing (ISP) 150. The image processor 150 extracts and optimizes the received image data (such as color correction, gamma correction, etc.) to obtain an image that can be displayed, stored and / or further processed, and outputs it through the interface circuit 160.

[0003] Research has found that current column memory circuits have a large area and high power consumption. Although they have been well applied in high-performance image sensors, they are difficult to apply in low-cost image sensors.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0005] To address the technical problems of large area and high power consumption in the column memory circuits of image sensors in the prior art, the present invention provides a column memory circuit, chip, image sensor, and imaging device. The present invention can significantly reduce the area of ​​the column memory circuit while ensuring good circuit performance. The column memory circuit provided by the present invention can significantly reduce the cost of the image sensor.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: a column memory circuit for an image sensor, the column memory circuit comprising M×N memory modules, N readout modules, and a data transmission module, wherein the correlated double sampling module of the column memory circuit is disposed in the readout module; a first end of the memory module is configured to receive a first data signal, a second end of the memory module is coupled to a first end of the corresponding readout module, and a second end of the readout module is coupled to the data transmission module, where M≥2;

[0007] The storage module is configured to convert the received first data signal into a second data signal, the readout module is configured to perform correlated double sampling processing on the second data signal through the correlated double sampling module to obtain a third data signal, and the data transmission module is configured to output the third data signal.

[0008] Optionally, the correlated double sampling module includes a plurality of first transistors.

[0009] Optionally, each of the memory modules includes a first latch, a transcoding module, and a buffer module coupled in sequence, and the readout module further includes a second latch, a trigger, and a multiplexer, and the second latch, the correlated double sampling module, the trigger, and the multiplexer are coupled in sequence;

[0010] The first latch is configured to latch the first data signal upon receiving a first control signal from the image sensor, and send the latched first data signal to the transcoding module; the transcoding module is configured to transcode the first data signal to obtain a fourth data signal; the buffer module is configured to buffer the fourth data signal to obtain a first group of the second data signals for sending to the second latch, and to buffer a second group of the second data signals for sending to the correlated double sampling module after obtaining the first group of the second data signals;

[0011] The second latch is configured to latch the first group of the second data signals when receiving a second control signal; the correlated double sampling module is configured to perform correlated double sampling processing on the second group of the second data signals based on the first group of the second data signals to obtain the third data signal; the trigger sends the third data signal to the multiplexer when receiving the third control signal of the image sensor, and the multiplexer is configured to select the corresponding third data signal according to the fourth control signal of the image sensor and send it to the data transmission module.

[0012] Optionally, the first data signal is encoded in a Gray code manner, and the fourth data signal is encoded in a binary code manner.

[0013] Optionally, the trigger includes a D trigger.

[0014] Optionally, each of the memory modules includes a first latch and a buffer module coupled in sequence, and the readout module further includes a transcoding module, a second latch, a trigger, and a multiplexer; the transcoding module, the second latch, the correlated double sampling module, the trigger, and the multiplexer are coupled in sequence;

[0015] The first latch is configured to latch the first data signal and send the latched first data signal to the buffer module when receiving the first control signal of the image sensor, and the buffer module is configured to buffer the first data signal to obtain the second data signal and send the second data signal to the transcoding module;

[0016] The transcoding module is configured to transcode the second data signal to obtain a first group of fifth data signals for sending to the second latch, and after obtaining the first group of fifth data signals, transcode the subsequently received second data signal to obtain a second group of fifth data signals for sending to the correlated double sampling module; the second latch is configured to latch the first group of fifth data signals when receiving a second control signal; the correlated double sampling module is configured to perform correlated double sampling processing based on the first group of fifth data signals and the second group of fifth data signals to obtain the third data signal; the trigger sends the third data signal to the multiplexer when receiving a third control signal from the image sensor, and the multiplexer is configured to select the corresponding third data signal according to a fourth control signal of the image sensor and send it to the data transmission module.

[0017] Optionally, the transcoding module includes several second transistors.

[0018] In order to achieve the above object, the present invention further provides a chip for an image sensor, on which any of the column memory circuits described above is integrated.

[0019] In order to achieve the above object, the present invention further provides an image sensor, which includes any one of the above-mentioned column memory circuits or the above-mentioned chip.

[0020] In order to achieve the above object, the present invention further provides an imaging device, which includes any one of the above-mentioned column memory circuits, or the above-mentioned chip, or the above-mentioned image sensor.

[0021] Compared with the prior art, the column memory circuit, chip, image sensor, and imaging device provided by the present invention have the following advantages:

[0022] The column memory circuit provided by the present invention abandons the design method of disposing the correlated double sampling module in the memory module in the prior art, and adopts a design method of disposing the correlated double sampling module in the readout module. Based on the objective fact that the number of readout modules is much smaller than the number of memory modules, the number of correlated double sampling modules can be greatly reduced, which not only saves costs but also reduces the circuit area occupied by the correlated double sampling modules. In turn, the area of ​​the column memory circuit can be significantly reduced while ensuring good circuit performance. The column memory circuit provided by the present invention can significantly reduce the cost of image sensors and can be well applied to low-cost image sensors.

[0023] Since the chip for an image sensor, the image sensor, and the imaging device provided by the present invention belong to the same inventive concept as the column memory circuit provided by the present invention, the chip for an image sensor, the image sensor, and the imaging device provided by the present invention have at least all the advantages of the column memory circuit provided by the present invention. For details on the beneficial effects of the chip for an image sensor, the image sensor, and the imaging device provided by the present invention, please refer to the above description of the beneficial effects of the column memory circuit provided by the present invention, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the flow of data signals during the imaging process;

[0025] Figure 2 A schematic diagram of the flow of data signals in a column memory circuit of an image sensor;

[0026] Figure 3 Schematic diagram of the topological structure of a column memory circuit of an image sensor in the prior art;

[0027] Figure 4 A schematic block diagram of a column memory circuit provided by the present invention;

[0028] Figure 5 A schematic diagram of the topological structure of a column memory circuit provided by a first embodiment of the present invention;

[0029] Figure 6 A schematic diagram of the topological structure of a column memory circuit provided by a second embodiment of the present invention;

[0030] Figure 7 A schematic block diagram of the imaging device provided by the present invention;

[0031] The accompanying drawings are numerals as follows:

[0032] Image sensor 100, pixel array 110, pixel unit 111, analog-to-digital converter 120, column memory circuits 130 and 140, image processor 150, interface circuit 160;

[0033] Memory bank modules - Bank0, Bank1, Bank2, Bank3, 130A, 141, 141A, 141B, read modules - R01, R23, 130B, 142, 142A, 142B, 142C, 142D, data transmission module - 170;

[0034] First latches 131, 141A1, and 141B1, transcoding modules 132, 141A2, and 142B1, second latches 133, 142A1, and 142B2, correlated double sampling modules 134 and 143, buffer modules 135, 141A3, and 141B2, flip-flops 136, 142A2, and 142B3, and multiplexers 137, 142A3, and 142B4;

[0035] Gray code data - GC, comparator data - CMP, black level signal - BLK_EN, adjacent readout module output signal terminal - GBL;

[0036] First data signal-D1, second data signal-D2, third data signal-D3, fourth data signal-D4, fifth data signal-D5;

[0037] First control signal -T1, second control signal -T2, third control signal -T3, fourth control signal -T4;

[0038] Application - 200. DETAILED DESCRIPTION

[0039] The following is a detailed description of a column memory circuit, chip, image sensor, and imaging device proposed by the present invention, with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of the embodiments of the present invention. To make the purposes, features, and advantages of the present invention more readily apparent, please refer to the accompanying drawings. It should be noted that the structures, proportions, and sizes illustrated in the drawings of this specification are intended solely to facilitate understanding and reading by those skilled in the art, and are not intended to limit the implementation of the present invention. Any structural modifications, changes in proportions, or adjustments in size, provided they produce the same or similar effects and achieve the same objectives, should still fall within the scope of the technical content disclosed herein. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and environment in which they are intended. Furthermore, in the embodiments described below, the same reference numerals may be used across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions may be omitted. In this specification, similar reference numerals and letters are used to refer to similar items, so once an item is defined in one figure, it need not be further discussed in subsequent figures. In addition, if the method described herein includes a series of steps, the order in which the steps are presented herein is not necessarily the only order in which the steps can be performed, and some of the steps described may be omitted and / or other steps not described herein may be added to the method.

[0040] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element. The singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features.

[0041] It should be understood that when an element is referred to as being "connected," "connected to," or "coupled to" another element, it can be directly connected to the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly connected to" another element, there are no intervening elements.

[0042] In order to facilitate understanding and explanation of the present invention, before describing the specific implementations of the column memory circuit, image sensor, and imaging device provided by the present invention, the main research process of the present invention is first described.

[0043] First, see Figure 2 , which schematically shows the flow of data signals in the column memory circuit of the image sensor. Figure 2 As shown, Figure 2 For example, a column memory circuit includes four memory bank modules Bank0, Bank1, Bank2, and Bank3, two readout modules R01 and R23, and a data transmission module 170. Memory bank modules Bank0 and Bank1 share the readout module R01, and memory bank modules Bank2 and Bank3 share the readout module R23. That is, every two memory bank modules share one readout module. The column memory circuit processes data signals as follows: The analog-to-digital converter 120 ( Figure 2 Not shown, please combine Figure 1Gray code data GC from the timing control circuit ( Figure 2 The comparator data CMP (not shown) enters the storage modules Bank0, Bank1, Bank2 and Bank3 from the outside. The storage modules Bank0 and Bank1 send the processed data to the corresponding read modules R01 and then transmit it to the data transmission module 170. The storage modules Bank2 and Bank3 first send the processed data to the corresponding read modules R23 and then send it to the data transmission module 170 through the read module R01. All the read modules R01 and R23 together constitute a shift read function. The data transmission module 170 receives the data processed by the read modules R01 and R23 and outputs the data from the column memory circuit 130.

[0044] See Figure 3 , Figure 3 FIG. 1 is a schematic diagram of the topological structure of a column memory circuit of an image processor in the prior art. Figure 3 As shown, in this example, the column memory circuit 130 includes M×N memory bank modules ( Figure 3 The i-th memory module 130A is used as an example, 1≤i≤(M×N)), N readout modules ( Figure 3 The jth readout module 130B is shown as an example, where 1≤j≤N, and one data transmission module 170. The data signal processing process is roughly as follows: Gray code data GC is latched into the first latch 131 at the falling edge of the comparator data CMP signal. The transcoding module 132 converts the latched Gray code data GC into binary data BC. The second latch 133 stores the image sensor's black level signal BLK_EN and, together with the Correlated Double Sampling (CDS) module 134, implements the CDS function. The buffer module 135 transmits the CDS-completed data signal BIT_OUT from the memory module 130A to the corresponding readout module 130B. As previously mentioned, the N readout modules together form a shift register. Furthermore, the read module 130A first connects the memory module 130A and the memory module ( Figure 3 Not shown) (e.g. Figure 2 The data in the memory modules bank0 and bank1 of the shared read module R01 are sent out, and then the multiplexer 137 is switched to the adjacent read module output signal terminal GBL, and the read module 130B sends the data of other memory modules through the multiplexer 137 (for example Figure 2The data of the memory modules bank2 and bank3 that share the read module R23 are first sent to the read module R23, then transmitted to the read module R01 for output, and then output from the column memory circuit 130 through the data transmission module 170.

[0045] It should be noted that this document only describes the column memory circuit portion related to the present invention. For more detailed information about the column memory circuit not mentioned herein, please refer to the relevant technical adaptability understanding known to those skilled in the art.

[0046] Depend on Figure 3 As can be seen, conventional column memory circuits typically include a data transmission module 170, N readout modules 130B, and M×N memory modules 130A (the specific values ​​of M and N are related to the image sensor's resolution). Most functions are implemented in the memory modules 130A. After extensive research, the inventors discovered that circuits with complex functions, such as the transcoding module 132 and the correlated double sampling module 134, typically consist of a large number of transistors. The combination of these complex functions and the large number of memory modules 130A results in the column memory circuit 130 occupying a large circuit area, making it difficult to apply to low-cost image sensor products.

[0047] Based on the above research, the core idea of ​​the present invention is to provide a column memory circuit, an image sensor and an imaging device. The present invention can significantly reduce the area of ​​the column memory circuit and well ensure the circuit performance. The column memory circuit provided by the present invention can significantly reduce the cost of the image sensor.

[0048] It should be noted that the column memory circuit and chip for an image sensor provided by the present invention can be applied to the image sensor and imaging device provided by the present invention, and the image sensor provided by the present invention can be applied to the imaging device provided by the present invention. It should be understood that the terms "imaging device" or "imaging device" or other similar terms used herein include general imaging devices, such as but not limited to cameras, video cameras, mobile phones, tablet computers, learning machines, and medical imaging devices equipped with image sensors.

[0049] In order to realize the above idea, the present invention provides a column memory circuit. For example, see Figure 4 , which schematically shows a block diagram of the column memory circuit provided by the present invention. Figure 4As can be seen, the column memory circuit 140 provided by the present invention includes M×N memory modules 141, N readout modules 142, and a data transmission module 170. The correlated double sampling module 143 of the column memory circuit 140 is disposed within the readout module 142. The first end of each memory module 141 is configured to receive a first data signal D1, the second end of each memory module 141 is coupled to the first end of the corresponding readout module 142, and the second end of each readout module 142 is coupled to the data transmission module 170, where M ≥ 2. Furthermore, the memory module 141 is configured to convert the received first data signal D1 into a second data signal D2. The readout module 142 is configured to perform correlated double sampling on the second data signal D2 via the correlated double sampling module 143 to obtain a third data signal D3. The data transmission module 170 is configured to output the third data signal D3.

[0050] Therefore, the column memory circuit provided by the present invention abandons the design method of arranging the correlated double sampling module in the memory module in the prior art, and adopts a design method of arranging the correlated double sampling module 143 in the readout module 142. By fully utilizing the objective fact that the number of the readout modules 142 is much smaller than the number of the memory modules 141, the number of the correlated double sampling modules 143 can be greatly reduced, which not only saves costs but also reduces the circuit area occupied by the correlated double sampling modules 143. In turn, the area of ​​the column memory circuit can be significantly reduced while ensuring good circuit performance. The column memory circuit provided by the present invention can significantly reduce the cost of the image sensor. The column memory circuit provided by the present invention can be well applied to low-cost image sensors.

[0051] Specifically, compared with the prior art design of arranging the correlated double sampling module in the memory module, the column memory circuit provided by the present invention has the correlated double sampling module 143 arranged in the readout module 142 , which can save (M−1)×N correlated double sampling modules 143 .

[0052] Preferably, in some exemplary embodiments, the correlated double sampling module 143 includes a plurality of first transistors ( Figure 4(not shown). Thus, the design method of implementing the correlated double sampling module 143 using a plurality of first transistors is not only easy to implement, but also the transistors are inexpensive and readily available. It should be noted that those skilled in the art should understand that the above-mentioned use of first transistors to implement the correlated double sampling module 143 is merely an exemplary description of a preferred embodiment and is not a limitation of the present invention. The present invention does not impose any limitation on the specific implementation of the correlated double sampling module 143. For more detailed information about the correlated double sampling module 143, please refer to the relevant technologies known to those skilled in the art. Due to space limitations, this article will not elaborate on this.

[0053] For example, taking the correlated double sampling module 143 including P first transistors as an example, the design method of setting the correlated double sampling module in the memory module in the prior art requires a total of M×N×P first transistors, while the column memory circuit provided by the present invention only requires N×P first transistors. Therefore, compared with the prior art, the present invention can save (M-1)×N×P transistors.

[0054] For example, see Figure 5 , which schematically shows a topological structure diagram of a column memory circuit provided by a first embodiment of the present invention. Figure 5 In the example, the i-th memory module 141A and the j-th read module 142A are used. Figure 5It can be seen that in the column memory circuit provided by the first embodiment of the present invention, each of the storage body modules 141A includes a first latch 141A1, a transcoding module 141A2 and a buffer module 141A3 coupled in sequence, and each of the readout modules 142A also includes a second latch 142A1, a trigger 142A2 and a multiplexer 142A3, and the second latch 142A1, the correlated double sampling module 143, the trigger 142A2 and the multiplexer 142A3 are coupled in sequence. Furthermore, the first latch 141A1 is configured to latch the first data signal D1 (for example, a voltage signal in a Gray code format, which represents the output voltage value of the pixel) when receiving the first control signal T1 of the image sensor (for example, the comparator data CMP), and send the latched first data signal D1 to the transcoding module 141A2; the transcoding module 141A2 is configured to transcode the first data signal D1 to obtain a fourth data signal D4 (for example, a voltage signal in a binary format); the buffer module 135 is configured to buffer the fourth data signal D4 to obtain a first group of the second data signals D21 (a voltage signal in a binary format, which represents the voltage value of the black level signal) for sending to the second latch, and buffer the second group of the second data signals D21 for sending to the correlated double sampling module 143 after obtaining the first group of the second data signals D21. The first and second data signals D21 are latched in the first and second latches 142A1 upon receiving a second control signal T2 (e.g., a black level storage signal); the correlated double sampling module 143 is configured to perform correlated double sampling processing on the first and second data signals D21 and D22 to obtain the third data signal D3 (a voltage signal in a binary format); the trigger 142A2 sends the third data signal D3 to the multiplexer 142A3 upon receiving a third control signal T3 (e.g., a readout clock signal) of the image sensor; the multiplexer 142A3 is configured to select the corresponding third data signal D3 according to a fourth control signal T4 (e.g., a memory block selection signal) of the image sensor and send it to the data transmission module 170.

[0055] The column memory circuit provided by the first embodiment of the present invention has a memory module 141A including a first latch 141A1, a transcoding module 141A2, and a buffer module 141A3. Thus, the stability of the first data signal D1 can be ensured by the first latch 141A1, and the first data signal D1 is converted into the fourth data signal D4 by the transcoding module 141A2, which can lay a solid foundation for the readout module 142A to efficiently process the data signal. The buffer module 141A3 buffers the fourth data signal D4, which can ensure that the fourth data signal D4 of the multiple memory modules connected to the readout module 142A is stably transmitted to the second latch 142A2. Furthermore, the readout module 142A of the column memory circuit includes the second latch 142 coupled in sequence. A1, the correlated double sampling module 143, the trigger 142A2 and the multiplexer 142A3. Therefore, the second latch 142A1 can lay a good foundation for the correlated double sampling module 143 to suppress the fixed pattern noise and reset noise in the second data signal D2, thereby laying a good foundation for improving image quality. The trigger 142A2 and the fourth control signal T4 can well coordinate and synchronize the switching and readout timing of the multiplexer 142A3 between the readout modules 142, so that the multiplexer 142A3 can select the third data signal D3 of the corresponding readout module 142 for output (for example, the multiplexer 142A3 can select whether to output the third signal data D3 of the readout module 142A or the third signal data D3 of the readout module 142C).

[0056] Preferably, still taking the readout module 142A as an example, one input terminal of the multiplexer 142A3 is coupled to the output terminal of the trigger 142A2 of the readout module 142A, and the other input terminal of the multiplexer 142A3 is coupled to the multiplexer ( Figure 5 Furthermore, most of the readout modules 142 are coupled to the data transmission module 170 via the multiplexers of other adjacent readout modules 142. For the last readout module 142, the output of its multiplexer is directly connected to the data transmission module 170.

[0057] For example, in some exemplary embodiments, the first data signal D1 is encoded using a Gray code, and the fourth data signal D4 is encoded using a binary code. Thus, using Gray code to encode the first data signal D1 effectively reduces transmission errors, while using binary encoding for the fourth data signal D4 facilitates efficient processing by a subsequent readout module. It should be noted that those skilled in the art will appreciate that the present invention does not impose excessive limitations on the specific formats of the first data signal D1 and the fourth data signal D4, and that these should be appropriately configured according to actual needs when implementing the present invention.

[0058] For example, in some exemplary embodiments, the trigger 142A2 includes a D flip-flop. Thus, the column memory circuit provided by the present invention, wherein the trigger 142A2 of the readout module 142A is designed as a D flip-flop, can well ensure serial transmission of the third data signal D3.

[0059] It is clear from the above description that the column memory circuit provided by the present invention sets the correlated double sampling module 134 in the readout module 142A, which will lead to an increase in the amount of data output by the memory module 141A. If the performance of the column memory circuit needs to be further improved, although the performance requirements of the buffer module 141A3 of the column memory circuit may be increased, overall, the column memory circuit provided by the present invention still has a good cost-effectiveness.

[0060] For example, see Figure 6 , Figure 6 The topological structure diagram of the column memory circuit provided by the second embodiment of the present invention is schematically shown. Figure 5 The column memory circuit in is similar to that in Figure 6 In the example, the i-th storage module 141B and the j-th read module 142B are used. Figure 5 and Figure 6 It can be seen that the column memory circuit provided by the second embodiment of the present invention has the same basic principle as the column memory circuit provided by the first embodiment of the present invention. In order to avoid redundancy, the same parts of the two will not be described in detail. For parts not mentioned in this document, please refer to the relevant description of the first embodiment of the present invention for adaptive understanding. The following only describes the differences from the first embodiment of the present invention.

[0061] like Figure 6As shown, the column memory circuit provided by the second embodiment of the present invention, each of the memory modules 141B includes a first latch 141B1 and a buffer module 141B2 coupled in sequence, and the read module 142B also includes a transcoding module 142B1, a second latch 142B2, a trigger 142B3 and a multiplexer 142B4; the transcoding module 142B1, the second latch

[0062] 142B2, the correlated double sampling module 143, the trigger 142B3 and the multiplexer 142B4 are coupled in sequence. Furthermore, the first latch 141B1 is configured to latch the first data signal D1 (for example, a voltage signal in a Gray code format, which represents the output voltage value of the pixel) when receiving the first control signal T1 of the image sensor (for example, the comparator data CMP) and send the latched first data signal D1 to the buffer module 141B2, the buffer module 141B2 is configured to buffer the first data signal D1 to obtain the second data signal D2 (for example, a voltage signal in a Gray code format, which represents the output voltage value of the pixel), and send the second data signal D2 to the transcoding module 142B1; the transcoding module 142B1 is configured to transcode the second data signal D2 to obtain a first group of fifth data signals D51 (for example, a voltage signal in a binary format, which represents the voltage value of the black level signal) for sending to the second latch, and after obtaining the first group of fifth data signals D51, transcode the subsequently received The second data signal D2 is transcoded to obtain a second group of fifth data signals D52 (a voltage signal in binary format, which represents the voltage value of the image pixel) for transmission to the correlated double sampling module 143. The second latch 142B2 is configured to latch the first group of fifth data signals D51 upon receiving a second control signal T2 (e.g., a black level storage signal). The correlated double sampling module 143 is configured to perform correlated double sampling processing based on the first group of fifth data signals D51 and the second group of fifth data signals D52 to obtain the third data signal D3. The flip-flop 142B3 transmits the third data signal D3 to the multiplexer 142B4 upon receiving a third control signal T3 (e.g., a readout clock signal) of the image sensor. The multiplexer 142B4 is configured to select the corresponding third data signal D3 according to a fourth control signal T4 (e.g., a memory block selection signal) of the image sensor and transmit it to the data transmission module 170.

[0063] The column memory circuit provided by the second embodiment of the present invention has a memory module 141B including a first latch 141B1 and a buffer module 141B2, whereby the stability of the first data signal D1 can be ensured by the first latch 141B1, and the first data signal D1 can be buffered by the buffer module 141B2, so that the second data signal D2 of multiple memory modules connected to the readout module 142B can be stably transmitted to the transcoding module 142B1; further, the readout module 142B of the column memory circuit includes the transcoding module 142B1, the second latch 142B2, the correlated double sampling module 143, the trigger 142B3 and the multiplexer 142B4 coupled in sequence, whereby the transcoding module 142B1 can transmit the first data signal D1 to the transcoding module 142B1. The second data signal D2 is converted into the fifth data signal D5, which can lay a solid foundation for the second latch 142B2 to efficiently process the data signal. The second latch 142B4 can be used by the correlated double sampling module 143 to suppress the fixed pattern noise and reset noise in the fifth data signal D5, thereby improving the image quality. The trigger 142B3 can synchronize the switching and readout timing of the multiplexer 142B4 between the readout modules 142, so that the multiplexer 142B4 can select the third data signal D3 of the corresponding readout module 142 for output (for example, the multiplexer 142B4 can select whether to output the third signal data D3 of the readout module 142B or the third signal data D3 of the readout module 142D).

[0064] Preferably, in some exemplary embodiments, the transcoding module 142B1 includes a plurality of second transistors ( Figure 6 (not shown). Thus, the transcoding module 142B1 adopts a design method of multiple second transistors, which is simple in logic and easy to implement. It should be noted that those skilled in the art should understand that the use of second transistors to implement the transcoding module 142B1 is merely an exemplary description of a preferred embodiment, and not a limitation of the present invention. The present invention does not impose any limitation on the specific implementation of the transcoding module 142B1. For more detailed information about the transcoding module 142B1, please refer to the relevant technologies known to those skilled in the art. Due to space limitations, this article will not elaborate on this.

[0065] For example, taking the correlated double sampling module including P first transistors and the transcoding module including Q second transistors as an example, in the prior art, the transcoding module and the correlated double sampling module are both arranged in the memory module design, and these two modules require a total of M×N×P first transistors and M×N×Q second transistors. However, using the column memory circuit provided by the second embodiment of the present invention, these two modules require a total of N×P first transistors and N×Q second transistors. Therefore, compared with the prior art, the present invention can save (M-1)×N×(P+Q) transistors.

[0066] It is clear from the above description that the column memory circuit provided by the second embodiment of the present invention sets both the transcoding module 142B1 and the correlated double sampling module 143 in the readout module 142B, which will result in an increase in the amount of data output by the storage module 141B. If the performance of the column memory circuit needs to be further improved, although the performance requirements for the buffer module 141B2 of the column memory circuit may be increased and support for a larger data bit width may be required, overall, the column memory circuit provided by the present invention still has a good cost-effectiveness.

[0067] It should be noted that, as those skilled in the art will appreciate, the present invention does not impose any particular limitations on the specific type of image sensor. For example, the image sensor may be, but is not limited to, a CMOS image sensor. Furthermore, the present invention does not impose any particular limitations on the specific values ​​of M, N, P, and Q. Preferably, the values ​​of M and N are related to the resolution of the image sensor and should be appropriately set according to actual needs when implementing the present invention.

[0068] A third embodiment of the present invention provides a chip for an image sensor, on which the column memory circuit described in any of the above embodiments is integrated. Thus, using a chip integrating the column memory circuit provided by the present invention not only reduces the cost of the image sensor but also further improves the image sensor's integration level.

[0069] A fourth embodiment of the present invention provides an image sensor, comprising the column memory circuit or chip described in any of the aforementioned embodiments. Because the image sensor provided by the present invention and the column memory circuit provided by the present invention are based on the same inventive concept, the image sensor provided by the present invention possesses at least all the advantages of the column memory circuit provided by the present invention. For details on the beneficial effects of the image sensor provided by the present invention, please refer to the above description of the beneficial effects of the column memory circuit provided by the present invention, and a detailed description thereof will not be repeated here.

[0070] A fifth embodiment of the present invention provides an imaging device. The imaging device provided by this embodiment includes the column memory circuit provided by any of the above embodiments, or the chip provided by the embodiments herein, or the image sensor provided by the present invention. For example, see Figure 7 , Figure 7 This is a structural block diagram of the imaging device provided in this embodiment. Figure 7 As shown, the image sensor 100 of the imaging device provided in this embodiment includes the column memory circuit 140 described in any of the above embodiments. Since the imaging device provided in this embodiment and the image sensor provided in the present invention are based on the same inventive concept, and the image sensor provided in the present invention and the column memory circuit provided in the present invention are based on the same inventive concept, the imaging device provided in this embodiment has at least all the advantages of the column memory circuit provided in the present invention. For details, please refer to the above description of the beneficial effects of the column memory circuit, and a detailed description thereof will not be provided here.

[0071] Furthermore, if Figure 7 As shown, the imaging device provided in this embodiment further includes an application (Application, APP) 200, and the image sensor 100 further includes a pixel array 110, an analog-to-digital converter 120, an image processor 150, and an interface circuit 160. For more detailed information about the image processor 150 and the application 200 of the imaging device, please refer to the relevant technologies known to those skilled in the art. Due to space limitations, this article will not elaborate on this. However, it is understandable that, as mentioned above, the present invention does not impose too many limitations on the imaging device. For example, the imaging device includes but is not limited to a video camera, a still camera, and a mobile phone with a camera function.

[0072] Compared with the prior art, the column memory circuit, chip, image sensor, and imaging device provided by the present invention have the following beneficial effects:

[0073] The column memory circuit provided by the present invention abandons the design method of disposing the correlated double sampling module in the memory module in the prior art, and adopts a design method of disposing the correlated double sampling module in the readout module. Based on the objective fact that the number of readout modules is much smaller than the number of memory modules, the number of correlated double sampling modules can be greatly reduced, which not only saves costs but also reduces the circuit area occupied by the correlated double sampling modules. In turn, the area of ​​the column memory circuit can be significantly reduced while ensuring good circuit performance. The column memory circuit provided by the present invention can significantly reduce the cost of image sensors and can be well applied to low-cost image sensors.

[0074] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0075] The foregoing description is merely an illustration of preferred embodiments of the column memory circuit, chip, image sensor, and imaging device provided by the present invention and is not intended to limit the scope of the present invention. Any changes or modifications made by persons skilled in the art based on the foregoing disclosure are considered within the scope of protection of the present invention. Obviously, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the present invention. Thus, the present invention is intended to encompass such modifications and variations as long as they fall within the scope of the present invention and its equivalents.

Claims

1. A column memory circuit for an image sensor, characterized in that: The method comprises M×N memory modules, N readout modules, and a data transmission module, wherein the correlated double sampling module of the column memory circuit is arranged in the readout module; a first end of the memory module is configured to receive a first data signal, a second end of the memory module is coupled to a first end of the corresponding readout module, and a second end of the readout module is coupled to the data transmission module, where M≥2; The storage module is configured to convert the received first data signal into a second data signal, the readout module is configured to perform correlated double sampling processing on the second data signal through the correlated double sampling module to obtain a third data signal, and the data transmission module is configured to output the third data signal.

2. The column memory circuit according to claim 1, wherein: The correlated double sampling module includes a plurality of first transistors.

3. The column memory circuit according to claim 1, wherein: Each of the memory modules includes a first latch, a transcoding module, and a buffer module coupled in sequence, and the readout module further includes a second latch, a trigger, and a multiplexer, and the second latch, the correlated double sampling module, the trigger, and the multiplexer are coupled in sequence; The first latch is configured to latch the first data signal upon receiving a first control signal from the image sensor, and send the latched first data signal to the transcoding module; the transcoding module is configured to transcode the first data signal to obtain a fourth data signal; the buffer module is configured to buffer the fourth data signal to obtain a first group of the second data signals for sending to the second latch, and to buffer a second group of the second data signals for sending to the correlated double sampling module after obtaining the first group of the second data signals; The second latch is configured to latch the first group of the second data signals when receiving a second control signal; the correlated double sampling module is configured to perform correlated double sampling processing based on the first group of the second data signals and the second group of the second data signals to obtain the third data signal; the trigger sends the third data signal to the multiplexer when receiving the third control signal of the image sensor, and the multiplexer is configured to select the corresponding third data signal according to the fourth control signal of the image sensor and send it to the data transmission module.

4. The column memory circuit according to claim 3, wherein: The first data signal is encoded using a Gray code, and the fourth data signal is encoded using a binary code.

5. The column memory circuit according to claim 3, wherein: The flip-flop includes a D flip-flop.

6. The column memory circuit according to claim 1, wherein: Each of the memory modules includes a first latch and a buffer module coupled in sequence, and the readout module further includes a transcoding module, a second latch, a trigger, and a multiplexer; the transcoding module, the second latch, the correlated double sampling module, the trigger, and the multiplexer are coupled in sequence; The first latch is configured to latch the first data signal and send the latched first data signal to the buffer module when receiving the first control signal of the image sensor, and the buffer module is configured to buffer the first data signal to obtain the second data signal and send the second data signal to the transcoding module; The transcoding module is configured to transcode the second data signal to obtain a first group of fifth data signals for sending to the second latch, and after obtaining the first group of fifth data signals, transcode the subsequently received second data signal to obtain a second group of fifth data signals for sending to the correlated double sampling module; the second latch is configured to latch the first group of fifth data signals when receiving a second control signal; the correlated double sampling module is configured to perform correlated double sampling processing based on the first group of fifth data signals and the second group of fifth data signals to obtain the third data signal; the trigger sends the third data signal to the multiplexer when receiving a third control signal from the image sensor, and the multiplexer is configured to select the corresponding third data signal according to a fourth control signal of the image sensor and send it to the data transmission module.

7. The column memory circuit according to claim 6, wherein: The transcoding module includes a plurality of second transistors.

8. A chip for an image sensor, characterized in that: The column memory circuit according to any one of claims 1 to 7 is integrated on the chip.

9. An image sensor, characterized in that: The method comprises the column memory circuit according to any one of claims 1 to 7 or the chip according to claim 8.

10. An imaging device, characterized in that: The method comprises the column memory circuit according to any one of claims 1 to 7, the chip according to claim 8, or the image sensor according to claim 9.

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