Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device includes forming a bit line structure on a substrate, forming spacers along sidewalls of the bit line structure, where each spacer includes an air gap. The method further includes forming a conductive structure between and over the bit line structures, wherein the conductive structure exposes a portion of the bit line structures. The method further includes forming an isolation structure between the conductive structure and the bit line structure, the isolation structure being implanted to form an implanted isolation structure, forming a support layer over the implanted isolation structure and the conductive structure, and forming a capacitive structure over the conductive structure and the implanted isolation structure. The implanted isolation structure has high etching resistance, and when the formation of the capacitor structure is not aligned, air gap breakdown can be prevented. Further, the width of the bottom surface of the bottom electrode layer in the capacitive structure may be enlarged, such that contact resistance between the capacitive structure and the conductive structure is improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] A traditional semiconductor device connects a capacitor and a transistor. For example, the capacitor can perfectly sit on the landing pad. When the technology is miniaturized, more precise overlay control between the capacitor and the landing pad is required to increase the process integration margin. However, the isolation structure of adjacent landing pads can be easily damaged during capacitor formation, resulting in electrical short and loss of air gap (AG) function. Summary of the Invention

[0003] The present disclosure provides a method for manufacturing a semiconductor device. The method includes forming a bit line structure on a substrate, forming spacers along sidewalls of the bit line structure, wherein each spacer includes an air gap. The method further includes forming a conductive structure between and above the bit line structures, wherein the conductive structure exposes a portion of the bit line structure. The method further includes forming an isolation structure between the conductive structure and the bit line structure, implanting the isolation structure to form an implanted isolation structure, forming a support layer above the implanted isolation structure and the conductive structure, and forming a capacitor structure above the conductive structure and the implanted isolation structure.

[0004] In some embodiments, forming spacers along sidewalls of the bit line structure, each spacer including an air gap includes sequentially forming a first spacer layer, a sacrificial spacer layer, and a second spacer layer along sidewalls of the bit line structure, and removing the sacrificial spacer layer after forming the conductive structure.

[0005] In some embodiments, forming a conductive structure between and above the bit line structures includes forming a first trench between the bit line structures, the first trench exposing a portion of the substrate. Forming a first conductive layer in the first trench. Forming a second conductive layer above the first conductive layer. Forming a barrier layer above the second conductive layer. Forming a landing pad to overfill the first trench. Forming a second trench by removing a portion of the barrier layer, a portion of the landing pad, and a portion of the bit line structure.

[0006] In some embodiments, forming an isolation structure between the conductive structure and the bit line structure includes forming an isolation layer between and above the conductive structure and the bit line structure, and removing a top portion of the isolation layer, wherein a top surface of the isolation layer is coplanar with a top surface of the conductive structure.

[0007] In some embodiments, an implantation isolation structure is implanted to form an implanted isolation structure including forming a photoresist over a conductive structure and implanting dopants into the isolation structure.

[0008] In some embodiments, the doping depth of the dopants is at 50 nm from the top surface of the implanted isolation structure.

[0009] In some embodiments, the implanted isolation structure has a first dry etching rate, and the first dry etching rate is less than a second dry etching rate of the isolation structure.

[0010] In some embodiments, the implanted isolation structure has a first dry etching rate, and the first dry etching rate is less than a third dry etching rate of a support layer.

[0011] In some embodiments, the ratio of the third dry etching rate to the first dry etching rate is greater than 8.87.

[0012] In some embodiments, forming a capacitor structure over the conductive structure and the implanted isolation structure includes forming a bottom electrode over the conductive structure. Forming a dielectric layer conformal to the bottom electrode. Forming a top electrode layer conformal to the dielectric layer.

[0013] The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a bit line structure over the substrate, spacers along sidewalls of the bit line structure, conductive structures between the spacers, and an isolation structure between the conductive structures and the bit line structure, wherein each spacer includes an air gap and an implanted isolation structure.

[0014] In some embodiments, each spacer includes a first spacer layer contacting one of the bit line structures and a second spacer layer contacting one of the conductive structures, wherein the first spacer layer is separated from the second spacer layer by the air gap.

[0015] In some embodiments, the semiconductor device further includes a capacitor structure over the conductive structure and the implanted isolation structure, wherein each capacitor structure includes a bottom electrode contacting the conductive structure. A dielectric layer conformal to the bottom electrode. A top electrode layer conformal to the dielectric layer.

[0016] In some embodiments, the bottom electrode of the capacitor structure further contacts the implanted isolation structure.

[0017] In some embodiments, the width of the bottom surface of the bottom electrode is greater than the width of the top surface of the conductive structure.

[0018] In some embodiments, the top surface of the implanted isolation structure is coplanar with the top surface of the conductive structure.

[0019] In some embodiments, boron and silicon are implanted as dopants into the implanted isolation structure.

[0020] In some embodiments, the doping depth of the doping is at 50 nm from the top surface of the implanted isolation structure.

[0021] In some embodiments, the implanted isolation structure contacts the spacer and the bit line structure.

[0022] A semiconductor device having an implanted isolation structure between a conductive structure and a bit line structure, the implanted isolation structure having a high etching resistance, can prevent punching through the air gap AG when the formation of the capacitor structure is misaligned. In addition, the width of the bottom surface of the bottom electrode layer can be enlarged, so as to improve the contact resistance between the capacitor structure and the landing pad. Description of the Drawings

[0023] The present disclosure can be more fully understood by reading the following embodiments in conjunction with the detailed description of the accompanying drawings below:

[0024] Figures 1 to 14 is a cross-sectional view of a method of manufacturing a semiconductor device at various stages according to some embodiments of the present invention.

[0025] Figure 15 and Figure 16 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Detailed Description of the Embodiments

[0026] Embodiments of the present invention will now be described in detail, and examples thereof are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or similar components.

[0027] Referring to Figure 1 , a substrate 100 is provided. The substrate 100 includes an active region 101 and an isolation structure 102 that defines the active region 101 in the substrate 100. A dielectric layer 106 is formed over the active region 101 and the isolation structure 102. A bit line contact 108 is formed in the dielectric layer 106 and contacts the active region 101. The substrate 100 may be a silicon substrate or other suitable semiconductor substrate. The isolation structure 102 may be formed of silicon oxide, silicon nitride, etc. The dielectric layer 106 may be formed of silicon oxide, silicon nitride, etc.

[0028] A bit line structure 110 is formed above a substrate 100. The bit line structure 110 includes a barrier layer 112, a metal layer 114 above the barrier layer 112, and a hard mask layer 116 above the metal layer 114. The bit line structure 110 can be formed by, for example, sequentially forming a barrier material layer, a metal material layer, and a hard mask material layer above the substrate 100. Then, the barrier material layer, the metal material layer, and the hard mask material layer are patterned into the barrier layer 112, the metal layer 114, and the hard mask layer 116 to form the bit line structure 110.

[0029] A first spacer layer 122, a sacrificial spacer layer 124, and a second spacer layer 126 are sequentially formed along the sidewalls of the bit line structure 110. First, a first spacer material layer conformal to the bit line structure 110 and the dielectric layer 106 is formed, and then an anisotropic process is performed to remove the horizontal portions of the first spacer material layer. The vertical portions of the first spacer material layer form the first spacer layer 122, and the first spacer layer 122 contacts the sidewalls of the bit line structure 110 and is conformal to the sidewalls of the bit line structure 110. After that, a second spacer material layer is formed conformal to the first spacer layer 122, the bit line structure 110, and the dielectric layer 106, and then an anisotropic process is performed to remove the horizontal portions of the second spacer material layer. The vertical portions of the second spacer material layer form the sacrificial spacer layer 124, and the sacrificial spacer layer 124 contacts the first spacer layer 122 and is conformal to the first spacer layer 122. After that, a second spacer layer 126 is formed conformal to the sacrificial spacer layer 124, the bit line structure 110, and the dielectric layer 106. The first spacer layer 122, the sacrificial spacer layer 124, and the second spacer layer 126 are formed of a dielectric material such as silicon oxide, silicon nitride, etc., and the sacrificial spacer layer 124 is formed of a material different from that of the first spacer layer 122 and the second spacer layer 126. For example, if the first spacer layer 122 and the second spacer layer 126 are formed of silicon nitride, the sacrificial spacer layer 124 is formed of silicon oxide.

[0030] See Figure 2 , a trench T1 is formed between the bit line structures 110 and exposes a portion of the substrate 100. Then, the trench T1 is formed by performing an etching process to pass through the second spacer layer 126 and the dielectric layer 106 to expose the substrate 100. During the formation of the trench T1, the second spacer layer 126 above the bit line structure 110 is also removed, such that the top surface of the bit line structure 110 is exposed.

[0031] See Figure 3, a first conductive layer 132 is formed in the trench T1 between the bit line structures 110. In particular, a first conductive material layer may be formed to overfill the trench T1 first. After that, a planarization process is performed to remove the excess portion of the first conductive material layer above the bit line structures 110 to expose the top surface of the bit line structures 110. After that, the first conductive material layer is etched back to form the first conductive layer 132 in the trench T1. In some embodiments, the first conductive layer 132 is formed of doped polysilicon.

[0032] Refer to Figure 4 , a second conductive layer 134 is formed above the first conductive layer 132, a barrier layer 136 is formed above the second conductive layer 134, and a landing pad material layer 138' is formed to overfill the trench T1 between the bit line structures 110. In some embodiments, the second conductive layer 134 may be formed by depositing a metal layer to contact the top surface of the first conductive layer 132. In some other embodiments, the second conductive layer 134 may be formed by forming a second conductive material layer to overfill the trench T1. After that, a planarization process is performed to remove the excess portion of the second conductive material layer above the bit line structures 110 to expose the top surface of the bit line structures 110. After that, the second conductive material layer is etched back to form the second conductive layer 134 in the trench T1 and above the first conductive layer 132.

[0033] After forming the second conductive layer 134, a barrier layer 136 is formed above the second conductive layer 134. In particular, a conformal barrier material layer is formed on the bit line structures 110 and the second conductive layer 134. After that, the barrier material layer above the bit line structures 110 is removed to expose the top surface of the bit line structures 110, and the remaining portion of the barrier material layer forms the barrier layer 136. After forming the barrier layer 136, a landing pad material layer 138' is formed to overfill the trench T1 between the bit line structures 110. In some embodiments, the second conductive layer 134 is formed of metal silicide, the barrier layer 136 is formed of TaN, TiN, etc., but not limited thereto, and the landing pad material layer 138' is formed of Ti, TiN, Ta, TaN, W, Cu, Au, or an alloy of the above, but not limited thereto.

[0034] Refer to Figure 5, a trench T2 is formed by removing a portion of the barrier layer 136, a portion of the landing pad material layer 138', and a portion of the bit line structure 110. After forming the trench T2, a landing pad 138 is formed on the remaining portion of the landing pad material layer 138' above the barrier layer 136 and the bit line structure 110. The vertically stacked first conductive layer 132, second conductive layer 134, barrier layer 136, and landing pad 138 may be collectively referred to as the conductive structure 130. That is, after forming the trench T2, the conductive structure 130 is formed between and above the bit line structures 110, and the conductive structure 130 can serve as a contact to connect the active region 101 in the substrate 100 and the subsequently formed capacitor structure 200. The trench T2 can be formed by performing an etching process to expose the sacrificial spacer layer 124 (as shown in Figure 4 ), and then the sacrificial spacer layer 124 is removed to form an air gap AG between the first spacer layer 122 and the second spacer layer 126. Thus, a spacer 120 including the first spacer layer 122, the second spacer layer 126, and the air gap AG is formed along the sidewalls of the bit line structure 110. The first spacer layer 122 contacts the bit line structure 110. The second spacer layer 126 contacts the conductive structure 130, and the first spacer layer 122 is separated from the second spacer layer 126 by the air gap AG. In some embodiments, the sacrificial spacer layer 124 is removed by performing a wet etching process.

[0035] Refer to Figure 6 , an isolation layer 140' is formed to overfill the trench T2. The isolation layer 140' is used to seal the air gap AG. The manufacturing process and materials of the isolation layer 140' are selected to allow the isolation layer 140' to seal the air gap AG but not flow into the air gap AG. In some embodiments, the isolation layer 140' is formed of any suitable dielectric material such as silicon, silicon nitride, etc.

[0036] Refer to Figure 7 , a planarization process is performed to remove the top of the isolation layer 140' above the landing pad 138 until the top surface of the landing pad 138 is exposed. Thus, an isolation structure 140 is formed between the bit line structure 110 and the conductive structure 130. In some embodiments, the top surface of the isolation structure 140 and the top surface of the landing pad 138 are coplanar.

[0037] Refer to Figure 8, a photoresist 142 is formed above the conductive structure 130. The photoresist 142 can be formed by depositing a photoresist layer above the conductive structure 130 and the isolation structure 140 and then patterning the photoresist layer to expose the isolation structure 140. After the photoresist 142 is formed, an implantation process is performed on the exposed isolation structure 140. The photoresist 142 can act as a hard mask layer during the implantation process and prevent the conductive structure 130 from being implanted. In some embodiments, doping such as B or Si can be selected in the implantation process, and distinct characteristics are provided, such as a significantly reduced dry etching rate. According to implantation studies on the nitride film material, when using Si with a dose exceeding 3.00E+16 (ion / cm 2 ) at an energy of 10 KeV, the dry etching rate of the material can be reduced to about 0.26 times that of the non-implanted material. When the material is implanted with B with a dose exceeding 5.00E+16 (ion / cm 2 ) at an energy of 10 KeV, the dry etching rate of the material can be reduced to about 0.75 times that of the non-implanted material. The dry etching rate is measured by using an etching gas including C4F6, CH2F2, C4F8, and O2 within 30 seconds. After the implantation process is performed, the doping depth of the doping can be distributed at about 50 nm on the top surface of the implanted isolation structure 144 through a subsequent thermal process (not shown).

[0038] See Figure 9 , an implanted isolation structure 144 is formed through the implantation process, and then the photoresist 142 is removed. After the isolation structure 140 is implanted, the dry etching rate of the implanted isolation structure 144 can be lower than that of the non-implanted isolation structure 140. Based on the selection of doping such as B or Si, during the implantation process, the dry etching rate of the implanted isolation structure 144 can be reduced to about 0.26 times to about 0.75 times. The implanted isolation structure 144 with such a low dry etching rate can act as an etch stop layer in subsequent processes and prevent breakdown of the air gap AG.

[0039] See Figure 10 , a first support layer 210, a first sacrificial layer 212, a second support layer 214, a second sacrificial layer 216, and a third support layer 218 are sequentially formed above the conductive structure 130 and the implanted isolation structure 144. In some embodiments, the first support layer 210, the second support layer 214, and the third support layer 218 are formed of a dielectric material such as silicon nitride. The first sacrificial layer 212 and the second sacrificial layer 216 are formed of a dielectric material different from the first support layer 210, the second support layer 214, and the third support layer 218. The first sacrificial layer 212 and the second sacrificial layer 216 can be formed of silicon oxide.

[0040] See Figure 11, a trench T3 is formed through the first support layer 210, the first sacrificial layer 212, the second support layer 214, the second sacrificial layer 216, and the third support layer 218 to expose the conductive structure 130. In some embodiments, the trench T3 can be formed by performing one or more etching processes. During the formation of the trench T3, the implantation isolation structure 144 is used to prevent process breakdown of the air gap AG. In particular, in an ideal case, the trench T3 completely covers the top surface of the conductive structure 130 and does not expose the implantation isolation structure 144. Thus, subsequent processes form a bottom electrode layer 220 in the trench T3 and have the maximum contact area with the conductive structure 130. However, in some embodiments, the trench T3 may be misaligned with the top surface of the conductive structure 130, so the trench T3 may expose a portion of the implantation isolation structure 144. For the etchant used during the formation of the trench T3, the implantation isolation structure 144 has a higher etching resistance than the first support layer 210. In some embodiments, the first support layer 210 may have a dry etching rate 8.87 times higher than that of the implantation isolation structure 144, such that the implantation isolation structure 144 can serve as an etch stop layer during the formation of the trench T3. Thus, even if the implantation isolation structure 144 is exposed during the formation of the trench T3, the implantation isolation structure 144 can avoid Figure 11 the process in

[0041] Referring to Figure 12 , the conformal trench T3 forms the bottom electrode layer 220. In some embodiments, the conformal trench T3 is first formed and a bottom electrode material layer is formed above the third support layer 218. Then, for example, the bottom electrode material layer above the third support layer 218 is removed by performing a planarization process. The remaining portion of the bottom electrode material layer forms the bottom electrode layer 220 of the conformal trench T3. In some embodiments, the bottom electrode layer 220 can be formed of a metal, a metal compound, an alloy compound, other conductive materials, or a combination thereof, such as titanium nitride or silicon-doped titanium nitride.

[0042] Referring to Figure 13 , the first sacrificial layer 212 and the second sacrificial layer 216 are removed. In particular, removing the first sacrificial layer 212 and the second sacrificial layer 216 includes forming a hole in some of the third support layer 218 until the top surface of the second sacrificial layer 216 is exposed. Then, by performing a wet etching process, the second sacrificial layer 216 is removed through the hole. After removing the second sacrificial layer 216, a hole is formed in some of the second support layer 214 until the top surface of the first sacrificial layer 212 is exposed, and then the first sacrificial layer 212 is removed through the hole by performing a wet etching process. In this way, the first support layer 210, the second support layer 214, the third support layer 218, and the bottom electrode layer 220 remain in place.

[0043] Refer to Figure 14 , a conformal bottom electrode layer 220, a first support layer 210, a second support layer 214, and a third support layer 218 form a dielectric layer 230, and a top electrode layer 240 is formed between the dielectric layers 230. In some embodiments, the dielectric layer 230 may be formed of a high dielectric constant dielectric material such as ZrO2, and the top electrode layer 240 may be formed of a metal, a metal compound, an alloy compound, other conductive materials, or a combination thereof, such as titanium nitride or silicon-doped titanium nitride. Thus, a capacitor structure 200 is formed above the conductive structure 130 and the isolation structure 140. The bottom electrode layer 220 of the capacitor structure 200 contacts the conductive structure 130. The dielectric layer 230 is conformal to the bottom electrode layer 220, and the top electrode layer 240 is conformal to the dielectric layer 230.

[0044] Figure 14 The resulting semiconductor device is shown in. The resulting semiconductor device includes a substrate 100, a bit line structure 110, spacers 120, a conductive structure 130, an implanted isolation structure 144, and a capacitor structure 200. The bit line structure 110 is above the substrate 100. The spacers 120 are along the sidewalls of the bit line structure 110, and each spacer 120 includes an air gap AG. The conductive structure 130 is between the spacers 120. The implanted isolation structure 144 is between the conductive structure 130 and the bit line structure 110. The capacitor structure 200 includes a first support layer 210 above the implanted isolation structure 144, a bottom electrode layer 220 above the conductive structure 130, a dielectric layer 230 conformal to the bottom electrode layer 220, a second support layer 214 and a third support layer 218 conformal to the dielectric layer 230, and a top electrode layer 240.

[0045] Each implanted isolation structure 144 seals the air gap AG, and the implanted isolation structure 144 contacts the bit line structure 110 and the conductive structure 130. Using Si and B as dopants in the implanted isolation structure 144 at a specific dose may have a lower dry etching rate than the non-implanted isolation structure 140. Further, the ratio of the dry etching rate between the first support layer 210 and the implanted isolation structure 144 is about 8.87. As Figure 15 shown, if the capacitor structure 200 is displaced from the top surface of the conductive structure 130, the implanted isolation structure 144 is used to prevent the process of fabricating the capacitor structure 200 from exposing the air gap AG by hitting.

[0046] In Figure 15 the trenches for forming the bottom electrode layer 220 (e.g. Figure 11The trench T3) in Figure 11 is displaced from the top surface of the conductive structure 130 due to misalignment. As previously described, the implant isolation structure 144 that performs the implantation process has a high etch resistance to the etchant used to form the trench T3 for the bottom electrode layer 220. Therefore, the implant isolation structure 144 serves as an etch stop layer, and after the capacitor structure 200 is formed, the underlying air gap AG remains sealed. The resulting bottom electrode layer 220 is also displaced from the top surface of the conductive structure 130 and contacts the implant isolation structure 144. If the implant isolation structure 144 does not have a high etch resistance to Figure 11 the etchant mentioned in

[0047] Figure 16 and the trench T3) (such as Figure 11 shown in

[0048] is displaced from the top surface of the conductive structure 130, the air gap AG will be opened. The bottom electrode layer 220 may fill the air gap AG and cause an electrical short circuit between the capacitor structure 200 and the bit line structure 110.

[0049] Other embodiments of the semiconductor device of the present invention are marked. The trench T3 may be formed to have a width W1, and due to the high etch resistance of the implant isolation structure 144 (such as

[0050] shown in

[0051] 100: Substrate

[0052] 101: Active region

[0053] 102: Isolation structure

[0054] 106: Dielectric layer

[0055] 108: Bit line contact

[0056] 110: Bit line structure

[0057] 112: Barrier layer

[0058] 114: Metal layer

[0059] 116: Hard mask layer

[0060] 120: Spacer

[0061] 122: First spacer layer

[0062] 124: Sacrificial spacer layer

[0063] 126: Second spacer layer

[0064] 130: Conductive structure

[0065] 132: First conductive layer

[0066] 134: Second conductive layer

[0067] 136: Barrier layer

[0068] 138: Landing pad

[0069] 138’: Landing pad material layer

[0070] 140: Isolation structure

[0071] 140’: Isolation layer

[0072] 142: Photoresist

[0073] 144: Implanted isolation structure

[0074] 200: Capacitor structure

[0075] 210: First support layer

[0076] 212: First sacrificial layer

[0077] 214: Second support layer

[0078] 216: Second sacrificial layer

[0079] 218: Third support layer

[0080] 220: Bottom electrode layer

[0081] 230: Dielectric layer

[0082] 240: Top electrode layer

[0083] AG: Air gap

[0084] T1: Groove

[0085] T2: Groove

[0086] T3: Groove

[0087] W1: Width

[0088] W2: Width.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a plurality of bit line structures above a substrate; Forming a plurality of spacers along a plurality of sidewalls of the plurality of bit line structures, each of the spacers including an air gap; Forming a plurality of conductive structures between and above the plurality of bit line structures, wherein the plurality of conductive structures expose portions of the plurality of bit line structures; Forming a plurality of isolation structures between the plurality of conductive structures and the plurality of bit line structures; The plurality of isolation structures are implanted to form a plurality of implanted isolation structures; Forming a support layer above the plurality of implanted isolation structures and the plurality of conductive structures; And Forming a plurality of capacitor structures above the plurality of conductive structures and the plurality of implanted isolation structures.

2. The method according to claim 1, wherein forming the plurality of spacers along the plurality of sidewalls of the plurality of bit line structures, each of the spacers including the air gap comprises: Sequentially forming a first spacer layer, a sacrificial spacer layer, and a second spacer layer along the plurality of sidewalls of the plurality of bit line structures; And After forming the plurality of conductive structures, removing the sacrificial spacer layer.

3. The method according to claim 1, wherein forming the plurality of conductive structures between and above the plurality of bit line structures comprises: Forming a first trench between the plurality of bit line structures, the first trench exposing a portion of the substrate; Forming a first conductive layer in the first trench; Forming a second conductive layer above the first conductive layer; Forming a barrier layer above the second conductive layer; Forming a landing pad to overfill the first trench; And Forming a second trench by removing a portion of the barrier layer, a portion of the landing pad, and a portion of the plurality of bit line structures.

4. The method according to claim 1, wherein forming the plurality of isolation structures between the plurality of conductive structures and the plurality of bit line structures comprises: Forming an isolation layer between and above the plurality of conductive structures and the plurality of bit line structures; And Removing the top of the isolation layer, wherein a top surface of the isolation layer is coplanar with a top surface of the plurality of conductive structures.

5. The method according to claim 1, wherein implanting the plurality of isolation structures to form the plurality of implanted isolation structures comprises: Forming a photoresist above the plurality of conductive structures; And Implanting a plurality of dopants into the plurality of isolation structures.

6. The method according to claim 5, wherein a doping depth of the plurality of dopants is at 50 nm of a top surface of the plurality of implanted isolation structures.

7. The method according to claim 1, wherein the plurality of implanted isolation structures have a first dry etching rate, and the first dry etching rate is less than a second dry etching rate of the plurality of isolation structures.

8. The method according to claim 1, wherein the plurality of implanted isolation structures have a first dry etching rate, and the first dry etching rate is less than a third dry etching rate of the support layer.

9. The method according to claim 8, wherein a ratio of the third dry etching rate to the first dry etching rate is greater than 8.

87.

10. The method according to claim 1, wherein forming the plurality of capacitive structures over the plurality of conductive structures and the plurality of implanted isolation structures comprises: forming a plurality of bottom electrodes over the plurality of conductive structures; forming a plurality of dielectric layers conformal to the plurality of bottom electrodes; and forming a plurality of top electrode layers conformal to the plurality of dielectric layers.

11. A semiconductor device, characterized in that, Comprising: a substrate; a plurality of bit line structures over the substrate; a plurality of spacers along a plurality of sidewalls of the plurality of bit line structures, wherein each of the spacers includes an air gap; a plurality of conductive structures between the plurality of spacers; and a plurality of implanted isolation structures between the plurality of conductive structures and the plurality of bit line structures.

12. The semiconductor device according to claim 11, wherein each of the spacers comprises: a first spacer layer contacting one of the plurality of bit line structures; and a second spacer layer contacting one of the plurality of conductive structures, wherein the first spacer layer is separated from the second spacer layer by the air gap.

13. The semiconductor device according to claim 11, wherein, Further comprising: a plurality of capacitive structures over the plurality of conductive structures and the plurality of implanted isolation structures, wherein each of the capacitive structures comprises: a bottom electrode contacting the conductive structure; a dielectric layer conformal to the bottom electrode; and a top electrode layer conformal to the dielectric layer.

14. The semiconductor device according to claim 13, wherein the plurality of bottom electrodes of the plurality of capacitive structures further contact the plurality of implanted isolation structures.

15. The semiconductor device according to claim 13, wherein a width of a bottom surface of the plurality of bottom electrodes is greater than a width of a top surface of the plurality of conductive structures.

16. The semiconductor device according to claim 11, wherein a top surface of the plurality of implanted isolation structures is coplanar with a top surface of the plurality of conductive structures.

17. The semiconductor device according to claim 11, wherein the plurality of implanted isolation structures are implanted with a plurality of doped boron and silicon.

18. The semiconductor device according to claim 17, wherein a doping depth of the plurality of dopants is at 50 nm of a top surface of the plurality of implanted isolation structures.

19. The semiconductor device according to claim 11, wherein the plurality of implanted isolation structures contact the plurality of spacers and the plurality of bit line structures.

Images