Polar plate capacitor structure and manufacturing method thereof

Abstract

The invention provides a polar plate capacitor structure. The polar plate capacitor structure comprises a first interlayer dielectric layer, a convex dielectric barrier layer, a stacked lower polar plate metal layer, a second interlayer dielectric layer and an etching barrier layer which are arranged on a substrate, the third interlayer dielectric layer covers the laminated structure; the first contact hole, the second contact hole and the upper pole plate groove penetrate through the third interlayer dielectric layer. The first contact hole extends to the first interlayer dielectric layer, the second contact hole extends to the lower pole plate metal layer, and the upper pole plate groove extends to the second interlayer dielectric layer. The holes and the grooves are filled with copper metal layers with Ti / TiN barrier layers, copper serves as an upper polar plate, and TiN serves as a lower polar plate. According to the manufacturing method, the laminated structure is etched through photoetching, the dielectric barrier layer is reserved, the contact hole and the groove are etched step by step, and a copper filling process is integrated. According to the invention, the copper upper pole plate avoids the damage of etching to the side wall medium, the TiN lower pole plate reduces the grain boundary defect, the electric leakage, the breakdown voltage and the TDDB reliability are obviously improved, and the method is compatible with the existing semiconductor technology and does not need to add a mask.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a plate capacitor structure and a manufacturing method thereof. Background Art

[0002] MIM (plate capacitor) devices are commonly used device structures in semiconductor manufacturing processes. Currently, the plate capacitors used have a metal Cu as the lower plate and TIN as the upper plate. Compared with the MIM structure where both the upper and lower plates are TIN, only one photomask for etching the upper plate is required. Currently, this MIM structure has the following problems:

[0003] 1. When etching the upper plate, it is easy to damage the sidewall dielectric SIN, which affects the reliability of TDDB (Transient Dielectric Breakdown).

[0004] 2. Defects caused by grain boundaries on the Cu surface affect the leakage current, BV (Breakdown Voltage), and reliability of MIM devices. The defects lead to low-voltage leakage current and a breakdown voltage lower than that of normal devices.

[0005] To solve the above problems, a new type of plate capacitor structure and a manufacturing method thereof need to be proposed. Summary of the Invention [[ID=—21]]

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a plate capacitor structure and a manufacturing method thereof, which are used to solve the problems in the prior art that when etching the upper plate of the MIM structure, it is easy to damage the sidewall dielectric SIN, which affects the reliability of TDDB (Transient Dielectric Breakdown); defects caused by grain boundaries on the Cu surface affect the leakage current, BV (Breakdown Voltage), and reliability of MIM devices, and the defects lead to low-voltage leakage current and a breakdown voltage lower than that of normal devices.

[0007] To achieve the above object and other related objects, the present invention provides a plate capacitor structure, including:

[0008] A substrate, on which a first interlayer dielectric layer is formed. On the first interlayer dielectric layer, a convex dielectric barrier layer is formed. On the upper convex surface of the dielectric barrier layer, a stacked lower plate metal layer, a second interlayer dielectric layer, and an etching barrier layer are sequentially formed from bottom to top;

[0009] A third interlayer dielectric layer covering the stacked structure;

[0010] First and second contact hole patterns, and an upper plate groove formed for forming an upper plate. Among them, the first contact hole pattern extends from the upper surface of the third interlayer dielectric layer to the first interlayer dielectric layer, the upper surface of the second contact hole pattern extends from the upper surface of the third interlayer dielectric layer to the lower plate metal layer, and the upper plate groove extends from the upper surface of the third interlayer dielectric layer to the second interlayer dielectric layer;

[0011] A barrier layer and a metal layer filling the remaining first and second contact hole patterns and the upper plate groove are formed on the surfaces of the first and second contact hole patterns and the upper plate groove. The metal layer in the first and second contact hole patterns serves as a contact, and the metal layer in the upper plate groove serves as an upper plate metal layer.

[0012] Preferably, the material of the interlayer dielectric layer is an oxide.

[0013] Preferably, the material of the dielectric barrier layer is silicon carbide.

[0014] Preferably, the material of the lower plate metal layer is titanium nitride.

[0015] Preferably, the material of the second interlayer dielectric layer is silicon nitride.

[0016] Preferably, the material of the third interlayer dielectric layer is undoped silicon glass.

[0017] Preferably, the material of the barrier layer includes Ti and TiN.

[0018] Preferably, the material of the metal layer is copper.

[0019] The present invention also provides a manufacturing method of the above-mentioned plate capacitor structure, including:

[0020] Step 1: Provide a substrate, on which a first interlayer dielectric layer is formed, and a stacked structure is formed on the first interlayer dielectric layer. The stacked structure is composed of a dielectric barrier layer, a lower plate metal layer, a second interlayer dielectric layer, and an etching barrier layer stacked in sequence from bottom to top;

[0021] Step 2: Pattern the stacked structure by photolithography and etching methods, and retain a part of the thickness of the dielectric barrier layer in the etched area. Then, form a third interlayer dielectric layer covering the stacked structure by deposition and grinding methods;

[0022] Step 3: Form a first anti-reflection coating that can be developed on the third interlayer dielectric layer. Then, form first and second opening patterns by photolithography and etching methods. The first opening pattern extends from the upper surface of the first anti-reflection coating to the dielectric barrier layer with a part of the thickness retained in the etched area, and the upper surface of the second opening pattern extends from the upper surface of the first anti-reflection coating to above the second interlayer dielectric layer;

[0023] Step 4: Define the etching regions above the first and second opening patterns and the formation region of the upper electrode plate by photolithography. The size of the etching region is larger than the size of the first and second opening patterns at this location. Form the opening patterns by etching respectively, where the remaining etching barrier layer is not etched through. The dielectric barrier layer at the bottom of the second opening pattern is etched through to expose the first interlayer dielectric layer below it, and the second interlayer dielectric layer at the bottom of the second opening pattern is etched through to expose the lower electrode plate metal layer. Then, remove the exposed etching barrier layer to form the first and second contact hole patterns corresponding to the etched first and second opening patterns respectively, and form an upper electrode plate groove for forming the upper electrode plate.

[0024] Step 5: Form a barrier layer on the surfaces of the first and second contact hole patterns and the upper electrode plate groove. Then, form a metal layer to fill the first and second contact hole patterns and the upper electrode plate groove, and polish the metal layer to the third interlayer dielectric layer. The metal layer in the first and second contact hole patterns serves as the contact member, and the metal layer in the upper electrode plate groove serves as the upper electrode plate metal layer.

[0025] Preferably, the material of the interlayer dielectric layer in Step 1 is an oxide.

[0026] Preferably, the material of the dielectric barrier layer in Step 1 is silicon carbide.

[0027] Preferably, the material of the lower electrode plate metal layer in Step 1 is titanium nitride.

[0028] Preferably, the material of the second interlayer dielectric layer in Step 1 is silicon nitride.

[0029] Preferably, the etching method in Step 2 is dry etching.

[0030] The polishing method in Step 2 is chemical mechanical planarization polishing.

[0031] The material of the third interlayer dielectric layer in Step 2 is undoped silicon glass.

[0032] The material of the first anti-reflection coating in Step 3 is SiON.

[0033] The etching method in Step 3 is dry etching.

[0034] The etching method in Step 4 is dry etching.

[0035] The method of forming the opening patterns by etching in Step 4 includes: forming a bottom anti-reflection coating filling the first and second contact holes, then forming a photoresist layer covering the first anti-reflection coating, and lithographically opening the photoresist layer to define the etching regions above the first and second contact holes and the formation region of the upper electrode plate; forming the opening patterns by etching, and then removing the remaining photoresist layer.

[0036] In Step 4, the exposed etching barrier layer is removed by wet etching.

[0037] The material of the barrier layer in Step 5 includes Ti and TiN.

[0038] The material of the metal layer in Step 5 is copper.

[0039] As described above, the electrode plate capacitance structure and its manufacturing method of the present invention have the following beneficial effects:

[0040] The present invention uses Cu as the upper electrode plate metal layer, avoiding damage to the sidewall dielectric layer (such as SiN) in the etching step, thereby improving the TDDB lifetime; the TiN lower electrode plate metal layer reduces grain boundary defects, reduces leakage current, and improves the breakdown voltage characteristics; the non-conductive etching barrier layer and the composite barrier layer (Ti / TiN) are used to prevent metal diffusion and improve interface stability; the structure is optimized without increasing the number of masks (Masks), and it is compatible with the existing semiconductor manufacturing process. Description of the Drawings

[0041] Figure 1 It shows the process flow schematic diagram of the present invention;

[0042] Figure 2 It shows the schematic diagram of forming a stacked structure on the first interlayer dielectric layer of the present invention;

[0043] Figure 3 It shows the schematic diagram of the patterned stacked structure of the present invention;

[0044] Figure 4 It shows the schematic diagram of forming the third interlayer dielectric layer of the present invention;

[0045] Figure 5 It shows the schematic diagram of forming the first and second opening patterns of the present invention;

[0046] Figure 6 It shows the schematic diagram of lithographically defining the etching regions above the first and second contact holes and the upper electrode plate groove region of the present invention;

[0047] Figure 7 It shows the schematic diagram of dry etching to sequentially etch through the dielectric barrier layer and the second interlayer dielectric layer of the present invention;

[0048] Figure 8 Shown is a schematic diagram of the plate capacitor structure of the present invention.

[0049] Symbol description:

[0050] 101: Substrate, 102: Dielectric barrier layer; 103: Lower plate metal layer; 104: Second interlayer dielectric layer; 105: Etch stop layer; 106: Third interlayer dielectric layer; 107: First anti-reflection coating; 108: Bottom anti-reflection coating; 109: Photoresist layer; 110: Barrier layer; 111: Metal layer. Specific embodiments

[0051] The following illustrates the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] Please refer to Figure 8 , the present invention provides a plate capacitor structure, including:

[0053] A substrate, on which a first interlayer dielectric layer 101 is formed. On the first interlayer dielectric layer 101, a convex dielectric barrier layer 102 is formed. On the upper convex surface of the dielectric barrier layer 102, a stacked lower plate metal layer 103, a second interlayer dielectric layer 104, and an etch stop layer 105 are formed in sequence from bottom to top;

[0054] In some embodiments, the material of the first interlayer dielectric layer 101 is an oxide, such as silicon dioxide (SiO2). Such an oxide has high insulation and can effectively isolate the substrate from other conductive layers.

[0055] In some embodiments, the material of the dielectric barrier layer 102 is silicon carbide (SiC), and the convex structure is formed by photolithography and dry etching. The high hardness and etching resistance of silicon carbide help to protect the lower plate metal layer 103 in subsequent processes.

[0056] In some embodiments, the material of the second interlayer dielectric layer 104 is silicon nitride (SiN). The high dielectric constant and breakdown resistance of silicon nitride help to improve the dielectric performance and reliability of the capacitor.

[0057] A third interlayer dielectric layer 106 covering the stacked structure;

[0058] In some embodiments, the material of the third interlayer dielectric layer 106 is undoped silicon glass (USG). USG has excellent planarization characteristics and low dielectric loss, and is suitable as a filling material for multi-layer structures.

[0059] The first and second contact hole patterns, and an upper plate groove for forming an upper plate are formed. Among them, the first contact hole pattern extends from the upper surface of the third interlayer dielectric layer 106 to the upper surface of the first interlayer dielectric layer 101, and the upper surface of the second contact hole pattern extends from the upper surface of the third interlayer dielectric layer 106 to the lower plate metal layer 103; the upper plate groove extends from the upper surface of the third interlayer dielectric layer 106 to the second interlayer dielectric layer 104;

[0060] In some embodiments, the material of the lower plate metal layer 103 is titanium nitride (TiN). Using TiN as the lower plate can reduce surface grain boundary defects, thereby reducing leakage current and increasing the breakdown voltage (BV).

[0061] A barrier layer 110 is formed on the surfaces of the first and second contact hole patterns and the upper plate groove, and a metal layer 111 fills the remaining first and second contact hole patterns and the upper plate groove. The metal layer 111 in the first and second contact hole patterns serves as a contact, and the metal layer 111 in the upper plate groove serves as the upper plate metal layer.

[0062] In some embodiments, the material of the barrier layer 110 includes Ti and TiN. This composite barrier layer can prevent the subsequent copper metal layer 111 from diffusing into the dielectric layer, ensuring structural stability and long-term reliability.

[0063] In some embodiments, the material of the metal layer 111 is copper (Cu). The high conductivity of copper helps reduce resistance loss, and at the same time, by using it as the upper plate, the risk of TDDB (time-dependent dielectric breakdown) caused by etching the sidewall dielectric layer 104 can be avoided.

[0064] Please refer to Figure 1 , the present invention also provides a manufacturing method of the above-mentioned plate capacitor structure, including:

[0065] Step 1: Provide a substrate, on which a first interlayer dielectric layer 101 is formed, and a stacked structure is formed on the first interlayer dielectric layer 101. The stacked structure is composed of a dielectric barrier layer 102, a lower plate metal layer 103, a second interlayer dielectric layer 104, and an etching barrier layer 105 stacked in sequence from bottom to top, forming a structure as Figure 2 shown.

[0066] In some embodiments, the first interlayer dielectric layer 101 generates silicon dioxide through plasma-enhanced chemical vapor deposition (PECVD).

[0067] In some embodiments, the silicon carbide of the dielectric barrier layer 102 is deposited by CVD, and the etching barrier layer 105 can be silicon nitride (SiN) or titanium nitride (TiN).

[0068] Step 2: Pattern the stacked structure by photolithography and dry etching. In the etched area, a partial thickness of the dielectric barrier layer 102 is retained to form the structure as shown in Figure 3 . After that, the third interlayer dielectric layer 106 is deposited by CVD, and its surface is planarized by chemical mechanical polishing (CMP) to form the structure as shown in Figure 4 .

[0069] In some embodiments, the dry etching uses a fluorine-based gas (such as a CF4 / O2 mixed gas).

[0070] Step 3: Spin-coat the first anti-reflection coating 107 of SiON material on the third interlayer dielectric layer 106; form the first and second opening patterns by photolithography and dry etching. The first opening pattern is etched to the retained dielectric barrier layer 102, and the second opening pattern is etched above the second interlayer dielectric layer 104 to form the structure as shown in Figure 5 .

[0071] Step 4: By spin-coating the bottom anti-reflection coating 108 and the photoresist layer 109, and photolithographically defining the etched areas above the first and second contact holes and the upper plate groove area, the size of the etched area is larger than the opening pattern to form the structure as shown in Figure 6 . Use dry etching to sequentially etch through the dielectric barrier layer 102 and the second interlayer dielectric layer 104 until the lower plate metal layer 103 and the first interlayer dielectric layer 101 are exposed to form the structure as shown in Figure 7 . Use wet etching to remove the exposed etch stop layer 105 to form the first and second contact hole patterns and the upper plate groove.

[0072] In some embodiments, the process of etching the dielectric barrier layer 102 uses a dry etching with a high selectivity. This step isolates the etched area from the upper plate area, avoids damage to the sidewall dielectric layer 104, and significantly improves the TDDB performance.

[0073] Step 5: Form a Ti / TiN barrier layer 110 in the contact holes and grooves by physical vapor deposition (PVD), and then electroplate copper to fill the metal layer 111 and polish it to the surface of the third interlayer dielectric layer 106 to form the structure as shown in Figure 8 . Copper is used as the upper plate for its low resistance characteristics, and at the same time, the barrier layer 110 inhibits copper diffusion. The overall structure has both high capacitance density and reliability.

[0074] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0075] In summary, the present invention uses Cu as the upper plate metal layer, avoiding damage to the sidewall dielectric layer (such as SiN) during the etching step, thereby improving the TDDB lifetime; the TiN lower plate metal layer reduces grain boundary defects, reduces leakage current, and improves the breakdown voltage characteristics; the use of a non-conductive etching barrier layer and a composite barrier layer (Ti / TiN) prevents metal diffusion and improves interface stability; the structure is optimized without increasing the number of masks (Mask), making it compatible with existing semiconductor manufacturing processes. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0076] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A plate capacitor structure, characterized in that, Including: A substrate, on which a first interlayer dielectric layer is formed, and on the first interlayer dielectric layer, a convex dielectric barrier layer is formed. On the upper convex surface of the dielectric barrier layer, a stacked lower electrode metal layer, a second interlayer dielectric layer, and an etching stop layer are sequentially formed from bottom to top; A third interlayer dielectric layer covering the stacked structure; First and second contact hole patterns, and an upper electrode groove for forming an upper electrode. Among them, the first contact hole pattern extends from the upper surface of the third interlayer dielectric layer to the first interlayer dielectric layer, the upper surface of the second contact hole pattern extends from the upper surface of the third interlayer dielectric layer to the lower electrode metal layer, and the upper electrode groove extends from the upper surface of the third interlayer dielectric layer to the second interlayer dielectric layer; A barrier layer is formed on the surfaces of the first and second contact hole patterns and the upper electrode groove, and a metal layer is filled in the remaining first and second contact hole patterns and the upper electrode groove. The metal layer in the first and second contact hole patterns serves as a contact, and the metal layer in the upper electrode groove serves as an upper electrode metal layer.

2. The plate capacitor structure according to claim 1, characterized in that: The material of the interlayer dielectric layer is an oxide.

3. The plate capacitor structure according to claim 1, wherein: The material of the dielectric barrier layer is silicon carbide.

4. The plate capacitor structure according to claim 1, wherein: The material of the lower electrode metal layer is titanium nitride.

5. The electrode plate capacitance structure according to claim 1, characterized in that: The material of the second interlayer dielectric layer is silicon nitride.

6. The plate capacitor structure according to claim 1, characterized in that: The material of the third interlayer dielectric layer is undoped silicon glass.

7. The plate capacitor structure according to claim 1, wherein: The material of the barrier layer includes Ti and TiN.

8. The plate capacitor structure according to claim 1, wherein: The material of the metal layer is copper.

9. The manufacturing method of the plate capacitor structure according to any one of claims 1 to 8, characterized in that, At least including: Step 1: Provide a substrate, on which a first interlayer dielectric layer is formed, and on the first interlayer dielectric layer, a stacked structure is formed. The stacked structure is composed of a dielectric barrier layer, a lower electrode metal layer, a second interlayer dielectric layer, and an etching stop layer stacked sequentially from bottom to top; Step 2: Pattern the stacked structure by photolithography and etching methods. In the etched area, a part of the thickness of the dielectric barrier layer is retained, and then a third interlayer dielectric layer covering the stacked structure is formed by deposition and polishing methods; Step 3: Form a developable first anti-reflection coating on the third interlayer dielectric layer, and then form first and second opening patterns by photolithography and etching methods. Among them, the first opening pattern extends from the upper surface of the first anti-reflection coating to the part of the thickness of the dielectric barrier layer retained in the etched area, and the upper surface of the second opening pattern extends from the upper surface of the first anti-reflection coating above the second interlayer dielectric layer; Step 4: Use photolithography to define the etching regions above the first and second opening patterns and the formation region of the upper electrode plate. The size of the etching regions is larger than the sizes of the first and second opening patterns at this location. Use etching to form the opening patterns respectively, where the remaining etching barrier layer is not etched through. The dielectric barrier layer at the bottom of the second opening pattern is etched through to expose the first interlayer dielectric layer below it, and the second interlayer dielectric layer at the bottom of the second opening pattern is etched through to expose the lower electrode plate metal layer. Then, remove the exposed etching barrier layer to form the first and second contact hole patterns corresponding to the etched first and second opening patterns respectively, and form an upper electrode plate groove for forming the upper electrode plate. Step 5: Form a barrier layer on the surfaces of the first and second contact hole patterns and the upper electrode plate groove. Then, form a metal layer to fill the first and second contact hole patterns and the upper electrode plate groove, and polish the metal layer to the third interlayer dielectric layer. The metal layer in the first and second contact hole patterns serves as the contact members, and the metal layer in the upper electrode plate groove serves as the upper electrode plate metal layer.

10. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The material of the interlayer dielectric layer in Step 1 is an oxide.

11. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The material of the dielectric barrier layer in Step 1 is silicon carbide.

12. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The material of the lower electrode plate metal layer in Step 1 is titanium nitride.

13. The manufacturing method of the electrode plate capacitance structure according to claim 9, characterized in that: The material of the second interlayer dielectric layer in Step 1 is silicon nitride.

14. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The method of etching in Step 2 is dry etching.

15. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The method of polishing in Step 2 is chemical mechanical planarization polishing.

16. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The material of the third interlayer dielectric layer in Step 2 is undoped silicon glass.

17. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The material of the first anti-reflection coating in Step 3 is SiON.

18. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The method of etching in Step 3 is dry etching.

19. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The method of etching in Step 4 is dry etching.

20. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The method of using etching to form the opening patterns respectively in Step 4 includes: forming a bottom anti-reflection coating to fill the first and second contact holes, then forming a photoresist layer covering the first anti-reflection coating, and photolithographically opening the photoresist layer to define the etching regions above the first and second contact holes and the formation region of the upper electrode plate; using etching to form the opening patterns, and then removing the remaining photoresist layer.

21. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: Use wet etching to remove the exposed etching barrier layer in Step 4.

22. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The material of the barrier layer in Step 5 includes Ti and TiN.

23. The manufacturing method of the plate capacitor structure according to claim 9, characterized in that: The material of the metal layer in Step 5 is copper.

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