P-GaN gate HEMT device with avalanche breakdown characteristic
By introducing a P-type doped hole compensation layer into the GaN-based HEMT device, the thermal failure problem caused by hole accumulation is solved, the avalanche breakdown characteristics of the device under high pressure is realized, and the reliability and safety of the device are improved.
Patent Information
- Application Number
- CN202510613217.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-08-01
AI Technical Summary
GaN-based HEMT devices lack effective hole removal mechanism during avalanche breakdown, resulting in heat failure caused by hole accumulation, and high-magnitude pulse voltage is prone to occur in switching circuits. The existing methods to increase the breakdown voltage cannot completely eliminate circuit safety hazards.
A p-GaN gate HEMT device with avalanche breakdown characteristics is designed to form a hole conduction channel by introducing a P-type doped hole compensation layer into the buffer layer, ensuring that the holes can be effectively removed under high pressure.
Trigger avalanche breakdown at high voltage, improve device reliability, avoid thermal failure, and enhance device safety and stability in practical applications.
Smart Images
Figure CN120417432A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to a p-GaN gate HEMT device with avalanche breakdown characteristics. Background Art
[0002] With the continuous development of social economy, people have put forward higher requirements for the demand and management of electric energy. Especially in the field of electric energy conversion, the application environment is becoming increasingly complex and challenging. The continuous progress of power semiconductor technology has significantly improved the utilization efficiency of electric energy. Among them, as one of the most promising wide-bandgap semiconductor materials, GaN has become an ideal solution for high-power switching applications due to its excellent characteristics such as high breakdown field strength, low dielectric constant, high electron mobility, and high thermal conductivity.
[0003] Although GaN-based HEMT devices exhibit many excellent performances, the problem of poor avalanche ability still restricts their further development. This is mainly because GaN HEMT lacks an effective hole removal mechanism. During the avalanche breakdown process, electrons can be discharged through the channel layer, while holes cannot be removed and are prone to accumulate inside the device, leading to thermal failure. In addition, in a switching circuit, due to the inductive characteristics of the load, the parasitic parameters in the circuit will also exhibit inductive effects. Without a voltage clamping diode in parallel with the inductive load, when the device is turned off, the inductive current cannot be interrupted instantaneously, and a high-amplitude pulsed voltage will be generated across the inductor, and the drain voltage of the switching device will rise rapidly, possibly exceeding the static breakdown voltage of the device, resulting in thermal failure. At present, although the safety margin can be increased by increasing the breakdown voltage of the device, this method cannot completely eliminate the potential safety hazards in the circuit. Therefore, designing a GaN HEMT device with avalanche breakdown characteristics is of milestone significance for improving its reliability. Such a design will significantly improve the safety and stability of the device in practical applications and accelerate the industrialization process of GaN HEMT devices. Summary of the Invention
[0004] The problem to be solved by the present invention is to propose a p-GaN gate HEMT device with avalanche breakdown characteristics to enable the fabricated device to trigger avalanche breakdown under high voltage to improve the reliability of the device.
[0005] To achieve the above object, the present invention adopts the following technical solutions:
[0006] A p-GaN gate HEMT device with avalanche breakdown characteristics includes a P-type doped hole compensation layer 1, a buffer layer 2, a substrate layer 3, a nucleation layer 4, a channel layer 5, an interface layer 6, a barrier layer 7, a gate dielectric layer 8, a silicon dioxide layer 9, a P-type cap layer 10, a drain 11, a source 12, a drain-side metal interconnection layer 13, a source-side metal interconnection layer 14, a gate 15, and a silicon dioxide layer 16;
[0007] The substrate layer 3, the nucleation layer 4, and the buffer layer 2 are stacked in sequence from bottom to top; the P-type doped hole compensation layer 1 is located in the buffer layer 2 and isolates the buffer layer 2 into upper and lower parts in the lateral direction;
[0008] The channel layer 5 is located on the upper surface of the buffer layer 2, and the lateral width of the channel layer 5 is smaller than the lateral width of the buffer layer 2; the interface layer 6 is disposed to cover the upper surface of the channel layer 5, and the barrier layer 7 is disposed to cover the upper surface of the interface layer 6;
[0009] The drain 11 and the source 12 are respectively disposed on both sides of the upper surface of the barrier layer 7, and the lower ends of the drain 11 and the source 12 are embedded in the upper layer of the barrier layer 7. At the same time, there is a gap between the lower surfaces of the drain 11 and the source 12 and the upper surface of the barrier layer 7;
[0010] The P-type capping layer 10 is located in the middle of the upper surface of the barrier layer 7; the gate dielectric layer 8 is disposed to cover the upper surface of the buffer layer 2 and the upper surface of the barrier layer 7, and the gate dielectric layer 8 completely covers the upper surfaces and the sides of the drain 11 and the source 12;
[0011] The gate 15 is located on the upper surface of the gate dielectric layer 8 above the P-type capping layer 10, and the lateral width of the gate 15 is greater than the lateral width of the P-type capping layer 10. There is a convex structure below the gate 15, and the convex structure penetrates through the gate dielectric layer 8 and contacts the upper surface of the P-type capping layer 10;
[0012] The silicon dioxide layer 9 is disposed to cover the upper surface of the gate dielectric layer 8, and the silicon dioxide layer 9 completely covers the upper surface and the sides of the gate 15;
[0013] The drain-side metal interconnect layer 13 and the source-side metal interconnect layer 14 are respectively located on both sides of the upper surface of the silicon dioxide layer 9; the lower surface of the drain-side metal interconnect layer 13 has two extending structures, which respectively extend to contact the upper surface of the drain 11 and extend into the buffer layer 2; the lower surface of the source-side metal interconnect layer 14 has two extending structures, which respectively extend to contact the upper surface of the source 12 and extend into the buffer layer 2;
[0014] The silicon dioxide layer 16 is located on the upper surfaces of the drain-side metal interconnect layer 13 and the source-side metal interconnect layer 14, and fills the gap between the drain-side metal interconnect layer 13 and the source-side metal interconnect layer 14 and then contacts the upper surface of the silicon dioxide layer 9.
[0015] Further, the material used for the P-type doped hole compensation layer 1 is GaN or AlGaN.
[0016] Further, the ions doped in the P-type doped hole compensation layer 1 are acceptor impurity ions.
[0017] Further, the doping concentration range of the P-type doped hole compensation layer 1 is 1×10 13 cm -3 —1×10 19 cm -3 。
[0018] Further, the thickness of the P-type doped hole compensation layer 1 is less than that of the buffer layer 2, and the thickness range of the P-type doped hole compensation layer 1 is 0.2 um - 0.6 um.
[0019] Further, the distance range of the P-type doped hole compensation layer 1 from the channel layer 5 in the vertical direction is 0.8 um - 1.5 um.
[0020] Further, the distance of the lower surface of the part where the drain-side metal interconnection layer 13 extends into the buffer layer from the channel layer 5 in the vertical direction is 0.1 um - 0.8 um. When the distance is 0.8 um, it contacts the upper surface of the P-type doped hole compensation layer 1.
[0021] Further, the distance of the lower surface of the part where the source-side metal interconnection layer 14 extends into the buffer layer from the channel layer 5 in the vertical direction is 0.1 um - 0.8 um. When the distance is 0.8 um, it contacts the upper surface of the P-type doped hole compensation layer 1.
[0022] Further, the lateral width of the P-type doped hole compensation layer 1 is less than or equal to the lateral width of the buffer layer 2.
[0023] The beneficial effect of the present invention is that by proposing a p-GaN gate HEMT device with avalanche breakdown characteristics, the prepared device can trigger avalanche breakdown under high voltage to improve the reliability of the device. Description of the Drawings
[0024] Figure 1 is a schematic diagram of a GaN-based HEMT device with a hole compensation layer in an embodiment of the present invention;
[0025] Figure 2 is a schematic energy band diagram with a hole compensation layer;
[0026] Figure 3 is a simulation breakdown characteristic curve (including electron current and hole current) of a device with a hole compensation layer;
[0027] Figure 4 is a repeated breakdown characteristic curve (experimental data) of a device with a hole compensation layer;
[0028] Figure 5The variable-temperature breakdown characteristic curve of the device with a hole compensation layer. Detailed implementation manners
[0029] The following will combine with the drawings to describe in detail the technical solutions of the embodiments of the present invention.
[0030] A GaN-based HEMT device proposed in an embodiment of the present invention has a structure as Figure 1 shown, including a P-type doped hole compensation layer 1, a buffer layer 2, a substrate layer 3, a nucleation layer 4, a channel layer 5, an interface layer 6, a barrier layer 7, a gate dielectric layer 8, a silicon dioxide layer 9, a P-type cap layer 10, a drain 11, a source 12, a drain-side metal interconnection layer 13, a source-side metal interconnection layer 14, a gate 15, and a thick silicon dioxide layer 16; the P-type doped charge compensation layer 1 is located in the buffer layer 2; the buffer layer 2 is located above the nucleation layer 4; the nucleation layer 4 is located above the substrate layer 3; the interface layer 6 is located above the channel layer 5; the lateral heterojunction structure formed by the channel layer 5 and the barrier layer 7 is located above the buffer layer 2, and a two-dimensional electron gas exists at the heterojunction interface; the P-type cap layer 10 is located on the upper surface of one side of the barrier layer 7, and the gate 15 is located on the upper surface of the P-type cap layer 10; the gate 15 forms an ohmic contact or a Schottky contact with the P-type cap layer 10; the gate dielectric layer 8 is located on the upper surface of the barrier layer 7 and completely covers the gate 15 and the P-type cap layer 10; the drain 12 is located on the upper surface of the end of the gate dielectric layer 8 away from the P-type cap layer 10, and sequentially penetrates through the gate dielectric layer 8, the barrier layer 7, and the interface layer 6 in the vertical direction and then extends into the channel layer 5, so as to form an ohmic contact with the two-dimensional electron gas channel; the source 12 covers the upper surface of the other end of the gate dielectric layer 8, and sequentially penetrates through the gate dielectric layer 8, the barrier layer 7, and the interface layer 6 in the vertical direction and then extends into the channel layer 5 to form an ohmic contact with the two-dimensional electron gas channel; there is a silicon dioxide layer 9 between the drain 11 and the source 12; the drain-side metal interconnection layer 13 covers the upper surface of the end of the silicon dioxide layer 9 away from the source-side metal interconnection layer 14, one end sequentially penetrates through the silicon dioxide layer 9 and the gate dielectric layer 8 in the vertical direction, so as to contact the upper surface of the drain 11, and the other end sequentially penetrates through the silicon dioxide layer 9 and the gate dielectric layer 8 in the vertical direction and then extends into the buffer layer 2; the source-side metal interconnection layer 14 covers the upper surface of the end of the silicon dioxide layer 9 away from the drain-side metal interconnection layer 13, one end sequentially penetrates through the silicon dioxide layer 9 and the gate dielectric layer 8 in the vertical direction, so as to contact the upper surface of the source 12, and the other end sequentially penetrates through the silicon dioxide layer 9 and the gate dielectric layer 8 in the vertical direction and then extends into the buffer layer 2; the thick silicon dioxide layer 16 covers the upper surfaces of the silicon dioxide layer 9, the drain-side metal interconnection layer 13, and the source-side metal interconnection layer 14.
[0031] The working principle of the present invention:
[0032] The key problem for GaN HEMTs not to have the avalanche breakdown characteristic is that the electrons generated by impact ionization in the device can be drained from the drain through the two-dimensional electron gas channel, while the generated holes lack a corresponding export channel. Therefore, a large number of holes will accumulate inside the device, leading to the occurrence of thermal breakdown. As Figure 2 shown, the energy band diagram of the device with a hole compensation layer shows that the hole compensation layer makes the valence band closer to the Fermi level by increasing the hole doping concentration, thereby reducing the hole conduction resistance of this layer. This mechanism enables holes to accumulate more easily in the hole compensation layer and initially forms a hole removal channel in this region. Figure 3 Figure shows the schematic diagrams of electron current and hole current obtained by simulation. When the drain voltage reaches a certain critical value, the P-type diode embedded in the buffer is triggered, and the hole channel is fully turned on, thereby forming a hole current from the drain to the source. Therefore, it can be observed that the hole current shows an instantaneous amplification phenomenon at this critical voltage (while the hole current in a conventional device can be ignored). This further indicates that holes are drained through the hole compensation layer and removed through this structure.
[0033] Figure 2 The energy band diagram of the device with a hole compensation layer is given. The resistance of the hole compensation layer can be regulated by the doping concentration of the hole compensation layer to form an effective hole conduction channel.
[0034] Figure 3 The schematic diagrams of electron current and hole current simulation at the breakdown voltage are given.
[0035] Figure 4 Figure shows the breakdown characteristic curve (experimental verification data) of the repeated breakdown voltage test for the device with a hole compensation layer. It can be seen from the figure that the device of the present invention can instantaneously release a large current when the drain is under high voltage bias, and the device does not undergo hard breakdown after multiple repeated breakdown voltage tests.
[0036] Figure 5 The variable-temperature breakdown characteristic curve of the device with a hole compensation layer. The variable-temperature breakdown characteristic curve of the device of the present invention shows that it exhibits a positive temperature coefficient of avalanche breakdown characteristics at different temperatures.
Claims
1. A p-GaN gate HEMT device with avalanche breakdown characteristics, characterized in that, It includes a P-type doped hole compensation layer (1), a buffer layer (2), a substrate layer (3), a nucleation layer (4), a channel layer (5), an interface layer (6), a barrier layer (7), a gate dielectric layer (8), a silicon dioxide layer (9), a P-type cap layer (10), a drain (11), a source (12), a drain-side metal interconnect layer (13), a source-side metal interconnect layer (14), a gate (15), and a silicon dioxide layer (16); The substrate layer (3), the nucleation layer (4), and the buffer layer (2) are stacked in sequence from bottom to top; the P-type doped hole compensation layer (1) is located in the buffer layer (2) and laterally isolates the buffer layer (2) into upper and lower parts; The channel layer (5) is located on the upper surface of the buffer layer (2), and the lateral width of the channel layer (5) is smaller than the lateral width of the buffer layer (2); the interface layer (6) covers the upper surface of the channel layer (5), and the barrier layer (7) covers the upper surface of the interface layer (6); The drain (11) and the source (12) are respectively arranged on both sides of the upper surface of the barrier layer (7), and the lower ends of the drain (11) and the source (12) are embedded in the upper layer of the barrier layer (7), and at the same time, there is a gap between the lower surfaces of the drain (11) and the source (12) and the upper surface of the barrier layer (7); The P-type cap layer (10) is located in the middle of the upper surface of the barrier layer (7); the gate dielectric layer (8) covers the upper surface of the buffer layer (2) and the upper surface of the barrier layer (7), and the gate dielectric layer (8) completely covers the upper surfaces and sides of the drain (11) and the source (12); The gate (15) is located on the upper surface of the gate dielectric layer (8) above the P-type cap layer (10), and the lateral width of the gate (15) is larger than the lateral width of the P-type cap layer (10). There is a convex structure below the gate (15), and the convex structure penetrates through the gate dielectric layer (8) and contacts the upper surface of the P-type cap layer (10); The silicon dioxide layer (9) covers the upper surface of the gate dielectric layer (8), and the silicon dioxide layer (9) completely covers the upper surface and sides of the gate (15); The drain-side metal interconnect layer (13) and the source-side metal interconnect layer (14) are respectively located on both sides of the upper surface of the silicon dioxide layer (9); the lower surface of the drain-side metal interconnect layer (13) has two extension structures, which respectively extend to contact the upper surface of the drain (11) and extend into the buffer layer (2); the lower surface of the source-side metal interconnect layer (14) has two extension structures, which respectively extend to contact the upper surface of the source (12) and extend into the buffer layer (2); The silicon dioxide layer (16) is located on the upper surfaces of the drain-side metal interconnect layer (13) and the source-side metal interconnect layer (14), and after filling the gap between the drain-side metal interconnect layer (13) and the source-side metal interconnect layer (14), it contacts the upper surface of the silicon dioxide layer (9).
2. The p-GaN gate HEMT device with avalanche breakdown characteristics according to claim 1, wherein The material used for the P-type doped hole compensation layer (1) is GaN or AlGaN.
3. The p-GaN gate HEMT device with avalanche breakdown characteristics according to claim 2, wherein The ions doped in the P-type doped hole compensation layer (1) are acceptor impurity ions.
4. A p-GaN gate HEMT device having avalanche breakdown characteristics according to claim 3, wherein, The doping concentration range of the P-type doped hole compensation layer (1) is 1×10 13 cm -3 —1×10 19 cm -3 .
5. The p-GaN gate HEMT device with avalanche breakdown characteristics according to claim 1, characterized in that, The thickness of the P-type doped hole compensation layer (1) is less than that of the buffer layer (2), and the thickness range of the P-type doped hole compensation layer (1) is 0.2 um - 0.6 um.
6. The p-GaN gate HEMT device with avalanche breakdown characteristics according to claim 1, characterized in that, The distance of the P-type doped hole compensation layer (1) from the channel layer (5) in the vertical direction ranges from 0.8 um to 1.5 um.
7. A p-GaN gate HEMT device with avalanche breakdown characteristics according to claim 1, characterized in that, The distance of the lower surface of the part of the drain-side metal interconnection layer (13) extending into the buffer layer from the channel layer (5) in the vertical direction is 0.1 um - 0.8 um. When the distance is 0.8 um, it contacts the upper surface of the P-type doped hole compensation layer (1).
8. A p-GaN gate HEMT device with avalanche breakdown characteristics according to claim 1, wherein The distance of the lower surface of the part of the source-side metal interconnection layer (14) extending into the buffer layer from the channel layer (5) in the vertical direction is 0.1 um - 0.8 um. When the distance is 0.8 um, it contacts the upper surface of the P-type doped hole compensation layer (1).
9. The p-GaN gate HEMT device with avalanche breakdown characteristics according to claim 1, wherein The lateral width of the P-type doped hole compensation layer (1) is less than or equal to the lateral width of the buffer layer (2).