Semiconductor device and preparation method thereof, and integrated circuit

Abstract

The invention provides a semiconductor device, a preparation method thereof and an integrated circuit, in the device, a first gate insulating layer comprises an oxidation part and a nitrogen oxidation part, and the oxidation part is located on the side, away from a substrate, of the nitrogen oxidation part. Therefore, on one hand, the high K value characteristic of the nitrogen element can be utilized, so that the nitrogen oxidation part has small EOT, the overall equivalent oxide layer thickness of the first gate oxide layer is reduced, the NBTI effect is inhibited, and the device performance is improved. On the other hand, the oxidation part in the first gate insulating layer is located on the side, deviating from the substrate, of the nitrogen oxidation part, so that the oxidation part can serve as a protection layer of the nitrogen oxidation part in the pattern definition process of the first gate insulating layer, the nitrogen oxidation part is prevented from reacting with cleaning liquid used for removing the mask, and the reliability of the mask is improved. Damage of the cleaning liquid to the top of the first gate insulating layer (namely, the side deviating from the substrate) is avoided, and the inhibition effect of the first gate insulating layer on the NBTI effect is guaranteed.

Description

Technical Field

[0001] This specification relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a method for manufacturing the same, and an integrated circuit. Background Art

[0002] Semiconductor devices are the core components of modern electronic technology and are widely used in various fields such as communication, computers, aerospace, etc. in production and life. Improvements in the structure and process of semiconductor devices are of great significance for the performance, reliability, power consumption, etc. of the devices.

[0003] With the continuous development of semiconductor technology, the process of semiconductor devices has entered the 28nm and below technology nodes, and the reliability problems of semiconductor devices have become more prominent. For example, Negative Bias Temperature Instability (NBTI) may affect the threshold voltage and saturation current of semiconductor devices, thereby having a negative impact on the working efficiency of the devices. Summary of the Invention

[0004] Embodiments of this specification provide a semiconductor device, a method for manufacturing the same, and an integrated circuit to achieve the purpose of suppressing the NBTI effect of semiconductor devices and improving device performance.

[0005] To achieve the above technical objectives, embodiments of this specification provide the following technical solutions: In a first aspect, a semiconductor device is provided, including: A substrate, the substrate including a first region; A first gate insulating layer located on one side of the first region of the substrate, the first gate insulating layer including an oxide portion and a nitrided oxide portion; The oxide portion is located on the side of the nitrided oxide portion away from the substrate.

[0006] In combination with the first aspect, in certain embodiments of the first aspect, the value range of the ratio of the thickness of the oxide portion to the thickness of the first gate insulating layer is: 0.05 - 0.1.

[0007] In combination with the first aspect, in certain embodiments of the first aspect, in the nitrided oxide portion, along a first direction, the doping concentration of nitrogen ions changes from low to high and then to low; The first direction includes the direction from the top surface of the first gate insulating layer to the bottom surface, the top surface includes the surface of the first gate insulating layer away from the substrate, and the bottom surface includes the surface of the first gate insulating layer facing the substrate.

[0008] In combination with the first aspect, in certain embodiments of the first aspect, the substrate further includes a second region; The semiconductor device further includes: The second gate insulating layer is located on a side of the second region of the substrate, the second gate insulating layer comprises a nitride oxide layer, and the thickness of the second gate insulating layer is less than that of the first gate insulating layer.

[0009] In combination with the first aspect, in some embodiments of the first aspect, the semiconductor device further includes: a first metal gate, the first metal gate being located on a side of the first gate insulating layer facing away from the substrate; A second metal gate is located on a side of the second gate insulating layer facing away from the substrate.

[0010] In a second aspect, an integrated circuit is provided, comprising: a semiconductor device as described in any one of the above items.

[0011] In a third aspect, a method for preparing a semiconductor device is provided, comprising: providing a substrate, the substrate comprising a first region; A first gate insulating layer is formed on one side of the first region of the substrate, wherein the first gate insulating layer includes an oxidized portion and a nitrided portion, and the oxidized portion is located on a side of the nitrided portion facing away from the substrate.

[0012] In conjunction with the third aspect, in some embodiments of the third aspect, forming a first gate insulating layer located in the first region of the substrate includes: forming a gate oxide layer covering the surface of the substrate, wherein the gate oxide layer includes a nitride oxide portion to be etched; Performing a reduction treatment on the gate oxide layer to reduce the oxynitride portion to be etched on a side facing away from the substrate to an oxidized portion to be etched, thereby obtaining a stacked structure; The stacked structure is etched to obtain the first gate insulating layer.

[0013] In conjunction with the third aspect, in certain embodiments of the third aspect, etching the stacked structure includes: forming a mask layer on a side of the stacked structure facing away from the substrate; Using the mask layer as a mask, etching the stacked structure to obtain the first gate insulating layer; The mask layer is removed by using a cleaning solution, and the oxidized portion protects the first gate insulating layer from reacting with the cleaning solution.

[0014] In conjunction with the third aspect, in certain embodiments of the third aspect, forming a gate oxide layer covering the surface of the substrate includes: forming an oxide layer to be doped covering the surface of the substrate; Inject nitrogen ions from the side of the to-be-doped oxide layer facing away from the substrate to form a nitrogen oxide portion of the gate oxide layer.

[0015] In a third aspect, a computing device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the classification method described above is implemented.

[0016] In a fourth aspect, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the classification method described above is implemented.

[0017] In a fifth aspect, a computer program product or a computer program is provided. The computer program product includes a computer program stored in a computer-readable storage medium. A processor of the computer device reads the computer program from the computer-readable storage medium. When the processor executes the computer program, the steps of the classification method described above are implemented. Optionally, the computer program can be stored in a readable storage medium or the cloud of the computer device. The processor of the computer device reads the computer program from the readable storage medium or the cloud.

[0018] As can be seen from the above technical solutions, in the semiconductor device provided by the embodiments of this specification, the first gate insulating layer includes an oxide portion and a nitrogen oxide portion. Among them, the oxide portion is located on the side of the nitrogen oxide portion facing away from the substrate. In this way, on the one hand, the high-K value characteristic of nitrogen can be utilized to make the nitrogen oxide portion have a smaller equivalent oxide thickness (Equivalent Oxide Thickness, EOT), thereby reducing the overall equivalent oxide thickness of the first gate oxide layer. In this way, when the equivalent oxide thickness is the same, the physical thickness of the first gate oxide layer as a whole can be increased. Under the same negative bias condition, the electric field strength in the first gate insulating layer will be correspondingly reduced, thereby reducing the driving force for hydrogen ions to migrate to the interface between the gate insulating layer and the gate, thereby reducing the interface state density, suppressing the NBTI effect, and improving the device performance. On the other hand, the oxide portion in the first gate insulating layer is located on the side of the nitrogen oxide portion facing away from the substrate, so that during the pattern definition process of the first gate insulating layer, the oxide portion can serve as a protective layer for the nitrogen oxide portion, avoiding the reaction of the nitrogen oxide portion with the cleaning liquid for removing the mask, and avoiding damage to the top (i.e., the side facing away from the substrate) of the first gate insulating layer by the cleaning liquid, ensuring the suppression effect of the first gate insulating layer on the NBTI effect. Description of the Drawings

[0019] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0020] Figure 1 It is an NBTI failure model in semiconductor devices.

[0021] Figure 2 It is a schematic diagram of the movement of hydrogen atoms between the substrate, the gate insulating layer, and the gate.

[0022] Figure 3 It is a schematic diagram of the process in which the nitrogen oxide part at the top of the gate insulating layer is damaged during the pattern definition process of the gate insulating layer after injecting nitrogen ions into the gate insulating layer using the ISSG process.

[0023] Figure 4 It is a schematic diagram of the process in which the top of the gate insulating layer of a high-voltage device is damaged when sub-devices with different operating voltages need to be formed in a semiconductor device.

[0024] Figure 5 It is a schematic cross-sectional structure diagram of a semiconductor device provided by an embodiment of this specification.

[0025] Figure 6 It is Figure 5 An enlarged schematic diagram of the dashed box in

[0026] Figure 7 It is Figure 5 An enlarged schematic diagram of the dashed box in

[0027] Figure 8 It is a schematic diagram of the change trend of the nitrogen ion doping concentration in the nitrogen oxide part provided by an embodiment of this specification.

[0028] Figure 9 It is another schematic cross-sectional structure diagram of a semiconductor device provided by an embodiment of this specification.

[0029] Figure 10 It is a schematic flowchart of a method for manufacturing a semiconductor device provided by an embodiment of this specification.

[0030] Figure 11 It is a schematic diagram of the preparation process of a first gate insulating layer provided by an embodiment of this specification.

[0031] Explanation of reference numerals: 10 - Insulating layer; 11 - Mask structure; 12 - Gate insulating layer; 13 - Top damage; 100 - Substrate; 100A - First region; 100B - Second region; 101 - Source; 102 - Drain; 200 - First gate insulating layer; 201 - Nitrided oxide portion; 202 - Oxide portion; 300 - Gate; 400 - Sidewall; D1 - First direction; 500 - Second gate insulating layer; 20 - Nitrided oxide portion to be etched; 21 - Oxide portion to be etched; 22 - Mask layer. Detailed implementation manners

[0032] Unless otherwise defined, the technical terms or scientific terms used in the implementation manners of this specification should have the ordinary meanings understood by those of ordinary skill in the art to which this specification pertains. The "first", "second" and similar terms used in the implementation manners of this specification do not denote any order, quantity or importance, but are merely set up to avoid confusion of components.

[0033] Unless otherwise required by the context, throughout this specification, "a plurality of" means "at least two", and "including" is construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one implementation manner", "some implementation manners", "exemplary implementation manners", "examples", "specific examples" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the implementation manner or example are included in at least one implementation manner or example of this specification. The schematic representations of the above terms do not necessarily refer to the same implementation manner or example.

[0034] Next, the technical solutions in the implementation manners of this specification will be clearly and completely described in conjunction with the accompanying drawings in the implementation manners of this specification. Obviously, the described implementation manners are only a part of the implementation manners of this specification, rather than all of the implementation manners. Based on the implementation manners in this specification, all other implementation manners obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of this specification.

[0035] Overview During the manufacturing process of semiconductor devices, hydrogen atoms are usually introduced into insulating layers such as silicon oxide layers to repair defects generated during the manufacturing process. However, the introduced hydrogen atoms may have a negative impact on the devices under conditions such as negative bias voltage and high temperature. For example, referring to Figure 1 and Figure 2 , Figure 1 shows the NBTI failure model in semiconductor devices, Figure 2 shows the hydrogen atoms in the substrate (which can be a silicon substrate, represented by Silicon in <s Figure 2 ), gate insulating layer (inFigure 2 between the oxide (denoted as Oxide in the figure) and the gate (e.g., a polysilicon gate, denoted as Poly in the figure). Figure 2 Under the condition of negative bias voltage V g Under the condition of negative bias voltage V, holes tunnel through the gate insulating layer (e.g., a silicon dioxide layer) from the substrate (e.g., a silicon substrate) to reach the interface between the gate insulating layer and the substrate. This process is called hole tunneling. The holes reaching the interface capture hydrogen atoms, causing the silicon-hydrogen bond (Si-H) originally combined with silicon atoms to break (Si-H Break). After the silicon-hydrogen bond breaks, the hydrogen atoms are released. The hydrogen atoms may pass through the gate insulating layer to reach the interface between the gate insulating layer and the gate (e.g., a polysilicon (poly) gate) (H moves into poly). This process is called hydrogen emission. The hydrogen atoms may form new interface traps at this interface. These traps capture charges, resulting in threshold voltage drift and reduced saturation current, and thus bringing a negative impact on the working efficiency of the device. The NBTI effect is particularly obvious in HKMG (High-K Metal Gate) semiconductor devices that require a thick gate insulating layer.

[0036] To solve this problem, ISSG (In-Situ Steam Generation) process nitridation can be used to inject plasma nitrogen ions into the side of the gate insulating layer close to the gate, forming a nitrogen oxide part (e.g., silicon oxynitride) in the side of the gate insulating layer close to the gate. In this way, using the high-K (dielectric constant) property of nitrogen is beneficial to reducing the equivalent oxide thickness of the gate insulating layer. Under the condition of the same equivalent oxide thickness, the overall physical thickness of the gate insulating layer injected with plasma nitrogen ions can be increased. Under the same negative bias voltage condition, the electric field strength in the first gate insulating layer will be correspondingly reduced, thereby reducing the driving force for hydrogen ions to migrate to the interface between the gate insulating layer and the gate, reducing the interface state density, suppressing the NBTI effect, and improving the device performance.

[0037] In addition, using ISSG process nitridation to inject nitrogen ions into the gate insulating layer will not increase the interface states between the gate insulating layer and the substrate. On the contrary, the nitrogen oxide part formed by nitridation can improve the interface quality between the high-K dielectric material and the substrate and reduce the interface trap density.

[0038] However, the inventors' research found that referring to Figure 3 , after using the ISSG process to inject nitrogen ions into the gate insulating layer, during the pattern definition process of the gate insulating layer, the nitrogen oxide part at the top of the gate insulating layer may be damaged. Specifically, referring to Figure 3, after forming a whole layer of insulating layer 10 on a substrate and implanting nitrogen ions into it, it is necessary to form a patterned photoresist or the like on the whole layer of insulating layer 10 as a mask structure 11. Then, using this mask structure 11 as a mask, the whole layer of insulating layer 10 is etched to retain the gate insulating layer 12 at the required positions. Finally, a cleaning solution such as SPM (Sulfuric acid - Hydrogenperoxide Mixture) is used to remove the mask structure 11. However, during the process of removing the mask structure 11, the nitrogen oxide part at the top of the gate insulating layer 12 may react with the cleaning solution, resulting in damage to the top of the gate insulating layer 12, reducing the overall physical thickness of the gate insulating layer 12, and weakening the inhibitory effect of the gate insulating layer 12 on the NBTI effect. Taking the insulating layer 10 as a silicon dioxide layer and the cleaning solution as SPM as an example, after implanting nitrogen ions into the silicon dioxide layer, a part of silicon oxynitride layer will be formed in the top region of the silicon dioxide layer. However, the silicon oxynitride layer may react with sulfuric acid, hydrogen peroxide, and water in the SPM to generate substances such as silicon dioxide and ammonium sulfate ((NH4)2SO4), resulting in top damage 13 of the gate insulating layer. This problem is particularly obvious when more than one sub-device needs to be formed in a semiconductor device. For example, referring to Figure 4 , when sub-devices with different operating voltages need to be formed in a semiconductor device ( Figure 4 in which, HV represents a high-voltage device, and LV represents a low-voltage device), the thicknesses of the gate insulating layers of different sub-devices are different. The gate insulating layer of a sub-device with a higher operating voltage may be thicker. When forming these sub-devices, the gate insulating layer of the high-voltage device can be defined first, and the above-mentioned problem may occur during the definition process of the gate insulating layer of the high-voltage device, resulting in the NBTI effect of the device not being effectively suppressed.

[0039] To solve this problem, the inventors provide a semiconductor device in which the first gate insulating layer includes an oxide portion and a nitrided oxide portion, where the oxide portion is located on the side of the nitrided oxide portion away from the substrate. In this way, on the one hand, the high-K value characteristic of nitrogen can be utilized to make the nitrided oxide portion have a smaller equivalent oxide thickness (EOT), thereby reducing the overall equivalent oxide thickness of the first gate oxide layer. Thus, when the equivalent oxide thickness is the same, the physical thickness of the first gate oxide layer as a whole can be increased. Under the same negative bias condition, the electric field strength in the first gate insulating layer will be correspondingly reduced, thereby reducing the driving force for hydrogen ions to migrate to the interface between the gate insulating layer and the gate, thereby reducing the interface state density, suppressing the NBTI effect, and improving the device performance. On the other hand, the oxide portion in the first gate insulating layer is located on the side of the nitrided oxide portion away from the substrate, so that during the patterning process of the first gate insulating layer, the oxide portion can serve as a protective layer for the nitrided oxide portion, avoiding the reaction of the nitrided oxide portion with the cleaning solution for removing the mask, and avoiding damage to the top of the first gate insulating layer (i.e., the side away from the substrate) by the cleaning solution, ensuring the suppression effect of the first gate insulating layer on the NBTI effect.

[0040] Based on the above concept, the embodiments of this specification provide a semiconductor device and a manufacturing method thereof. Below, the semiconductor device and the manufacturing method thereof will be described exemplarily with reference to the accompanying drawings.

[0041] Exemplary Device The embodiments of this specification provide a semiconductor device, as Figure 5 and Figure 6 shown, the semiconductor device includes: A substrate 100, the substrate 100 includes a first region; A first gate insulating layer 200, located on one side of the first region of the substrate 100, the first gate insulating layer 200 includes an oxide portion 202 and a nitrided oxide portion 201; The oxide portion 202 is located on the side of the nitrided oxide portion 201 away from the substrate 100.

[0042] In some embodiments, the semiconductor device may include one or more sub-devices, and the sub-devices may include HKMG devices. The HKMG devices may include planar transistors (Planar Field-Effect Transistors, Planar FETs) or multi-gate transistors. Among them, the multi-gate transistors may include at least one of FinFETs (Fin Field-Effect Transistors), GAAFETs (Gate-All-Around Field-Effect Transistors), and MBCFETs (Multi-Bridge Channel Field-Effect Transistors). Taking the planar transistor as an example, in some embodiments, the sub-devices in the semiconductor device may further include structures such as a source 101, a drain 102, a gate 300, a channel (not marked in the figure), and a spacer 400. Among them, the spacer 400 can be used to protect the gate 300 and control the distance between the gate 300 and the source-drain. In some embodiments, the semiconductor device may further include structures such as shallow trench isolation (STI), and the shallow trench isolation can be used to isolate different sub-devices.

[0043] Reference Figure 6 , Figure 6 For Figure 5An enlarged schematic diagram of the structure in the dashed box. In the semiconductor device provided in this embodiment, the first gate insulating layer 200 includes an oxide portion 202 and a nitrided oxide portion 201. Among them, the oxide portion 202 is located on the side of the nitrided oxide portion 201 away from the substrate 100. In this way, on the one hand, the high-K value characteristic of nitrogen can be utilized, so that the nitrided oxide portion 201 has a smaller equivalent oxide thickness (Equivalent Oxide Thickness, EOT), thereby reducing the overall equivalent oxide thickness of the first gate oxide layer. In this way, when the overall equivalent oxide thickness is the same, the physical thickness of the first gate oxide layer can be increased. Under the same negative bias condition, the electric field strength in the first gate insulating layer 200 will be correspondingly reduced, thereby reducing the driving force for hydrogen ions to migrate to the interface between the gate insulating layer and the gate 300, thereby reducing the interface state density, suppressing the NBTI effect, and improving the device performance. On the other hand, the oxide portion 202 in the first gate insulating layer 200 is located on the side of the nitrided oxide portion 201 away from the substrate 100, so that during the patterning process of the first gate insulating layer 200, the oxide portion 202 can serve as a protective layer for the nitrided oxide portion 201, avoiding the reaction of the nitrided oxide portion 201 with the cleaning solution for removing the mask, and avoiding damage to the top of the first gate insulating layer 200 (i.e., the side away from the substrate 100) by the cleaning solution, ensuring the inhibitory effect of the first gate insulating layer 200 on the NBTI effect.

[0044] In one embodiment, in order to ensure the protective effect of the oxide portion 202, the value range of the ratio of the thickness of the oxide portion 202 to the thickness of the first gate insulating layer 200 is: 0.05~0.1. That is, referring to Figure 7 , in the first gate insulating layer 200, the thickness of the oxide portion 202 is represented by H1, and the thickness of the first gate insulating layer 200 is represented by H2. Then the value range of H1 / H2 is: 0.05~0.1. Through experiments, it is found that when the ratio of H1 to H2 is within this range, on the one hand, the inhibitory effect of the nitrided oxide portion 201 on the NBTI effect can be ensured, and on the other hand, the oxide portion 202 can play a better protective role, avoiding the situation that the top of the first gate insulating layer 200 is damaged by the cleaning solution.

[0045] It should be noted that in Figure 7 , the cross-section of the oxide portion 202 is represented by a regular rectangle, but it can be understood that in an actual semiconductor device, the cross-section of the oxide portion 202 may be an irregular shape. At this time, the thickness of the oxide portion 202 can refer to the average thickness of the oxide portion 202, or the maximum thickness or the minimum thickness of the oxide portion 202. This specification does not make any limitations in this regard, and it depends on the actual situation specifically.

[0046] In one embodiment, in order to improve the ability of the nitrogen-oxide portion 201 in the first gate insulating layer 200 to suppress the NBTI effect, refer to Figure 8 , in the nitrogen-oxide portion 201, along the first direction D1, the doping concentration of nitrogen ions changes from low to high and then to low; The first direction D1 includes the direction from the top surface of the first gate insulating layer 200 to the bottom surface. The top surface includes the surface of the first gate insulating layer 200 facing away from the substrate 100, and the bottom surface includes the surface of the first gate insulating layer 200 facing the substrate 100.

[0047] In this embodiment, the nitrogen-oxide portion 201 can be formed by nitridation based on the ISSG process. In this way, the doping concentration of nitrogen ions in the nitrogen-oxide portion 201 can be precisely controlled, and the nitrogen ions can be mainly located on the side close to the oxidation portion 202 (gate 300) (that is, along the first direction D1, the doping concentration of nitrogen ions changes from low to high and then to low). On the side of the nitrogen-oxide portion 201 facing the substrate 100, the doping concentration of nitrogen ions is 0, or the doping concentration of nitrogen ions approaches zero, avoiding the increase of interface states between the first gate insulating layer 200 and the substrate 100. At the same time, the high dielectric constant characteristic of nitrogen ions can reduce the equivalent oxide thickness of the nitrogen-oxide portion 201, thereby facilitating the reduction of the overall equivalent oxide thickness of the first gate insulating layer 200. In the case of the same equivalent oxide thickness, the overall physical thickness of the gate insulating layer injected with plasma-state nitrogen ions can be increased. Under the same negative bias condition, the electric field strength in the first gate insulating layer 200 will be correspondingly reduced, thereby reducing the driving force for hydrogen ions to migrate to the interface between the gate insulating layer and the gate 300, thereby reducing the interface state density and suppressing the NBTI effect, and improving the device performance.

[0048] In one embodiment, the semiconductor device may include multiple sub-devices. For example, refer to Figure 9 , the substrate 100 further includes a second region 100B; The semiconductor device further includes: A second gate insulating layer 500, located on one side of the second region 100B of the substrate 100. The second gate insulating layer 500 includes a nitrogen-oxide layer, and the thickness of the second gate insulating layer 500 is less than the thickness of the first gate insulating layer 200.

[0049] In this embodiment, the semiconductor device may include two sub-devices. Of course, in some embodiments, the semiconductor device may further include more sub-devices, which are not limited in this specification.

[0050] In this embodiment, the first region 100A can be used to form structures such as the first gate insulating layer 200 of high-voltage devices, and the second region 100B can be used to form structures such as the second gate insulating layer 500 of low-voltage devices (in order to clearly show the thickness relationship between the gate insulating layers, other structures of the sub-devices are not shown in the figure). During the manufacturing process, the first gate insulating layer 200 can be defined first. During the definition process of the first gate insulating layer 200, a mask is required to define the pattern of the first gate insulating layer 200. When removing the mask, the top of the oxynitride portion 201 may be damaged. Therefore, an oxide portion 202 for protecting the oxynitride portion 201 is provided in the first gate insulating layer 200. During the formation process of the second gate insulating layer 500, the patterning of the second gate insulating layer 500 can be carried out simultaneously with the patterning of the gate 300, and there may be no step of removing the mask on the surface of the second gate insulating layer 500. Therefore, the second gate insulating layer 500 only needs to include an oxynitride layer, which can include a silicon oxynitride layer. The silicon oxynitride layer can be formed by implanting nitrogen ions into the silicon oxide layer based on the ISSG process to suppress the NBTI effect of the sub-devices.

[0051] In one embodiment, the semiconductor device further includes: A first metal gate located on the side of the first gate insulating layer 200 away from the substrate 100; A second metal gate located on the side of the second gate insulating layer 500 away from the substrate 100.

[0052] In this embodiment, the first gate insulating layer 200 and the second gate insulating layer 500 can be formed using a high-K material. However, the compatibility between the high-K material and the polysilicon gate is poor. To improve the compatibility between the high-K material and the gate 300, in this embodiment, a metal gate can be used as the gate of the sub-devices, thereby improving the compatibility between the high-K material and the gate. In some embodiments, the metal gates (the first metal gate and the second metal gate) can be formed using the GateLast process to avoid possible problems of the metal gates in high-temperature processes, thereby improving the device performance.

[0053] Correspondingly, an embodiment of the present specification further provides an integrated circuit including the semiconductor device described in any of the above embodiments.

[0054] The integrated circuit includes, but is not limited to, a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), a graphics processing unit (GPU), a data processing unit (DPU), a central processing unit (CPU), a random access memory (RAM), a read-only memory (ROM), a microcontroller unit (MCU), etc., which are not limited in this specification.

[0055] In the integrated circuit, the first gate insulating layer 200 of the semiconductor device includes an oxide portion 202 and a nitrided oxide portion 201. Among them, the oxide portion 202 is located on the side of the nitrided oxide portion 201 away from the substrate 100. In this way, on the one hand, the high-K value characteristic of nitrogen can be utilized, so that the nitrided oxide portion 201 has a smaller equivalent oxide thickness (EOT), thereby reducing the overall equivalent oxide thickness of the first gate oxide layer. Thus, in the case of the same equivalent oxide thickness, the physical thickness of the first gate oxide layer as a whole can be increased. Under the same negative bias condition, the electric field strength in the first gate insulating layer 200 will be correspondingly reduced, thereby reducing the driving force for hydrogen ions to migrate to the interface between the gate insulating layer and the gate 300, thereby reducing the interface state density, suppressing the NBTI effect, and improving the device performance. On the other hand, the oxide portion 202 in the first gate insulating layer 200 is located on the side of the nitrided oxide portion 201 away from the substrate 100, so that during the patterning process of the first gate insulating layer 200, the oxide portion 202 can serve as a protective layer for the nitrided oxide portion 201, avoiding the reaction of the nitrided oxide portion 201 with the cleaning solution for removing the mask, and avoiding damage to the top of the first gate insulating layer 200 (i.e., the side away from the substrate 100), ensuring the suppression effect of the first gate insulating layer 200 on the NBTI effect.

[0056] Exemplary Method Correspondingly, the embodiment of this specification also provides a method for manufacturing a semiconductor device, as Figure 10 shown, including: S1001: Provide a substrate 100, and the substrate 100 includes a first region; S1002: Form a first gate insulating layer 200 on one side of the first region of the substrate 100. The first gate insulating layer 200 includes an oxidized portion 202 and a nitrided oxide portion 201, and the oxidized portion 202 is located on the side of the nitrided oxide portion 201 away from the substrate 100.

[0057] The structure of the semiconductor device obtained by the method for manufacturing a semiconductor device provided in the embodiments of this specification can be referred to Figure 5 , in this semiconductor device, the first gate insulating layer 200 includes an oxidized portion 202 and a nitrided oxide portion 201, wherein the oxidized portion 202 is located on the side of the nitrided oxide portion 201 away from the substrate 100. In this way, on the one hand, the high-K value characteristic of nitrogen can be utilized, so that the nitrided oxide portion 201 has a smaller equivalent oxide thickness (Equivalent Oxide Thickness, EOT), thereby reducing the overall equivalent oxide thickness of the first gate oxide layer. Thus, when the overall equivalent oxide thickness is the same, the physical thickness of the first gate oxide layer can be increased. Under the same negative bias condition, the electric field strength in the first gate insulating layer 200 will be correspondingly reduced, thereby reducing the driving force for hydrogen ions to migrate to the interface between the gate insulating layer and the gate 300, thereby reducing the interface state density and suppressing the NBTI effect, and improving the device performance. On the other hand, the oxidized portion 202 in the first gate insulating layer 200 is located on the side of the nitrided oxide portion 201 away from the substrate 100, so that during the patterning process of the first gate insulating layer 200, the oxidized portion 202 can serve as a protective layer for the nitrided oxide portion 201, avoiding the reaction of the nitrided oxide portion 201 with the cleaning solution for removing the mask, and avoiding damage to the top of the first gate insulating layer 200 (i.e., the side away from the substrate 100), ensuring the suppression effect of the first gate insulating layer 200 on the NBTI effect.

[0058] Optionally, in an embodiment of this specification, refer to Figure 11 , step S1002 specifically includes: S10021: Form a gate oxide layer covering the surface of the substrate 100, and the gate oxide layer includes an etched nitrided oxide portion 20; S10022: Perform a reduction treatment on the gate oxide layer to reduce the side of the etched nitrided oxide portion 20 away from the substrate 100 to an etched oxidized portion 21, obtaining a stacked structure; S10023: Etch the stacked structure to obtain the first gate insulating layer 200.

[0059] Optionally, in an embodiment, the etching of the stacked structure includes: Form a mask layer 22 on the side of the stacked structure away from the substrate 100; Using the mask layer 22 as a mask, etching the stacked structure to obtain the first gate insulating layer 200; The mask layer 22 is removed by using a cleaning solution, and the oxidized portion 202 protects the first gate insulating layer 200 from reacting with the cleaning solution.

[0060] In this embodiment, in the process of defining the first gate insulating layer 200, the oxynitride portion 20 to be etched is reduced to the side of the oxidized nitrogen portion 20 to be etched away from the substrate 100 to the oxidized nitrogen portion 21 to be etched. Therefore, after the stacked structure is etched to obtain the first gate insulating layer 200, the oxidized portion 202 in the first gate insulating layer 200 can protect the oxynitride portion 201 below, thereby avoiding the problem of damage to the top of the first gate insulating layer 200.

[0061] Optionally, in one embodiment, forming a gate oxide layer covering the surface of the substrate 100 includes: forming an oxide layer to be doped covering the surface of the substrate 100; Nitrogen ions are implanted from the side of the oxide layer to be doped away from the substrate 100 to form a nitride-oxidized portion of the gate oxide layer.

[0062] The oxide layer to be doped may include a silicon oxide layer, and the ISSG process may be used when injecting nitrogen ions. For details, please refer to the relevant description in the above text, and this specification will not elaborate on it here.

[0063] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above-described embodiments merely represent a few embodiments of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the solutions provided by the embodiments of this specification. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of this specification shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate, the substrate comprising a first region; A first gate insulating layer located on one side of the first region of the substrate, the first gate insulating layer comprising an oxide portion and a oxynitride portion; The oxide portion is located on the side of the oxynitride portion away from the substrate.

2. The semiconductor device according to claim 1, wherein The value range of the ratio of the thickness of the oxide portion to the thickness of the first gate insulating layer is: 0.05 to 0.

1.

3. The semiconductor device according to claim 1, wherein, In the oxynitride portion, along a first direction, the doping concentration of nitrogen ions changes from low to high and then to low; The first direction includes the direction from the top surface of the first gate insulating layer to the bottom surface, the top surface includes the surface of the first gate insulating layer away from the substrate, and the bottom surface includes the surface of the first gate insulating layer facing the substrate.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The substrate further comprises a second region; The semiconductor device further comprises: A second gate insulating layer located on one side of the second region of the substrate, the second gate insulating layer comprising an oxynitride layer, and the thickness of the second gate insulating layer is less than the thickness of the first gate insulating layer.

5. The semiconductor device according to claim 4, wherein Further comprising: A first metal gate located on the side of the first gate insulating layer away from the substrate; A second metal gate located on the side of the second gate insulating layer away from the substrate.

6. An integrated circuit, characterized in that, Comprising: The semiconductor device according to any one of claims 1 to 5.

7. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate, the substrate comprising a first region; Forming a first gate insulating layer on one side of the first region of the substrate, the first gate insulating layer comprising an oxide portion and a oxynitride portion, and the oxide portion is located on the side of the oxynitride portion away from the substrate.

8. The method according to claim 7, wherein The forming of the first gate insulating layer on the first region of the substrate comprises: Forming a gate oxide layer covering the surface of the substrate, the gate oxide layer comprising an oxynitride portion to be etched; Performing a reduction treatment on the gate oxide layer to reduce the side of the oxynitride portion to be etched away from the substrate to an oxide portion to be etched, obtaining a stacked structure; Etching the stacked structure to obtain the first gate insulating layer.

9. The method according to claim 8, wherein The etching of the stacked structure comprises: Forming a mask layer on the side of the stacked structure away from the substrate; Using the mask layer as a mask to etch the stacked structure to obtain the first gate insulating layer; Removing the mask layer by using a cleaning solution, and the oxide portion protects the first gate insulating layer from reacting with the cleaning solution.

10. The method according to claim 8, wherein The forming of the gate oxide layer covering the surface of the substrate comprises: Forming a dopant oxide layer covering the surface of the substrate; Injecting nitrogen ions from the side of the dopant oxide layer away from the substrate to form the oxynitride portion of the gate oxide layer.

Images