Method of manufacturing semiconductor device

Abstract

The invention relates to a method of manufacturing a semiconductor device. A resist pattern having an opening that exposes a portion of the conductive film positioned on the gate insulating film is formed on the conductive film. Next, an anisotropic etching process is performed using the resist pattern as a mask to selectively remove the conductive film exposed from the resist pattern, and a gate pattern and a dummy gate pattern are formed from the remaining conductive film. Next, a tilted ion implantation is performed using the resist pattern as a mask to form a p-type body region in the semiconductor substrate.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2024-013479, including the specification, drawings, and abstract, filed on January 31, 2024, is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a method of manufacturing a semiconductor device. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2019-192741

[0006] As disclosed in Patent Document 1, a laterally diffused metal oxide semiconductor (LDMOS), known as a metal-insulator-semiconductor field effect transistor (MISFET), has a low-concentration drift region provided between a high-concentration drain region and a gate electrode.

[0007] In a semiconductor device including a plurality of LDMOSs, the LDMOSs are arranged axially symmetrically around the drain region and the source region, and adjacent LDMOSs share the drain region or the source region.

[0008] In addition, a method has been implemented in which a conductive film for a gate electrode is patterned into a gate pattern, and the resist pattern for patterning is used as a mask as it is to perform tilted ion implantation. Thereby, a main region constituting a channel region of the LDMOS is formed between adjacent gate patterns. Subsequently, a source region is formed in the main region. Summary of the Invention

[0009] Among the outermost LDMOSs among a plurality of LDMOSs, the drain region is shared with the LDMOS adjacent to the outermost LDMOS, but the main region and the source region are not shared with other LDMOSs. Therefore, in the outermost LDMOS, only one gate pattern is used as a mask to form the main region. Therefore, the impurity distribution in the main region of the outermost LDMOS may be different from the impurity distribution in the main regions of other LDMOSs.

[0010] Therefore, for example, the threshold voltage of the outermost LDMOS may be lower than the threshold voltages of other LDMOSs, such that leakage current may flow more easily in the outermost LDMOS than in other LDMOSs. Therefore, there is a concern that the reliability of the semiconductor device may be reduced.

[0011] Through the description and drawings of this specification, other problems and novel features will become apparent.

[0012] In one embodiment, a method of manufacturing a semiconductor device includes: a step of forming an element isolation part in a semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, a step of forming a first conductive film on the gate insulating film and the element isolation part, a step of forming a first resist pattern on the first conductive film, a step of performing an anisotropic etching process using the first resist pattern as a mask to selectively remove the first conductive film exposed from the first resist pattern and form a first gate pattern and a dummy gate pattern from the first conductive film, and a step of performing an inclined ion implantation using the first resist pattern as a mask to form a first body region of a first conductivity type in the semiconductor substrate.

[0013] According to one embodiment, the reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a plan view showing a semiconductor device according to a first embodiment.

[0015] Figure 2 is showing Figure 1 an enlarged plan view of a part of

[0016] Figure 3 is a cross-sectional view showing a semiconductor device according to a first embodiment.

[0017] Figure 4 is showing Figure 3 an enlarged cross-sectional view of a part of

[0018] Figure 5 is a cross-sectional view showing a manufacturing step of a semiconductor device according to a first embodiment.

[0019] Figure 6 is showing Figure 5 a cross-sectional view of a manufacturing step of a semiconductor device after

[0020] Figure 7 is showing Figure 6 a cross-sectional view of a manufacturing step of a semiconductor device after

[0021] Figure 8 is showing Figure 7 a cross-sectional view of a manufacturing step of a semiconductor device after

[0022] Figure 9 is showing Figure 8 a cross-sectional view of a manufacturing step of a semiconductor device after

[0023] Figure 10 is showing Figure 8 a cross-sectional view of a manufacturing step of a semiconductor device after

[0024] Figure 11 is a cross-sectional view showing the manufacturing steps of a semiconductor device Figure 9 after

[0025] Figure 12 is a cross-sectional view showing the manufacturing steps of a semiconductor device Figure 11 after

[0026] Figure 13 is a cross-sectional view showing the manufacturing steps of a semiconductor device Figure 12 after

[0027] Figure 14 is a cross-sectional view showing the manufacturing steps of a semiconductor device Figure 13 after

[0028] Figure 15 is a cross-sectional view showing the manufacturing steps of a semiconductor device Figure 14 after

[0029] Figure 16 is a cross-sectional view showing the manufacturing steps of a semiconductor device Figure 15 after

[0030] Figure 17 is a cross-sectional view for explaining Figure 11 tilted ion implantation

[0031] Figure 18 is a graph showing the experimental data of the present inventor

[0032] Figure 19 is a cross-sectional view showing the manufacturing steps of a semiconductor device according to the first modification example

[0033] Figure 20 is a cross-sectional view showing a semiconductor device according to the second modification example

[0034] Figure 21 is a cross-sectional view of the main part showing the manufacturing steps of a semiconductor device according to the second modification example

[0035] Figure 22 is a cross-sectional view of the main part showing the manufacturing steps of a semiconductor device according to the second modification example DETAILED DESCRIPTION

[0036] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals, and their repetitive description will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

[0037] In addition, the X-direction, Y-direction, and Z-direction described in this application intersect with each other and are orthogonal to each other. In this application, the Z-direction is described as the vertical direction, depth direction, or thickness direction of a specific structure. The expressions "planar view" or "plane view" used in this application mean that the plane formed by the X-direction and Y-direction is regarded as the "plane", and this "plane" is viewed from the Z-direction.

[0038] First Embodiment

[0039] Structure of Semiconductor Device

[0040] As Figure 1 shown, the semiconductor device includes a plurality of n-type MISFETs 1Q, each n-type MISFET 1Q having a gate electrode GE, two dummy gate electrodes DGE, a p-type well region (impurity region) HPW1, an n-type well region (impurity region) HNW, and a p-type well region (impurity region) HPW2. The well regions HPW1, HNW, and HPW2 extend in the X-direction and Y-direction so as to surround the plurality of MISFETs 1Q and the two dummy gate electrodes DGE in a planar view. In the planar view, the well region HNW surrounds the well region HPW1. In the planar view, the well region HPW2 surrounds the well region HNW.

[0041] Although not shown here, the element isolation portion STI also extends in the X-direction and Y-direction so as to surround the plurality of MISFETs 1Q in a planar view. The two dummy gate electrodes DGE are respectively formed on the element isolation portion STI extending along the Y-direction.

[0042] As Figure 2 shown, each of the plurality of MISFETs 1Q has a gate electrode GE, a p-type body region (impurity region) PB, an n-type source region (impurity region) NS, a p-type high-concentration diffusion region (impurity region) PR, an n-type drift region (impurity region) NLD, and an n-type drain region (impurity region) ND. The gate electrode GE is formed of, for example, an n-type polysilicon film. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. The drift region NLD has a lower impurity concentration than the drain region ND and the source region NS.

[0043] The gate electrode GE, the body region PB, the drain region ND, and the dummy gate electrode DGE extend in the Y-direction. A plurality of source regions NS are formed in the body region PB so as to be separated from each other in the Y-direction. High-concentration diffusion regions PR are respectively formed between the source regions NS adjacent to each other in the Y-direction. A portion of the body region PB located between the drain region ND and the source region NS and overlapping with the gate electrode GE in a planar view serves as the channel region of the MISFET 1Q.

[0044] A plurality of MISFETs 1Q are arranged axially symmetrically around a drain region ND and a source region NS. Among the MISFETs 1Q adjacent to each other in the X direction, the drain region ND or the source region NS is shared. In the outermost MISFET 1Q among the plurality of MISFETs 1Q, the drain region ND is shared with the MISFET 1Q adjacent to the outermost MISFET 1Q, but the body region PB and the source region NS are not shared with other MISFETs 1Q.

[0045] Figure 3 is a cross-sectional view along Figure 1 and Figure 2 the line A1 - A3 shown. Figure 4 is a cross-sectional view along Figure 1 and Figure 2 the line A1 - A2 shown, and shows a part of Figure 3 in an enlarged manner.

[0046] The semiconductor substrate SUB is formed of p-type silicon. In the first embodiment, the semiconductor substrate SUB includes a support substrate SS made of, for example, a p-type silicon substrate and a p-type semiconductor layer (silicon layer) EP formed on the support substrate SS by epitaxial growth. In the following description, various impurity regions formed in the semiconductor substrate SUB are specifically formed in the semiconductor layer EP.

[0047] An element isolation portion STI is formed in the semiconductor substrate SUB. The element isolation portion STI includes a trench formed in the semiconductor substrate SUB to reach a predetermined depth from the upper surface of the semiconductor substrate SUB and an insulating film buried in the trench. The insulating film is, for example, a silicon oxide film.

[0048] In the semiconductor substrate SUB, an n-type drift region NLD, a p-type impurity region PLD, and an n-type buried region NBL are formed. The drift region NLD is formed to a predetermined depth from the upper surface of the semiconductor substrate SUB and is located on the impurity region PLD and the buried region NBL. The impurity region PLD is located on the buried region NBL. In the semiconductor substrate SUB, the impurity region PLD and the buried region NBL are formed at a position deeper than the element isolation portion STI.

[0049] Furthermore, in the semiconductor substrate SUB, a body region PB, a well region HPW1, a well region HNW, and a well region HPW2 are formed. The body region PB, the well region HPW1, the well region HNW, and the well region HPW2 are formed to a position deeper from the upper surface of the semiconductor substrate SUB than the element isolation portion STI. The body region PB and the well region HPW1 are in contact with the impurity region PLD. The buried region NBL is in contact with the well region HNW.

[0050] A gate insulating film GI is formed on a semiconductor substrate SUB. The gate insulating film GI is, for example, a silicon oxide film. A gate electrode GE is formed on the gate insulating film GI. Sidewall spacers SW are formed on side surfaces of the gate electrode GE. The sidewall spacers SW include, for example, a silicon oxide film and a silicon nitride film formed on the silicon oxide film. An insulating film IF1 is formed on an upper surface of the semiconductor substrate SUB to cover the gate electrode GE and a part of the sidewall spacers SW. The insulating film IF1 is, for example, a silicon oxide film.

[0051] A source region NS is formed in a body region PB. As Figure 2 shown, a high-concentration diffusion region PR is also formed in the body region PB. A drain region ND is formed in a drift region NLD. A part of the drain region ND and the drift region NLD is covered by the insulating film IF1, but other parts of the drain region ND are exposed from the insulating film IF1.

[0052] In the X direction, the gate electrode GE is formed on a part of the semiconductor substrate SUB located between the source region NS and the drain region ND. A part of the body region PB located between the source region NS and the drain region ND and under the gate electrode GE serves as a channel region of the MISFET 1Q.

[0053] High-concentration diffusion regions PR are formed in a well region HPW1 and a well region HPW2. An n-type high-concentration diffusion region (impurity region) NR is formed in a well region HNW. The impurity concentration of each of the source region NS, the drain region ND, and the high-concentration diffusion region NR is higher than the impurity concentration of the drift region NLD. The impurity concentration of the high-concentration diffusion region PR is higher than the impurity concentration of each of the well region HPW1 and the well region HPW2.

[0054] A silicide film SI is formed on a part of the semiconductor substrate SUB exposed from the insulating film IF1. That is, the silicide film SI is formed on upper surfaces of the gate electrode GE, the source region NS, the drain region ND, a part of the high-concentration diffusion region PR, and the high-concentration diffusion region NR. The source region NS and the high-concentration diffusion region PR formed in the body region PB are electrically connected through the same silicide film SI. The silicide film S1 is, for example, a cobalt silicide (CoSi2) film, a nickel silicide (NiSi) film, or a nickel platinum silicide (NiPtSi) film.

[0055] An interlayer insulating film IL is formed on an upper surface of the semiconductor substrate SUB. The interlayer insulating film IL is, for example, a silicon oxide film. A plurality of holes CH1 are formed in the interlayer insulating film IL. Plugs PG are formed in each of the plurality of holes CH1. The plugs PG include, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film includes, for example, a titanium film and a titanium nitride film, and the conductive film is, for example, a tungsten film.

[0056] A plurality of holes CH1 are formed to reach the source region NS, the drain region ND, the high-concentration diffusion region PR, and the high-concentration diffusion region NR. Although not shown here, a plurality of wirings connected to the plurality of plugs PG are formed on the interlayer insulating film IL. A predetermined potential is supplied from the plurality of wirings to the source region NS, the drain region ND, the high-concentration diffusion region PR, and the high-concentration diffusion region NR.

[0057] The drain region ND and the drift region NLD are respectively turned on as n-type impurity regions and are fixed at the same potential. The well region HPW1, the impurity region PLD, the body region PB, the high-concentration diffusion region PR formed in the well region HPW1, and the high-concentration diffusion region PR formed in the body region PB are respectively turned on as p-type impurity regions and are fixed at the same potential. The well region HPW2, the semiconductor layer EP, the support substrate SS, and the high-concentration diffusion region PR formed in the well region HPW2 are respectively turned on as p-type impurity regions and are fixed at the same potential.

[0058] The high-concentration diffusion region NR, the well region HNW, and the buried region NBL are respectively turned on as n-type impurity regions and are fixed at the same potential. By using the buried region NBL and the well region HNW to electrically isolate the plurality of MISFETs 1Q and the semiconductor substrate SUB, the noise resistance of the plurality of MISFETs 1Q can be enhanced.

[0059] Although not shown here, the holes CH1 and the plugs PG are also formed on the upper surface of the gate electrode GE, and the silicide film SI is formed on this upper surface. During the operation of the MISFET 1Q, the gate potential is supplied to the gate electrode GE, the drain potential is supplied to the drain region ND, and the source potential is supplied to the source region NS.

[0060] In addition, a dummy gate electrode DGE is formed on the element isolation portion STI where the body region PB and the well region HPW1 are in contact. Although the silicide film SI is formed on the upper surface of the dummy gate electrode DGE, the holes CH1 and the plugs PG are not formed on the upper surface of the dummy gate electrode DGE. Therefore, the dummy gate electrode DGE is not electrically connected to any wiring, and no potential is supplied to the dummy gate electrode DGE. That is, the dummy gate electrode DGE is in an electrically floating state.

[0061] Method of manufacturing a semiconductor device

[0062] Hereinafter, Figures 5 to 15 each manufacturing step included in the method of manufacturing a semiconductor device in the first embodiment will be described.

[0063] As Figure 5As shown, a semiconductor substrate SUB is prepared. The semiconductor substrate SUB may be a single-layer p-type silicon substrate, but in the first embodiment, the semiconductor substrate SUB includes a support substrate SS and a semiconductor layer EP. First, the support substrate SS is prepared. The support substrate SS is made of p-type silicon. Next, a semiconductor layer EP as a p-type silicon layer is formed on the support substrate SS by epitaxial growth.

[0064] Next, a buried region NBL is formed in the semiconductor substrate SUB by photolithography and ion implantation. After the buried region NBL is formed in the support substrate SS, the semiconductor layer EP can be formed on the support substrate SS.

[0065] As Figure 6 shown, an element isolation portion STI is formed in the semiconductor substrate SUB. First, trenches are formed in the semiconductor substrate SUB by photolithography and anisotropic etching to a predetermined depth from the upper surface of the semiconductor substrate SUB. Next, an insulating film (such as a silicon oxide film) is formed on the semiconductor substrate SUB to fill the trenches. Next, the insulating film buried in the trenches is retained, and the insulating film located outside the trenches is removed by polishing using a CMP method.

[0066] As Figure 7 shown, impurity regions PLD, a drift region NLD, well regions HPW1, HPW2, and a well region HNW are sequentially formed in the semiconductor substrate SUB by photolithography and ion implantation. The order of forming these regions can be any sequence.

[0067] As Figure 8 shown, first, for example, a gate insulating film GI is formed on the semiconductor substrate SUB by thermal oxidation treatment. Next, for example, a conductive film CF1 is formed on the gate insulating film GI and on the element isolation portion STI by a film formation process using a CVD method. The conductive film CF1 is, for example, a polysilicon film into which n-type impurities have been introduced.

[0068] As Figure 9 shown, first, a resist pattern RP1 is formed on the conductive film CF1. The resist pattern RP1 has an opening that exposes a part of the conductive film CF1 located on the gate insulating film GI, the boundary between the element isolation portion STI and the semiconductor substrate SUB, and a part of the conductive film CF1 located on the element isolation portion STI.

[0069] Next, by performing an anisotropic etching process using the resist pattern RP1 as a mask, the conductive film CF1 exposed from the resist pattern RP1 is selectively removed to form a gate pattern GP and a dummy gate pattern DGP from the conductive film CF1. The dummy gate pattern DGP is at least located on the element isolation portion STI.

[0070] As Figure 9 shown, the resist pattern RP1 also has openings exposing a plurality of locations of the conductive film CF1 on the gate insulating film GI, and a plurality of gate patterns GP are formed by an anisotropic etching process.

[0071] Figure 10 FIG. is a cross-sectional view along line A1 - A3 showing the state after the anisotropic etching process. As Figure 10 shown, the well regions HPW1, HNW, and HPW2 are covered with the dummy gate pattern DGP and the resist pattern RP1. Therefore, due to subsequent inclined ion implantation, the body regions PB are not formed in the well regions HPW1, HNW, and HPW2.

[0072] As Figure 11 shown, the body regions PB are formed by performing inclined ion implantation using the resist pattern RP1 as a mask. In this inclined ion implantation, ions are implanted from a direction inclined by an angle, for example, greater than 20 degrees and less than 45 degrees, with respect to the direction (Z direction) perpendicular to the upper surface of the semiconductor substrate SUB.

[0073] The body regions PB are formed in a part of the semiconductor substrate SUB between the gate patterns GP and the dummy gate pattern DGP in a plan view, and are formed in a part of the semiconductor substrate SUB between the plurality of gate patterns GP in a plan view. In addition, the body regions PB are also formed in a part of the semiconductor substrate SUB under each gate pattern GP. Subsequently, the resist pattern RP1 is removed by ashing.

[0074] The opening widths W3 of the plurality of openings of the resist pattern RP1 are the same as each other. The opening width W3 is the width in the direction in which the plurality of gate patterns GP and the dummy gate pattern DGP are adjacent to each other, and it is the width in the X direction. Therefore, after Figure 9 the anisotropic etching process, the shortest distances between the plurality of gate patterns GP are the same as each other, and this shortest distance is also the same as the shortest distance between the gate pattern GP and the dummy gate pattern DGP.

[0075] Since the inclined ion implantation is performed using the same resist pattern RP1, a plurality of body regions PB are formed in self - alignment. Therefore, under each gate pattern GP, the width of the region where the body region PB and the gate pattern GP overlap with each other in a plan view is constant.

[0076] That is, by performing an anisotropic etching process on the conductive film CF1 and performing ion implantation on the body regions PB using the same resist pattern RP1, variations in the channel lengths of the plurality of MISFETs 1Q can be suppressed.

[0077] AsFigure 12 As shown, first, a resist pattern RP2 is formed to cover a part of the gate pattern GP on the gate insulating film GI, the body region PB, and a part of the dummy gate pattern DGP on the element isolation STI.

[0078] Subsequently, by using the resist pattern RP2 as a mask and performing an anisotropic etching process, the exposed gate pattern GP and dummy gate pattern DGP are selectively removed to form a gate electrode GE from the gate pattern GP and a dummy gate electrode DGE from the dummy gate pattern DGP. Thereafter, the resist pattern RP2 is removed by ashing.

[0079] As Figure 13 shown, sidewall spacers SW are formed on each side surface of the gate electrode GE and the dummy gate electrode DGE. First, for example, by a film formation process using a CVD method, a laminated film including, for example, a silicon oxide film and a silicon nitride film is formed on the semiconductor substrate SUB to cover the gate electrode GE and the dummy gate electrode DGE. Next, by performing an anisotropic etching process on the laminated film, sidewall spacers SW are formed from the laminated film remaining on each side surface of the gate electrode GE and the dummy gate electrode DGE. Note that the gate insulating film GI exposed from the gate electrode GE is also removed by the anisotropic etching process.

[0080] As Figure 14 shown, first, a resist pattern RP3 is formed, which has an opening exposing the well region HPW1. Although not shown, the resist pattern RP3 also has an opening exposing a part of the body region PB and the well region HPW2. Next, by using the resist pattern RP3 as a mask and performing ion implantation, high-concentration diffusion regions PR are formed in the well region HPW1, in the body region PB, and in the well region HPW2 (see Figure 2 and Figure 3 ). Thereafter, the resist pattern RP3 is removed by ashing.

[0081] As Figure 15 shown, first, a resist pattern RP4 is formed, which has an opening exposing a part of the body region PB and a part of the drift region NLD. Although not shown, the resist pattern RP4 also has an opening exposing the well region HNW. Next, by using the resist pattern RP4 as a mask and performing ion implantation, a source region NS is formed in the body region PB, a drain region ND is formed in the drift region NLD, and a high-concentration diffusion region NR is formed in the well region HNW (see Figure 3 ). Note that the drain region ND is formed in the semiconductor substrate SUB at a position away from each gate electrode GE. Thereafter, the resist pattern RP4 is removed by ashing.

[0082] Figure 14 ion implantation and Figure 15 ion implantation can be performed in any order. After these ion implantations, a heat treatment is performed on the semiconductor substrate SUB to activate the impurities included in each impurity region.

[0083] As Figure 16 shown, first, for example, by a film formation process using the CVD method, an insulating film IF1 is formed on the upper surface of the semiconductor substrate SUB to cover the gate electrode GE, dummy gate electrode DGE, and sidewall spacer SW. Next, the insulating film IF1 is patterned by photolithography and anisotropic etching processes. As a result, the insulating film IF1 remains on a part of the drain region ND, the drift region NLD, the sidewall spacer SW, and a part of the upper surface of the gate electrode GE.

[0084] Next, by using a self-aligned silicide technique, a silicide film SI is formed on the upper surfaces of the gate electrode GE, dummy gate electrode DGE, drain region ND, source region NS, and high-concentration diffusion region PR, each of which is exposed from the insulating film IF1. Although not shown, the silicide film SI is also formed on the upper surface of the high-concentration diffusion region NR.

[0085] Thereafter, through the following manufacturing steps, a semiconductor device as Figure 3 and Figure 4 shown is manufactured.

[0086] First, for example, by using the CVD method for film formation, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB. Next, through photolithography and anisotropic etching processes, a plurality of holes CH1 are formed in the interlayer insulating film IL. Each of the plurality of holes CH1 reaches the silicide film SI formed on the upper surfaces of the source region NS, drain region ND, high-concentration diffusion region PR, high-concentration diffusion region NR, and gate electrode GE.

[0087] Next, a plug PG is formed in each of the plurality of holes CH1. To form the plug PG, first, for example, a barrier metal film is formed in the plurality of holes CH1 and on the interlayer insulating film IL by sputtering. The barrier metal film includes, for example, a titanium film and a titanium nitride film. Next, for example, a conductive film (such as a tungsten film) is formed on the barrier metal film by the CVD method. Then, the conductive film and the barrier metal film formed outside the plurality of holes CH1 are removed by, for example, the CMP method for polishing.

[0088] Main features of the first embodiment

[0089] The main feature of the first embodiment is that asFigure 11 As shown, tilt ion implantation is performed on the body region PB in a state where a dummy gate pattern DGP is formed.

[0090] As Figure 17 shown, in the tilt ion implantation, there are ions IJ1 directly implanted into the drift region NLD and ions IJ2 implanted into the drift region NLD after being reflected or scattered by the resist pattern RP1. Therefore, when the opening width of the resist pattern RP1 changes, the implantation position of the ions IJ2 changes, and the impurity distribution in the body region PB changes. As described above, a part of the body region PB located under the gate pattern GP serves as the channel region of the MISFET 1Q. However, the change in the opening width of the resist pattern RP1 changes the impurity distribution in the channel region, and the threshold voltage of the MISFET 1Q changes.

[0091] Figure 18 The relationship between the opening width of the resist pattern RP1 and the change in the threshold voltage (Vth) of the MISFET 1Q is shown. As Figure 18 shown, the opening width W3 is, for example, 0.65 μm or more and 1.0 μm or less, and is used for the resist pattern RP1 described in Figure 11 . The opening width W4 is smaller than the opening width W3, for example, less than 0.65 μm. The opening width W5 is larger than the opening width W3, for example, wider than 1.0 μm. The opening widths W3, W4, and W5 are widths in the X direction, respectively.

[0092] In the case of the opening width W4, a part of the implanted ions IJ1 and IJ2 is blocked by the upper surface of the resist pattern RP1. Therefore, the number of ions implanted into the channel region decreases, resulting in a decrease in the threshold voltage. In the case of the opening width W3, compared with the case of the opening width W4, the ions IJ1 and IJ2 are more likely to reach the channel region, resulting in an increase in the threshold voltage. In the case of the opening width W5, compared with the case of the opening width W3, the number of ions IJ2 that can reach the channel region decreases, resulting in a decrease in the threshold voltage. The MISFET 1Q with a decreased threshold voltage is formed as a semiconductor element that is more likely to have a leakage current flow than other MISFET 1Qs, which may reduce the reliability of the semiconductor device.

[0093] As Figure 1 shown, in the first embodiment, a dummy gate electrode DGE is formed outside the outermost MISFET 1Q (outermost MISFET 1Q) in the X direction. The dummy gate electrode DGE and the dummy gate pattern DGP that is the base of the dummy gate electrode DGE do not serve as semiconductor devices. Therefore, initially, it is not necessary to form the dummy gate electrode DGE and the dummy gate pattern DGP. However, asFigure 18 As shown, performing the tilted ion implantation in a state where the dummy gate pattern DGP is not formed is almost synonymous with forming the body region PB of the outermost MISFET 1Q in a state where the opening width is W5.

[0094] In the first embodiment, the dummy gate electrode DGE is formed further outside the outermost MISFET 1Q. In other words, as Figure 11 shown, the dummy gate pattern DGP is formed further outside the gate pattern GP of the outermost MISFET 1Q. Therefore, as Figure 18 shown, the tilted ion implantation can be performed in a state where the opening width is W3. Therefore, the number of ions implanted into the channel region can be sufficiently ensured and the decrease in the threshold voltage can be suppressed, thereby ensuring the reliability of the semiconductor device.

[0095] In addition, the opening widths W3 of the plurality of openings of the resist pattern RP1 are the same as each other. Therefore, in the plan view, below each gate pattern GP, the width of the region where the body region PB and the gate pattern GP overlap with each other is constant. Therefore, the variation in the channel lengths of the plurality of MISFETs 1Q can be suppressed, and the variation in the impurity distribution in the channel regions of the plurality of MISFETs 1Q can also be suppressed.

[0096] In addition, as Figure 2 shown, the plurality of source regions NS are formed to be separated from each other in the Y direction. Preferably, the variation in the impurity distribution across the plurality of channel regions between the plurality of source regions NS and the drain region ND is suppressed.

[0097] Therefore, at Figure 11 the time, preferably, the width of the dummy gate pattern DGP in the Y direction is greater than the width of the drain region ND formed in a later manufacturing step. Finally, as Figure 2 shown, preferably, the width W1 of the dummy gate electrode DGE in the Y direction is greater than the width W2 of the drain region ND.

[0098] The width W2 of the drain region ND can also be understood as follows using the source regions NS. As Figure 2 shown, the plurality of source regions NS include one outermost source region NS1 located in the Y direction and another outermost source region NS2 located in the Y direction. In other words, the plurality of source regions NS include the source region NS1 and the source region NS2 that are farthest apart from each other in the Y direction. The source region NS1 has an outermost end portion NS1e that is farthest from the source region NS2 in the Y direction. The source region NS2 has an outermost end portion NS2e that is farthest from the source region NS1 in the Y direction. In the Y direction, the width of the dummy gate electrode DGE is greater than the distance from the outermost end portion NS1e to the outermost end portion NS2e.

[0099] First modification example

[0100] Hereinafter, reference will be made to Figure 19 Describe a semiconductor device according to a first modification example of the first embodiment. It should be noted that the following description will mainly address the differences from the first embodiment, and the description of aspects overlapping with the first embodiment will be omitted.

[0101] Figure 19 Illustrated in Figure 11 After the process of Figure 12 And instead of Figure 12 As shown, in the first embodiment, a part of the dummy gate pattern DGP is processed with the resist pattern RP2 to form the dummy gate electrode DGE. In the first modification example, as Figure 19 Shown, the dummy gate pattern DGP is completely removed using the resist pattern RP5.

[0102] As Figure 19 Shown, first, a resist pattern RP5 is formed to cover a part of the gate pattern GP located on the gate insulating film GI, the body region PB, and a part of the element isolation portion STI exposed from the dummy gate pattern DGP. In order to completely remove the dummy gate pattern DGP and avoid etching the semiconductor substrate SUB, the edge of the resist pattern RP5 is positioned on the part of the element isolation portion STI between the dummy gate pattern DGP and the body region PB.

[0103] Next, by performing an anisotropic etching process using the resist pattern RP5 as a mask, the gate pattern GP and the dummy gate pattern DGP exposed from the resist pattern RP5 are selectively removed to form the gate electrode GE from the gate pattern GP. Since the dummy gate pattern DGP is completely removed, the dummy gate electrode DGE is not formed. Thereafter, the resist pattern RP5 is removed by ashing.

[0104] Therefore, the dummy gate pattern DGP can be removed after the body region PB is formed. The subsequent manufacturing steps are the same as those from Figures 13 to 16 The manufacturing steps of

[0105] Second modification example

[0106] Hereinafter, reference will be made to Figures 20 to 22 Describe a semiconductor device according to a second modification example of the first embodiment. It should be noted that the following description will mainly address the differences from the first embodiment, and the description of aspects overlapping with the first embodiment will be omitted.

[0107] In the first embodiment, the dummy gate electrode DGE is formed on the element isolation portion STI. In the second modification example, asFigure As shown, the dummy gate electrode DGE is formed not only on the element isolation portion STI but also on the gate insulating film. To form the dummy gate electrode DGE in this way, a dummy gate pattern DGP is formed on the element isolation portion STI and on the gate insulating film.

[0108] ​ shows the manufacturing steps corresponding to ​ and ​ The manufacturing steps are as follows. As ​ shown, a resist pattern RP1 is formed to expose a part of the conductive film CF1 located on the gate insulating film GI on the conductive film CF1. The resist pattern RP1 of the second modified example is different from that of the first embodiment in that it covers the conductive film CF1 located on the element isolation portion STI and the boundary between the element isolation portion STI and the semiconductor substrate SUB. In the second modified example, the opening width W3 of the resist pattern RP1 is the same as the opening width W3 of the first embodiment.

[0109] Next, by using the resist pattern RP1 as a mask and performing an anisotropic etching process, the conductive film CF1 exposed from the resist pattern RP1 is selectively removed to form a gate pattern GP and a dummy gate pattern DGP from the conductive film CF1. The dummy gate pattern DGP is located on the gate insulating film GI and the element isolation portion STI and intersects the boundary between the element isolation portion STI and the semiconductor substrate SUB. Then, by using the resist pattern RP1 as a mask and performing a tilted ion implantation, a body region PB is formed. The body region PB is also formed in a part of the semiconductor substrate SUB located below the dummy gate pattern DGP.

[0110] As ​ shown, there may be a step between the upper surface of the semiconductor substrate SUB (the upper surface of the gate insulating film GI) and the upper surface of the element isolation portion STI. If such a step occurs, the symmetry of the implantation positions of the ions IJ1 and IJ2 implanted from above the dummy gate pattern DGP toward the gate pattern GP and the implantation positions of the ions IJ1 and IJ2 implanted from above the gate pattern GP toward the dummy gate pattern DGP tends to shift. That is, the ion implantation amounts near the gate pattern GP and near the dummy gate pattern DGP tend to show differences.

[0111] Similar to the second modified example, by also positioning the dummy gate pattern DGP on the gate insulating film, the influence of the above steps does not have to be considered, thereby improving the symmetry of the implantation positions of the ions IJ1 and IJ2 and allowing the ion implantation amount into the channel region to be uniform.

[0112] In addition, since there is no step between the upper surface of the semiconductor substrate SUB and the upper surface of the element isolation portion STI, the conditions for ion implantation performed between the gate pattern GP and the dummy gate pattern DGP are the same as the conditions for ion implantation performed between the plurality of gate patterns GP. Therefore, the impurity distribution in the channel regions of the plurality of MISFETs 1Q can be made uniform.

[0113] Next, the difference between the second modification example and the first embodiment will be described, which is regarding the width in the X direction of the source region NS located between the gate pattern GP and the dummy gate pattern DGP in the plan view.

[0114] In the first embodiment, the width in the X direction of the source region NS is mainly determined by the distance between the gate pattern GP and the element isolation portion STI. Therefore, if the formation position of the gate pattern GP changes, the distance between the gate pattern GP and the element isolation portion STI also changes, which may cause the width of the source region NS in the X direction to decrease.

[0115] The width in the X direction of the source region NS located between the gate pattern GP and the dummy gate pattern DGP in the plan view can be smaller than the width in the X direction of the source region NS located between the plurality of gate patterns GP in the plan view. Therefore, in the MISFET 1Q using the source region NS located between the gate pattern GP and the dummy gate pattern DGP in the plan view, there is a possibility that the parasitic resistance increases and the on-current decreases compared to other MISFETs 1Q.

[0116] As ​ shown, in the Y direction, a high-concentration diffusion region PR is formed between adjacent source regions NS. Similar to the above source region NS, the width in the X direction of the high-concentration diffusion region PR located between the gate pattern GP and the dummy gate pattern DGP in the plan view may become smaller. Therefore, in the MISFET 1Q using the source region NS located between the gate pattern GP and the dummy gate pattern DGP in the plan view, there is a possibility that the resistance in the body region PB increases and the on-voltage durability decreases compared to other MISFETs 1Q.

[0117] ​ Shows the manufacturing steps corresponding to ​ . As ​ shown, the dummy gate pattern DGP is also located on the gate insulating film.

[0118] In the second modification example, the width of the source region NS and the high-concentration diffusion region PR in the X direction is mainly determined by the distance between the gate pattern GP and the dummy gate pattern DGP. Even if the formation positions of the gate pattern GP and the dummy gate pattern DGP change, the distance between the gate pattern GP and the dummy gate pattern DGP is constant.

[0119] That is, in the second modification example, the width of the source region NS in the X direction located between the gate pattern GP and the dummy gate pattern DGP in the plan view becomes the same as the width of the source region NS in the X direction located between the plurality of gate patterns GP in the plan view. Therefore, in the MISFET 1Q using the source region NS located between the gate pattern GP and the dummy gate pattern DGP in the plan view, the parasitic resistance is unlikely to increase, and the on-current is unlikely to decrease.

[0120] In addition, in the second modification example, the width of the high-concentration diffusion region PR in the X direction located between the gate pattern GP and the dummy gate pattern DGP in the plan view becomes the same as the width of the high-concentration diffusion region PR in the X direction located between the plurality of gate patterns GP in the plan view. Therefore, in the MISFET 1Q using the source region NS located between the gate pattern GP and the dummy gate pattern DGP in the plan view, the resistance in the body region PB is unlikely to increase, and the on-voltage durability is unlikely to decrease.

[0121] As described above, the present invention has been specifically described based on the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from its spirit.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: (a) preparing a semiconductor substrate; (b) after (a), forming an element isolation part in the semiconductor substrate; (c) after (b), forming a gate insulating film on the semiconductor substrate; (d) after (c), forming a first conductive film on the gate insulating film and on the element isolation part; (e) after (d), forming a first resist pattern on the first conductive film, the first resist pattern having a first opening that exposes a part of the first conductive film located on the gate insulating film; (f) after (e), performing an anisotropic etching process using the first resist pattern as a mask to selectively remove the first conductive film exposed from the first resist pattern and forming a first gate pattern and a dummy gate pattern from the first conductive film; (g) after (f), performing an inclined ion implantation using the first resist pattern as a mask to form a first main region of a first conductivity type in a part of the semiconductor substrate located between the first gate pattern and the dummy gate pattern in a plan view; and (h) after (g), removing the first resist pattern, wherein the dummy gate pattern is at least located on the element isolation part, and wherein the first main region is formed in a part of the semiconductor substrate located below the first gate pattern.

2. The method according to claim 1, wherein in (e), the first resist pattern includes a second opening that exposes another part of the first conductive film located on the gate insulating film, wherein in (f), a second gate pattern is formed from the remaining first conductive film, wherein after (f), the second gate pattern is located on the gate insulating film, wherein in (g), a second main region of the first conductivity type is formed in a part of the semiconductor substrate located between the first gate pattern and the second gate pattern in a plan view, wherein the second main region is formed in another part of the semiconductor substrate located below the first gate pattern and in a part of the semiconductor substrate located below the second gate pattern, and wherein in a direction in which the second gate pattern, the first gate pattern, and the dummy gate pattern are adjacent to each other, the shortest distance between the first gate pattern and the dummy gate pattern is the same as the shortest distance between the first gate pattern and the second gate pattern.

3. The method according to claim 1, comprising: (i) after (h), forming a second resist pattern that covers a part of the first gate pattern located on the gate insulating film, the first main region, and a part of the dummy gate pattern located on the element isolation part; (j)After the (i), perform an anisotropic etching process using the second resist pattern as a mask to selectively remove the first gate pattern and the dummy gate pattern exposed from the second resist pattern, form a first gate electrode from the remaining first gate pattern, and form a dummy gate electrode from the remaining dummy gate pattern; And (k)After the (j), remove the second resist pattern, wherein the dummy gate electrode is at least located on the element isolation portion.

4. The method according to claim 3, comprising: (l)After the (k), form a first source region of a second conductivity type opposite to the first conductivity type in the first body region, and form a first drain region of the second conductivity type in the semiconductor substrate, wherein the first gate electrode, the dummy gate electrode, and the first drain region extend in a first direction in a plan view, wherein the first gate electrode is formed in a second direction intersecting the first direction in the plan view on a part of the semiconductor substrate located between the first source region and the first drain region, and wherein in the first direction, the width of the dummy gate electrode is greater than the width of the first drain region.

5. The method according to claim 4, wherein in the (l), the first source region includes a plurality of first source regions, and the plurality of first source regions are formed in the first body region such that the plurality of first source regions are separated from each other in the first direction, wherein the plurality of first source regions include a first source region and another first source region that are the farthest apart from each other in the first direction, wherein the first source region includes a first outermost end portion that is the farthest from the other first source region in the first direction, wherein the other first source region includes a second outermost end portion that is the farthest from the first source region in the first direction, and wherein in the first direction, the width of the dummy gate electrode is greater than the distance from the first outermost end portion to the second outermost end portion.

6. The method according to claim 4, wherein the semiconductor device includes a MISFET, wherein the MISFET includes the first gate electrode, the first source region, and the first drain region, wherein a part of the first body region located between the first source region and the first drain region and under the first gate electrode serves as a channel region of the MISFET, and wherein during the operation of the MISFET, a gate voltage is applied to the first gate electrode, and the dummy gate electrode is in an electrically floating state.

7. The method according to claim 4, comprising: (m)Before the (c), form a first well region of the first conductivity type in the semiconductor substrate, The first well region extends in the first direction and the second direction so as to contact the device isolation part and at least surround the first gate electrode, the first source region, the first drain region, the first body region, the device isolation part, and the dummy gate electrode in a plan view.

8. The method according to claim 7, comprising: (n) Before (c), forming a first impurity region of the first conductivity type in the semiconductor substrate at a position deeper than the device isolation part, wherein the first well region is formed from the upper surface of the semiconductor substrate to a position deeper than the device isolation part and contacts the first impurity region, and wherein the first body region is formed from the upper surface of the semiconductor substrate to a position deeper than the device isolation part and contacts the first impurity region.

9. The method according to claim 4, wherein in (e), the first resist pattern includes a second opening that exposes another part of the first conductive film located on the gate insulating film, wherein in (f), a second gate pattern is formed from the remaining first conductive film, wherein in (g), a second body region of the first conductivity type is formed in a part of the semiconductor substrate located between the first gate pattern and the second gate pattern in a plan view, wherein the second body region is formed in another part of the semiconductor substrate located under the first gate pattern and a part of the semiconductor substrate located under the second gate pattern, wherein in the second direction, the shortest distance between the first gate pattern and the dummy gate pattern is the same as the shortest distance between the first gate pattern and the second gate pattern, wherein in (i), the second resist pattern covers another part of the first gate pattern located on the gate insulating film, the second body region, and a part of the second gate pattern located on the gate insulating film, wherein in (j), the first gate pattern and the second gate pattern exposed from the second resist pattern are selectively removed to form the first gate electrode and the second gate electrode from the remaining first gate pattern and form the third gate electrode from the remaining second gate pattern, wherein in (l), a second source region of the second conductivity type is formed in the second body region, and a second drain region of the second conductivity type is formed in the semiconductor substrate, wherein the second gate electrode, the third gate electrode, and the second drain region extend in the first direction, wherein the second gate electrode is formed on a part of the semiconductor substrate located between the first drain region and the second source region in the second direction, wherein the third gate electrode is formed on a part of the semiconductor substrate located between the second drain region and the second source region in the second direction, and In the first direction, the width of the dummy gate electrode is greater than the width of the second drain region.

10. The method according to claim 1, wherein (b) includes: (b1) forming a trench in the semiconductor substrate; (b2) forming an insulating film on the semiconductor substrate to fill the trench; and (b3) removing the insulating film located outside the trench so that the insulating film buried in the trench remains.

11. The method according to claim 1, including: (o) after (h), forming a third resist pattern that covers a portion of the first gate pattern on the gate insulating film, the first body region, and a portion of the element isolation part exposed from the dummy gate pattern; and (p) after (o), performing an anisotropic etching process using the third resist pattern as a mask to selectively remove the first gate pattern and the dummy gate pattern exposed from the third resist pattern, and forming a first gate electrode from the first gate pattern.

12. The method according to claim 1, wherein the element isolation part surrounds the gate insulating film, the first gate pattern, and the first body region in a plan view.

13. The method according to claim 1, wherein the first gate pattern is located on the gate insulating film, wherein the dummy gate pattern is located on the gate insulating film and the element isolation part so as to cross the boundary between the element isolation part and the semiconductor substrate, and wherein the first body region is formed in a portion of the semiconductor substrate located below the dummy gate pattern.

14. The method according to claim 3, wherein the dummy gate electrode is formed on the element isolation part and the gate insulating film.

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