Semiconductor device and manufacturing method thereof
By adopting a grille isolation structure in SOI, the problem of poor heat dissipation performance of traditional SOI is solved and better heat dissipation effect is achieved.
Patent Information
- Application Number
- CN202510538539.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-27
- Publication Date
- 2025-08-01
AI Technical Summary
The poor heat dissipation performance of traditional SOI is mainly due to the poor thermal conductivity of the embedded isolation structure and the trench isolation structure.
The active area is isolated by a grille type isolation structure. The grille type isolation structure consists of at least two isolation layers, and adjacent layers are isolated by materials with better thermal conductivity, ensuring that the isolation effect remains unchanged while improving heat dissipation performance.
Without affecting the isolation effect, the heat dissipation performance of the device is significantly improved.
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Figure CN120417481A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art
[0002] As Figure 1 shown, a conventional SOI (Silicon on Insulator) generally consists of a silicon substrate 100, a top silicon layer 200, and a buried oxide layer 300 located between the silicon substrate and the top silicon layer. Among them, the top silicon layer is a key area for manufacturing transistors and other active devices. Active regions 500 separated by a trench isolation structure 400 are formed in the top silicon layer. The active regions 500 are used to define the channels, source electrodes (S), and drain electrodes (D) of transistors. In the active regions 500, conductive channels are formed through doping and gate control to achieve the switching function of the transistors.
[0003] SOI has advantages such as low delay, low dynamic power consumption, and small leakage current, but there is a problem of poor heat dissipation in the active regions 500 after the device is turned on. Summary of the Invention
[0004] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof for a semiconductor structure to solve the problem of poor heat dissipation performance of conventional SOI.
[0005] To solve the above problems, the present invention provides a semiconductor device, which includes:
[0006] A substrate layer, a first isolation structure, and a device layer stacked in sequence from bottom to top, where the device layer has active regions; and,
[0007] A second isolation structure disposed around the active regions within the device layer;
[0008] Wherein, at least one of the first isolation structure and the second isolation structure is a grid structure including at least two isolation layers. In the grid structure, adjacent two isolation layers are separated by a heat dissipation interlayer, and the sum of the thicknesses of all the isolation layers is a thickness setting value that meets the isolation requirements of the active regions under the current process platform.
[0009] Optionally, in the semiconductor device, both the first isolation structure and the second isolation structure are the grid structures.
[0010] Optionally, in the semiconductor device, in the grid structure, each of the isolation layers has the same thickness.
[0011] Optionally, in the semiconductor device, the thickness setting value is 0.5 μm to 2 μm.
[0012] Optionally, in the semiconductor device, the thickness of the heat dissipation interlayer is greater than or equal to 0.5 μm and less than the thickness setting value.
[0013] Optionally, in the semiconductor device, the material of the isolation layer includes silicon oxide.
[0014] Optionally, in the semiconductor device, the materials of the substrate layer and the device layer include silicon, and the material of the heat dissipation interlayer is the same as the materials of the substrate layer and the device layer.
[0015] The present invention also provides a method for manufacturing a semiconductor device, including:
[0016] Forming a first isolation structure and a device layer stacked in sequence from bottom to top on the surface of the substrate layer, where the device layer has an active region;
[0017] Etching the device layer to form a trench surrounding the active region, and filling the trench with an isolation material to form a second isolation structure;
[0018] Wherein, at least one of the first isolation structure and the second isolation structure is a grid structure including at least two isolation layers. In the grid structure, adjacent two isolation layers are separated by a heat dissipation interlayer, and the sum of the thicknesses of all the isolation layers is the thickness setting value that meets the isolation requirement of the active region under the current process platform.
[0019] Optionally, in the method for manufacturing the semiconductor device, the first isolation structure is the grid structure, and the method for forming the first isolation structure includes:
[0020] Providing an intermediate layer, forming a first buried oxide layer on the surface of one of the intermediate layer and the substrate layer, and bonding the intermediate layer and the substrate layer together. The intermediate layer and the substrate layer are isolated by the first buried oxide layer, and,
[0021] Forming a second buried oxide layer on the surface of one of the device layer and the intermediate layer, and bonding the intermediate layer and the device layer together. The intermediate layer and the device layer are isolated by the second buried oxide layer;
[0022] Wherein, the first buried oxide layer and the second buried oxide layer respectively constitute the two isolation layers of the first isolation structure, and the intermediate layer constitutes the heat dissipation interlayer for separating the two isolation layers of the first isolation structure.
[0023] Optionally, in the method for manufacturing the semiconductor device, the second isolation structure is the grid structure, and the method for forming the second isolation structure includes:
[0024] Etch the device layer to obtain at least two concentrically distributed grooves, and fill each groove with an isolation material to obtain the second isolation structure including at least two layers of the isolation layer. The device layer that is not etched away between adjacent grooves forms the heat dissipation interlayer that separates the two layers of the isolation layer of the second isolation structure.
[0025] In summary, for the semiconductor device and its manufacturing method provided by the present invention, a grid-type isolation structure is used to isolate the active region. Compared with the non-grid-type isolation structure, the total thickness of the grid-type isolation structure remains unchanged. However, since the isolation layers of the grid-type isolation structure are thermally conductive through materials with better thermal conductivity, the device has better heat dissipation performance while ensuring the isolation effect remains unchanged. Description of the Drawings
[0026] Figure 1 is a schematic structural diagram of a traditional SOI;
[0027] Figures 2 to 4 is a schematic structural diagram of the device corresponding to each step in the manufacturing process of the semiconductor device provided by the embodiment of the present invention;
[0028] Figure 5 is a simulation comparison diagram of the internal temperature of the semiconductor device provided by the embodiment of the present invention and the traditional SOI in the working state;
[0029] Among them, the descriptions of each reference numeral are as follows:
[0030] 100 - silicon substrate; 200 - top silicon; 300 - buried oxide layer; 400 - trench isolation structure; 500 - active region;
[0031] 10 - substrate layer; 20 - first isolation structure; 30 - device layer; 40 - second isolation structure;
[0032] 21 - first buried oxide layer; 22 - intermediate layer; 23 - second buried oxide layer;
[0033] 31 - active region. Detailed Embodiments
[0034] The technical personnel of the present application have found that the reason for the poor heat dissipation performance of traditional SOI is as follows:
[0035] The buried oxide layer at the bottom of the active region of traditional SOI is used as an embedded isolation structure. This embedded isolation structure and the trench isolation structure jointly surround the active region. Generally, the materials of the embedded isolation structure and the trench isolation structure are silicon oxide, and the thermal conductivity is poor. Therefore, traditional SOI has the problem of poor heat dissipation performance.
[0036] In view of this, the present invention aims to isolate the active region by using a grid-type isolation structure, so as to ensure that the device has better heat dissipation performance while maintaining the isolation effect unchanged.
[0037] The following further elaborates on the semiconductor device and its manufacturing method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes use different scales. It should be recognized that relative terms such as "above", "below", "top", "bottom", etc. shown in the accompanying drawings can be used to describe the relationships between various elements with respect to each other. These relative terms are intended to cover different orientations of the elements other than the orientations depicted in the accompanying drawings. For example, if the device is inverted relative to the view in the accompanying drawing, then an element described as "above" another element will now be below that element. It should also be understood that unless otherwise specifically stated or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship between each component, element, step, etc.
[0038] As Figure 4 shown, an embodiment of the present invention provides a semiconductor device, and the semiconductor device includes:
[0039] A substrate layer 10, a first isolation structure 20, and a device layer 30 stacked in sequence from bottom to top, the device layer 30 having an active region 31; and,
[0040] A second isolation structure 40, the second isolation structure 40 being disposed around the active region 31 within the device layer 30;
[0041] Wherein, at least one of the first isolation structure 20 and the second isolation structure 40 is a grid structure including at least two isolation layers. In the grid structure, adjacent two isolation layers are separated by a heat dissipation interlayer, and the sum of the thicknesses of all the isolation layers is a thickness setting value that meets the isolation requirements of the active region 31 under the current process platform.
[0042] It can be understood that under different process platforms, to meet the isolation requirements for the active region 31, the thickness requirements for the buried isolation structure and the trench isolation structure are not the same. Therefore, the thickness setting value described in this embodiment is determined by the process platform applied and will change with the change of the process platform. Compared with the shallow trench isolation structure of the traditional SOI, for the semiconductor device provided in the embodiment of the present invention, only the isolation structure surrounding the active region 31 changes from the traditional single layer to at least two layers, while the thickness does not change. For example, if under the current process platform, to ensure the isolation effect, the thickness setting value is 10 μm, then for the semiconductor device provided in the embodiment of the present invention, the total thickness of all the isolation layers of the first isolation structure 20 designed as a grid structure is 10 μm. If the second isolation structure 40 is designed as a grid structure, then similarly, the total thickness of all the isolation layers of the second isolation structure 40 is 10 μm.
[0043] Since the semiconductor device provided in the embodiment of the present invention uses a grid-type isolation structure to isolate the active region 31, compared with the non-grid-type isolation structure, the total thickness of the grid-type isolation structure remains unchanged. However, since the isolation layers of the grid-type isolation structure conduct heat through materials with better thermal conductivity, therefore, while ensuring the same isolation effect, the device has better heat dissipation performance.
[0044] Preferably, both the first isolation structure 20 and the second isolation structure 40 are grid structures. In this way, the heat dissipation performance at the bottom and side of the active region 31 of the device is improved. Figure 4 As shown, it is schematically shown with both the first isolation structure 20 and the second isolation structure 40 being grid structures. In some other embodiments, only one of the first isolation structure 20 and the second isolation structure 40 can be a grid structure, and the other remains a single-layer structure design.
[0045] The manufacturing method of the semiconductor device provided in this embodiment is described below. Through the description of the manufacturing method, the structural features of the first isolation structure 20 and the second isolation structure 40 will also be clearer.
[0046] First, please refer to Figure 3 and in combination with Figure 4 , perform the steps: provide a substrate layer 10, and form a first isolation structure 20 and a device layer 30 stacked in sequence on the substrate layer 10, and the active region 31 is provided in the device layer 30.
[0047] The position of the active region 31 is defined by the second isolation structure 40 formed subsequently. Therefore, Figure 3 the active region 31 is schematically shown in Figure 4 .
[0048] Preferably, the first isolation structure 20 is formed by a multi-bonding process, specifically including:
[0049] As Figure 2 shown, provide an intermediate layer 22, form a first buried oxide layer 21 on the surface of one of the intermediate layer 22 and the substrate layer 10, and bond the intermediate layer 22 and the substrate layer 10 together. The intermediate layer 22 and the substrate layer 10 are isolated by the first buried oxide layer 21. And, as Figure 3 shown, form a second buried oxide layer 23 on the surface of one of the device layer 30 and the intermediate layer 22, and bond the intermediate layer 22 and the device layer 30 together. The intermediate layer 22 and the device layer 30 are isolated by the second buried oxide layer 23; wherein, the first buried oxide layer 21 and the second buried oxide layer 23 respectively constitute two isolation layers of the first isolation structure 20, and the intermediate layer 22 constitutes the heat dissipation interlayer for separating the two isolation layers of the first isolation structure 20.
[0050] That is, in this embodiment, the substrate layer 10, the intermediate layer 22, and the device layer 30 may be wafer chips. The two are bonded together by a bonding technology, and are respectively isolated from each other by the first buried oxide layer 21 and the second buried oxide layer 23. The first buried oxide layer 21 and the second buried oxide layer 23 together constitute the first isolation structure 20, and the wafer chip located between the first buried oxide layer 21 and the second buried oxide layer 23 constitutes the heat dissipation interlayer.
[0051] As an example, in this embodiment, the substrate layer 10, the intermediate layer 22, and the device layer 30 are all silicon wafers, and the first buried oxide layer 21 and the second buried oxide layer 23 are oxide silicon layers. The thermal conductivity of silicon is stronger than that of oxide silicon. Therefore, when the thickness of the oxide silicon layer is the same, by designing the oxide silicon layer into a grid structure and separating each grid layer by a silicon layer, the thermal conductivity can be improved.
[0052] Adopting the bonding technology can reduce the process difficulty of forming a stacked structure including the substrate layer 10, the first buried oxide layer 21, the intermediate layer 22, the second buried oxide layer 23, and the device layer 30. This bonding technology may specifically be the smart-cut technology. The stacked structure can be formed by two smart-cut technologies, and the thickness of the intermediate layer 22 can be better controlled through the smart-cut technology. However, adopting the bonding technology does not constitute a limitation to this application. In another embodiment, other processes capable of forming this stacked structure are within the protection scope of this application. The smart-cut technology includes process steps such as hydrogen ion implantation, wafer bonding, peeling and heat treatment, and surface treatment, which are well known to those skilled in the art and will not be elaborated here.
[0053] In addition, in another embodiment, if other materials such as silicon germanium are used for the substrate layer 10, the intermediate layer 22, and the device layer 30, and other materials such as silicon nitride are used for the first buried oxide layer 21 and the second buried oxide layer 23, designing the first isolation structure 20 as a grid structure can also achieve the effect of improving the heat dissipation performance. Therefore, this application does not limit the materials of the substrate layer 10, the intermediate layer 22, the device layer 30, and the first isolation structure 20. When the thermal conductivity of the material of the substrate layer 10 / the intermediate layer 22 / the device layer 30 is better than that of the material of the first isolation structure 20, the grid-shaped first isolation structure 20 can play a role in improving the heat dissipation effect.
[0054] As mentioned above, the thickness of the isolation structure is related to the process platform used. In the currently common process platforms, in order to meet the isolation effect, the value of the thickness setting is 0.5 μm to 2 μm, for example, it can be 0.5 μm, 1 μm, 2 μm, etc. And in order to play a good role in improving the heat dissipation effect, the thickness of the heat dissipation interlayer is greater than or equal to 0.5 μm and less than the total thickness of all the isolation layers of the first isolation structure 20 (that is, the thickness setting value). For example, when the total thickness of all the isolation layers of the first isolation structure 20 is 1 μm, the thickness of the heat dissipation interlayer does not exceed 1 μm. Additionally, preferably, each isolation layer of the first isolation structure 20 has the same thickness so that heat can be transferred better. For example, if the total thickness of all the isolation layers of the first isolation structure 20 is 1 μm, the thickness of each isolation layer is 0.5 μm.
[0055] Then, as Figure 4 shown, perform the steps of: etching the device layer 30 to form trenches surrounding the active region 31, and filling the trenches with an isolation material to form a second isolation structure 40.
[0056] Preferably, the method for forming the second isolation structure 40 includes:
[0057] etching the device layer 30 to obtain at least two concentrically distributed trenches, and filling each trench with an isolation material to obtain the second isolation structure 40 including at least two isolation layers, and the device layer 30 that is not etched away between adjacent trenches forms the heat dissipation interlayer.
[0058] Through this method, the thickness of each isolation layer of the second isolation structure 40 and the thickness of the heat dissipation interlayer can be accurately controlled. In some other embodiments, trenches with a larger width can also be formed by etching, and then isolation layers are deposited on the sidewalls of the trenches, and the trenches are filled with isolation materials. Optionally, the isolation material is silicon oxide.
[0059] Preferably, all the trenches have the same trench width, so that the isolation layers filled in each trench have the same thickness. To meet the isolation effect, the sum of the trench widths of all the trenches, that is, the total thickness of all the isolation layers of the first isolation structure 20, is 0.5 μm to 2 μm, for example, it can be 0.5 μm, 1 μm, 2 μm, etc. To play a good role in improving the heat dissipation effect, the thickness of the heat dissipation interlayer is greater than or equal to 0.5 μm and less than the total thickness of all the isolation layers of the grid structure. For example, if the total thickness of all the grid layers of the first isolation structure 20 is 1 μm, when forming the trenches by etching, by making the thickness of the active region 31 that is not etched between two adjacent trenches not exceed 1 μm, so that the thickness of the heat dissipation interlayer does not exceed 1 μm.
[0060] Optionally, when etching the device layer 30 to form the trenches, the etching can stop on the surface of the first isolation structure 20. In this way, after filling the trenches with insulating materials to form the second isolation structure 40 subsequently, the second isolation structure 40 is connected to the upper isolation layer (corresponding to the second buried oxide layer 23) of the first isolation structure 20; or, when etching the device layer 30 to form the trenches, after etching through the device layer 30, further etch downward and stop on the surface of the lower isolation layer (corresponding to the first buried oxide layer 21) of the first isolation structure 20. In this way, after filling the trenches with insulating materials to form the second isolation structure 40 subsequently, the second isolation structure 40 is connected to the lower isolation layer of the first isolation structure 20. Figure 4 As shown, it is a schematic illustration of the latter implementation manner.
[0061] In addition, after forming the second isolation structure 40, the process steps of manufacturing transistors and other active devices can be continued. The subsequent process steps are well-known to those skilled in the art and will not be elaborated here.
[0062] The technical personnel of the present application have conducted electrical performance simulation comparisons between the semiconductor device provided by the embodiments of the present invention and the traditional SOI. The simulation results are shown in Table 1 as follows:
[0063] Table 1
[0064] BV (V) RSP (mΩ·mm) Prior art 152 272 This application 153 274
[0065] As can be seen from Table 1, after improvement, the electrical performance of the semiconductor device provided by the embodiment of the present invention is basically the same as that of the traditional SOI. Thus, it can be shown that the improvement proposed in this application will not affect the electrical performance of the device.
[0066] Figure 5 This is a simulation comparison diagram of the internal temperature of the semiconductor device provided by the embodiment of the present invention and the traditional SOI under the working state. As can be seen from Figure 5 it that, under the working state of the semiconductor device provided by the embodiment of the present invention, the temperature of the active region is 375K, while the temperature of the active region of the traditional SOI under the working state is 393K. Thus, it can be seen that, without changing the total thickness, splitting the isolation structure surrounding the active region from a single layer into multiple layers can improve the heat dissipation performance of the active region of the device.
[0067] In summary, for the semiconductor device and its manufacturing method provided by the present invention, a grid-type isolation structure is used to isolate the active region. Compared with the non-grid-type isolation structure, the total thickness of the grid-type isolation structure remains unchanged. However, since the isolation layers of the grid-type isolation structure are thermally conductive through materials with better thermal conductivity, the device has better heat dissipation performance while ensuring the same isolation effect.
[0068] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes: a substrate layer, a first isolation structure, and a device layer stacked in sequence from bottom to top, the device layer having an active region; and, a second isolation structure disposed in the device layer around the active region; wherein at least one of the first isolation structure and the second isolation structure is a grid structure including at least two isolation layers, and in the grid structure, adjacent two of the isolation layers are separated by a heat dissipation interlayer, and the sum of the thicknesses of all the isolation layers is a thickness set value that meets the isolation requirement of the active region under the current process platform.
2. The semiconductor device according to claim 1, wherein, Both the first isolation structure and the second isolation structure are the grid structure.
3. The semiconductor device according to claim 1, characterized in that, In the grid structure, each of the isolation layers has the same thickness.
4. The semiconductor device according to claim 1, characterized in that, The thickness set value is 0.5 μm to 2 μm.
5. The semiconductor device according to claim 1, characterized in that, The thickness of the heat dissipation interlayer is greater than or equal to 0.5 μm and less than the thickness set value.
6. The semiconductor device according to claim 1, wherein The material of the isolation layer includes silicon oxide.
7. The semiconductor device according to claim 1, characterized in that, The materials of the substrate layer and the device layer include silicon, and the material of the heat dissipation interlayer is the same as the materials of the substrate layer and the device layer.
8. A method for manufacturing a semiconductor device, characterized in that, including: forming a first isolation structure and a device layer stacked in sequence from bottom to top on the surface of the substrate layer, the device layer having an active region; etching the device layer to form a trench around the active region, and filling the trench with an isolation material to form a second isolation structure; wherein at least one of the first isolation structure and the second isolation structure is a grid structure including at least two isolation layers, and in the grid structure, adjacent two of the isolation layers are separated by a heat dissipation interlayer, and the sum of the thicknesses of all the isolation layers is a thickness set value that meets the isolation requirement of the active region under the current process platform.
9. The manufacturing method of the semiconductor device according to claim 8, characterized in that, The first isolation structure is the grid structure, and the method for forming the first isolation structure includes: providing an intermediate layer, forming a first buried oxide layer on the surface of one of the intermediate layer and the substrate layer, and bonding the intermediate layer and the substrate layer together, and the intermediate layer and the substrate layer are isolated by the first buried oxide layer, and, forming a second buried oxide layer on the surface of one of the device layer and the intermediate layer, and bonding the intermediate layer and the device layer together, and the intermediate layer and the device layer are isolated by the second buried oxide layer; wherein the first buried oxide layer and the second buried oxide layer respectively constitute two of the isolation layers of the first isolation structure, and the intermediate layer constitutes the heat dissipation interlayer for separating the two isolation layers of the first isolation structure.
10. The manufacturing method of the semiconductor device according to claim 8, characterized in that, The second isolation structure is the grid structure, and the method for forming the second isolation structure includes: etching the device layer to obtain at least two concentrically distributed trenches, and filling each trench with an isolation material to obtain the second isolation structure including at least two isolation layers, and the device layer that is not etched away between adjacent trenches constitutes the heat dissipation interlayer for separating the two isolation layers of the second isolation structure.