Array substrate, manufacturing method thereof and display panel

Abstract

The invention is applicable to the technical field of display equipment, and provides an array substrate, a manufacturing method thereof and a display panel, the array substrate comprises a substrate and a plurality of thin film transistors, the thin film transistors are arranged on the substrate at intervals, each thin film transistor comprises a semiconductor layer, a bottom gate layer and a top gate layer, the semiconductor layer comprises a lower-layer semiconductor and an upper-layer semiconductor which are stacked, the mobility of the lower-layer semiconductor and the mobility of the upper-layer semiconductor are different, the bottom gate layer is arranged on the side, close to the substrate, of the lower-layer semiconductor, the top gate layer is arranged on the side, away from the substrate, of the upper-layer semiconductor, and the thin film transistor meets the condition that L0 is larger than L2 and smaller than L1; or L1 < L0 < L2. According to the invention, the advantages of a high-mobility semiconductor can be fully utilized, a narrow frame can be realized, the refresh rate can be improved, the advantages of a low-mobility semiconductor can be utilized, a large sub-threshold swing can be realized, and the requirement of gray scale expansion is considered.

Description

Technical Field

[0001] This application belongs to the technical field of display devices, and particularly relates to an array substrate, a manufacturing method thereof, and a display panel. Background Art

[0002] With the development of technology, the application of oxide thin-film transistors has gradually matured, becoming the preferred choice in large-size display products and having great commercial potential.

[0003] However, in current display products using oxide thin-film transistors, it is difficult to meet the requirements of the gray-scale expansion of the screen while satisfying the narrow border and refresh rate of the screen. Summary of the Invention

[0004] In view of this, embodiments of this application provide an array substrate, a manufacturing method thereof, and a display panel to solve the problem that in current display products using oxide thin-film transistors, it is difficult to meet the requirements of the gray-scale expansion of the screen while satisfying the narrow border and refresh rate of the screen.

[0005] A first aspect of embodiments of this application provides an array substrate, including: a substrate and a plurality of thin-film transistors, each of the thin-film transistors being disposed on the substrate at intervals from each other. The thin-film transistor includes a semiconductor layer, a bottom gate layer, and a top gate layer. The bottom gate layer is disposed on a side of the semiconductor layer close to the substrate, and the top gate layer is disposed on a side of the semiconductor layer away from the substrate. The semiconductor layer includes a lower semiconductor and an upper semiconductor stacked, and the mobilities of the lower semiconductor and the upper semiconductor are different. The bottom gate layer is disposed on a side of the lower semiconductor close to the substrate, and the top gate layer is disposed on a side of the upper semiconductor facing away from the substrate. The thin-film transistor satisfies: L2 < L0 < L1; or L1 < L0 < L2; where L1 is the thickness of the lower semiconductor in a direction perpendicular to the plane of the substrate, L2 is the thickness of the upper semiconductor in a direction perpendicular to the surface of the substrate, and L0 is the Debye length of the thin-film transistor.

[0006] The above-mentioned array substrate is configured such that the semiconductor layer of the thin-film transistor includes a lower semiconductor and an upper semiconductor, and the mobilities of the lower semiconductor and the upper semiconductor are different. Since the farthest electric field depth that the field effect of the thin-film transistor can reach is the Debye length of the thin-film transistor, and the portion of the semiconductor layer beyond this depth range cannot be induced by the field effect. Therefore, while making the thickness L2 of the upper semiconductor in the direction perpendicular to the substrate surface less than the Debye length L0 of the thin-film transistor and also less than the thickness L1 of the lower semiconductor in the direction perpendicular to the substrate plane, at this time, the field effect of the top gate layer can induce both the upper semiconductor and the lower semiconductor, while the field effect of the bottom gate layer can only induce the lower semiconductor. By reasonably setting the use or switching of the top gate layer and the bottom gate layer, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to achieving a narrow border of the product and increasing the refresh rate. At the same time, it is also possible to utilize the advantages of the semiconductor with low mobility, making it have a large subthreshold swing and taking into account the requirements of gray-scale expansion. Or making the thickness L1 of the lower semiconductor in the direction perpendicular to the substrate plane less than the Debye length L0 of the thin-film transistor and also less than the thickness L2 of the upper semiconductor in the direction perpendicular to the substrate surface. At this time, the field effect of the top gate layer can only induce the upper semiconductor, while the field effect of the bottom gate layer can induce both the upper semiconductor and the lower semiconductor. By reasonably setting the use or switching of the top gate layer and the bottom gate layer, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to achieving a narrow border of the product and increasing the refresh rate. At the same time, it is also possible to utilize the advantages of the semiconductor with low mobility, making it have a large subthreshold swing and taking into account the requirements of gray-scale expansion.

[0007] In one embodiment, the array substrate has a display area. The thin-film transistor includes a first transistor located in the display area. The first transistor further includes a first source electrode and a first drain electrode. The first source electrode and the first drain electrode are provided on the side of the top gate layer of the first transistor facing away from the substrate. The first source electrode and the first drain electrode are electrically connected to the semiconductor layer of the first transistor respectively, and the top gate layer of the first transistor is electrically connected to the first source electrode. With such a setting, after the top gate layer of the first transistor is electrically connected to the first source electrode, the top gate layer becomes ineffective, and the first transistor only adopts the single-channel structure of the bottom gate layer.

[0008] In one embodiment, the thin film transistor further includes a first gate insulating layer and a second gate insulating layer. The first gate insulating layer is disposed between the bottom gate layer and the semiconductor layer, and the second gate insulating layer is disposed between the semiconductor layer and the top gate layer. The thin film transistor further satisfies: L4 < L3; where L3 is the thickness of the first gate insulating layer in a direction perpendicular to the plane of the substrate, and L4 is the thickness of the second gate insulating layer in a direction perpendicular to the surface of the substrate. Preferably, the thin film transistor further satisfies: 300 nm ≤ L3 ≤ 500 nm; and / or 90 nm ≤ L4 ≤ 150 nm. With such a setting, since the thickness of the second gate insulating layer in the direction perpendicular to the surface of the substrate is relatively thin, the subthreshold swing can be reduced in the single-channel structure with the top gate layer, which is beneficial to improving the turn-on speed of the thin film transistor device and ensuring the rapid writing of data.

[0009] In one embodiment, the array substrate has a display area, and the thin film transistor includes a second transistor located in the display area. The second transistor further includes a second source electrode and a second drain electrode. The second source electrode and the second drain electrode are disposed on a side of the top gate layer of the second transistor facing away from the substrate. The second source electrode and the second drain electrode are electrically connected to the semiconductor layer of the second transistor respectively, and the bottom gate layer of the second transistor is electrically connected to the second source electrode. With such a setting, after the bottom gate layer of the second transistor is electrically connected to the second source electrode, the bottom gate layer becomes ineffective, and the second transistor only adopts a single-channel structure with the top gate layer.

[0010] In one embodiment, the array substrate has a non-display area, and the thin film transistor includes a third transistor located in the non-display area. The third transistor further includes a third source electrode and a third drain electrode. The third source electrode and the third drain electrode are disposed on a side of the top gate layer of the third transistor facing away from the substrate. The third source electrode and the third drain electrode are electrically connected to the semiconductor layer of the third transistor respectively, and the top gate layer of the third transistor is electrically connected to the bottom gate layer of the third transistor. With such a setting, after the top gate layer of the third transistor is electrically connected to the bottom gate layer of the third transistor, the third transistor adopts a stacked double-gate structure, which can make full use of the advantage of high mobility to achieve the mobility improvement of the double channel, and is beneficial to realizing the narrow border of the product and improving the refresh rate.

[0011] In one embodiment, the mobilities of the lower-layer semiconductor and the upper-layer semiconductor are different. Preferably, the thin film transistor further satisfies: m1 < m2; where m1 is the mobility of the lower-layer semiconductor and m2 is the mobility of the upper-layer semiconductor. Preferably, the thin film transistor further satisfies: 8 cm 2 / V·s ≤ m1 ≤ 15 cm 2 / V·s; and / or m2 ≥ 20 cm 2This design, where the lower semiconductor has relatively low mobility and the upper semiconductor has relatively high mobility, can fully utilize the high mobility of the upper semiconductor in a single-channel structure using a top gate layer, and the low mobility of the lower semiconductor in a single-channel structure using a bottom gate layer. This allows for a larger subthreshold swing, while also meeting the requirements for grayscale development.

[0012] In one embodiment, the lower semiconductor layer is made of at least one of indium gallium zinc oxide, indium hafnium zinc oxide, indium aluminum zinc oxide, and indium zirconium zinc oxide; and the upper semiconductor layer is made of at least one of indium gallium oxide, indium gallium titanium oxide, indium zinc oxide, and indium titanium zirconium zinc oxide. Using these materials to manufacture the lower and upper semiconductor layers can meet their respective mobility requirements, resulting in improved performance.

[0013] A second aspect of an embodiment of the present application provides an array substrate, comprising: a substrate and a plurality of thin film transistors, each of the thin film transistors being spaced apart from each other and arranged on the substrate, the thin film transistor comprising a semiconductor layer, a bottom gate layer and a top gate layer, the semiconductor layer comprising a lower semiconductor, a middle semiconductor and an upper semiconductor arranged in a stacked manner, the lower semiconductor and the middle semiconductor having different mobilities, the upper semiconductor and the middle semiconductor having different mobilities, the bottom gate layer being arranged on a side of the lower semiconductor close to the substrate, the top gate layer being arranged on a side of the upper semiconductor away from the substrate, the thin film transistor satisfying: L2<L0<L1; or L1<L0<L2; wherein L1 is the thickness of the lower semiconductor in a direction perpendicular to the substrate plane, L2 is the thickness of the upper semiconductor in a direction perpendicular to the substrate surface, and L0 is the Debye length of the thin film transistor.

[0014] The above-mentioned array substrate is configured such that the semiconductor layer of the thin-film transistor includes a lower-layer semiconductor, a middle-layer semiconductor, and an upper-layer semiconductor. The mobilities of the lower-layer semiconductor and the middle-layer semiconductor are different, and the mobilities of the upper-layer semiconductor and the middle-layer semiconductor are different. Since the maximum electric field depth that can be achieved by the field effect of the thin-film transistor is the Debye length of the thin-film transistor, and the portion of the semiconductor layer beyond this depth range cannot be induced by the field effect. Therefore, simultaneously, the thickness L2 of the upper-layer semiconductor in the direction perpendicular to the substrate surface is made less than the Debye length L0 of the thin-film transistor and also less than the thickness L1 of the lower-layer semiconductor in the direction perpendicular to the substrate plane. At this time, the field effect of the top gate layer can induce both the upper-layer semiconductor and the middle-layer semiconductor, while the field effect of the bottom gate layer can only induce the lower-layer semiconductor. By reasonably setting the use or switching of the top gate layer and the bottom gate layer, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to achieving a narrow border and increasing the refresh rate of the product. At the same time, it is also possible to utilize the advantages of the semiconductor with low mobility, so that it has a large subthreshold swing and meets the requirements of gray-scale expansion. Or the thickness L1 of the lower-layer semiconductor in the direction perpendicular to the substrate plane is made less than the Debye length L0 of the thin-film transistor and also less than the thickness L2 of the upper-layer semiconductor in the direction perpendicular to the substrate surface. At this time, the field effect of the top gate layer can only induce the upper-layer semiconductor, while the field effect of the bottom gate layer can induce both the lower-layer semiconductor and the middle-layer semiconductor. By reasonably setting the use or switching of the top gate layer and the bottom gate layer, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to achieving a narrow border and increasing the refresh rate of the product. At the same time, it is also possible to utilize the advantages of the semiconductor with low mobility, so that it has a large subthreshold swing and meets the requirements of gray-scale expansion.

[0015] The third aspect of the embodiments of the present application provides a method for manufacturing an array substrate, including: sequentially forming a bottom gate layer, a lower-layer semiconductor material layer, an upper-layer semiconductor material layer, and a top gate layer on a substrate, where the mobilities of the lower-layer semiconductor material layer and the upper-layer semiconductor material layer are different; performing ion implantation on the lower-layer semiconductor material layer and the upper-layer semiconductor material layer to form a semiconductor layer, the semiconductor layer including a lower-layer semiconductor and an upper-layer semiconductor arranged in a stacked manner; forming a source electrode and a drain electrode on a side of the top gate layer facing away from the substrate, and the source electrode and the drain electrode are electrically connected to the semiconductor layer respectively.

[0016] The display panel manufactured by the above manufacturing method can make full use of the advantages of the semiconductor with high mobility, which is beneficial to achieving a narrow border and increasing the refresh rate of the product. At the same time, it is also possible to utilize the advantages of the semiconductor with low mobility, so that it has a large subthreshold swing and meets the requirements of gray-scale expansion.

[0017] The fourth aspect of the embodiments of the present application provides a display panel, including the array substrate as described in the first aspect or the second aspect.

[0018] It can be understood that for the beneficial effects of the fourth aspect above, reference can be made to the relevant descriptions of the first aspect and the second aspect above, and details are not repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 is a cross-sectional view of the overall structure of an array substrate provided by an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of a connection structure in an array substrate provided by an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of a connection structure in an array substrate provided by another embodiment of the present application;

[0023] Figure 4 is a schematic diagram of a connection structure in an array substrate provided by yet another embodiment of the present application;

[0024] Figure 5 is a cross-sectional view of the overall structure of an array substrate provided by another embodiment of the present application;

[0025] Figure 6 is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present application;

[0026] Figure 7 is a cross-sectional view of an intermediate state during the manufacturing process of an array substrate provided by an embodiment of the present application;

[0027] Figure 8 is a cross-sectional view of an intermediate state during the manufacturing process of an array substrate provided by another embodiment of the present application;

[0028] Figure 9 is a cross-sectional view of an intermediate state during the manufacturing process of an array substrate provided by still another embodiment of the present application.

[0029] Reference Numerals in the Drawings:

[0030] 100. Array substrate;

[0031] 110. Substrate;

[0032] 120. Thin-film transistor, 120A. First transistor, 120B. Second transistor, 120C. Third transistor, 121. Semiconductor layer, 1211. Lower-layer semiconductor, 1212. Upper-layer semiconductor, 1213. Middle-layer semiconductor, 1214. Conductive region, 122. Bottom gate layer, 123. Top gate layer, 124A. First source electrode, 125A. First drain electrode, 124B. Second source electrode, 125B. Second drain electrode, 124C. Third source electrode, 125C. Third drain electrode, 126. First gate insulating layer, 127. Second gate insulating layer, 128. Lower-layer semiconductor material layer, 129. Upper-layer semiconductor material layer;

[0033] AA. Display area, NA. Non-display area. Detailed implementation manners

[0034] In the following description, specific details such as specific system architectures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0035] It should also be understood that the term "and / or" used in the specification and appended claims of the present application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0036] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0037] It should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0038] In addition, in the description of the specification and appended claims of the present application, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0039] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that a specific feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having", and their variants all mean "including but not limited to", unless otherwise specifically emphasized. "A plurality" means two or more.

[0040] In display products using oxide thin-film transistors in the related art, since it is difficult for oxide thin-film transistors to balance mobility (Mob) and subthreshold swing (SS), when developing oxide thin-film transistor devices using high-mobility materials, narrow bezels and high refresh rates of the display product screen body can be achieved, but its subthreshold swing is difficult to meet the requirements of gray-scale expansion of the display product screen body. When developing oxide thin-film transistor devices using low-mobility materials, its subthreshold swing is large, and it is difficult to meet the requirements of narrow bezels and high refresh rates of the display product screen body. Therefore, how to achieve narrow bezels and a refresh rate of the all-oxide product screen body while meeting the requirements of gray-scale expansion of the display product screen body has become a hot topic and a difficult problem in the industry.

[0041] To at least partially solve the above problems, refer to Figures 1 to 4 As shown, an embodiment of this application provides an array substrate 100, and the array substrate 100 includes: a substrate 110 and a plurality of thin-film transistors 120.

[0042] Among them, the thin-film transistors 120 are arranged on the substrate 110 at intervals from each other. The substrate 110 can be a rigid substrate made of materials such as transparent or opaque glass, quartz, or metal, or a flexible substrate made of organic materials such as polyimide, polyethylene, or polyethylene terephthalate, and can be flexibly selected according to actual usage requirements. The array substrate 100 may also include film layers such as a buffer layer and an insulating layer that can perform different functional roles. Here, it is only an example. In actual embodiments, the array substrate 100 may also include other similar more film layers, which are not limited herein.

[0043] The thin film transistor 120 includes a semiconductor layer 121, a bottom gate layer 122, and a top gate layer 123. The bottom gate layer 122 is disposed on one side of the semiconductor layer 121 close to the substrate 110, and the top gate layer 123 is disposed on one side of the semiconductor layer 121 away from the substrate 110. The semiconductor layer 121 includes a lower semiconductor 1211 and an upper semiconductor 1212 which are stacked. The semiconductor layer 121 also has conductorized regions 1214 located on its opposite sides, and the conductorized regions 1214 correspond to the lower semiconductor 1211 and the upper semiconductor 1212. The mobilities of the lower semiconductor 1211 and the upper semiconductor 1212 are different. The bottom gate layer 122 is disposed on one side of the lower semiconductor 1211 close to the substrate 110, and the top gate layer 123 is disposed on one side of the upper semiconductor 1212 facing away from the substrate 110.

[0044] Specifically, the lower semiconductor 1211 and the upper semiconductor 1212 can be made of metal oxide. The bottom gate layer 122 and the top gate layer 123 can be selected from any one of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum (Ta), and tungsten (W), or a stack or alloy of these elements. The thin film transistor 120 can also include a source electrode and a drain electrode, and the source electrode and the drain electrode can also be selected from any one of copper (Cu), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum (Ta), and tungsten (W), or a stack or alloy of these elements.

[0045] The mobilities of the lower semiconductor 1211 and the upper semiconductor 1212 are different. Mobility refers to the average drift velocity of carriers generated under a unit electric field strength. It can be that the mobility of the lower semiconductor 1211 is relatively high while the mobility of the upper semiconductor 1212 is relatively low, or the mobility of the lower semiconductor 1211 is relatively low while the mobility of the upper semiconductor 1212 is relatively high, and no limitation is made here.

[0046] The thin film transistor 120 satisfies: L2 < L0 < L1; or L1 < L0 < L2; where L1 is the thickness of the lower semiconductor 1211 in the direction perpendicular to the plane of the substrate 110, L2 is the thickness of the upper semiconductor 1212 in the direction perpendicular to the surface of the substrate 110, and L0 is the Debye length of the thin film transistor 120.

[0047] Since the farthest electric field depth that the field effect of the thin film transistor 120 can reach is the Debye length of the thin film transistor 120, and the part of the semiconductor layer 121 beyond this depth range cannot be induced by the field effect. When L2 < L0 < L1, the field effect of the top gate layer 123 can induce both the upper semiconductor 1212 and the lower semiconductor 1211, while the field effect of the bottom gate layer 122 can only induce the lower semiconductor 1211. When L1 < L0 < L2, the field effect of the top gate layer 123 can only induce the upper semiconductor 1212, while the field effect of the bottom gate layer 122 can induce both the upper semiconductor 1212 and the lower semiconductor 1211. Moreover, due to the different mobilities of the lower semiconductor 1211 and the upper semiconductor 1212, by reasonably setting the use or switching of the top gate layer 123 and the bottom gate layer 122, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to achieving a narrow border and high refresh rate of the product. At the same time, it is also possible to utilize the advantages of the semiconductor with low mobility, which has a large subthreshold swing, to meet the requirements of gray scale expansion, and is also beneficial to improving the device stability of the thin film transistor 120.

[0048] In the array substrate 100 according to the embodiment of the present application, by making the semiconductor layer 121 of the thin-film transistor 120 include a lower-layer semiconductor 1211 and an upper-layer semiconductor 1212, and the mobilities of the lower-layer semiconductor 1211 and the upper-layer semiconductor 1212 are different. Since the farthest electric field depth that the field effect of the thin-film transistor 120 can reach is the Debye length of the thin-film transistor 120, and the part of the semiconductor layer 121 beyond this depth range cannot be induced by the field effect. Therefore, at the same time, making the thickness L2 of the upper-layer semiconductor 1212 in the direction perpendicular to the surface of the substrate 110 less than the Debye length L0 of the thin-film transistor 120 and less than the thickness L1 of the lower-layer semiconductor 1211 in the direction perpendicular to the plane of the substrate 110. At this time, the field effect of the top gate layer 123 can induce both the upper-layer semiconductor 1212 and the lower-layer semiconductor 1211, while the field effect of the bottom gate layer 122 can only induce the lower-layer semiconductor 1211. By reasonably setting the use or switching of the top gate layer 123 and the bottom gate layer 122, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to realizing the narrow border of the product and improving the refresh rate. At the same time, it is also possible to make use of the advantages of the semiconductor with low mobility, so that it has a large subthreshold swing and meets the requirements of gray-scale expansion. Or making the thickness L1 of the lower-layer semiconductor 1211 in the direction perpendicular to the plane of the substrate 110 less than the Debye length L0 of the thin-film transistor 120 and less than the thickness L2 of the upper-layer semiconductor 1212 in the direction perpendicular to the surface of the substrate 110. At this time, the field effect of the top gate layer 123 can only induce the upper-layer semiconductor 1212, while the field effect of the bottom gate layer 122 can induce both the upper-layer semiconductor 1212 and the lower-layer semiconductor 1211. By reasonably setting the use or switching of the top gate layer 123 and the bottom gate layer 122, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to realizing the narrow border of the product and improving the refresh rate. At the same time, it is also possible to make use of the advantages of the semiconductor with low mobility, so that it has a large subthreshold swing and meets the requirements of gray-scale expansion.

[0049] Such as Figure 1 And Figure 2As shown, in some embodiments, optionally, the array substrate 100 has a display area AA. The thin film transistor 120 includes a first transistor 120A located in the display area AA. The first transistor 120A further includes a first source electrode 124A and a first drain electrode 125A. The first source electrode 124A and the first drain electrode 125A are disposed on a side of the top gate layer 123 of the first transistor 120A facing away from the substrate 110. The first source electrode 124A and the first drain electrode 125A are electrically connected to the semiconductor layer 121 of the first transistor 120A respectively. The top gate layer 123 of the first transistor 120A is electrically connected to the first source electrode 124A. With such an arrangement, after the top gate layer 123 of the first transistor 120A is electrically connected to the first source electrode 124A, the top gate layer 123 becomes ineffective, and the first transistor 120A only adopts the single-channel structure of the bottom gate layer 122.

[0050] In Figure 1 and Figure 2 In the embodiments shown, the thickness L2 of the upper semiconductor 1212 in the direction perpendicular to the surface of the substrate 110 is less than the Debye length L0 of the thin film transistor 120 and is also less than the thickness L1 of the lower semiconductor 1211 in the direction perpendicular to the plane of the substrate 110, that is, L2 < L0 < L1. When the mobility of the lower semiconductor 1211 is relatively low and the mobility of the upper semiconductor 1212 is relatively high, the first transistor 120A adopts the single-channel structure of the bottom gate layer 122. A conductive channel is formed between the bottom gate layer 122 and the lower semiconductor 1211, and its subthreshold swing is relatively large, which is beneficial to accurately controlling the output current and thus beneficial to gray scale expansion.

[0051] In the above embodiments, the specific connection manner between the top gate layer 123 and the first source electrode 124A of the first transistor 120A is not limited. In Figure 2 In the embodiments shown, a part of the area of the first source electrode 124A can be connected to the semiconductor layer 121, and at the same time, another part of the area of the first source electrode 124A is connected to the top gate layer 123 of the first transistor 120A.

[0052] Please continue to refer to Figure 1 and Figure 2 , in some embodiments, optionally, the thin film transistor 120 further includes a first gate insulating layer 126 and a second gate insulating layer 127. The first gate insulating layer 126 is disposed between the bottom gate layer 122 and the semiconductor layer 121, and the second gate insulating layer 127 is disposed between the semiconductor layer 121 and the top gate layer 123. The thin film transistor 120 also satisfies: L4 < L3; where L3 is the thickness of the first gate insulating layer 126 in the direction perpendicular to the plane of the substrate 110, and L4 is the thickness of the second gate insulating layer 127 in the direction perpendicular to the surface of the substrate 110.

[0053] Among them, the gate insulating layer is usually required to have a relatively large dielectric constant to ensure that the gate electrode voltage has a strong control ability over the thin film transistor 120 and to ensure the switching speed of the thin film transistor 120. The gate insulating layer can be a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy) layer, or a stacked structure of their combination. With such a setting, since the thickness of the second gate insulating layer 127 in the direction perpendicular to the surface of the substrate 110 is relatively thin, the subthreshold swing can be reduced in the single-channel structure with the top gate layer 123, which is beneficial to improving the turn-on speed of the thin film transistor 120 device and ensuring the rapid writing of data.

[0054] Based on the above embodiments, the thin film transistor 120 further satisfies: 300 nm ≤ L3 ≤ 500 nm; and / or 90 nm ≤ L4 ≤ 150 nm.

[0055] In some specific embodiments, the thickness L3 of the first gate insulating layer 126 in the direction perpendicular to the plane of the substrate 110 can be 300 nm, 310 nm, 375 nm, 400 nm, 434 nm, 500 nm, etc., and the thickness L4 of the second gate insulating layer 127 in the direction perpendicular to the surface of the substrate 110 can be 90 nm, 95 nm, 100 nm, 123 nm, 137 nm, 150 nm, etc. The above are only examples of the thickness L3 of the first gate insulating layer 126 in the direction perpendicular to the plane of the substrate 110 and the thickness L4 of the second gate insulating layer 127 in the direction perpendicular to the surface of the substrate 110. In actual embodiments, the thickness L3 of the first gate insulating layer 126 in the direction perpendicular to the surface of the substrate 110 and the thickness L4 of the second gate insulating layer 127 in the direction perpendicular to the plane of the substrate 110 can also be other thickness values that satisfy the above ranges.

[0056] Please combine Figure 1 and refer to Figure 3 and Figure 4 , based on the above embodiments, optionally, the array substrate 100 has a display area AA, the thin film transistor 120 includes a second transistor 120B located in the display area AA, the second transistor 120B further includes a second source electrode 124B and a second drain electrode 125B, the second source electrode 124B and the second drain electrode 125B are provided on the side of the top gate layer 123 of the second transistor 120B facing away from the substrate 110, the second source electrode 124B and the second drain electrode 125B are respectively electrically connected to the semiconductor layer 121 of the second transistor 120B, and the bottom gate layer 122 of the second transistor 120B is electrically connected to the second source electrode 124B. With such a setting, when the bottom gate layer 122 of the second transistor 120B is electrically connected to the second source electrode 124B, the bottom gate layer 122 can only function as a light-shielding layer and does not play a role in controlling the channel. The second transistor 120B only adopts a single-channel structure with the top gate layer 123.

[0057] In Figure 1 、 Figure 3 and Figure 4 In the embodiments shown, the thickness L2 of the upper semiconductor 1212 in the direction perpendicular to the surface of the substrate 110 is less than the Debye length L0 of the thin film transistor 120 and is also less than the thickness L1 of the lower semiconductor 1211 in the direction perpendicular to the plane of the substrate 110, that is, L2 < L0 < L1. When the mobility of the lower semiconductor 1211 is relatively low and the mobility of the upper semiconductor 1212 is relatively high, the second transistor 120B adopts a single-channel structure of the top gate layer 123, and its subthreshold swing is relatively small, which is beneficial to improving the turn-on speed of the second transistor 120B device and ensuring the rapid writing of data.

[0058] In the above embodiments, the specific connection manner between the bottom gate layer 122 of the second transistor 120B and the second source electrode 124B is not limited. In Figure 3 the embodiment shown, a part of the second source electrode 124B can pass through the semiconductor layer 121 and be connected to both the semiconductor layer 121 and the bottom gate layer 122 of the second transistor 120B at the same time. In Figure 4 the embodiment shown, a part of the second source electrode 124B can be connected to the semiconductor layer 121, and another part of the second source electrode 124B can be connected to the bottom gate layer 122 of the second transistor 120B.

[0059] Please continue to refer to Figures 1 to 4 , in some embodiments, optionally, the array substrate 100 has a non-display area NA. The thin film transistor 120 includes a third transistor 120C located in the non-display area NA. The third transistor 120C further includes a third source electrode 124C and a third drain electrode 125C. The third source electrode 124C and the third drain electrode 125C are disposed on a side of the top gate layer 123 of the third transistor 120C away from the substrate 110. The third source electrode 124C and the third drain electrode 125C are electrically connected to the semiconductor layer 121 of the third transistor 120C respectively. The top gate layer 123 of the third transistor 120C is electrically connected to the bottom gate layer 122 of the third transistor 120C.

[0060] With such an arrangement, after the top gate layer 123 of the third transistor 120C is electrically connected to the bottom gate layer 122 of the third transistor 120C, the third transistor 120C adopts a stacked double-gate structure, which can make full use of the advantages of high mobility, realize the mobility improvement of the double channels, and is beneficial to realizing the narrow border of the product and improving the refresh rate.

[0061] As described above, the mobilities of the lower semiconductor 1211 and the upper semiconductor 1212 are different. It can be that the mobility of the lower semiconductor 1211 is relatively high and the mobility of the upper semiconductor 1212 is relatively low, or the mobility of the lower semiconductor 1211 is relatively low and the mobility of the upper semiconductor 1212 is relatively high. In some embodiments, optionally, the thin film transistor 120 further satisfies: m1 < m2; where m1 is the mobility of the lower semiconductor 1211 and m2 is the mobility of the upper semiconductor 1212.

[0062] With such a design, that is, the mobility of the lower semiconductor 1211 is relatively low and the mobility of the upper semiconductor 1212 is relatively high, the advantage of the high mobility of the upper semiconductor 1212 can be fully utilized in the single-channel structure with the top gate layer 123, and the advantage of the low mobility of the lower semiconductor 1211 can be utilized in the single-channel structure with the bottom gate layer 122, so that it has a relatively large subthreshold swing and meets the requirements of gray scale expansion.

[0063] Based on the above embodiments, the thin film transistor 120 further satisfies: 8 cm 2 / V·s ≤ m1 ≤ 15 cm 2 / V·s; and / or m2 ≥ 20 cm 2 / V·s.

[0064] In some specific embodiments, the mobility m1 of the lower semiconductor 1211 can be 8 cm 2 / V·s, 10 cm 2 / V·s, 11 cm 2 / V·s, 13 cm 2 / V·s, 14 cm 2 / V·s, 15 cm 2 / V·s, etc., and the mobility m2 of the upper semiconductor 1212 can be 20 cm 2 / V·s, 22 cm 2 / V·s, 25 cm 2 / V·s, 31 cm 2 / V·s, 43 cm 2 / V·s, 50 cm 2 / V·s, etc. The above are only examples of the mobility m1 of the lower semiconductor 1211 and the mobility m2 of the upper semiconductor 1212. In actual embodiments, the mobility m1 of the lower semiconductor 1211 and the mobility m2 of the upper semiconductor 1212 can also be other mobility values that satisfy the above ranges.

[0065] As described above, the lower semiconductor 1211 and the upper semiconductor 1212 can be made of metal oxides. In some embodiments, optionally, the material for making the lower semiconductor 1211 includes at least one of indium gallium zinc oxide, indium hafnium zinc oxide, indium aluminum zinc oxide, and indium zirconium zinc oxide. The material for making the upper semiconductor 1212 includes at least one of indium gallium oxide, indium gallium tin oxide, indium zinc oxide, and indium gallium zinc tin oxide.

[0066] By using the above materials to make the lower semiconductor 1211 and the upper semiconductor 1212, their respective mobility requirements can be met, enabling them to have good performance in use.

[0067] Similarly, please refer to Figure 5 , an array substrate 100 is further provided in an embodiment of the present application. The array substrate 100 includes: a substrate 110 and a plurality of thin film transistors 120.

[0068] Among them, the thin film transistors 120 are disposed on the substrate 110 at intervals from each other. The thin film transistor 120 includes a semiconductor layer 121, a bottom gate layer 122, and a top gate layer 123. The semiconductor layer 121 includes a lower semiconductor 1211, a middle semiconductor 1213, and an upper semiconductor 1212 that are stacked. The semiconductor layer 121 also has conductorized regions 1214 located on its opposite sides, and the conductorized regions 1214 correspond to the lower semiconductor 1211, the middle semiconductor 1213, and the upper semiconductor 1212. The mobility of the lower semiconductor 1211 is different from that of the middle semiconductor 1213, and the mobility of the upper semiconductor 1212 is different from that of the middle semiconductor 1213. The bottom gate layer 122 is disposed on the side of the lower semiconductor 1211 close to the substrate 110, and the top gate layer 123 is disposed on the side of the upper semiconductor 1212 facing away from the substrate 110. The thin film transistor 120 satisfies: L2 < L0 < L1; or L1 < L0 < L2; where L1 is the thickness of the lower semiconductor 1211 in the direction perpendicular to the plane of the substrate 110, L2 is the thickness of the upper semiconductor 1212 in the direction perpendicular to the surface of the substrate 110, and L0 is the Debye length of the thin film transistor 120.

[0069] Figure 5 The difference between the shown embodiment and Figures 1 to 4 the shown embodiment is that the semiconductor layer 121 includes a lower semiconductor 1211, a middle semiconductor 1213, and an upper semiconductor 1212 that are stacked. Among them, the mobility of the lower semiconductor 1211 is different from that of the middle semiconductor 1213, and the mobility of the upper semiconductor 1212 is different from that of the middle semiconductor 1213, while the mobility of the lower semiconductor 1211 and the upper semiconductor 1212 can be the same. The working principle and technical effects of the array substrate 100 in this embodiment are similar to those of the array substrate 100 in Figure 1 the shown embodiment, and will not be elaborated here.

[0070] In the array substrate 100 according to the embodiment of the present application, by making the semiconductor layer 121 of the thin film transistor 120 include a lower semiconductor 1211, a middle semiconductor 1213, and an upper semiconductor 1212, the mobility of the lower semiconductor 1211 is different from that of the middle semiconductor 1213, and the mobility of the upper semiconductor 1212 is different from that of the middle semiconductor 1213. Since the farthest electric field depth that the field effect of the thin film transistor 120 can reach is the Debye length of the thin film transistor 120, and the part of the semiconductor layer 121 beyond this depth range cannot be induced by the field effect. Therefore, at the same time, the thickness L2 of the upper semiconductor 1212 in the direction perpendicular to the surface of the substrate 110 is made less than the Debye length L0 of the thin film transistor 120 and less than the thickness L1 of the lower semiconductor 1211 in the direction perpendicular to the plane of the substrate 110. At this time, the field effect of the top gate layer 123 can induce both the upper semiconductor 1212 and the middle semiconductor 1213, while the field effect of the bottom gate layer 122 can only induce the lower semiconductor 1211. By reasonably setting the use or switching of the top gate layer 123 and the bottom gate layer 122, while making full use of the advantages of the semiconductor with high mobility, which is beneficial to realizing the narrow border of the product and improving the refresh rate, the advantages of the semiconductor with low mobility can also be utilized to make it have a large subthreshold swing and meet the requirements of gray scale expansion. Or make the thickness L1 of the lower semiconductor 1211 in the direction perpendicular to the plane of the substrate 110 less than the Debye length L0 of the thin film transistor 120 and less than the thickness L2 of the upper semiconductor 1212 in the direction perpendicular to the surface of the substrate 110. At this time, the field effect of the top gate layer 123 can only induce the upper semiconductor 1212, while the field effect of the bottom gate layer 122 can induce both the lower semiconductor 1211 and the middle semiconductor 1213. By reasonably setting the use or switching of the top gate layer 123 and the bottom gate layer 122, while making full use of the advantages of the semiconductor with high mobility, which is beneficial to realizing the narrow border of the product and improving the refresh rate, the advantages of the semiconductor with low mobility can also be utilized to make it have a large subthreshold swing and meet the requirements of gray scale expansion.

[0071] Please combine Figures 1 to 5 and refer to Figures 6 to 9 , the embodiment of the present application also provides a manufacturing method of the array substrate 100. The manufacturing method includes the following steps:

[0072] S102. Form a bottom gate layer 122, a lower semiconductor material layer 128, an upper semiconductor material layer 129, and a top gate layer 123 on the substrate 110 in sequence, and the mobility of the lower semiconductor material layer 128 is different from that of the upper semiconductor material layer 129.

[0073] The product obtained after step S102 is as Figure 7 shown.

[0074] S104. Ionize and implant the lower semiconductor material layer 128 and the upper semiconductor material layer 129 to form a semiconductor layer 121, where the semiconductor layer 121 includes a lower semiconductor 1211 and an upper semiconductor 1212 arranged in a stacked manner.

[0075] The product obtained after step S104 is as Figure 8 shown. The structures of both the lower semiconductor 1211 and the upper semiconductor 1212 are made by an implanted conductorization process, which can improve the overall uniformity of the device.

[0076] S106. Form a source electrode and a drain electrode on the side of the top gate layer 123 facing away from the substrate 110, and the source electrode and the drain electrode are electrically connected to the semiconductor layer 121 respectively.

[0077] The product obtained after step S106 is as Figure 9 shown. An interlayer insulating layer may be provided on the top gate layer 123, and through holes are provided on the interlayer insulating layer. The source electrode and the drain electrode can be electrically connected to the semiconductor layer 121 respectively by means of the through holes on the interlayer insulating layer.

[0078] The display panel manufactured by the above manufacturing method can make full use of the advantages of the semiconductor with high mobility, which is beneficial to realizing a narrow border and improving the refresh rate of the product. At the same time, it can also utilize the advantages of the semiconductor with low mobility, making it have a large subthreshold swing and meeting the requirements of gray-scale expansion.

[0079] The embodiment of the present application further provides a display panel, including the array substrate 100 in any one of the above embodiments.

[0080] Among them, the display panel may further include a border for carrying the array substrate 100. For the description of the array substrate 100, reference can be made to the above embodiments, and details will not be repeated here.

[0081] Due to the adoption of the array substrate 100 in any of the above embodiments, the display panel according to the embodiment of the present application enables the semiconductor layer 121 of the thin-film transistor 120 to include a lower-layer semiconductor 1211 and an upper-layer semiconductor 1212, and the mobilities of the lower-layer semiconductor 1211 and the upper-layer semiconductor 1212 are different. Since the farthest electric field depth that the field effect of the thin-film transistor 120 can reach is the Debye length of the thin-film transistor 120, and the part of the semiconductor layer 121 beyond this depth range cannot be induced by the field effect. Therefore, while making the thickness L2 of the upper-layer semiconductor 1212 in the direction perpendicular to the surface of the substrate 110 less than the Debye length L0 of the thin-film transistor 120 and also less than the thickness L1 of the lower-layer semiconductor 1211 in the direction perpendicular to the plane of the substrate 110, at this time, the field effect of the top gate layer 123 can induce both the upper-layer semiconductor 1212 and the lower-layer semiconductor 1211, while the field effect of the bottom gate layer 122 can only induce the lower-layer semiconductor 1211. By reasonably setting the use or switching of the top gate layer 123 and the bottom gate layer 122, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to achieving a narrow border and improving the refresh rate of the product. At the same time, it is also possible to utilize the advantages of the semiconductor with low mobility, making it have a large subthreshold swing and taking into account the requirements of gray-scale expansion. Or making the thickness L1 of the lower-layer semiconductor 1211 in the direction perpendicular to the plane of the substrate 110 less than the Debye length L0 of the thin-film transistor 120 and also less than the thickness L2 of the upper-layer semiconductor 1212 in the direction perpendicular to the surface of the substrate 110. At this time, the field effect of the top gate layer 123 can only induce the upper-layer semiconductor 1212, while the field effect of the bottom gate layer 122 can induce both the upper-layer semiconductor 1212 and the lower-layer semiconductor 1211. By reasonably setting the use or switching of the top gate layer 123 and the bottom gate layer 122, it is possible to make full use of the advantages of the semiconductor with high mobility, which is beneficial to achieving a narrow border and improving the refresh rate of the product. At the same time, it is also possible to utilize the advantages of the semiconductor with low mobility, making it have a large subthreshold swing and taking into account the requirements of gray-scale expansion.

[0082] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0083] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that, Including: A substrate (110) and a plurality of thin film transistors (120), each of the thin film transistors (120) being disposed on the substrate (110) at intervals from each other. The thin film transistor (120) includes a semiconductor layer (121), a bottom gate layer (122), and a top gate layer (123). The bottom gate layer (122) is disposed on a side of the semiconductor layer (121) close to the substrate (110), and the top gate layer (123) is disposed on a side of the semiconductor layer (121) away from the substrate (110). The semiconductor layer (121) includes a lower semiconductor (1211) and an upper semiconductor (1212) which are stacked, and the mobilities of the lower semiconductor (1211) and the upper semiconductor (1212) are different. The bottom gate layer (122) is disposed on a side of the lower semiconductor (1211) close to the substrate (110), and the top gate layer (123) is disposed on a side of the upper semiconductor (1212) facing away from the substrate (110). The thin film transistor (120) satisfies: L2 < L0 < L1; or L1 < L0 < L2; wherein, L1 is the thickness of the lower semiconductor (1211) in a direction perpendicular to the plane of the substrate (110), L2 is the thickness of the upper semiconductor (1212) in a direction perpendicular to the surface of the substrate (110), and L0 is the Debye length of the thin film transistor (120).

2. The array substrate according to claim 1, wherein The array substrate (100) has a display area. The thin film transistor (120) includes a first transistor (120A) located in the display area. The first transistor (120A) further includes a first source electrode (124A) and a first drain electrode (125A). The first source electrode (124A) and the first drain electrode (125A) are disposed on a side of the top gate layer (123) of the first transistor (120A) away from the substrate (110). The first source electrode (124A) and the first drain electrode (125A) are electrically connected to the semiconductor layer (121) of the first transistor (120A) respectively, and the top gate layer (123) of the first transistor (120A) is electrically connected to the first source electrode (124A).

3. The array substrate according to claim 1, wherein The thin film transistor (120) further includes a first gate insulating layer (126) and a second gate insulating layer (127). The first gate insulating layer (126) is disposed between the bottom gate layer (122) and the semiconductor layer (121), and the second gate insulating layer (127) is disposed between the semiconductor layer (121) and the top gate layer (123). The thin film transistor (120) further satisfies: L4 < L3; wherein, L3 is the thickness of the first gate insulating layer (126) in a direction perpendicular to the plane of the substrate (110), and L4 is the thickness of the second gate insulating layer (127) in a direction perpendicular to the surface of the substrate (110); Preferably, the thin film transistor (120) further satisfies: 300 nm ≤ L3 ≤ 500 nm; and / or 90 nm ≤ L4 ≤ 150 nm.

4. The array substrate according to claim 1 or 3, characterized in that, The array substrate (100) has a display area. The thin film transistor (120) includes a second transistor (120B) located in the display area. The second transistor (120B) further includes a second source electrode (124B) and a second drain electrode (125B). The second source electrode (124B) and the second drain electrode (125B) are disposed on a side of the top gate layer (123) of the second transistor (120B) facing away from the substrate (110). The second source electrode (124B) and the second drain electrode (125B) are electrically connected to the semiconductor layer (121) of the second transistor (120B) respectively. The bottom gate layer (122) of the second transistor (120B) is electrically connected to the second source electrode (124B).

5. The array substrate according to claim 1, characterized in that, The array substrate (100) has a non-display area. The thin film transistor (120) includes a third transistor (120C) located in the non-display area. The third transistor (120C) further includes a third source electrode (124C) and a third drain electrode (125C). The third source electrode (124C) and the third drain electrode (125C) are disposed on a side of the top gate layer (123) of the third transistor (120C) facing away from the substrate (110). The third source electrode (124C) and the third drain electrode (125C) are electrically connected to the semiconductor layer (121) of the third transistor (120C) respectively. The top gate layer (123) of the third transistor (120C) is electrically connected to the bottom gate layer (122) of the third transistor (120C).

6. The array substrate according to claim 1, wherein The thin film transistor (120) further satisfies: m1 < m2; wherein, m1 is the mobility of the lower layer semiconductor (1211), and m2 is the mobility of the upper layer semiconductor (1212); Preferably, the thin film transistor (120) further satisfies: 8 cm 2 / v·s ≤ m1 ≤ 15 cm 2 / v·s; and / or m2≥20cm 2 / v·s。 7. The array substrate according to claim 1, characterized in that, The manufacturing material of the lower layer semiconductor (1211) includes at least one of indium gallium zinc oxide, indium hafnium zinc oxide, indium aluminum zinc oxide, and indium zirconium zinc oxide; The manufacturing material of the upper layer semiconductor (1212) includes at least one of indium gallium oxide, indium gallium titanium oxide, indium zinc oxide, and indium titanium zirconium zinc oxide.

8. An array substrate, characterized in that, Comprising: A substrate (110) and a plurality of thin film transistors (120), each of the thin film transistors (120) being disposed on the substrate (110) at intervals from each other. The thin film transistor (120) includes a semiconductor layer (121), a bottom gate layer (122), and a top gate layer (123). The semiconductor layer (121) includes a stacked lower semiconductor (1211), a middle semiconductor (1213), and an upper semiconductor (1212). The lower semiconductor (1211) and the middle semiconductor (1213) have different mobilities, and the upper semiconductor (1212) and the middle semiconductor (1213) have different mobilities. The bottom gate layer (122) is disposed on a side of the lower semiconductor (1211) close to the substrate (110), and the top gate layer (123) is disposed on a side of the upper semiconductor (1212) facing away from the substrate (110). The thin film transistor (120) satisfies: L2 < L0 < L1; or L1 < L0 < L2; wherein, L1 is the thickness of the lower semiconductor (1211) in a direction perpendicular to the plane of the substrate (110), L2 is the thickness of the upper semiconductor (1212) in a direction perpendicular to the surface of the substrate (110), and L0 is the Debye length of the thin film transistor (120).

9. A manufacturing method of an array substrate, characterized in that, Comprising: Successively forming a bottom gate layer (122), a lower semiconductor material layer (128), an upper semiconductor material layer (129), and a top gate layer (123) on the substrate (110), the lower semiconductor material layer (128) and the upper semiconductor material layer (129) having different mobilities; Ion implantation is performed on the lower semiconductor material layer (128) and the upper semiconductor material layer (129) to form a semiconductor layer (121), the semiconductor layer (121) including a stacked lower semiconductor (1211) and an upper semiconductor (1212); A source electrode and a drain electrode are formed on a side of the top gate layer (123) facing away from the substrate (110), and the source electrode and the drain electrode are electrically connected to the semiconductor layer (121) respectively.

10. A display panel, characterized in that, Comprising: An array substrate (100) according to any one of claims 1 to 8.

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