Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a plurality of pixel driving circuits arranged in a first direction and a second direction, a first reset signal auxiliary line extending in the first direction and a data signal line extending in the second direction. The pixel driving circuit comprises a first capacitor, a switch transistor connected with a data signal line and a switch reset transistor connected with a first reset signal auxiliary line, and the switch transistor, the switch reset transistor and the first capacitor are all connected to a first node; the first reset signal auxiliary line and the data signal line are partially overlapped in the thickness direction of the display panel, the first reset signal auxiliary line comprises a first protruding part extending in the second direction, and the first capacitor comprises a second protruding part extending in the second direction; the first protruding part and the second protruding part are at least partially overlapped in the thickness direction of the display panel; according to the invention, signal crosstalk generated by capacitance formed between the second reset signal auxiliary line and the data signal line can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] As a new type of self-emitting display panel, an Organic Light-Emitting Diode (OLED) display panel is ultra-clear, thin, flexible, and highly designable. At the same time, it uses organic semiconductors to emit light, and the range of material selection is relatively wide, making it easy to achieve full-color display within the visible light range. In particular, the top-emitting OLED display panel has advantages such as a large aperture ratio and is increasingly widely used in various fields.

[0003] Specifically, the OLED display panel includes a planarization layer disposed on a thin-film transistor device layer, an anode layer disposed on the planarization layer, a pixel definition layer disposed on the anode layer, and a light-emitting layer disposed on the pixel definition layer; wherein, the anode layer includes a plurality of anodes, the pixel definition layer includes a plurality of pixel openings corresponding one-to-one to the plurality of anodes, and the light-emitting layer includes a light-emitting portion disposed on the anode corresponding to each pixel opening.

[0004] Currently, the VDD power supply line passes through the area of the pixel opening. In order to improve the flatness within the pixel opening to improve the film thickness uniformity of the light-emitting portion, the width of the VDD power supply line is often increased to improve the flatness within the pixel opening; however, after the width of the VDD power supply line is increased, the wiring space within the film layer will be reduced, resulting in a reduction in the distance between adjacent traces, and signal crosstalk is likely to occur. Summary of the Invention

[0005] Embodiments of this application provide a display panel and a display device, which can reduce the signal crosstalk between the second reset signal auxiliary line and the data signal line.

[0006] Embodiments of this application provide a display panel, the display panel includes a plurality of pixel driving circuits arranged along a first direction and a second direction, a first reset signal auxiliary line extending along the first direction, and a data signal line extending along the second direction, and the first direction and the second direction intersect;

[0007] The pixel driving circuit includes a first capacitor, a switching transistor connected to the data signal line, and a switching reset transistor connected to the first reset signal auxiliary line, and the switching transistor, the switching reset transistor, and the first capacitor are all connected to a first node;

[0008] Among them, the first reset signal auxiliary line overlaps with the data signal line at least partially in the thickness direction of the display panel. The first reset signal auxiliary line includes a first protrusion extending in the second direction, and the first capacitor includes a second protrusion extending in the second direction. The first protrusion and the second protrusion overlap at least partially in the thickness direction of the display panel.

[0009] In an embodiment of the present application, in the same pixel driving circuit, the first capacitor includes at least two of the second protrusions arranged in the first direction;

[0010] The first reset signal auxiliary line includes a plurality of the first protrusions arranged in the first direction, and the plurality of the first protrusions in the first reset signal auxiliary line are correspondingly arranged with the plurality of the second protrusions in the plurality of pixel driving circuits arranged in the first direction.

[0011] In an embodiment of the present application, in the same pixel driving circuit, the first node is located between two adjacent first protrusions.

[0012] In an embodiment of the present application, in the same pixel driving circuit, the switch reset transistor is connected to the first reset signal auxiliary line through the first protrusion.

[0013] In an embodiment of the present application, the display panel includes a plurality of the data signal lines arranged in the first direction, and the first capacitor is located between two adjacent data signal lines;

[0014] In the same pixel driving circuit, both the first protrusion and the second protrusion are located between two adjacent data signal lines.

[0015] In an embodiment of the present application, the switching transistor and the switch reset transistor are adjacent and connected in the first direction, and the first reset signal auxiliary line is located on a side of the first capacitor close to the switching transistor.

[0016] In an embodiment of the present application, the first protrusion is located on a side of the first reset signal line close to the switching transistor, and the second protrusion is located on a side of the first capacitor close to the switching transistor.

[0017] In an embodiment of the present application, the display panel further includes:

[0018] a substrate;

[0019] A semiconductor layer is disposed on one side of the substrate. The semiconductor layer includes a switching active portion of the switching transistor and the first reset signal auxiliary line. The data signal line is located on one side of a plurality of pixel driving circuits arranged along the second direction and is connected to the switching active portion in the pixel driving circuit;

[0020] A first gate layer is disposed on the side of the semiconductor layer away from the substrate. The first gate layer includes a first electrode plate of the first capacitor;

[0021] A second gate layer is disposed on the side of the first gate layer away from the semiconductor layer. The second gate layer includes a second electrode plate of the first capacitor, and the first electrode plate and the second electrode plate are disposed opposite to each other in the thickness direction of the display panel. The second protrusion is connected to the second electrode plate.

[0022] In an embodiment of the present application, the first electrode plate is connected to the first node.

[0023] In an embodiment of the present application, the pixel driving circuit further includes a second capacitor connected to the first node. The second capacitor is located on the side of the first capacitor away from the first reset signal auxiliary line;

[0024] The first gate layer includes a third electrode plate of the second capacitor, and the second gate layer includes a fourth electrode plate of the second capacitor. The third electrode plate and the fourth electrode plate are disposed opposite to each other in the thickness direction of the display panel, and the fourth electrode plate is connected to the first node.

[0025] In an embodiment of the present application, the first protrusion is located on the side of the first reset signal auxiliary line away from the second capacitor, and the second protrusion is located on the side of the second electrode plate away from the second capacitor.

[0026] In an embodiment of the present application, the second gate layer further includes a plate connection line connected to the second electrode plate. At least a part of the plate connection line extends along the second direction and is located between two second capacitors in two adjacent pixel driving circuits arranged along the first direction;

[0027] The plate connection line and the data signal line do not overlap at least partially in the thickness direction of the display panel.

[0028] In an embodiment of the present application, the plate connection line includes a third line segment extending along the second direction, a fourth line segment extending along the first direction, and a fifth line segment extending along the first direction. The fourth line segment is connected between the third line segment and the fifth line segment, and the third line segment is connected between the fourth line segment and the second electrode plate;

[0029] The width of the fourth line segment in the second direction is smaller than the width of the fifth line segment in the second direction. The data signal line partially overlaps with the fourth line segment in the thickness direction of the display panel, and the data signal line does not overlap with the fifth line segment in the thickness direction of the display panel.

[0030] In an embodiment of the present application, the pixel driving circuit further includes a driving transistor, a compensating transistor, and a first reset transistor. The driving transistor, the second capacitor, the compensating transistor, and the first reset transistor are all connected to a second node, and the driving transistor and the compensating transistor are both connected to a third node;

[0031] The semiconductor layer further includes a driving active part of the driving transistor, a compensating active part of the compensating transistor, and a first reset active part of the first reset transistor;

[0032] The compensating active part is disposed opposite to the fifth line segment in the thickness direction of the display panel, and the first reset active part is disposed opposite to the fifth line segment in the thickness direction of the display panel.

[0033] In an embodiment of the present application, the display panel further includes a first power signal line extending in the second direction. The pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The first light-emitting control transistor is connected to the third node, the second light-emitting control transistor is connected between the first power signal line and the driving transistor, and the second electrode plate is electrically connected to the first power signal line.

[0034] In an embodiment of the present application, the display panel further includes a second reset signal auxiliary line extending in the second direction, and the second reset signal auxiliary line is located between the first power signal line and the data signal line;

[0035] Wherein, the second reset signal auxiliary line includes a first line segment and a second line segment connected to each other. The minimum distance between the first line segment and the data signal line is greater than the minimum distance between the second line segment and the data signal line.

[0036] In an embodiment of the present application, the first line segment is parallel to the data signal line. The second line segment includes an intermediate sub-part and a connecting sub-part connecting the intermediate sub-part and the first line segment. The intermediate sub-part is parallel to the data signal line, and the extending direction of the connecting sub-part intersects with the data signal line.

[0037] In an embodiment of the present application, the semiconductor layer further includes a switching and reset active portion of the switching and reset transistor. The switching and reset active portion is disposed adjacent to the switching active portion along the first direction and is connected to the first node. The first reset signal auxiliary line is connected to the switching and reset active portion;

[0038] The second reset signal auxiliary line is located on one side of a plurality of the pixel driving circuits arranged along the second direction and is electrically connected to the switching and reset active portion in the pixel driving circuit.

[0039] In an embodiment of the present application, the display panel further includes a plurality of light emitting portions arranged along the first direction and the second direction. A plurality of the light emitting portions arranged along the second direction are located on one side of a corresponding one of the first power signal lines;

[0040] Wherein, the first power signal line includes overlapping line segments. The light emitting portion includes a bottom surface close to the first power signal line. The overlapping line segments and the bottom surface of the light emitting portion overlap along the thickness direction of the display panel. The ratio of the area of the overlapping line segments projected onto the substrate to the area of the bottom surface of the light emitting portion projected onto the substrate is greater than or equal to 0.5 and less than or equal to 1.

[0041] According to the above object of the present application, an embodiment of the present application further provides a display device, and the display device includes the display panel.

[0042] The present application provides a display panel and a display device. By providing a first protrusion on the first reset signal auxiliary line and a second protrusion in the first capacitor, the overlapping area between the first reset signal auxiliary line and the first capacitor is increased. Furthermore, the total capacitance formed by the first reset signal auxiliary line in the pixel driving circuit can be increased, the capacitance ratio between the second reset signal auxiliary line and the data signal line can be reduced, and the signal crosstalk generated by the capacitance formed between the second reset signal auxiliary line and the data signal line can be effectively reduced.

[0043] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0045] To more fully understand the present application and its beneficial effects, the following description will be made in conjunction with the accompanying drawings, where the same reference numerals in the following description denote the same parts.

[0046] Figure 1 It is a film stack diagram of sub-pixels in a display panel provided by an embodiment of the present application;

[0047] Figure 2 It is a structural diagram of a pixel driving circuit of a display panel provided by an embodiment of the present application;

[0048] Figure 3 It is a schematic plan view of a display panel provided by an embodiment of the present application;

[0049] Figure 4 It is a schematic cross-sectional view of a display panel provided by an embodiment of the present application;

[0050] Figure 5 Provided by an embodiment of the present application Figure 1 The structural diagram of the semiconductor layer in;

[0051] Figure 6 Provided by an embodiment of the present application Figure 1 The structural diagram of the first gate layer in;

[0052] Figure 7 Provided by an embodiment of the present application Figure 1 The stack diagram of the semiconductor layer and the first gate layer in;

[0053] Figure 8 Provided by an embodiment of the present application Figure 1 The structural diagram of the second gate layer in;

[0054] Figure 9 Provided by an embodiment of the present application Figure 1 The stack diagram of the semiconductor, the first gate layer and the second gate layer in;

[0055] Figure 10 Provided by an embodiment of the present application Figure 1 The structural diagram of the first conductive layer in;

[0056] Figure 11 Provided by an embodiment of the present application Figure 1 The stack diagram of the semiconductor, the first gate layer, the second gate layer and the first conductive layer in;

[0057] Figure 12 Provided by an embodiment of the present application Figure 1 The structural diagram of the second conductive layer in;

[0058] Figure 13 Provided by an embodiment of the present application Figure 1Stacked diagram of a semiconductor, a first gate layer, a second gate layer, a first conductive layer, and a second conductive layer;

[0059] Figure 14 Provided by an embodiment of the present application Figure 1 Structural diagram of the anode layer in

[0060] Figure 15 Provided by an embodiment of the present application Figure 1 Stacked diagram of a semiconductor, a first gate layer, a second gate layer, a first conductive layer, a second conductive layer, and an anode layer;

[0061] Figure 16 Provided by an embodiment of the present application Figure 4 Schematic plan view of a first pixel defining layer and a second pixel defining layer in

[0062] Explanation of reference numerals:

[0063] AA, display area; NA, non-display area; PX, sub-pixel; PD, pixel driving circuit; EL, light-emitting device;

[0064] 10, substrate; 11, gate driving circuit; 12, bonding terminal; 13, light-emitting layer; 100, light-emitting portion; 1001, bottom surface; 20, semiconductor layer; 21, first reset signal auxiliary line; 211, first protrusion; 22, first connecting sub-portion; 23, second connecting sub-portion; 24, third connecting sub-portion; 25, fourth connecting sub-portion; 26, fifth connecting sub-portion; 27, sixth connecting sub-portion; 30, first gate layer; 40, second gate layer; 41, first jumper wire; 42, plate connection wire; 421, third line segment; 422, fourth line segment; 423, fifth line segment; 43, second protrusion; 50, first conductive layer; 51, second jumper wire; 52, third jumper wire; 53, node connection wire; 54, fourth jumper wire; 55, fifth jumper wire; 56, sixth jumper wire; 57, seventh jumper wire; 58, eighth jumper wire; 59, ninth jumper wire; 510, tenth jumper wire; 511, eleventh jumper wire; 512, twelfth jumper wire; 60, second conductive layer; 61, first power signal line; 611, overlapping line segment; 62, second reset signal auxiliary line; 621, first line segment; 622, second line segment; 6221, intermediate sub-portion; 6222, connecting sub-portion; 63, functional trace; 64, anode connection portion; 70, anode layer; 71, anode; 81, first gate insulating layer; 82, second gate insulating layer; 83, interlayer dielectric layer; 84, first planarization layer; 85, second planarization layer; 86, pixel defining layer; 861, first pixel defining layer; 862, second pixel defining layer; 860, pixel opening;

[0065] T1, switching transistor; T2, driving transistor; T3, compensating transistor; T4, first reset transistor; T5, second reset transistor; T6, third reset transistor; T7, switching reset transistor; T8, first light-emitting control transistor; T9, second light-emitting control transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; SCAN1, first control signal line; SCAN2, second control signal line; SCAN3, third control signal line; SCAN4, fourth control signal line; EM1, first light-emitting control signal line; EM2, second light-emitting control signal line; DATA, data signal line; DATA1, first data signal line; DATA2, second data signal line; DATA3, third data signal line; VI1, first reset signal line; VI2, second reset signal line; VI3, third reset signal line; VI4, fourth reset signal line; VDD, second power supply signal line; VDD1, first sub-section; VDD2, second sub-section; VSS, third power supply signal line; N1, first node; N2, second node; N3, third node; N4, fourth node; N5, fifth node;

[0066] C11, first electrode plate; C12, second electrode plate; C21, third electrode plate; C22, fourth electrode plate; C31, fifth electrode plate; C41, sixth electrode plate;

[0067] T1A, switching active part; T2A, driving active part; T3A, compensating active part; T4A, first reset active part; T5A, second reset active part; T6A, third reset active part; T7A, switching reset active part; T8A, first light-emitting control active part; T9A, second light-emitting control active part;

[0068] T1G, switching gate; T2G, driving gate; T3G, compensating gate; T4G, first reset gate; T5G, second reset gate; T6G, third reset gate; T7G, switching reset gate; T8G, first light-emitting control gate; T9G, second light-emitting control gate;

[0069] T1D, switching drain; T2D, driving drain; T3D, compensating drain; T4D, first reset drain; T5D, second reset drain; T6D, third reset drain; T7D, switching reset drain; T8D, first light-emitting control drain; T9D, second light-emitting control drain;

[0070] T1S, switching source; T2S, driving source; T3S, compensating source; T4S, first reset source; T5S, second reset source; T6S, third reset source; T7S, switching reset source; T8S, first light-emitting control source; T9S, second light-emitting control source. Detailed implementation manners

[0071] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0072] Please refer to Figure 1 , an embodiment of the present application provides a display panel, the display panel includes a plurality of pixel driving circuits PD arranged along a first direction X and a second direction Y, a first reset signal auxiliary line 21 extending along the first direction X, and a data signal line DATA extending along the second direction Y, and the first direction X and the second direction Y intersect.

[0073] The pixel driving circuit PD includes a first capacitor C1, a switching transistor T1 connected to the data signal line DATA, and a switching reset transistor T7 connected to the first reset signal auxiliary line 21, and the switching transistor T1, the switching reset transistor T7, and the first capacitor C1 are all connected to a first node N1.

[0074] Wherein, the first reset signal auxiliary line 21 and the data signal line DATA partially overlap in the thickness direction of the display panel, the first reset signal auxiliary line 21 includes a first protrusion 211 extending along the second direction Y, and the first capacitor C1 includes a second protrusion 43 extending along the second direction Y, and the first protrusion 211 and the second protrusion 43 at least partially overlap in the thickness direction of the display panel.

[0075] In the implementation and application process, in the embodiment of the present application, by providing the first protrusion 211 on the first reset signal auxiliary line 21 and the second protrusion 43 in the first capacitor C1, the overlapping area between the first reset signal auxiliary line 21 and the first capacitor C1 is increased, and thus the total capacitance formed by the first reset signal auxiliary line 21 in the pixel driving circuit PD can be increased, the capacitance ratio between the first reset signal auxiliary line 21 and the data signal line DATA can be reduced, and the signal crosstalk generated by the capacitance formed between the first reset signal auxiliary line 21 and the data signal line DATA can be effectively reduced.

[0076] Specifically, please refer to Figure 2 and Figure 3, the display panel may include a display area AA and a non-display area NA adjacent to the display area AA. The non-display area NA may be disposed around the display area AA, and the non-display area NA may be a border area of the display panel.

[0077] In some embodiments, the display panel further includes a plurality of sub-pixels PX disposed in the display area AA and configured to implement the display function of the display panel, and a gate driving circuit 11 disposed in the non-display area NA. The gate driving circuit 11 is configured to input a control signal into the sub-pixels PX in the display area AA.

[0078] In some embodiments, a pixel driving circuit PD is provided in each sub-pixel PX, and the gate driving circuit 11 is configured to input a gate control signal into a transistor in the pixel driving circuit PD.

[0079] In some embodiments, a bonding terminal 12 is disposed on the lower side of the display area AA. The display panel further includes a data signal line DATA extending into the display area AA and connected to the pixel driving circuit PD. The bonding terminal 12 may be connected to an external circuit, and the bonding terminal 12 transmits a signal input by the external circuit to the data signal line DATA, thereby driving the display panel to display an image. For example, the bonding terminal 12 may be bonded to a chip or a chip-on-film, etc., for providing a power supply and a driving signal, etc., to the display panel.

[0080] In some embodiments, the gate driving circuit 11 is disposed in the non-display area NA, and the gate driving circuit 11 may be disposed on both sides of the display area AA. The gate driving circuit 11 may include a plurality of cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in this application.

[0081] In some embodiments, a plurality of the pixel driving circuits PD may be arranged in an array in the display area AA. The pixel driving circuit PD may be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, 9T2C, 9T6C, etc. pixel driving circuit PD. In the following embodiments, the 9T6C pixel driving circuit PD is taken as an example for illustration.

[0082] Please refer to Figure 2, the pixel driving circuit PD includes a switching transistor T1, a driving transistor T2, a compensating transistor T3, a first reset transistor T4, a second reset transistor T5, a third reset transistor T6, a switching reset transistor T7, a first light-emitting control transistor T8, a second light-emitting control transistor T9, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The display panel further includes a light-emitting device EL connected to the pixel driving circuit PD.

[0083] Further, the display panel further includes a plurality of signal lines, and the plurality of signal lines are used to connect to the pixel driving circuit PD and transmit signals to the pixel driving circuit PD; in some embodiments, the signal lines include a first control signal line SCAN1, a second control signal line SCAN2, a third control signal line SCAN3, a fourth control signal line SCAN4, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, a data signal line DATA, a first reset signal line VI1, a second reset signal line VI2, a third reset signal line VI3, a fourth reset signal line VI4, a first power supply signal line 61, a second power supply signal line VDD, and a third power supply signal line VSS.

[0084] Wherein, the drain of the switching transistor T1 is connected to the data signal line DATA to receive a data signal Data, the source of the switching transistor T1 is connected to a first node N1, and the gate of the switching transistor T1 is connected to the first control signal line SCAN1 to receive a first control signal Scan1.

[0085] The drain of the driving transistor T2 is connected to a fifth node N5, the source of the driving transistor T2 is connected to a third node N3, and the gate of the driving transistor T2 is connected to a second node N2.

[0086] The drain of the compensating transistor T3 is connected to the second node N2, the source of the compensating transistor T3 is connected to the third node N3, and the gate of the compensating transistor T3 is connected to the second control signal line SCAN2 to receive a second control signal Scan2.

[0087] The drain of the first reset transistor T4 is connected to the first reset signal line VI1 to receive a first reset signal Vi1, the source of the first reset transistor T4 is connected to the second node N2, and the gate of the first reset transistor T4 is connected to the third control signal line SCAN3 to receive a third control signal Scan3.

[0088] The drain of the second reset transistor T5 is connected to a second reset signal line VI2 to receive a second reset signal Vi2. The source of the second reset transistor T5 is connected to a fourth node N4. The gate of the second reset transistor T5 is connected to a fourth control signal line SCAN4 to receive a fourth control signal Scan4.

[0089] The drain of the third reset transistor T6 is connected to a third reset signal line VI3 to receive a third reset signal Vi3. The source of the third reset transistor T6 is connected to the fifth node N5. The gate of the third reset transistor T6 is connected to the fourth control signal line SCAN4 to receive a fourth control signal Scan4.

[0090] The drain of the switch reset transistor T7 is connected to a fourth reset signal line VI4 to receive a fourth reset signal Vi4. The source of the switch reset transistor T7 is connected to the first node N1. The gate of the switch reset transistor T7 is connected to a second control signal line SCAN2 to receive a second control signal Scan2.

[0091] The drain of the first light-emitting control transistor T8 is connected to the third node N3. The source of the first light-emitting control transistor T8 is connected to the fourth node N4. The gate of the first light-emitting control transistor T8 is connected to a first light-emitting control signal line EM1 to receive a first light-emitting control signal Em1.

[0092] The drain of the second light-emitting control transistor T9 is connected to a first power supply signal line 61 to receive a first power supply signal Vdd. The source of the second light-emitting control transistor T9 is connected to the fifth node N5, that is, the second light-emitting control transistor T9 is connected between the first power supply signal line 61 and the driving transistor T2. The gate of the second light-emitting control transistor T9 is connected to the second light-emitting control signal to receive a second light-emitting control signal Em2.

[0093] The display panel further includes a light-emitting device EL connected to the pixel driving circuit PD. One end of the light-emitting device EL is connected to the fourth node N4. The other end of the light-emitting device EL is connected to a third power supply signal line VSS to receive a third power supply signal Vss.

[0094] One plate of the second capacitor C2 is connected to the first node N1, and the other plate of the second capacitor C2 is connected to the second node N2; one plate of the first capacitor C1 is connected to the first node N1, and the other plate of the first capacitor C1 is connected to the second power supply signal line VDD; the third capacitor C3 and the fourth capacitor C4 are connected in series between the active part of the switching transistor T1 and the active part of the switching reset transistor T7; one plate of the fifth capacitor C5 is connected to the active part of the first reset transistor T4, and the other plate of the fifth capacitor C5 is connected to the second power supply signal line VDD; one plate of the sixth capacitor C6 is connected to the active part of the compensation transistor T3, and the other plate of the sixth capacitor C6 is connected to the second power supply signal line VDD.

[0095] It should be noted that in the embodiment of the present application, the signal can be coupled to the second node N2 through the second capacitor C2, that is, to the gate of the driving transistor T2; and the second capacitor C2 and the first capacitor C1 can stabilize the potentials of the first node N1 and the second node N2, reducing the probability of signal instability and signal flicker; the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5 and the sixth capacitor C6 are respectively used to prevent the switching transistor T1, the switching reset transistor T7, the first reset transistor T4 and the compensation transistor T3 from leaking electricity, and can also reduce the probability of signal flicker.

[0096] For the switching transistors T1 in different sub-pixels PX, the data signal lines DATA they are connected to are different. In the present application, only one of them is taken as an example for illustration.

[0097] In this embodiment, the first power supply signal line 61 and the second power supply signal line VDD are used to provide a constant voltage high level for the pixel driving circuit PD, and the first power supply signal line 61 and the second power supply signal line VDD can be connected, and the third power supply signal line VSS is used to provide a constant voltage low level for the pixel driving circuit PD.

[0098] In this embodiment, the switching transistor T1, the driving transistor T2, the compensating transistor T3, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, the switching reset transistor T7, the first light-emitting control transistor T8, and the second light-emitting control transistor T9 are each independently selected from one of a P-type transistor and an N-type transistor; in this application, the switching transistor T1, the driving transistor T2, the compensating transistor T3, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, the switching reset transistor T7, the first light-emitting control transistor T8, and the second light-emitting control transistor T9 are all P-type transistors as an example for illustration.

[0099] In this embodiment, the source electrode is only the output end of this application, and the drain electrode is only the input end of this application, and they only have a difference in naming.

[0100] Next, for the Figure 4 structure, the film layer structure of the pixel circuit of this application will be described.

[0101] The display area AA and the non-display area NA of the display panel may be provided with a substrate 10 and an array driving layer provided on the substrate 10; within the display area AA, the display panel may further include a pixel definition layer 86 provided on the array driving layer, and a light-emitting portion 100 provided on the pixel definition layer 86. Next, the film layer structure within the display area AA will be mainly described.

[0102] In some embodiments, the substrate 10 supports each layer provided on the substrate 10. When the display panel is a bottom-emitting light-emitting display device or a double-sided emitting light-emitting display device, a transparent substrate may be used. When the display panel is a top-emitting light-emitting display device, a semi-transparent or opaque substrate and a transparent substrate may be used.

[0103] In this embodiment, the substrate 10 is used to support each film layer provided on the substrate 10, and the substrate 10 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 10 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0104] In this embodiment, the substrate 10 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer stacked, the first flexible substrate and the second flexible substrate may be formed of the same material such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0105] Please refer to Figure 4 , the array driving layer may include a plurality of thin film transistors, and the thin film transistors may be etch-blocking type, back-channel etching type, or may be divided into bottom-gate thin film transistors, top-gate thin film transistors, etc. according to the positions of the gate and the active part, or may be divided into N-type thin film transistors and P-type thin film transistors according to the performance of the thin film transistors; wherein, Figure 4 the thin film transistors in Figure 2 do not represent the structure diagram of any transistor in

[0106] Please refer to Figure 4 , the array driving layer may include a semiconductor layer 20 disposed on the substrate 10, a first gate insulating layer 81 disposed on the semiconductor layer 20, a first gate layer 30 disposed on the first gate insulating layer 81, a second gate insulating layer 82 disposed on the first gate layer 30, a second gate layer 40 disposed on the second gate insulating layer 82, an interlayer dielectric layer 83 disposed on the second gate layer 40, a first conductive layer 50 disposed on the interlayer dielectric layer 83, a first planarization layer 84 disposed on the first conductive layer 50, a second conductive layer 60 disposed on the first planarization layer 84, a second planarization layer 85 disposed on the second conductive layer 60, a light-emitting device EL and a pixel definition layer 86 disposed on the second planarization layer 85.

[0107] In some embodiments, the material of the semiconductor layer 20 may be a silicon semiconductor. For example, the material of the semiconductor layer 20 in the present application may be low-temperature polycrystalline silicon.

[0108] In some embodiments, the first gate insulating layer 81, the second gate insulating layer 82, and the interlayer dielectric layer 83 are respectively disposed on the corresponding metal layer or semiconductor layer 20 and are separated by different layers of metal layers or semiconductor layers 20; and the materials of the first gate insulating layer 81, the second gate insulating layer 82, and the interlayer dielectric layer 83 may be inorganic substances combined with silicon and oxygen or organic materials with flatness.

[0109] In some embodiments, the first gate layer 30 and the second gate layer 40 are respectively disposed on the corresponding insulating layer, and the materials of the first gate layer 30 and the second gate layer 40 may be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0110] In some embodiments, the materials of the first conductive layer 50 and the second conductive layer 60 may be copper, molybdenum, molybdenum-titanium alloy, or a three-layer metal of titanium-aluminum-titanium, etc.

[0111] In some embodiments, the first flat layer 84 and the second flat layer 85 are laid as a whole layer to ensure the flatness of the film layer of the array driving layer. The materials of the first flat layer 84 and the second flat layer 85 can be inorganic substances combined with silicon oxynitride or organic materials with flatness.

[0112] It should be noted that the pixel defining layer 86 is disposed on the flat layer and is provided with a plurality of pixel openings 860. The light emitting device EL may include an anode 71, a light emitting portion 100, and a cathode which are stacked. The anode 71 is located within the pixel opening 860. The light emitting portion 100 is disposed within the pixel opening 860 and on the anode 71. The cathode is located on the light emitting portion 100.

[0113] It can be understood that each thin film transistor and signal line in the pixel driving circuit PD can be located in the array driving layer. For example, the active portions of each thin film transistor can be located in the semiconductor layer 20, and other electrodes of each thin film transistor or the connected signal lines can be located in the first gate layer 30, the second gate layer 40, the first conductive layer 50, or the second conductive layer 60.

[0114] Please refer to Figure 1 , the display panel may include a plurality of pixel driving circuits PD arranged along the first direction X and the second direction Y, and the first direction and the second direction intersect; in some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0115] Among them, the display panel includes a plurality of repeating units, and Figure 1 as shown is one of the repeating units. Each repeating unit includes three pixel driving circuits PD arranged along the first direction X and three data signal lines DATA connected to the three pixel driving circuits PD in the repeating unit.

[0116] In the following embodiments, the technical solution of the present application will be described by taking the structure of each film layer in the pixel driving circuit PD in one repeating unit as an example.

[0117] Please refer to Figure 5, the semiconductor layer 20 includes a switching active part T1A of the switching transistor T1, a driving active part T2A of the driving transistor T2, a compensating active part T3A of the compensating transistor T3, a first reset active part T4A of the first reset transistor T4, a second reset active part T5A of the second reset transistor T5, a third reset active part T6A of the third reset transistor T6, a switching reset active part T7A of the switching reset transistor T7, a first light emission control active part T8A of the first light emission control transistor T8, a second light emission control active part T9A of the second light emission control transistor T9, and a first reset signal auxiliary line 21.

[0118] Among them, the switching active part T1A is connected to the switching reset active part T7A and is spaced apart from other active parts; the first reset signal auxiliary line 21 extends along the first direction X and connects the switching reset active parts T7A in a plurality of pixel driving circuits PD arranged along the first direction X together.

[0119] Among them, the switching active part T1A is in an n shape, and one end of the switching active part T1A is used to be connected to the data signal line DATA, and the other end of the switching active part T1A is connected to the switching reset active part T7A; the switching reset active part T7A is in an n shape, one end of the switching reset active part T7A is connected to the switching active part T1A, and the other end of the switching reset active part T7A is connected to the first reset signal auxiliary line 21; the switching active part T1A and the switching reset active part T7A are connected to each other at the first node N1.

[0120] In some embodiments, the switching active part T1A includes a first connection sub - part 22 and a second connection sub - part 23 arranged along the first direction X, and a third connection sub - part 24 extending along the first direction X and connected between the first connection sub - part 22 and the second connection sub - part 23, and both the first connection sub - part 22 and the second connection sub - part 23 extend along the second direction Y.

[0121] The switching reset active part T7A includes a fourth connection sub - part 25 and a fifth connection sub - part 26 arranged along the first direction X, and a sixth connection sub - part 27 extending along the first direction X and connected between the fourth connection sub - part 25 and the fifth connection sub - part 26, and both the fourth connection sub - part 25 and the fifth connection sub - part 26 extend along the second direction Y.

[0122] The first connection sub - part 22 is used to connect with the data signal line DATA. The second connection sub - part 23 and the fourth connection sub - part 25 are connected to the first node N1. The fifth connection sub - part 26 is used to connect the fourth reset signal line VI4.

[0123] Among them, there is a first distance along the first direction X between the first connection sub - part 22 and the second connection sub - part 23, and a second distance along the first direction X between the fourth connection sub - part 25 and the fifth connection sub - part 26. The first distance is greater than or equal to the second distance. In the embodiment of the present application, by increasing the distance between the first connection sub - part 22 and the second connection sub - part 23, the distance between the data signal line DATA and the first node N1 can be increased, and the signal crosstalk between the data signal line DATA and the first node N1 can be reduced.

[0124] The driving active part T2A, the compensating active part T3A, the first reset active part T4A, the second reset active part T5A, the third reset active part T6A, the first light - emitting control active part T8A and the second light - emitting control active part T9A are connected, and the third reset active parts T6A in the plurality of pixel driving circuits PD arranged along the first direction X are connected together.

[0125] Among them, the driving active part T2A is in an n - shape. One end of the driving active part T2A is connected to the third node N3, and the other end of the driving active part T2A is connected to the fifth node N5. One end of the compensating active part T3A is connected to the second node N2, and the other end of the compensating active part T3A is connected to the third node N3. One end of the first reset active part T4A is connected to the second node N2, and the other end of the first reset active part T4A is used for signal input. One end of the first light - emitting control active part T8A is connected to the third node N3, and the other end of the first light - emitting control active part T8A is connected to the fourth node N4. One end of the second reset active part T5A is connected to the fourth node N4, and the other end of the second reset active part T5A is used for signal input. One end of the second light - emitting control active part T9A is connected to the fifth node N5, and the other end of the second light - emitting control active part T9A is used for signal input. One end of the third reset active part T6A is connected to the fifth node N5, and the other end of the third reset active part T6A is used for signal input.

[0126] Further, the compensation active part T3A, the first reset active part T4A, the second reset active part T5A, the third reset active part T6A, the first light-emitting control active part T8A, and the second light-emitting control active part T9A are all located on the side of the driving active part T2A away from the switching active part T1A; furthermore, the first light-emitting control active part T8A is located on the side of the compensation active part T3A away from the driving active part T2A, and the second light-emitting control active part T9A is located on the side of the first reset active part T4A away from the driving active part T2A.

[0127] In some embodiments, the switching active part T1A and the switching reset active part T7A are adjacent and connected along the first direction X, and the first reset active part T4A and the compensation active part T3A are adjacent and connected along the first direction X.

[0128] In some embodiments, in the same pixel driving circuit PD, the first light-emitting control active part T8A is located on the side of the driving active part away from the switching active part and extends along the second direction Y.

[0129] Please refer to Figure 6 and ​ , the first gate layer 30 is disposed on the side of the semiconductor layer 20 away from the substrate 10, and the first gate layer 30 includes the gates of the transistors in the pixel driving circuit PD.

[0130] Specifically, the first gate layer 30 includes the switching gate T1G of the switching transistor T1, the driving gate T2G of the driving transistor T2, the compensation gate T3G of the compensation transistor T3, the first reset gate T4G of the first reset transistor T4, the second reset gate TTG of the second reset transistor T5, the third reset gate T6G of the third reset transistor T6, the switching reset gate T7G of the switching reset transistor T7, the first light-emitting control gate T8G of the first light-emitting control transistor T8, the second light-emitting control gate T9G of the second light-emitting control transistor T9, as well as the first electrode plate C11 of the first capacitor C1 and the third electrode plate C21 of the second capacitor C2.

[0131] Among them, the third electrode plate C21 of the second capacitor C2 is multiplexed as the driving gate T2G.

[0132] Please combine ​ , ​ and ​, there are two overlapping positions between the switching gate T1G and the switching active part T1A, so that the switching transistor T1 can form a double-gate structure; there are two overlapping positions between the switching reset gate T7G and the switching reset active part T7A, so that the switching reset transistor T7 can form a double-gate structure; there are two overlapping positions between the compensation gate T3G and the compensation active part T3A, which can make the compensation transistor T3 form a double-gate structure; there are two overlapping positions between the first reset transistor T4 and the first reset active part T4A, so that the first reset transistor T4 can form a double-gate structure; it can be understood that the thin-film transistors with the double-gate structure can effectively reduce the leakage current and improve the electrical properties of the thin-film transistors.

[0133] In addition, the driving gate T2G is disposed on a side of the driving active part T2A away from the substrate 10, the driving gate T2G overlaps with the driving active part T2A, the second reset gate T5G overlaps with the second reset active part T5A, the third reset gate T6G overlaps with the third reset active part T6A, the first light-emitting control gate T8G overlaps with the first light-emitting control active part T8A, and the second light-emitting control gate T9G overlaps with the second light-emitting control active part T9A.

[0134] It should be noted that the fourth control signal line SCAN4 extends along the first direction X and overlaps with the second reset active part T5A and the third reset active part T6A at the same time to be multiplexed as the second reset gate T5G and the third reset gate T6G.

[0135] In some embodiments, the widths of the overlapping parts between the second reset active part T5A and the second reset gate T5G, the overlapping parts between the third reset active part T6A and the third reset gate T6A, the overlapping parts between the first light-emitting control active part T8A and the first light-emitting control gate T8G, and the overlapping parts between the second light-emitting control active part T9A and the second light-emitting control active part T9A are all increased, and are all greater than the widths of the active parts of other thin-film transistors in the pixel driving circuit PD, such as the overlapping parts between the switching active part T1A and the switching gate T1G, the overlapping parts between the driving active part T2A and the driving gate T2G, the overlapping parts between the compensation active part T3A and the compensation gate T3G, the overlapping parts between the first reset active part T4A and the first reset gate T4G, and the overlapping parts between the switching reset active part T7A and the switching reset gate T7G.

[0136] Further, the opposite end of the switching active part T1A away from the first node N1 can be multiplexed as the switching drain T1D, and the end of the switching active part T1A close to the first node N1 can be multiplexed as the switching source T1S; the opposite end of the switching reset active part T7A away from the first node N1 can be multiplexed as the switching reset drain T7D, and the end of the switching reset active part T7A close to the first node N1 can be multiplexed as the switching reset source T7S.

[0137] The end of the driving active part T2A close to the fifth node N5 can be multiplexed as the driving drain T2D, and the end of the driving active part T2A close to the third node N3 can be multiplexed as the driving source T2S; the end of the compensating active part T3A close to the second node N2 can be multiplexed as the compensating drain T3D, and the end of the compensating active part T3A close to the third node N3 can be multiplexed as the compensating source T3S; the end of the first reset active part T4A close to the second node N2 can be multiplexed as the first reset source T4S, and the end of the first reset active part T4A away from the second node N2 can be multiplexed as the first reset drain T4D; the end of the first light-emitting control active part T8A close to the third node N3 can be multiplexed as the first light-emitting control drain T8D, and the end of the first light-emitting control active part T8A close to the fourth node N4 can be multiplexed as the first light-emitting control source T8S; the end of the second reset active part T5A close to the fourth node N4 can be multiplexed as the second reset drain T5D, and the opposite end of the second reset active part T5A away from the fourth node N4 can be multiplexed as the second reset source T5S; the end of the second light-emitting control active part T9A close to the fifth node N5 can be multiplexed as the second light-emitting control source T9S, and the opposite end of the second light-emitting control active part T9A away from the fifth node N5 can be multiplexed as the second light-emitting control drain T9D; the end of the third reset active part T6A close to the fifth node N5 can be multiplexed as the third reset source T6S, and the opposite end of the third reset active part T6A away from the fifth node N5 can be multiplexed as the third reset drain T6D.

[0138] Please refer to ​ and ​ , the second gate layer 40 is disposed on a side of the first gate layer 30 away from the semiconductor layer 20, and the second gate layer 40 includes a plurality of signal lines and capacitor plates.

[0139] Specifically, the second gate layer 40 includes the second electrode plate C12 of the first capacitor C1, the fourth electrode plate C22 of the second capacitor C2, the fifth electrode plate C31, the sixth electrode plate C41, the first reset signal line VI1, the third reset signal line VI3, the first light emission control signal line EM1, the second light emission control signal line EM2, the first jumper wire 41, and the electrode plate connection wire 42; and the fifth electrode plate C31 and the sixth electrode plate C41 are both connected to the third reset signal line VI3, the seventh electrode plate C51 and the eighth electrode plate C61 are both connected to the second electrode plate C12, and the second electrode plate C12 can be connected to the first power supply signal line 61 and the second power supply signal line VDD.

[0140] Among them, the second electrode plate C12 is disposed opposite to the first electrode plate C11 to form the first capacitor C1, the third electrode plate C21 is disposed opposite to the fourth electrode plate C22 to form the second capacitor C2, the fifth electrode plate C31 is disposed opposite to the switch active part T1A to form the third capacitor C3, and the sixth electrode plate C41 is disposed opposite to the switch reset active part T7A to form the fourth capacitor C4.

[0141] In addition, the electrode plate connection wire 42 is connected to the second electrode plate C12; at least a part of the electrode plate connection wire 42 extends along the second direction Y and is located between two of the second capacitors C2 in two adjacent pixel driving circuits PD arranged along the first direction X, and further located between two of the fourth electrode plates C22 in two adjacent pixel driving circuits PD arranged along the first direction X.

[0142] Among them, the electrode plate connection wire 42 and the data signal line DATA do not overlap at least partially in the thickness direction of the display panel; thus, the capacitance between the first power supply signal line 61 and the data signal line DATA can be effectively reduced, and signal interference can be reduced.

[0143] In some embodiments, the electrode plate connection wire 42 includes a third line segment 421 extending along the second direction Y, a fourth line segment 422 extending along the first direction X, and a fifth line segment 423 extending along the first direction X. The fourth line segment 422 is connected between the third line segment 421 and the fifth line segment 423, and the third line segment 421 is connected between the fourth line segment 423 and the second electrode plate C12.

[0144] The width of the fourth line segment 422 along the second direction Y is smaller than the width of the fifth line segment 423 along the second direction Y. The data signal line DATA partially overlaps with the fifth line segment 423 in the thickness direction of the display panel, and the data signal line DATA does not overlap with the fifth line segment 423 in the thickness direction of the display panel. That is, in the embodiment of the present application, by reducing the line width of the electrode connection line 42 and making the reduced part of the line width overlap with the data signal line DATA, the capacitance between the data signal line DATA and the first power signal line 61 can be further reduced, and signal interference can be reduced.

[0145] The first reset active part T4A and the fifth line segment 423 are aligned in the thickness direction of the display panel to form the fifth capacitor C5. The compensation active part T3A and the fifth line segment 423 are aligned in the thickness direction of the display panel to form the sixth capacitor C6. In the embodiment of the present application, the fifth line segment 423 is maintained at a relatively large line width without line width reduction, so as to increase the overlapping area between the first reset active part T4A and the fifth line segment 423 and between the compensation active part T3A and the fifth line segment 423. Furthermore, the capacitance between the fifth capacitor C5 and the sixth capacitor C6 can be increased, and the electrical stability of the first reset transistor T4 and the compensation transistor T3 can be improved.

[0146] The first light emission control signal line EM1 is used to electrically connect to the first light emission control gate T8G to transmit signals. The second light emission control signal line EM2 is used to electrically connect to the second light emission control gate T9G to transmit signals. The first reset signal line VI1 is used to electrically connect to the first reset drain T4D. The third reset signal line VI3 is used to electrically connect to the third reset drain T6D. The specific connection relationship can be referred to the subsequent embodiments.

[0147] In some embodiments, the semiconductor layer 20 further includes a first reset signal auxiliary line 21 extending along the first direction X. In a top view, the first reset signal auxiliary line 21 is located on a side of the first capacitor C1 away from the second capacitor C2. The first reset signal auxiliary line 21 is connected to the second reset signal auxiliary line 62, and a first protrusion 211 extending along the second direction Y is connected to the first reset signal auxiliary line 21.

[0148] A second protruding portion 43 extending along the second direction Y is connected to the second electrode plate C12, and the first protruding portion 211 and the second protruding portion 43 at least partially overlap in the thickness direction of the display panel; since the second electrode plate C12 is connected to the first power signal line 61, the capacitance between the first power signal line 61 and the first reset signal auxiliary line 21 can be increased, and the total capacitance that the first power signal line 61 can form in the pixel driving circuit PD can be increased. Furthermore, the proportion of the capacitance formed between the first power signal line 61 and the data signal line DATA in the total capacitance is reduced, and the signal crosstalk generated by the capacitance formed between the first power signal line 61 and the data signal line DATA can be effectively reduced; at the same time, the total capacitance that the first reset signal auxiliary line 21 can form in the pixel driving circuit PD can also be increased, and thus the capacitance proportion between the first reset signal auxiliary line 21 and the data signal line DATA can be reduced, and the signal crosstalk generated by the capacitance formed between the first reset signal auxiliary line 21 and the data signal line DATA can be effectively reduced.

[0149] In some embodiments, the switching transistor T1 and the switching reset transistor T7 are adjacent and connected along the first direction X, and the first reset signal auxiliary line 21 is located on a side of the first capacitor C1 close to the switching transistor T1. The first protruding portion 211 is located on a side of the first reset signal auxiliary line 21 close to the switching transistor T1, and the second protruding portion 42 is located on a side of the first capacitor C1 close to the switching transistor T1, that is, the second protruding portion 42 is located on a side of the second electrode plate C21 close to the switching transistor T1.

[0150] Furthermore, the first protruding portion 211 is located on a side of the first reset signal auxiliary line 21 away from the second capacitor C2, and the second protruding portion 43 is located on a side of the second electrode plate C12 away from the second capacitor C2.

[0151] In some embodiments, in the same pixel driving circuit PD, the first capacitor C1 includes at least two second protruding portions 43 arranged along the first direction X; the first reset signal auxiliary line 21 includes a plurality of first protruding portions 211 arranged along the first direction X, and the plurality of first protruding portions 211 in the first reset signal auxiliary line 21 are correspondingly arranged with the plurality of second protruding portions 43 in the plurality of pixel driving circuits PD arranged along the first direction X.

[0152] In some embodiments, in the same pixel driving circuit PD, the first node N1 is located between two adjacent first protrusions 211. Similarly, the first node N1 is also located between two adjacent second protrusions 43.

[0153] Further, in the same pixel driving circuit PD, the switch reset transistor T7 is connected to the first reset signal auxiliary line 21 through the first protrusion 211.

[0154] In some embodiments, the display panel includes a plurality of data signal lines DATA arranged along the first direction X, and the first capacitor C1 is located between two adjacent data signal lines DATA; in the same pixel driving circuit PD, both the first protrusion 211 and the second protrusion 43 are located between two adjacent data signal lines DATA.

[0155] Please refer to ​ and ​ , the first conductive layer 50 is disposed on a side of the second gate layer 40 away from the first gate layer 30, and the first conductive layer 50 includes the first control signal line SCAN1, the second control signal line SCAN2, the third control signal line SCAN3, the second reset signal line VI2, the fourth reset signal line VI4, the second power supply signal line VDD, the second jumper wire 51, the third jumper wire 52, the node connection wire 53, the fourth jumper wire 54, the fifth jumper wire 55, the sixth jumper wire 56, the seventh jumper wire 57, the eighth jumper wire 58, the ninth jumper wire 59, the tenth jumper wire 510, the eleventh jumper wire 511, and the twelfth jumper wire 512.

[0156] Among them, please combine ​ , ​ and ​ , the second power supply signal line VDD extends along the first direction X and is connected to the second electrode plate C12.

[0157] The switch gate T1G is connected to the first control signal line SCAN1, and the switch active part T1A is connected to the second jumper wire 51.

[0158] The switch reset gate T7G is connected to the second control signal line SCAN2, and the switch reset active part T7A is connected to the first reset signal auxiliary line 21.

[0159] The third jumper wire 52 is connected between the switch reset active part T7A and the first reset signal auxiliary line 21.

[0160] The first electrode plate C11 and the fourth electrode plate C22 are both connected to the first node N1. Specifically, one end of the node connection line 53 is connected to the first node N1, and the other end of the node connection line 53 is connected to the first electrode plate C11 and the fourth electrode plate C22; the fourth connection line 54 is connected between the second node N2 and the third electrode plate C21; the fifth connection line 55 is connected between the second light-emitting control signal line EM2 and the second light-emitting control gate T9G; the sixth connection line 56 is connected between the first reset signal line VI1 and the first reset active part T4A; the seventh connection line 57 is connected to the second light-emitting control active part T9A; the eighth connection line 58 is connected between the first light-emitting control signal line EM1 and the first light-emitting control gate T8G; the ninth connection line 59 is connected to the fourth node N4; the eleventh connection line 510 is connected between the third reset active part T6A and the first connection line 41, and the third connection line 52 is connected to ​ the third reset signal line VI3 in another repeating unit in the lower middle; the eleventh connection line 511 and the twelfth connection line 512 are both connected between the second reset active part T5A and the second reset signal line VI2. For example, one repeating unit contains three pixel driving circuits PD, and in some of the pixel driving circuits PD, the eleventh connection line 511 is used to connect between the second reset active part T5A and the second reset signal line VI2, and in another part of the pixel driving circuits PD, the twelfth connection line 512 is used to connect between the second reset active part T5A and the second reset signal line VI2.

[0161] Please refer to ​ and ​ , the second conductive layer 60 includes a data signal line DATA extending along the second direction Y, a first power supply signal line 61 extending along the second direction Y, a second reset signal auxiliary line 62 extending along the second direction Y, a functional trace 63 extending along the second direction Y, and an anode connection part 64.

[0162] The data signal line DATA is connected to the second connection line 51, and further the data signal line DATA is connected to the switch active part T1A through the second connection line 51.

[0163] In some embodiments, the fourth control signal line SCAN4 reduces its width at a position close to the fifth jumper wire 64 to avoid the connection control arrangement of the subsequent jumper wire 64 and the anode 71. Moreover, the width of the fourth control signal line SCAN4 at the position close to the fifth jumper wire 64 is less than the width of the second reset gate T5G and also less than the width of the third reset gate T6G.

[0164] In some embodiments, the second conductive layer 60 includes a plurality of the data signal lines DATA arranged along the first direction X and a plurality of the first power supply signal lines 61 arranged along the first direction. Moreover, one of the first power supply signal lines 61 is located between two adjacent data signal lines DATA.

[0165] In some embodiments, within a repeating unit, the data signal lines DATA may include a first data signal line DATA1, a second data signal line DATA2, and a third data signal line DATA3. The first data signal line DATA1, the second data signal line DATA2, and the third data signal line DATA3 are respectively connected to one of the pixel driving circuits PD. For example, the light-emitting device EL corresponding to the pixel driving circuit PD connected to the first data signal line DATA1 emits red light, the light-emitting device EL corresponding to the pixel driving circuit PD connected to the second data signal line DATA2 emits green light, and the light-emitting device EL corresponding to the pixel driving circuit PD connected to the third data signal line DATA3 emits blue light.

[0166] The second reset signal auxiliary line 62 is connected to the third jumper wire 52. Further, the second reset signal auxiliary line 62 is connected to the switch reset active part T7A and the first reset signal auxiliary line 21 through the third jumper wire 52. The first reset signal auxiliary lines 21 extending along the first direction X and the second reset signal auxiliary lines 62 extending along the second direction Y among the plurality of pixel driving circuits PD are connected to form a network, which can reduce the impedance while realizing signal transmission.

[0167] The first power supply signal line 61 is connected to the second power supply signal line VDD and can also be used to transmit a high-level potential. The second power supply signal lines VDD extending along the first direction X and the first power supply signal lines 61 extending along the second direction Y among the plurality of pixel driving circuits PD are connected to form a network, which can reduce the impedance while realizing signal transmission.

[0168] In some embodiments, the first power supply signal line 61 is further connected to the seventh patch cord 57 and is connected to the second light-emitting control active part T9A through the seventh patch cord 57.

[0169] Among them, the first power supply signal line 61 is used to transmit a constant voltage high level, and has a large thickness and width, and the first power supply signal line 61 is located below the light-emitting part 100. Therefore, the first power supply signal line 61 has a great influence on the film layer flatness of the position where the light-emitting part 100 is located. Therefore, in the embodiments of the present application, the first power supply signal line 61 includes an overlapping line segment 611, the light-emitting part 100 includes a bottom surface 1001 on one side close to the first power supply signal line 61, and the orthographic projection of the overlapping line segment 611 on the substrate 10 is located within the orthographic projection of the bottom surface 1001 on the substrate 10. The ratio of the orthographic projection area of the overlapping line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 on the substrate 10 is greater than or equal to 0.5 and less than or equal to 1. Furthermore, in the embodiments of the present application, by increasing the width and coverage range of the overlapping line segment 611, the film layer flatness of the position where the light-emitting part 100 is located can be improved, the film thickness uniformity and yield of the light-emitting part 100 can be improved, and thus the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0170] In some embodiments, the ratio of the orthographic projection area of the overlapping line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 on the substrate 10 is 0.5, 0.6, 0.7, 0.8, 0.9 or 1; further preferably, the ratio of the orthographic projection area of the overlapping line segment 611 on the substrate 10 to the orthographic projection area of the bottom surface 1001 on the substrate 10 is greater than or equal to 0.5 and less than or equal to 0.8.

[0171] In some embodiments, the ratio of the width of the overlapping line segment 611 in the first direction X to the width of the bottom surface 1001 in the first direction X is greater than or equal to 0.5 and less than or equal to 1.

[0172] In some embodiments, the ratio of the width of the overlapping line segment 611 in the first direction X to the width of the bottom surface 1001 in the first direction X is 0.5, 0.6, 0.7, 0.8, 0.9 or 1; further preferably, the ratio of the width of the overlapping line segment 611 in the first direction X to the width of the bottom surface 1001 in the first direction X is greater than or equal to 0.5 and less than or equal to 0.8.

[0173] In some embodiments, the ratio of the width of the overlapping line segment 611 in the first direction X to the width of the bottom surface 1001 in the first direction X is greater than or equal to 0.5 and less than or equal to 1.

[0174] It can be understood that after the width of the first power supply signal line 61 increases, the wiring space in the film layer will be reduced, resulting in a decrease in the distance between adjacent traces, and signal crosstalk is likely to occur.

[0175] In the embodiments of the present application, each of the first power supply signal lines 61 is correspondingly located on one side of a plurality of the pixel driving circuits PD arranged along the second direction Y and is connected to the second light-emitting control transistor T9.

[0176] Each of the data signal lines DATA is correspondingly located on one side of a plurality of the pixel driving circuits PD arranged along the second direction Y and is connected to the switching transistor T1 in the pixel driving circuit PD.

[0177] The second reset signal auxiliary line 62 is located between the first power supply signal line 61 and the data signal line DATA. Wherein, the second reset signal auxiliary line 62 includes a first line segment 621 and a second line segment 622 connected to each other, and the minimum distance L1 between the first line segment 621 and the data signal line DATA is greater than the minimum distance L2 between the second line segment 622 and the data signal line DATA.

[0178] Therefore, due to the increase in the line width of the first power supply signal line 61, the wiring space in the film layer is reduced, the distance between adjacent signal lines is decreased, and the signal crosstalk is enhanced; in the embodiments of the present application, by increasing the distance between the first line segment 621 in the second reset signal auxiliary line 62 and the data signal line DATA, the signal crosstalk between the second reset signal auxiliary line 62 and the data signal line DATA can be effectively reduced, and the signal transmission stability between the second reset signal auxiliary line 62 and the data signal line DATA can be improved.

[0179] It should be noted that in the embodiments of the present application, one second reset signal auxiliary line 62 can be correspondingly set for each of the repeating units, or one second reset signal auxiliary line 62 can be set for multiple repeating units; each of the first power supply signal lines 61 extends along the second direction Y, each of the first power supply signal lines 61 is located on one side of a plurality of the pixel driving circuits PD arranged along the second direction Y, and is electrically connected to the pixel driving circuit PD.

[0180] For a pixel driving circuit PD, the first power supply signal line 61 is disposed near the middle region of the pixel driving circuit PD, and the second reset signal auxiliary line 62 and the data signal line DATA are respectively located on the opposite first side and second side of the pixel driving circuit PD. Further, the second reset signal auxiliary line 62 is closer to the data signal line DATA connected to a pixel driving circuit PD adjacent to the first side. Therefore, the minimum distance between the first line segment 621 and the data signal line DATA can be regarded as the minimum distance between the first line segment 621 and the data signal line DATA connected to a pixel driving circuit PD adjacent to the first side. Similarly, the minimum distance between the second line segment 622 and the data signal line DATA can be regarded as the minimum distance between the second line segment 622 and the data signal line DATA connected to a pixel driving circuit PD adjacent to the second side.

[0181] Each second reset signal auxiliary line 62 is correspondingly located on one side of a plurality of pixel driving circuits PD arranged along the second direction Y, and the second reset signal auxiliary line 62 and the data signal line DATA can be located on opposite sides of the same pixel driving circuit PD. The second reset signal auxiliary line 62 is electrically connected to the switch reset transistor T7 in the pixel driving circuit PD, and the second reset signal auxiliary line 62 is connected to the fourth reset signal line VI4.

[0182] In some embodiments, the minimum distance from the node connection line 53 along the first direction X to the data signal line DATA is greater than or equal to the minimum distance from the second line segment 622 along the first direction X to the data signal line DATA. Further, the side of the node connection line 53 closest to the data signal line DATA will be covered by the second line segment 622, so that the second line segment 622 is spaced between the node connection line 53 and the side of the node connection line 53 closest to the data signal line DATA, to play a shielding role and reduce the signal crosstalk between the node connection point 53 (i.e., the first node N1) and the data signal line DATA.

[0183] Further, the first line segment 621 is parallel to the data signal line DATA. The second line segment 622 includes an intermediate sub - portion 6221 and a connecting sub - portion 6222 connecting the intermediate sub - portion 6221 and the first line segment 621. The intermediate sub - portion 6221 is parallel to the data signal line DATA, and the extending direction of the connecting sub - portion 6222 intersects the data signal line DATA. It should be noted that in the embodiment of the present application, the second reset signal auxiliary line 62 is designed with a broken line at the second line segment 622 in the direction of the data signal line DATA, increasing the distance between the first line segment 621 and the data signal line DATA to reduce the signal crosstalk between the data signal line DATA and the second reset signal auxiliary line 62. And the second line segment 621 is spaced between the node connection line 53 and the data signal line DATA closest to the node connection line 53 to play a shielding role and reduce the signal crosstalk between the node connection point 53 (i.e., the first node N1) and the data signal line DATA.

[0184] Further, in some embodiments, the node connection line 53 and the second line segment 622 have an overlapping portion in the thickness direction of the display panel. The minimum distance from the overlapping portion along the first direction X to the data signal line DATA is greater than or equal to the minimum distance from the second line segment 622 along the first direction X to the data signal line DATA, so as to ensure that the side of the node connection line 53 closest to the data signal line DATA is covered by the second line segment 622.

[0185] In some embodiments, the node connection line 53 is connected to the fourth electrode plate C22. The minimum distance from the fourth electrode plate C22 along the first direction X to the data signal line DATA is greater than or equal to the minimum distance from the second line segment 622 along the first direction X to the data signal line DATA. Since the fourth electrode plate C22 is also electrically connected to the first node N1, in the embodiment of the present application, the second line segment 622 can cover the side of the second substrate C12 closest to the data signal line DATA, and further, the second line segment 621 can be spaced between the first capacitor C12 and the data signal line DATA closest to the first capacitor C12 to play a shielding role and reduce the signal crosstalk between the first node N1 and the data signal line DATA.

[0186] In some embodiments, the second power supply signal line VDD extends along the first direction X. The second power supply signal line VDD includes a plurality of first sub - parts VDD1 arranged along the first direction X. The first sub - parts VDD1 extend along the second direction Y. The first sub - parts VDD1 are located between the node connection line 53 and the data signal line DATA. The first sub - parts VDD1 at least partially overlap with the node connection line 52 along the first direction X.

[0187] Further, the center of the plate connection line 42 extending along the second direction Y is on one side of the center of the data signal line DATA, and the center of the first sub - part VDD1 is on the opposite side of the center of the data signal line DATA; thus, the first sub - part VDD1 and the plate connection line 42 extending along the second direction Y are respectively located on opposite sides of the data signal line DATA, and can be used to shield the signal crosstalk between the data signal line DATA and the first node N1 (i.e., the node connection line 53).

[0188] In some embodiments, a plurality of the first sub - parts VDD1 arranged along the first direction X are correspondingly arranged with a plurality of pixel driving circuits PD arranged along the first direction X. A plurality of the data signal lines DATA are correspondingly connected to a plurality of the pixel driving circuits PD arranged along the first direction X; for the same pixel driving circuit PD, the minimum distance between the fourth electrode plate C22 and the data signal line DATA along the first direction X is greater than or equal to the minimum distance between the first sub - part VDD1 and the data signal line DATA along the first direction X.

[0189] In some embodiments, the second power supply signal line VDD further includes a second sub - part VDD2 connected between adjacent first sub - parts VDD1, and the extending direction of the second sub - part VDD2 intersects both the first direction X and the second direction Y. The acute - angle between the extending direction of the second sub - part VDD2 and the first direction X is less than the acute - angle between the extending direction of the second sub - part VDD2 and the second direction Y.

[0190] In some embodiments, one end of the anode connection part 64 is connected to the ninth jumper wire 59, and the other end of the anode connection part 64 is used to connect to the anode 71.

[0191] The functional trace 63 extends along the second direction Y, and one functional trace 63 can be provided in each repeating unit.

[0192] In some embodiments, the functional trace 63 may extend into the non-display area NA and be connected to a constant low-level signal located in the non-display area NA to form an auxiliary cathode line, reducing the resistance of the cathode in the display panel.

[0193] In some embodiments, the functional trace 63 may be used to connect at least one of the first reset signal line VI1, the second reset signal line VI2, and the third reset signal line VI3 extending along the first direction X to form a mesh trace structure, reducing the trace resistance.

[0194] Please refer to ​ and ​ , the anode layer 70 is disposed on a side of the second flat layer 85 away from the first flat layer 84. The anode layer 70 includes a plurality of anodes 71, and the anodes 71 are connected to the anode connection portion 64, that is, the anodes 71 are connected to the first light-emitting control active portion T8A through the anode connection portion 64.

[0195] Please refer to ​ , the pixel definition layer 86 is disposed on a side of the anode layer 70 away from the second conductive layer 60. A plurality of pixel openings 860 are formed in the pixel definition layer 86, and a partial surface of the corresponding anode 71 is exposed through each pixel opening 860.

[0196] In some embodiments, the pixel definition layer 86 may include a first pixel definition layer 861 and a second pixel definition layer 862. Wherein, the first pixel definition layer 861 may extend along the first direction X, the second pixel definition layer 862 may extend along the second direction Y, and the first pixel definition layer 861 and the second pixel definition layer 862 intersect to enclose the pixel opening 860.

[0197] The light-emitting layer 13 is disposed on the pixel definition layer 86. The light-emitting layer 13 includes a plurality of light-emitting portions 100. The plurality of light-emitting portions 100 are disposed corresponding to the plurality of pixel openings 860. One light-emitting portion 100 is disposed in the corresponding pixel opening 860 and is located on a side of the anode 71 away from the substrate 10.

[0198] In some embodiments, the cathode covers the pixel definition layer 86 and the plurality of light-emitting portions 100, and the stacked anodes 71, the light-emitting portions 100, and the cathode may form the light-emitting device EL.

[0199] In some embodiments, within the same pixel driving circuit PD, the second capacitor C2 and the driving transistor T2 partially overlap in the thickness direction of the display panel. The first capacitor C1 is located between the second capacitor C2 and the switching transistor T1, and the first capacitor is located between the driving transistor T2 and the switching transistor T1.

[0200] Continuing from the above, for the pixel driving circuit PD described in the above embodiments, at least a part of the thin film transistors partially overlap with the overlapping line segment 611 in the first direction X to further increase the coverage range of the overlapping line segment 611.

[0201] In some embodiments, the switching transistor T1 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, the driving transistor T2 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, and the second capacitor C2 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel.

[0202] Among them, in the switching transistor T1, the switching active part T1A partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, the switching gate T1G partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, the driving active part T2A partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, the driving gate T1G partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel, and both the third electrode C21 and the fourth electrode C22 in the second capacitor C2 partially overlap with the overlapping line segment 611 in the thickness direction of the display panel.

[0203] In some embodiments, the first capacitor C1 is electrically connected to the first power supply signal line 61, and the first capacitor C1 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel.

[0204] Among them, both the first electrode C11 and the second electrode C12 in the first capacitor C1 partially overlap with the overlapping line segment 611 in the thickness direction of the display panel.

[0205] In some embodiments, the first reset transistor T4 is located on the side of the driving transistor T2 away from the switching transistor T1, and the first reset transistor T4 partially overlaps with the overlapping line segment 611 in the thickness direction of the display panel.

[0206] Among them, in the first reset transistor T4, the first reset active part T4A and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel, and the first reset gate T4G and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0207] In some embodiments, the compensation transistor T3 is located on a side of the driving transistor T2 away from the switching transistor T1. The compensation transistor T3 and the first reset transistor T4 are arranged adjacent to each other along the first direction X. The compensation transistor T3 and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0208] Among them, in the compensation transistor T3, the compensation active part T3A and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel, and the compensation gate T3G and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0209] It should be noted that the compensation gate T3G and the compensation active part T3A are arranged close to the edge of the bottom surface 1001 of the light emitting part 100. In the embodiments of the present application, the overlapping line segment 611 is arranged to be partially overlapped with the compensation gate T3G and the compensation active part T3A, so as to effectively increase the coverage range of the overlapping line segment 611 and improve the flatness of the film layer where the light emitting part 100 is located.

[0210] In some embodiments, the first light emission control transistor T8 is located on a side of the compensation transistor T3 away from the driving transistor T2, and the first light emission control transistor T8 and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0211] Among them, in the first light emission control transistor T8, the first light emission control active part T8A and the overlapping line segment 611 are partially non - overlapped in the thickness direction of the display panel, and the first light emission control gate T8G and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0212] In some embodiments, the second light emission control transistor T9 is located on a side of the first reset transistor T4 away from the driving transistor T2, and the second light emission control transistor T9 and the overlapping line segment 611 are partially overlapped in the thickness direction of the display panel.

[0213] Among them, in the second light-emitting control transistor T9, the second light-emitting control active part T9A and the overlapping line segment 611 partially overlap in the thickness direction of the display panel, and the second light-emitting control gate T9G and the overlapping line segment 611 partially overlap in the thickness direction of the display panel.

[0214] In some embodiments, the second reset transistor T5 and the overlapping line segment 611 do not partially overlap in the thickness direction of the display panel, and the third reset transistor T6 and the overlapping line segment 611 do not partially overlap in the thickness direction of the display panel.

[0215] Among them, in the second reset transistor T5, both the second reset active part T5A and the second reset gate T5G do not overlap with the overlapping line segment 611 in the thickness direction of the display panel; in the third reset transistor T6, both the third reset active part T6A and the third reset gate T6G do not overlap with the overlapping line segment 611 in the thickness direction of the display panel.

[0216] In some embodiments, the switch reset transistor T7 is disposed adjacent to the switch transistor T1 along the first direction X, and the switch reset transistor T7 and the overlapping line segment 611 partially overlap in the thickness direction of the display panel.

[0217] Among them, in the switch reset transistor T7, the switch reset active part T7A and the overlapping line segment 611 partially overlap in the thickness direction of the display panel, and the switch reset gate T7G and the overlapping line segment 611 partially overlap in the thickness direction of the display panel.

[0218] Further, in some embodiments, please refer to ​, the overlapping line segment 611 includes a first side 6111 and a second side 6112 that are oppositely arranged along the first direction X. In at least a part of the overlapping line segment 611 of the first power supply signal line 61, both the first side 6111 and the second side 6112 are parallel to the second direction Y. For example, in the first power supply signal line 61 adjacent to the first data signal line DATA1, the first side 6111 of the overlapping line segment 611 is parallel to the second direction Y, and a part of the second side 6112 is parallel to the second direction Y. In the first power supply signal line 61 adjacent to the second data signal line DATA2, the first side 6111 of the overlapping line segment 611 is parallel to the second direction Y, and the second side 6112 is parallel to the second direction Y. In the first power supply signal line 61 adjacent to the third data signal line DATA3, the first side 6111 of the overlapping line segment 611 is parallel to the second direction Y, and the second side 6112 is parallel to the second direction Y.

[0219] In summary, in the embodiment of the present application, by providing the first protrusion 211 on the first reset signal auxiliary line 21 and the second protrusion 43 in the first capacitor C1, the overlapping area between the first reset signal auxiliary line 21 and the first capacitor C1 is increased. Furthermore, the total capacitance formed by the first reset signal auxiliary line 21 in the pixel driving circuit PD can be increased, the capacitance ratio between the first reset signal auxiliary line 21 and the data signal line DATA can be reduced, and the signal crosstalk generated by the capacitance formed between the first reset signal auxiliary line 21 and the data signal line DATA can be effectively reduced.

[0220] According to the above object of the present application, an embodiment of the present application further provides a display device, and the display device includes the display panel in the above embodiment.

[0221] It can be understood that since the display device has the same display panel as that in the above embodiment, therefore, the display device has the same beneficial effects as the display panel, and details are not described herein again.

[0222] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0223] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0224] Among the embodiments, implementation manners and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0225] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that, The display panel includes a plurality of pixel driving circuits arranged in a first direction and a second direction, a first reset signal auxiliary line extending in the first direction, and a data signal line extending in the second direction, and the first direction and the second direction intersect each other; The pixel driving circuit includes a first capacitor, a switching transistor connected to the data signal line, and a switching reset transistor connected to the first reset signal auxiliary line, and the switching transistor, the switching reset transistor, and the first capacitor are all connected to a first node; Wherein, the first reset signal auxiliary line and the data signal line partially overlap in the thickness direction of the display panel, the first reset signal auxiliary line includes a first protrusion extending in the second direction, the first capacitor includes a second protrusion extending in the second direction, and the first protrusion and the second protrusion at least partially overlap in the thickness direction of the display panel.

2. The display panel according to claim 1, wherein In the same pixel driving circuit, the first capacitor includes at least two of the second protrusions arranged in the first direction; The first reset signal auxiliary line includes a plurality of the first protrusions arranged in the first direction, and the plurality of the first protrusions in the first reset signal auxiliary line are correspondingly arranged with the plurality of the second protrusions in the plurality of pixel driving circuits arranged in the first direction.

3. The display panel according to claim 2, wherein In the same pixel driving circuit, the first node is located between two adjacent first protrusions.

4. The display panel according to claim 1, wherein In the same pixel driving circuit, the switching reset transistor is connected to the first reset signal auxiliary line through the first protrusion.

5. The display panel according to claim 1, characterized in that The display panel includes a plurality of the data signal lines arranged in the first direction, and the first capacitor is located between two adjacent data signal lines; In the same pixel driving circuit, the first protrusion and the second protrusion are both located between two adjacent data signal lines.

6. The display panel according to claim 1, wherein The switching transistor and the switching reset transistor are adjacent and connected in the first direction, and the first reset signal auxiliary line is located on a side of the first capacitor close to the switching transistor.

7. The display panel according to claim 6, wherein The first protrusion is located on a side of the first reset signal line close to the switching transistor, and the second protrusion is located on a side of the first capacitor close to the switching transistor.

8. The display panel according to any one of claims 1 to 7, characterized in that, The display panel further includes: A substrate; A semiconductor layer disposed on one side of the substrate, the semiconductor layer includes a switching active portion of the switching transistor and the first reset signal auxiliary line, the data signal line is located on a side of a plurality of pixel driving circuits arranged in the second direction, and is connected to the switching active portion in the pixel driving circuit; A first gate layer disposed on a side of the semiconductor layer away from the substrate, the first gate layer includes a first electrode plate of the first capacitor; The second gate layer is disposed on a side of the first gate layer away from the semiconductor layer. The second gate layer includes a second electrode plate of the first capacitor, and the first electrode plate and the second electrode plate are disposed opposite to each other in the thickness direction of the display panel. The second protrusion is connected to the second electrode plate.

9. The display panel according to claim 8, wherein The first electrode plate is connected to the first node.

10. The display panel according to claim 8, characterized in that, The pixel driving circuit further includes a second capacitor connected to the first node. The second capacitor is located on a side of the first capacitor away from the first reset signal auxiliary line. The first gate layer includes a third electrode plate of the second capacitor, and the second gate layer includes a fourth electrode plate of the second capacitor. The third electrode plate and the fourth electrode plate are disposed opposite to each other in the thickness direction of the display panel. The fourth electrode plate is connected to the first node.

11. The display panel according to claim 10, characterized in that, The first protrusion is located on a side of the first reset signal auxiliary line away from the second capacitor, and the second protrusion is located on a side of the second electrode plate away from the second capacitor.

12. The display panel according to claim 10, wherein, The second gate layer further includes a plate connection line connected to the second electrode plate. At least a part of the plate connection line extends along the second direction and is located between two second capacitors in two adjacent pixel driving circuits arranged along the first direction. The plate connection line and the data signal line do not overlap at least partially in the thickness direction of the display panel.

13. The display panel according to claim 12, wherein The plate connection line includes a third line segment extending along the second direction, a fourth line segment extending along the first direction, and a fifth line segment extending along the first direction. The fourth line segment is connected between the third line segment and the fifth line segment, and the third line segment is connected between the fourth line segment and the second electrode plate. The width of the fourth line segment along the second direction is smaller than the width of the fifth line segment along the second direction. The data signal line and the fourth line segment overlap partially in the thickness direction of the display panel, and the data signal line and the fifth line segment do not overlap in the thickness direction of the display panel.

14. The display panel according to claim 13, wherein The pixel driving circuit further includes a driving transistor, a compensating transistor, and a first reset transistor. The driving transistor, the second capacitor, the compensating transistor, and the first reset transistor are all connected to a second node. The driving transistor and the compensating transistor are both connected to a third node. The semiconductor layer further includes a driving active portion of the driving transistor, a compensating active portion of the compensating transistor, and a first reset active portion of the first reset transistor. The compensating active portion is disposed opposite to the fifth line segment in the thickness direction of the display panel, and the first reset active portion is disposed opposite to the fifth line segment in the thickness direction of the display panel.

15. The display panel according to claim 14, wherein The display panel further includes a first power signal line extending along the second direction. The pixel driving circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The first light-emitting control transistor is connected to the third node. The second light-emitting control transistor is connected between the first power signal line and the driving transistor. The second electrode plate is electrically connected to the first power signal line.

16. The display panel according to claim 15, wherein The display panel further includes a second reset signal auxiliary line extending along the second direction, and the second reset signal auxiliary line is located between the first power signal line and the data signal line. Wherein, the second reset signal auxiliary line includes a connected first line segment and a second line segment, and the minimum distance between the first line segment and the data signal line is greater than the minimum distance between the second line segment and the data signal line.

17. The display panel according to claim 16, wherein The first line segment is parallel to the data signal line. The second line segment includes an intermediate sub-part and a connecting sub-part connecting the intermediate sub-part and the first line segment. The intermediate sub-part is parallel to the data signal line, and the extending direction of the connecting sub-part intersects with the data signal line.

18. The display panel according to claim 16, wherein The semiconductor layer further includes a switching reset active part of the switching reset transistor. The switching reset active part and the switching active part are arranged adjacent to each other along the first direction and are connected to the first node. The first reset signal auxiliary line is connected to the switching reset active part. The second reset signal auxiliary line is located on one side of a plurality of the pixel driving circuits arranged along the second direction and is electrically connected to the switching reset active part in the pixel driving circuit.

19. The display panel according to claim 15, wherein The display panel further includes a plurality of light-emitting parts arranged along the first direction and the second direction. A plurality of the light-emitting parts arranged along the second direction are located on one side of a corresponding one of the first power signal lines. Wherein, the first power signal line includes an overlapping line segment. The light-emitting part includes a bottom surface on a side close to the first power signal line. The overlapping line segment and the bottom surface of the light-emitting part overlap in the thickness direction of the display panel. The ratio of the area of the positive projection of the overlapping line segment on the substrate to the area of the positive projection of the bottom surface of the light-emitting part on the substrate is greater than or equal to 0.5 and less than or equal to 1.

20. A display device, characterized in that, The display device includes the display panel according to any one of claims 1 to 19.

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