Reverse overshoot voltage test loop for simulating high voltage rise rate of converter valve and damping loop thereof

Abstract

The invention provides a reverse overshoot voltage test loop for simulating the high voltage rise rate of a converter valve and a damping loop thereof. The reverse overshoot voltage test loop comprises a direct-current energy storage capacitor, a thyristor converter valve, a diode valve, a damping resistor, a wave modulation inductor and a wave modulation resistor, before the voltage of the test product damping capacitor is reversed, the initial voltage value of the test product damping capacitor is zero; when the thyristor converter valve is switched on, the DC energy storage capacitor charges the test damping capacitor through the thyristor converter valve, the wave modulation inductor and the wave modulation resistor, and the energy of the DC energy storage capacitor is transmitted to the test damping capacitor. When the voltage of the sample damping capacitor exceeds that of the direct-current energy storage capacitor, energy is continuously transmitted to the sample damping capacitor from the direct-current energy storage capacitor; when the inductive current crosses zero, the energy of the damping capacitor of the test object is reversely sent to the direct-current energy storage capacitor; and after the inductive current passes zero again, the diode valve is cut off, and the energy exchange process of the direct-current energy storage capacitor and the test damping capacitor disappears. The loop can generate a reverse overshoot voltage with a high voltage rise rate.

Description

Technical Field

[0001] The present invention relates to the field of high-voltage tests, and particularly to a reverse overshoot voltage test circuit for simulating the high-voltage rising rate of a converter valve and its damping circuit. Background Art

[0002] In a high-voltage DC converter valve, each converter valve arm is composed of multiple thyristors connected in series. There are differences in the parameters of thyristor devices. Voltage imbalance problems will occur when thyristors with different parameters are directly connected in series. Overshoot voltages will also appear during the valve commutation process. A damping capacitor is connected in parallel across the thyristor and together with a damping resistor forms a damping circuit, which plays a role in damping and voltage equalization during the conduction and turn-off processes of the thyristor. The damping capacitor bears the switching overshoot voltage for a long time, and a high voltage rising rate du / dt will cause deterioration or even failure of the metallized film capacitor, which needs to be considered emphatically during the performance test stage of capacitor products.

[0003] When the damping capacitor operates normally, the voltage waveform is a sawtooth wave. The most significant feature is that a reverse overshoot voltage will be generated on the damping capacitor at the moment when the parallel-connected thyristor turns off. The voltage rising rate du / dt can reach 130V / μs. The current test and assessment methods for damping capacitors are factory tests, type tests, etc. There is no test for the reverse overshoot voltage tolerance. The existing test methods are different from the actual operating conditions of the damping capacitor, and there is a lack of a circuit for simulating the reverse overshoot voltage on the damping capacitor, resulting in relatively serious failures still occurring in products passing the assessment using conventional test methods during engineering applications. For the assessment of the ability of the damping capacitor to withstand the reverse overshoot voltage, using a test circuit consistent with the converter valve is too costly and the parameters cannot be adjusted. Conventional test circuits are difficult to meet the requirements of du / dt. ZL 202210765303.7 provides a test circuit for assessing the performance of a thyristor converter valve and its damping circuit, which can simulate the actual operating waveform of the damping capacitor. However, the reverse overshoot part of this circuit only generates an overshoot voltage on the test capacitor by the turn-on and turn-off of the thyristor. When du / dt is relatively high, the voltage peak time will be much lower than the recovery time of the thyristor, which may cause the thyristor to mis-trigger again during the turn-off process. Therefore, it is necessary to make an improved design based on ZL 202210765303.7 to ensure the operability of the reverse overshoot voltage with high du / dt and accurately assess the tolerance performance of the damping circuit. Summary of the Invention

[0004] In view of the above technical problems, the present invention provides a reverse overshoot voltage test circuit for simulating the high-voltage rising rate of a converter valve and its damping circuit, which is characterized by including: a DC energy storage capacitor Cdc, a thyristor converter valve Td, a diode valve D, a damping resistor Rr, a wave-shaping inductor Ld, and a wave-shaping resistor Rd;

[0005] Before the voltage of the test sample damping capacitor \(C_d\) reverses, the initial voltage of the DC energy storage capacitor \(C_{dc}\) is \(U_{dc}\), and the initial voltage of the test sample damping capacitor \(C_d\) is zero;

[0006] When the thyristor commutation valve \(T_d\) conducts, the DC energy storage capacitor \(C_{dc}\) charges the test sample damping capacitor \(C_d\) through the thyristor commutation valve \(T_d\), the wave - tuning inductor \(L_d\) and the wave - tuning resistor \(R_d\), and the energy of the DC energy storage capacitor \(C_{dc}\) is delivered to the test sample damping capacitor \(C_d\);

[0007] When the voltage of the test sample damping capacitor \(C_d\) exceeds that of the DC energy storage capacitor \(C_{dc}\), the inductor bears a reverse voltage, the current starts to decline, and the energy continues to be sent from the DC energy storage capacitor \(C_{dc}\) to the test sample damping capacitor \(C_d\);

[0008] When the inductor current passes through zero, due to the existence of the diode valve \(D\), the energy of the test sample damping capacitor \(C_d\) is sent back to the DC energy storage capacitor \(C_{dc}\);

[0009] When the inductor current passes through zero again, the diode valve \(D\) cuts off, and the energy exchange process between the DC energy storage capacitor \(C_{dc}\) and the test sample damping capacitor \(C_d\) disappears.

[0010] Furthermore, it also includes:

[0011] A damping resistor \(R_r\) is added to the branch of the anti - parallel diode valve \(D\); The selection principle of the damping resistor \(R_r\):

[0012]

[0013] Furthermore, it also includes: A reverse over - shoot voltage test circuit, which, together with the DC power supply, the commutation tooth circuit, the flip - over circuit and the forward trigger circuit, constitutes a commutation valve and its damping circuit working condition test circuit, where:

[0014] The DC power supply is connected to the reverse over - shoot voltage test circuit and includes a voltage regulator \(TY\), a step - up transformer \(TF\), a rectifier bridge \(Rec\), and a current - limiting resistor \(R_{dc}\);

[0015] One end of the reverse over - shoot voltage test circuit is connected to the DC power supply, and the other end is respectively connected to the commutation tooth circuit, the flip - over circuit, the forward trigger circuit and an additional auxiliary capacitor;

[0016] The commutation tooth circuit includes an auxiliary valve \(Q_g\), a diode valve \(D_2\) and a power - consuming resistor \(R_{g2}\);

[0017] The flip - over circuit includes a flip - over inductor \(L_s\) and flip - over auxiliary valves \(T_{s1}\) and \(T_{s2}\);

[0018] The forward trigger circuit includes a test sample thyristor \(T_f\) and a damping resistor \(R_f\).

[0019] Furthermore, the inversion circuit realizes multiple inversions of the damping capacitor voltage by means of the antiparallel valve composed of inversion auxiliary thyristor valves Ts1 and Ts2, simulating the double-trigger process occurring in the commutation valve under the 90-degree condition.

[0020] Furthermore, a discharging branch is connected in parallel to the DC energy storage capacitor Cdc, including a discharging switch Kg1 and a discharging resistor Rg1.

[0021] Furthermore, the system states of the commutation valve and its damping circuit working condition test circuit include a shutdown state, a charging state, and an operating state, including:

[0022] In the shutdown state, it is disconnected from the external power supply, Kg1 is closed, the voltage regulator is at zero position, and the valve is blocked.

[0023] In the charging state, after the commutation valve and its damping circuit working condition test circuit are connected to the external power supply, Kg1 is opened, the valve is blocked. In this state, the system charges the DC support capacitor Cdc by controlling the operation of the voltage regulator according to the background command until the DC bus voltage Udc reaches the command value.

[0024] In the operating state, Kg1 is opened, the valve is unlocked, and the system enters the operating state according to the control timing sequence.

[0025] Furthermore, in the operating state, test waveforms corresponding to typical working conditions are generated on the commutation valve and its damping circuit by controlling the triggering timing sequence of the valve, including:

[0026] In the single-trigger operating mode, the inversion auxiliary thyristor valve Ts2 is blocked; the thyristor commutation valve Td, the auxiliary valve Qg, the inversion auxiliary thyristor valve Ts1, and the test thyristor Tf are triggered according to the preset sequence control timing. The operating cycle is 20 ms, and the voltage waveforms of the commutation valve and its damping circuit are obtained correspondingly.

[0027] In the 90° triggering operating mode, the auxiliary valve Qg does not participate. The thyristor commutation valve Td, the auxiliary valve Qg, the inversion auxiliary thyristor valve Ts1, and the test thyristor Tf are triggered according to the preset sequence control timing, with a period of 20 ms. The voltage waveforms of the commutation valve and its damping circuit are obtained correspondingly.

[0028] Furthermore, when the test circuit capacitor is at three levels of 2.5 uF, 5 uF, and 10 uF, the adjustable reverse overshoot voltage du / dt of the test capacitor is realized through several sets of wave-adjusting inductors and wave-adjusting resistors that have been set. When the capacitance value of the test capacitor deviates from the above three levels, an auxiliary capacitor is connected in parallel at both ends of the test capacitor to adjust the test capacitor to a fixed value for testing.

[0029] The present invention provides a reverse overshoot voltage test circuit for simulating a commutation valve and its damping circuit with a high voltage rise rate, which can generate a reverse overshoot voltage with a du / dt not less than 130 V / μs on the commutation valve and its damping circuit, and the overshoot peak value and rise rate are adjustable, providing a simple test circuit for generating an overshoot voltage on the commutation valve and its damping circuit. This test circuit and control method can simulate the electrical stress conditions under normal operating conditions and 90° operating conditions of the commutation valve and its damping circuit, and solve the problem that the conventional test circuits and methods in the existing standards cannot accurately evaluate the actual operating performance of the product. This circuit can be used to evaluate the reliable performance of the thyristor commutation valve and its damping circuit during long-term operation under actual operating conditions, and has important application value for improving the accuracy of performance evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is the schematic diagram of the damping capacitor reverse overshoot test circuit provided by an embodiment of the present invention;

[0031] Figure 2 is the schematic diagram of the commutation valve and its damping circuit working condition test circuit provided by an embodiment of the present invention;

[0032] Figure 3 is the voltage waveform diagram and corresponding trigger timing generated by the working condition test circuit in the single trigger operation mode provided by an embodiment of the present invention;

[0033] Figure 4 is the voltage waveform diagram and corresponding trigger timing generated by the working condition test circuit in the 90° trigger operation mode provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0035] The present invention provides a reverse overshoot voltage test circuit for simulating a commutation valve and its damping circuit with a high voltage rise rate, the principle of which is as Figure 1 shown, including: a DC energy storage capacitor Cdc, a thyristor commutation valve Td, a diode valve D, a damping resistor Rr, a wave-shaping inductor Ld, and a wave-shaping resistor Rd;

[0036] Before the voltage of the test product damping capacitor Cd reverses, the initial voltage value of the DC energy storage capacitor Cdc is Udc, and the initial voltage value of the test product damping capacitor Cd is zero;

[0037] When the thyristor commutation valve Td is conducting, the DC energy storage capacitor Cdc charges the test sample damping capacitor Cd through the thyristor commutation valve Td, the wave tuning inductor Ld, and the wave tuning resistor Rd. The energy of the DC energy storage capacitor Cdc is transferred to the test sample damping capacitor Cd.

[0038] When the voltage of the test sample damping capacitor Cd exceeds that of the DC energy storage capacitor Cdc, the inductor bears a reverse voltage and the current starts to decrease. The energy continues to be sent from the DC energy storage capacitor Cdc to the test sample damping capacitor Cd.

[0039] When the inductor current passes through zero, due to the existence of the diode valve D, the energy of the test sample damping capacitor Cd is sent back to the DC energy storage capacitor Cdc.

[0040] After the inductor current passes through zero again, the diode valve D turns off and the energy exchange process between the DC energy storage capacitor Cdc and the test sample damping capacitor Cd disappears.

[0041] The Laplace transform of the voltage of the test sample damping capacitor Cd is as follows:

[0042]

[0043] Where: U dc is the initial voltage of Cdc;

[0044] Let the equivalent capacitance after the test sample damping capacitor Cd and the DC energy storage capacitor Cdc are connected in series be Ce, then the above formula can be converted to:

[0045]

[0046] Taking the voltage of the test sample damping capacitor Cd in formula (2) as the step response of a second-order system, the time-domain form of the unit step response is:

[0047]

[0048] Where: ζ is the damping coefficient, ω d is the damped oscillation angular frequency of the system;

[0049]

[0050] The peak voltage time tp is as follows:

[0051]

[0052] Substituting formula (7) into formula (3), the peak voltage can be obtained as:

[0053]

[0054] According to theoretical analysis, when du / dt > 130 V / μs, the peak time of the circuit is about 172 μs, which is much lower than the thyristor recovery time. When achieving a high voltage rise rate du / dt while ensuring that the thyristor valve Td has sufficient recovery time, a damping resistor Rr is added to the branch of the antiparallel diode valve D to avoid misfiring of Td;

[0055] Selection principle of the damping resistor Rr:

[0056]

[0057] As Figure 2 shown, the reverse overshoot voltage test circuit for simulating the high voltage rise rate of the converter valve and its damping circuit, where:

[0058] DC power supply, connected to the reverse overshoot voltage test circuit, including a voltage regulator TY, a step-up transformer TF, a rectifier bridge Rec, and a current-limiting resistor Rdc;

[0059] Reverse overshoot voltage test circuit, one end of which is connected to the DC power supply, and the other end is respectively connected to the commutation tooth circuit, the flip circuit, the forward trigger circuit, and an additional auxiliary capacitor;

[0060] Commutation tooth circuit, including:

[0061] Auxiliary valve Qg, diode valve D2, and energy-consuming resistor Rg2.

[0062] Flip circuit, including:

[0063] Flip inductor Ls, and flip auxiliary thyristor valves Ts1 and Ts2;

[0064] Forward trigger circuit, including the test thyristor Tf and the damping resistor Rf.

[0065] The flip circuit realizes multiple flips of the damping capacitor voltage through the antiparallel valve formed by the flip auxiliary thyristor valves Ts1 and Ts2, simulating the double-trigger process that occurs in the converter valve under the 90-degree condition.

[0066] A discharge branch is connected in parallel beside the DC energy storage capacitor Cdc, including a discharge switch Kg1 and a discharge resistor Rg1, which are used to discharge the remaining energy of Cdc and improve the safety of the test circuit.

[0067] The system states of the converter valve and its damping circuit working condition test circuit include a shutdown state, a charging state, and an operating state, including:

[0068] In the shutdown state, it is disconnected from the external power supply, Kg1 is closed, the voltage regulator is in the zero position, and the valve is blocked. In this state, the test system is in a safe state, allowing personnel to perform operations such as wiring and opening the safety door;

[0069] When in the charging state, after the commutation valve and its damping circuit test circuit are connected to an external power supply, Kg1 opens, the valve is blocked. In this state, the system charges the DC support capacitor Cdc by controlling the action of the voltage regulator according to the background command until the DC bus voltage Udc reaches the command value;

[0070] When in the operating state, Kg1 opens, the valve is unlocked, and the system enters the operating state according to the control timing sequence.

[0071] In the operating state, test waveforms corresponding to the working conditions are generated on the commutation valve and its damping circuit by controlling the trigger timing sequence of the valve, including:

[0072] In the single-trigger operation mode, the reverse-assist thyristor valve Ts2 is blocked; the thyristor commutation valve Td, the assist valve Qg1, the reverse-assist thyristor valve Ts1, and the test thyristor Tf are triggered according to the preset sequential control timing sequence. The operation period is 20 ms, and the voltage waveforms of the commutation valve and its damping circuit are obtained correspondingly, as Figure 3 shown;

[0073] Table 1 Trigger times (ms) of each valve in the single-trigger operation mode

[0074]

[0075]

[0076] In the 90° trigger operation mode, the assist valve Qg does not participate. The thyristor commutation valve Td, the assist valve Qg, the reverse-assist thyristor valve Ts1, and the test thyristor Tf are triggered according to the preset sequential control timing sequence, and the period is 20 ms. The voltage waveforms of the commutation valve and its damping circuit are obtained correspondingly, as Figure 4 shown.

[0077] Table 2 Trigger times (ms) of each valve in the 90° trigger operation mode

[0078] Td valve Ts1 valve Ts2 valve Tf valve 0.0000 2.5614 4.0789 15.0000 1.0526 7.0352 8.5526 / 5.5263 11.5789 / / 10.0000 / / /

[0079] For the said test circuit, when in the shutdown state, it is disconnected from the external power supply, Kg1 is closed, the voltage regulator is in the zero position, and the valve is blocked. In this state, the test system is in a safe state, allowing personnel to perform operations such as wiring and opening the safety door.

[0080] For the said test circuit, when in the charging state, after the circuit is connected to the external power supply, Kg1 opens, the valve is blocked. In this state, the test system charges the DC support capacitor Cdc by controlling the action of the voltage regulator according to the background command until the DC bus voltage Udc reaches the command value.

[0081] Considering that the capacitance value range of the damping capacitor of the test sample is 0.05 uF to 10 μF, if it is necessary to achieve adjustable du / dt of the reverse overshoot voltage, theoretically, an infinite number of groups of wave - tuning parameters are required to cooperate with it to generate the required electrical stress, which is unrealistic both economically and technically. Therefore, it is considered to connect an auxiliary capacitor in parallel at both ends of the test sample and adjust the test - sample capacitor to a fixed value for testing. The auxiliary capacitor is equipped with 5 groups of 1 - uF capacitors, which are connected in parallel according to the demand of the test - sample capacitor, and the total capacitance is controlled at about 2.5 uF, 5 uF and 10 uF. In this way, the adjustable du / dt of the reverse overshoot voltage of the test - sample capacitor can be achieved through a fixed number of groups of wave - tuning inductors and wave - tuning resistors.

[0082] A test circuit for the reverse overshoot voltage of a quasi - converter valve and its damping circuit provided by the present invention can generate a reverse overshoot voltage with du / dt not less than 130 V / μs on the converter valve and its damping circuit, and the overshoot peak value and the rising rate are adjustable. It provides a simple test circuit for generating overshoot voltage on the converter valve and its damping circuit. This test circuit and control method can simulate the electrical stress conditions under the normal operating conditions and 90° operating conditions of the converter valve and its damping circuit, and solve the problem that the conventional test circuits and methods in the existing standards cannot accurately evaluate the actual operating performance of the product. This circuit can be used to evaluate the reliable performance of the thyristor converter valve and its damping circuit during long - term operation under actual operating conditions, and has important application value for improving the accuracy of performance evaluation.

[0083] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer - usable storage media (including but not limited to disk storage, CD - ROM, optical storage, etc.) containing computer - usable program code.

[0084] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and the combination of processes and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general - purpose computers, special - purpose computers, embedded processors, or other programmable data - processing devices to generate a machine, so that the instructions executed by the processors of the computer or other programmable data - processing devices generate means for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0085] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction device that implements the functions specified in one or more processes and / or blocks Figure 1 in one or more processes and / or blocks Figure 1 specified in the function.

[0086] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are performed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes and / or blocks Figure 1 in one or more processes and / or blocks Figure 1 specified in the function.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that the specific implementation manners of the present invention can still be modified or equivalently replaced, and any modification or equivalent replacement without departing from the spirit and scope of the present invention should be covered by the scope of the claims of the present invention.

Claims

1. A reverse overshoot voltage test circuit simulating the high voltage rise rate of a converter valve and its damping circuit, characterized in that: include: DC energy storage capacitor Cdc, thyristor commutation valve Td, diode valve D, damping resistor Rr, wave modulation inductor Ld, wave modulation resistor Rd; Before the voltage of the test sample's damping capacitor Cd is reversed, the initial voltage value of the DC energy storage capacitor Cdc is Udc, and the initial voltage value of the test sample's damping capacitor Cd is zero; When the thyristor commutator valve Td is turned on, the DC energy storage capacitor Cdc charges the test sample damping capacitor Cd through the thyristor commutator valve Td, the wave modulation inductor Ld and the wave modulation resistor Rd, and the energy of the DC energy storage capacitor Cdc is transferred to the test sample damping capacitor Cd; When the voltage of the test sample's damping capacitor Cd exceeds that of the DC energy storage capacitor Cdc, the inductor is subjected to reverse pressure, the current begins to decrease, and energy is continuously transferred from the DC energy storage capacitor Cdc to the test sample's damping capacitor Cd; When the inductor current passes through zero, due to the presence of the diode valve D, the energy of the test sample's damping capacitor Cd is fed back to the DC energy storage capacitor Cdc. When the inductor current passes through zero again, the diode valve D is cut off, and the energy exchange process between the DC energy storage capacitor Cdc and the sample damping capacitor Cd disappears.

2. The test circuit according to claim 1, characterized in that Also includes: Add a damping resistor Rr to the branch of the anti-parallel diode valve D; the selection principle of the damping resistor Rr is:

3. The test circuit according to claim 1, characterized in that Also includes: The reverse overshoot voltage test circuit, together with the DC power supply, commutation tooth circuit, flip circuit and forward trigger circuit, constitutes the working condition test circuit of the commutation valve and its damping circuit, where: A DC power supply is connected to a reverse overshoot circuit, comprising a voltage regulator TY, a step-up transformer TF, a rectifier bridge Rec, and a current limiting resistor Rdc; A reverse overshoot voltage test circuit, one end of which is connected to a DC power supply, and the other end is connected to the commutation tooth circuit, the flip circuit, the forward trigger circuit and the additional auxiliary capacitor; The commutation tooth circuit includes an auxiliary valve Qg, a diode valve D2 and an energy-consuming resistor Rg2; A reversing circuit, comprising a reversing inductor Ls and reversing auxiliary valves Ts1 and Ts2; The forward trigger circuit includes the test thyristor Tf and the damping resistor Rf.

4. The test circuit according to claim 3, characterized in that The flipping circuit realizes multiple flips of the damping capacitor voltage by flipping the anti-parallel valve composed of auxiliary thyristor valves Ts1 and Ts2, simulating the double triggering process of the converter valve under the 90-degree working condition.

5. The test circuit according to claim 3, characterized in that An energy dissipation branch is connected in parallel next to the DC energy storage capacitor Cdc, and includes an energy dissipation switch Kg1 and an energy dissipation resistor Rg1.

6. The test circuit according to claim 3, characterized in that The system states of the converter valve and its damping circuit operating test circuit include shutdown state, charging state, and operating state, including: In the shutdown state, disconnect from the external power supply, close Kg1, the voltage regulator is at zero position, and the valve is locked; In the charging state, after the converter valve and its damping circuit operating test circuit are connected to the external power supply, Kg1 is opened and the valve is locked. In this state, the system charges the DC support capacitor Cdc by controlling the voltage regulator according to the background instructions until the DC bus voltage Udc reaches the command value; In the running state, Kg1 is opened, the valve is unlocked, and the system enters the running state according to the control sequence.

7. The test circuit according to claim 6, characterized in that In the operating state, the trigger sequence of the control valve is used to generate test waveforms corresponding to typical operating conditions on the converter valve and its damping circuit, including: In the single-shot operation mode, the flip auxiliary thyristor valve Ts2 is locked; the thyristor commutator valve Td, the auxiliary valve Qg, the flip auxiliary thyristor valve Ts1, and the test thyristor Tf are triggered according to the preset sequential control timing, with an operation cycle of 20ms. The corresponding voltage waveform of the commutator valve and its damping circuit is obtained; In the 90° triggering mode, auxiliary valve Qg is not involved. The thyristor converter valve Td, auxiliary valve Qg, flip-up auxiliary thyristor valve Ts1, and test thyristor Tf are triggered according to the preset sequential control sequence with a period of 20ms. The corresponding voltage waveforms of the converter valve and its damping circuit are obtained.

8. The test circuit according to claim 1, characterized in that When the test loop capacitance is at three gears, 2.5uF, 5uF and 10uF, the reverse overshoot voltage du / dt of the test capacitance can be adjusted through several sets of pre-set modulation inductors and modulation resistors. When the capacitance value of the test capacitance deviates from the above three gears, auxiliary capacitors are connected in parallel at both ends of the test capacitance to adjust the test capacitance to a fixed value for testing.

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