Test circuit, working method thereof and layout test circuit

Abstract

A test circuit, a working method thereof and a layout test circuit are used for performing performance test on a digital unit, the test circuit comprises at least two ring oscillation circuits which are connected in series, each ring oscillation circuit comprises main test units which are connected in series in odd number stages, each main test unit comprises a main test input end and a main test output end, the main measurement output end of each main measurement unit is connected with the main measurement input end of the next-stage main measurement unit, and the main measurement output end of the last-stage main measurement unit is connected with the main measurement input end of the first-stage main measurement unit; and the plurality of load units are connected to each main test input end in parallel, the main test units and the load units are the same digital units, and the number of the load units on the main test input end in each ring oscillation circuit is different.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a testing circuit and a working method thereof, and a layout testing circuit. Background Art

[0002] In semiconductor design, a standard cell is a method for designing application-specific integrated circuits (ASICs) with primarily digital logic features. A standard cell is a group of transistors and interconnects that provide a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverter) or a memory function (flip-flop or latch).

[0003] The key performance indicators of standard cell design are frequency and power consumption, and these two parameters also affect the frequency and power consumption results of the final chip. Improving the accuracy of standard cell frequency and power consumption evaluation and verification, so that they are closer to actual manufacturing test values, can improve the accuracy of subsequent chip design, reduce design verification deviations, and improve chip quality from design to final manufacturing.

[0004] However, the typical parameters of existing digital units are generally obtained by extracting RC parasitic parameters, and additional computing tools are required to perform complex calculations to obtain the input and output capacitance or resistance values. This is not conducive to directly evaluating the pros and cons of layout design and guiding layout optimization, and reduces the speed of layout optimization and the working performance of the layout. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a test circuit and a working method thereof, and a layout test circuit, so as to improve the speed of layout optimization and the working performance of the layout.

[0006] To solve the above technical problems, an embodiment of the present invention provides a test circuit for performing performance testing on a digital unit, comprising: at least two ring oscillator circuits connected in series, each ring oscillator circuit including an odd number of main test units connected in series, each of the main test units including a main test input and a main test output, the main test output of each main test unit being connected to the main test input of a subsequent main test unit, and the main test output of the last main test unit being connected to the main test input of the first main test unit; and a plurality of load units connected in parallel to the main test inputs, the main test units and the load units being the same digital unit, and the number of load units on the main test input in each ring oscillator circuit being different.

[0007] Optionally, the main measurement unit and the load unit include: an input capacitor, a first end of the input capacitor is connected to the main measurement input end; an input resistor, a first end of the input resistor is connected to the main measurement input end; a unit to be measured, a first end of the unit to be measured is connected to the second end of the input resistor; an output resistor, a first end of the output resistor is connected to the second end of the unit to be measured, and the second end of the output resistor is connected to the main measurement output end; an output capacitor, a first end of the output capacitor is connected to the second end of the output resistor and the main measurement output end.

[0008] Optionally, the number of the load units ranges from 1 to 8.

[0009] Optionally, the number of load units connected in parallel on the main test input terminals of different levels is the same, and the main test units of different levels are the same digital units.

[0010] Optionally, the main test unit and the load unit are a combination of one or more of an AND gate circuit standard unit, an OR gate circuit standard unit, and a multiplexer standard unit.

[0011] Optionally, the main testing unit has at least one input terminal, and one of the at least one input terminal is the main testing input terminal.

[0012] Optionally, the test circuit also includes: a test module, used to apply a first voltage V1 to the power supply voltage end, apply a start signal to the main test input end of the first-level main test unit, generate an oscillation signal in the ring oscillation loop, and then obtain the electrical parameters of the main test unit; based on the electrical parameters, obtain the performance parameters of the main test unit.

[0013] Optionally, the test circuit also includes: a test module, used to apply a first voltage V1 to the power supply voltage end, apply a start signal to the main test input end of the first-level main test unit, generate an oscillation signal in the ring oscillation loop, and then obtain the electrical parameters of the main test unit; based on the electrical parameters, obtain the performance parameters of the main test unit.

[0014] Optionally, obtaining the input capacitance value, output capacitance value, and output resistance value of the main measurement unit according to the first frequency f and the first current I1 includes: obtaining the delay time t according to the first frequency f delay =1 / f; According to the first current I1 and the delay time t delay , the power consumption of the main test unit is obtained as P=I1*V1*t delay ; Get the delay time t delay The first linear relationship t between the input capacitance Cin, the output capacitance Cout and the output resistance Rout delay=FO*Rout*Cin+Rout*Cout; obtain the second linear relationship between the power consumption P of the main test unit and the input capacitance value and the output capacitance value P=FO*(Cin+Cout)*V1 2 , where FO is the load quantity value; for the delay time t in the first linear relationship delay A linear fitting analysis is performed on the power consumption P and the load quantity value FO to obtain a first slope Rout*Cin and an intercept Rout*Cout; a linear fitting analysis is performed on the power consumption P and the load quantity value FO in the second linear relationship to obtain a second slope Cin+Cout; according to the first slope Rout*Cin, the intercept Rout*Cout and the second slope Cin+Cout, the input capacitance value Cin, the output capacitance value Cout and the output resistance value Rout are obtained.

[0015] Correspondingly, the technical solution of the present invention also provides a working method of a test circuit, wherein the test circuit includes at least two ring oscillation circuits connected in series, each ring oscillation circuit includes an odd number of main measuring units connected in series, each main measuring unit includes a main measuring input terminal and a main measuring output terminal, the main measuring output terminal of each main measuring unit is connected to the main measuring input terminal of the next stage main measuring unit, and the main measuring output terminal of the last stage main measuring unit is connected to the main measuring input terminal of the first stage main measuring unit; a plurality of load units, wherein the plurality of load units are connected in parallel to each main measuring input terminal, the main measuring unit and the load units are the same digital units, and the number of load units on the main measuring input terminal of each ring oscillation circuit is different, including: applying a first voltage V1 to the power supply voltage terminal, applying a start signal to the main measuring input terminal of the first stage main measuring unit to generate an oscillation signal in the ring oscillation circuit, and obtaining the electrical parameters of the main measuring unit after generating an oscillation signal in the ring oscillation circuit; and obtaining the performance parameters of the main measuring unit based on the electrical parameters.

[0016] Optionally, the electrical parameters of the main measuring unit are obtained, and the method for obtaining the performance parameters of the main measuring unit based on the electrical parameters includes: obtaining the first frequency f and the first current I1 of the ring oscillation circuit at the power supply voltage end; and obtaining the input capacitance value, output capacitance value and output resistance value of the main measuring unit based on the first frequency f and the first current I1.

[0017] Optionally, obtaining the input capacitance value, output capacitance value, and output resistance value of the main measurement unit according to the first frequency f and the first current I1 includes: obtaining the delay time t according to the first frequency f delay =1 / f; According to the first current I1 and the delay time t delay , the power consumption of the main test unit is obtained as P=I1*V1*t delay ; Get the delay time t delay The first linear relationship t between the input capacitance Cin, the output capacitance Cout and the output resistance Routdelay =FO*Rout*Cin+Rout*Cout; obtain the second linear relationship between the power consumption P of the main test unit and the input capacitance value and the output capacitance value P=FO*(Cin+Cout)*V1 2 , where FO is the load quantity value; for the delay time t in the first linear relationship delay A linear fitting analysis is performed on the power consumption P and the load quantity value FO to obtain a first slope Rout*Cin and an intercept Rout*Cout; a linear fitting analysis is performed on the power consumption P and the load quantity value FO in the second linear relationship to obtain a second slope Cin+Cout; according to the first slope Rout*Cin, the intercept Rout*Cout and the second slope Cin+Cout, the input capacitance value Cin, the output capacitance value Cout and the output resistance value Rout are obtained.

[0018] Correspondingly, the technical solution of the present invention also provides a layout test circuit, including: a ring oscillation circuit, including an odd number of main test unit layouts connected in series, each main test unit layout including a main test input terminal and a main test output terminal, the main test output terminal of each main test unit layout is connected to the main test input terminal of the next level main test unit layout, and the main test output terminal of the last level main test unit layout is connected to the main test input terminal of the first level main test unit layout; a plurality of load unit layouts, the plurality of load unit layouts are connected in parallel to each main test input terminal, the main test unit layout and the load unit layout are the same digital unit layout, and the number of load unit layouts on the main test input terminal in each ring oscillation circuit is different.

[0019] Optionally, the main test unit layout and the load unit layout include: an input capacitor, a first end of the input capacitor is connected to the main test input terminal; an input resistor, a first end of the input resistor is connected to the main test input terminal; a unit to be tested layout, a first end of the unit to be tested layout is connected to the second end of the input resistor; an output resistor, a first end of the output resistor is connected to the second end of the unit to be tested layout, and the second end of the output resistor is connected to the main test output terminal; an output capacitor, a first end of the output capacitor is connected to the second end of the output resistor and the main test output terminal.

[0020] Optionally, the number of the load unit layouts ranges from 1 to 8.

[0021] Optionally, the number of load unit layouts connected in parallel on the main test input terminals of different levels is the same, and the main test unit layouts of different levels are the same digital unit layouts.

[0022] Optionally, the main test unit layout and the load unit layout are a combination of one or more of an AND gate circuit standard cell layout, an OR gate circuit standard cell layout, and a multiplexer standard cell layout.

[0023] Optionally, the main test unit layout has at least one input terminal, and one of the at least one input terminal is the main test input terminal.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] The test circuit provided by the technical solution of the present invention connects odd-numbered main test units in series to form several ring oscillation loops, connects several load units in parallel to each main test input end, and has a different number of load units at the main test output end of each ring oscillation circuit. By measuring the delay time and current of each ring oscillation loop, the performance and power consumption of the main test unit are obtained, thereby implementing testing of the main test unit and improving optimization speed and working performance.

[0026] Furthermore, the number of load units in the technical solution of the present invention can be flexibly selected according to the test requirements, so as to realize the accurate measurement of the input capacitance value, output capacitance value and output resistance value of the main test unit, and optimize the main test unit according to the input capacitance value, output capacitance value and output resistance value of the main test unit, thereby improving the optimization speed and working performance.

[0027] The working method of the test circuit provided by the technical solution of the present invention obtains the electrical parameters of the main test unit during the oscillation of the ring oscillation loop, and obtains the performance parameters of the main test unit based on the electrical parameters, thereby improving the optimization speed and working performance, and thus realizing the performance testing of the main test unit and the optimization of the main test unit.

[0028] Furthermore, by obtaining the first frequency on the main measurement input end, the first voltage V1 on the power supply voltage end, and the first current flowing through the power supply voltage end, the delay time and power consumption of the ring oscillation loop, as well as the first linear relationship between the delay time and the input capacitance value, the output capacitance value, and the output resistance value, and the second linear relationship between the power consumption of the main measurement unit and the input capacitance value and the output capacitance value are obtained. By performing linear fitting analysis on the first linear relationship and the second linear relationship, the input capacitance value, the output capacitance value, and the output resistance value are obtained, thereby improving the optimization speed and working performance, thereby realizing the testing of the performance of the main measurement unit and the optimization of the main measurement unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic structural diagram of a test circuit in one embodiment of the present invention;

[0030] Figure 2 1 is a schematic structural diagram of a main test unit in a test circuit according to an embodiment of the present invention;

[0031] Figure 3Schematic diagram of the linear relationship between delay time and load quantity value in a test circuit in one embodiment of the present invention;

[0032] Figure 4 Schematic diagram of the linear relationship between power consumption and load quantity in a test circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As mentioned in the background technology, the optimization speed and working performance of the current digital unit layout need to be further improved.

[0034] The capacitance and resistance of digital cells significantly impact their speed and power consumption. Capacitance originates from within transistors and metal interconnects, while resistance originates from metal interconnects and vias. Obtaining the resistance and capacitance of input and output terminals can better guide digital cell circuit and layout design, ultimately achieving target performance. Furthermore, this allows for timely process monitoring and optimization, enhancing product competitiveness.

[0035] The typical parameters of existing digital units, namely the resistance and capacitance of the input and output ends, are generally obtained by extracting RC parasitic parameters. Additional calculation tools are required to perform complex calculations to obtain the input and output capacitance or resistance values. This is not conducive to directly evaluating the pros and cons of layout design and guiding layout optimization, reducing the speed of layout optimization and the working performance of the layout.

[0036] To address the above-mentioned problems, the present invention provides a test circuit, an operating method thereof, and a layout test circuit. By connecting odd-numbered main test units in series to form a plurality of ring oscillation circuits, a plurality of load units are connected in parallel to each main test input terminal, and the number of load units at the main test output terminal of each ring oscillation circuit is different. By measuring the delay time and current of each ring oscillation circuit, the performance and power consumption of the main test unit are obtained, thereby implementing testing of the main test unit and improving optimization speed and working performance.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figure 1 FIG. 1 is a schematic structural diagram of a test circuit in one embodiment of the present invention.

[0039] Please refer to Figure 1The test circuit is used to perform performance testing on a digital unit, and includes: at least two ring oscillator circuits 1 connected in series, each ring oscillator circuit 1 including an odd number of main test units 2 connected in series, each main test unit 2 including a main test input and a main test output, the main test output of each main test unit 2 being connected to the main test input of the main test unit 2 of the next stage, and the main test output of the main test unit 2 of the last stage being connected to the main test input of the main test unit 2 of the first stage; and a plurality of load units 3 connected in parallel to each main test input, the main test units 2 and the load units 3 being the same digital unit, and the number of load units 3 on the main test input of each ring oscillator circuit 1 being different.

[0040] The number of the load units 3 ranges from 1 to 8.

[0041] In this embodiment, the number of load units 3 connected in parallel on the main test input terminals of different levels is the same, and the main test units 2 of different levels are the same digital units.

[0042] The main test unit 2 and the load unit 3 are a combination of one or more of an AND gate circuit standard unit, an OR gate circuit standard unit, and a multiplexer standard unit. The technical solution of the present invention is not limited to this, and combinations of other standard units are within the protection scope of the present invention.

[0043] The main measuring unit 2 has at least one input terminal, one of which is the main measuring input terminal.

[0044] Specifically, the number of levels of the main testing unit 2 can be 3, or any odd number of levels such as 5 or 7, and the present invention does not limit this. The number of levels of the main testing unit 2 can be set according to actual testing requirements.

[0045] Specifically, when any master testing unit 2 in the odd-numbered stages of master testing units 2 is the current unit to be tested, all standard cells in the master testing unit 2 in the next stage are fan-outs of the current unit to be tested.

[0046] In the above scheme, an odd number of main test units are connected in series to form several ring oscillation loops, and several load units are connected in parallel to each main test input end. The number of load units on the main test output end of each ring oscillation circuit is different. By measuring the delay time and current of each ring oscillation loop, the performance and power consumption of the main test unit are obtained, and then the main test unit is tested, thereby improving the optimization speed and working performance.

[0047] Figure 2 FIG. 1 is a structural diagram of the main testing unit 2 in the testing circuit according to an embodiment of the present invention.

[0048] Please refer to Figure 2The main measuring unit 2 and the load unit 3 include: an input capacitor 201, a first end of the input capacitor 201 is connected to the main measuring input terminal; an input resistor 2, a first end of the input resistor 2 is connected to the main measuring input terminal; a unit to be measured 203, a first end of the unit to be measured 203 is connected to the second end of the input resistor 2; an output resistor 204, a first end of the output resistor 204 is connected to the second end of the unit to be measured 203, and a second end of the output resistor 204 is connected to the main measuring output terminal; an output capacitor 205, a first end of the output capacitor 205 is connected to the second end of the output resistor 204 and the main measuring output terminal.

[0049] The test circuit also includes: a test module, which is used to apply a first voltage V1 to the power supply voltage terminal, apply a start signal to the main test input terminal of the first-level main test unit 2, generate an oscillation signal in the ring oscillation loop, and then obtain the electrical parameters of the main test unit 2; and obtain the performance parameters of the main test unit 2 based on the electrical parameters.

[0050] The method of obtaining the electrical parameters of the main measuring unit 2 and obtaining the performance parameters of the main measuring unit 2 according to the electrical parameters includes: obtaining the first frequency f and the first current I1 of the ring oscillation circuit 1 at the power supply voltage end; and obtaining the input capacitance value, output capacitance value and output resistance value of the main measuring unit 2 according to the first frequency f and the first current I1.

[0051] Obtaining the input capacitance value, output capacitance value, and output resistance value of the main measuring unit 2 according to the first frequency f and the first current I1 includes: obtaining the delay time t according to the first frequency f delay =1 / f; According to the first current I1 and the delay time t delay , the power consumption of the main test unit 2 is obtained as P=I1*V1*t delay ; Get the delay time t delay The first linear relationship t between the input capacitance Cin, the output capacitance Cout and the output resistance Rout delay =FO*Rout*Cin+Rout*Cout; obtain the second linear relationship between the power consumption P of the main test unit 2 and the input capacitance value and the output capacitance value P=FO*(Cin+Cout)*V1 2 , where FO is the load quantity value; for the delay time t in the first linear relationship delayA linear fitting analysis is performed on the power consumption P and the load quantity value FO to obtain a first slope Rout*Cin and an intercept Rout*Cout; a linear fitting analysis is performed on the power consumption P and the load quantity value FO in the second linear relationship to obtain a second slope Cin+Cout; according to the first slope Rout*Cin, the intercept Rout*Cout and the second slope Cin+Cout, the input capacitance value Cin, the output capacitance value Cout and the output resistance value Rout are obtained.

[0052] In the above scheme, the number of load units can be flexibly selected according to the test requirements to achieve accurate measurement of the input capacitance, output capacitance and output resistance of the main test unit, and the main test unit is optimized according to the input capacitance, output capacitance and output resistance of the main test unit, thereby improving the optimization speed and working performance.

[0053] In addition, the test circuit in the technical solution of the present invention can complete the performance test in a shorter time by measuring the underlying metal interconnect layer, which is helpful for researching and optimizing digital units in the early stage of the process.

[0054] Please refer to Figure 1 The technical solution of the present invention also provides an operating method of a test circuit, the test circuit comprising at least two ring oscillator circuits 1 connected in series, each ring oscillator circuit 1 comprising an odd number of main test units 2 connected in series, each main test unit 2 comprising a main test input terminal and a main test output terminal, the main test output terminal of each main test unit 2 being connected to the main test input terminal of a subsequent main test unit, and the main test output terminal of the last main test unit 2 being connected to the main test input terminal of a first main test unit 2; and a plurality of load units 3 connected in parallel to each main test input terminal, the main test units 2 and the load units 3 being the same digital unit, and the number of load units 3 at the main test input terminal of each ring oscillator circuit 1 being different. The method comprises: applying a first voltage V1 to a power supply voltage terminal, applying a start signal to the main test input terminal of the first main test unit to generate an oscillation signal in the ring oscillation circuit, and obtaining electrical parameters of the main test units after generating an oscillation signal in the ring oscillation circuit; and obtaining performance parameters of the main test units based on the electrical parameters.

[0055] In this embodiment, the electrical parameters of the main measurement unit are obtained, and the method for obtaining the performance parameters of the main measurement unit based on the electrical parameters includes: obtaining the first frequency f and the first current I1 of the ring oscillation circuit at the power supply voltage end; and obtaining the input capacitance value, output capacitance value, and output resistance value of the main measurement unit based on the first frequency f and the first current I1.

[0056] Figure 3 Schematic diagram of the linear relationship between delay time and load quantity in a test circuit according to an embodiment of the present invention.

[0057] Figure 4 Schematic diagram of the linear relationship between power consumption and load quantity in a test circuit according to an embodiment of the present invention.

[0058] Please refer to Figure 3 as well as Figure 4 In this embodiment, obtaining the input capacitance value, output capacitance value, and output resistance value of the main measuring unit according to the first frequency f and the first current I1 includes: obtaining the delay time t according to the first frequency f delay =1 / f; According to the first current I1 and the delay time t delay , the power consumption of the main test unit is obtained as P=I1*V1*t delay ; Get the delay time t delay The first linear relationship t between the input capacitance Cin, the output capacitance Cout and the output resistance Rout delay =FO*Rout*Cin+Rout*Cout; obtain the second linear relationship between the power consumption P of the main test unit and the input capacitance value and the output capacitance value P=FO*(Cin+Cout)*V1 2 , where FO is the load quantity value; for the delay time t in the first linear relationship delay A linear fitting analysis is performed on the power consumption P and the load quantity value FO to obtain a first slope Rout*Cin and an intercept Rout*Cout; a linear fitting analysis is performed on the power consumption P and the load quantity value FO in the second linear relationship to obtain a second slope Cin+Cout; according to the first slope Rout*Cin, the intercept Rout*Cout and the second slope Cin+Cout, the input capacitance value Cin, the output capacitance value Cout and the output resistance value Rout are obtained.

[0059] Specifically, according to the delay time t delay According to the linear relationship between the power consumption P and the load quantity value FO, the first slope is the first constant K1, and the intercept is the second constant A, that is, Rout*Cin=K1, Rout*Cout=A. According to the linear relationship between the power consumption P and the load quantity value FO, the second slope is the third constant K2, that is, Cin+Cout=K2. A linear equation operation of two variables is performed on Rout*Cin=K1, Rout*Cout=A and Cin+Cout=K2 to finally obtain the input capacitance value Cin, output capacitance value Cout and output resistance value Rout.

[0060] Specifically, the range of the first constant K1 and the second constant K2 is 0.99 to 1.

[0061] In the above scheme, the electrical parameters of the main measuring unit are obtained during the oscillation of the ring oscillation loop, and the performance parameters of the main measuring unit are obtained based on the electrical parameters, thereby improving the optimization speed and working performance, thereby realizing the performance testing of the main measuring unit and the optimization of the main measuring unit.

[0062] In addition, by obtaining the first frequency on the main measurement input terminal, the first voltage V1 on the power supply voltage terminal, and the first current flowing through the power supply voltage terminal, the delay time and power consumption of the ring oscillation loop, as well as the first linear relationship between the delay time and the input capacitance value, the output capacitance value, and the output resistance value, and the second linear relationship between the power consumption of the main measurement unit and the input capacitance value and the output capacitance value are obtained. By performing linear fitting analysis on the first linear relationship and the second linear relationship, the input capacitance value, the output capacitance value, and the output resistance value are obtained, thereby improving the optimization speed and working performance, thereby realizing the testing of the performance of the main measurement unit and the optimization of the main measurement unit.

[0063] Correspondingly, the technical solution of the present invention also provides a layout test circuit, including: a ring oscillation circuit, including an odd number of main test unit layouts connected in series, each main test unit layout including a main test input terminal and a main test output terminal, the main test output terminal of each main test unit layout is connected to the main test input terminal of the next level main test unit layout, and the main test output terminal of the last level main test unit layout is connected to the main test input terminal of the first level main test unit layout; a plurality of load unit layouts, the plurality of load unit layouts are connected in parallel to each main test input terminal, the main test unit layout and the load unit layout are the same digital unit layout, and the number of load unit layouts on the main test input terminal in each ring oscillation circuit is different.

[0064] In this embodiment, the main test unit layout and the load unit layout include: an input capacitor, a first end of the input capacitor is connected to the main test input terminal; an input resistor, a first end of the input resistor is connected to the main test input terminal; a unit to be tested layout, a first end of the unit to be tested layout is connected to the second end of the input resistor; an output resistor, a first end of the output resistor is connected to the second end of the unit to be tested layout, and the second end of the output resistor is connected to the main test output terminal; an output capacitor, a first end of the output capacitor is connected to the second end of the output resistor and the main test output terminal.

[0065] In this embodiment, the number of the load unit layouts ranges from 1 to 8.

[0066] In this embodiment, the number of load unit layouts connected in parallel on the main test input terminals of different levels is the same, and the main test unit layouts of different levels are the same digital unit layouts.

[0067] In this embodiment, the main test unit layout and the load unit layout are one or more combinations of an AND gate circuit standard unit layout, an OR gate circuit standard unit layout, and a multiplexer standard unit layout.

[0068] In this embodiment, the main test unit layout has at least one input terminal, and one of the at least one input terminal is the main test input terminal.

[0069] In the above solution, to reduce the impact of capacitance and resistance introduced by interconnects between digital units, the layout design requires arranging adjacent primary test units as close as possible, using underlying metal lines for interconnection. This reduces the length and area of the metal interconnects, thereby minimizing the impact of capacitance and resistance introduced by the metal interconnects and improving the performance of the digital units. Furthermore, by reducing the distance between different ring oscillator circuits, process variations caused by the different positions of the digital units can be reduced.

[0070] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A test circuit for performing performance testing on a digital unit, characterized in that: include: At least two ring oscillator circuits connected in series, each ring oscillator circuit including an odd number of main measuring units connected in series, each main measuring unit including a main measuring input and a main measuring output, the main measuring output of each main measuring unit being connected to the main measuring input of a subsequent main measuring unit, and the main measuring output of the final main measuring unit being connected to the main measuring input of the first main measuring unit; A plurality of load units are connected in parallel to each main measurement input terminal. The main measurement unit and the load unit are the same digital unit. The number of load units on the main measurement input terminal in each ring oscillation circuit is different.

2. The test circuit according to claim 1, wherein: The main measuring unit and the load unit include: an input capacitor, a first end of the input capacitor is connected to the main measuring input terminal; an input resistor, a first end of the input resistor is connected to the main measuring input terminal; a unit to be measured, a first end of the unit to be measured is connected to the second end of the input resistor; an output resistor, a first end of the output resistor is connected to the second end of the unit to be measured, and the second end of the output resistor is connected to the main measuring output terminal; and an output capacitor, a first end of the output capacitor is connected to the second end of the output resistor and the main measuring output terminal.

3. The test circuit according to claim 1, wherein: The number of the load units ranges from 1 to 8.

4. The test circuit according to claim 1, wherein: The number of load units connected in parallel on the main test input terminals of different levels is the same, and the main test units of different levels are the same digital units.

5. The test circuit according to claim 1, wherein: The main test unit and the load unit are a combination of one or more of an AND gate circuit standard unit, an OR gate circuit standard unit, and a multiplexer standard unit.

6. The test circuit according to claim 1, wherein: The main testing unit has at least one input terminal, and one of the at least one input terminal is the main testing input terminal.

7. The test circuit according to claim 1, wherein: The test circuit also includes: a test module, which is used to apply a first voltage V1 to the power supply voltage terminal, apply a start signal to the main test input terminal of the first-level main test unit, generate an oscillation signal in the ring oscillation loop, and then obtain the electrical parameters of the main test unit; and obtain the performance parameters of the main test unit based on the electrical parameters.

8. The test circuit according to claim 7, wherein: The method of obtaining the electrical parameters of the main measurement unit and obtaining the performance parameters of the main measurement unit based on the electrical parameters includes: obtaining the first frequency f and the first current I1 of the ring oscillation circuit at the power supply voltage end; and obtaining the input capacitance value, output capacitance value and output resistance value of the main measurement unit based on the first frequency f and the first current I1.

9. The test circuit according to claim 8, wherein: Obtaining the input capacitance value, output capacitance value, and output resistance value of the main measuring unit according to the first frequency f and the first current I1 includes: obtaining the delay time t according to the first frequency f delay =1 / f; According to the first current I1 and the delay time t delay , the power consumption of the main test unit is obtained as P=I1*V1*t delay ; Get the delay time t delay The first linear relationship t between the input capacitance Cin, the output capacitance Cout and the output resistance Rout delay =FO*Rout*Cin+Rout*Cout; obtain the second linear relationship between the power consumption P of the main test unit and the input capacitance value and the output capacitance value P=FO*(Cin+Cout)*V1 2 , where FO is the load quantity value; for the delay time t in the first linear relationship delay A linear fitting analysis is performed on the power consumption P and the load quantity value FO to obtain a first slope Rout*Cin and an intercept Rout*Cout; a linear fitting analysis is performed on the power consumption P and the load quantity value FO in the second linear relationship to obtain a second slope Cin+Cout; according to the first slope Rout*Cin, the intercept Rout*Cout and the second slope Cin+Cout, the input capacitance value Cin, the output capacitance value Cout and the output resistance value Rout are obtained.

10. A method for operating a test circuit, the test circuit comprising at least two ring oscillator circuits connected in series, each ring oscillator circuit comprising an odd number of main test units connected in series, each main test unit comprising a main test input and a main test output, the main test output of each main test unit being connected to the main test input of a subsequent main test unit, and the main test output of the last main test unit being connected to the main test input of the first main test unit; and a plurality of load units connected in parallel to each main test input, the main test units and the load units being the same digital unit, and the number of load units on the main test input of each ring oscillator circuit being different, characterized in that: include: Applying a first voltage V1 to the power supply voltage terminal, applying a start signal to the main measurement input terminal of the first-stage main measurement unit to generate an oscillation signal in the ring oscillation loop, and then obtaining the electrical parameters of the main measurement unit; The performance parameters of the main test unit are obtained according to the electrical parameters.

11. The operating method of the test circuit according to claim 10, wherein: The method of obtaining the electrical parameters of the main measurement unit and obtaining the performance parameters of the main measurement unit based on the electrical parameters includes: obtaining the first frequency f and the first current I1 of the ring oscillation circuit at the power supply voltage end; and obtaining the input capacitance value, output capacitance value and output resistance value of the main measurement unit based on the first frequency f and the first current I1.

12. The operating method of the test circuit according to claim 11, wherein: Obtaining the input capacitance value, output capacitance value, and output resistance value of the main measuring unit according to the first frequency f and the first current I1 includes: obtaining the delay time t according to the first frequency f delay =1 / f; According to the first current I1 and the delay time t delay , the power consumption of the main test unit is obtained as P=I1*V1*t delay ; Get the delay time t delay The first linear relationship t between the input capacitance Cin, the output capacitance Cout and the output resistance Rout delay =FO*Rout*Cin+Rout*Cout; obtain the second linear relationship between the power consumption P of the main test unit and the input capacitance value and the output capacitance value P=FO*(Cin+Cout)*V1 2 , where FO is the load quantity value; for the delay time t in the first linear relationship delay A linear fitting analysis is performed on the power consumption P and the load quantity value FO to obtain a first slope Rout*Cin and an intercept Rout*Cout; a linear fitting analysis is performed on the power consumption P and the load quantity value FO in the second linear relationship to obtain a second slope Cin+Cout; according to the first slope Rout*Cin, the intercept Rout*Cout and the second slope Cin+Cout, the input capacitance value Cin, the output capacitance value Cout and the output resistance value Rout are obtained.

13. A layout test circuit, characterized in that: include: The ring oscillator circuit includes an odd number of main test unit layouts connected in series, each main test unit layout including a main test input terminal and a main test output terminal, the main test output terminal of each main test unit layout being connected to the main test input terminal of the main test unit layout of the next stage, and the main test output terminal of the main test unit layout of the last stage being connected to the main test input terminal of the main test unit layout of the first stage; A plurality of load unit layouts are connected in parallel to each main test input terminal, the main test unit layout and the load unit layout are the same digital unit layout, and the number of load unit layouts on the main test input terminal in each ring oscillator circuit is different.

14. The layout test circuit according to claim 13, wherein: The main test unit layout and the load unit layout include: an input capacitor, a first end of the input capacitor is connected to the main test input terminal; an input resistor, a first end of the input resistor is connected to the main test input terminal; a unit to be tested layout, a first end of the unit to be tested layout is connected to the second end of the input resistor; an output resistor, a first end of the output resistor is connected to the second end of the unit to be tested layout, and the second end of the output resistor is connected to the main test output terminal; an output capacitor, a first end of the output capacitor is connected to the second end of the output resistor and the main test output terminal.

15. The layout test circuit according to claim 13, wherein: The number of the load unit layouts ranges from 1 to 8.

16. The layout test circuit according to claim 13, wherein: The number of load unit layouts connected in parallel on the main test input terminals of different levels is the same, and the main test unit layouts of different levels are the same digital unit layouts.

17. The layout test circuit according to claim 13, wherein: The main test unit layout and the load unit layout are one or more combinations of an AND gate circuit standard unit layout, an OR gate circuit standard unit layout, and a multiplexer standard unit layout.

18. The layout test circuit according to claim 13, wherein: The main test unit layout has at least one input terminal, and one of the at least one input terminal is the main test input terminal.

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