Testing device and operation method thereof
By introducing APCM into the semiconductor integrated circuit test device, the switching device is activated sequentially and equal or compensation voltage is provided in its inactive state, the problem of leakage current of the switching device is solved, and the testing efficiency and accuracy are improved.
Patent Information
- Application Number
- CN202510274318.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-09
- Filing Date
- 2025-03-10
- Publication Date
- 2025-08-05
AI Technical Summary
In the manufacturing process of semiconductor integrated circuits, it is difficult for the prior art to effectively manage and reduce leakage currents of switching devices, affecting the efficiency and accuracy of the test device.
The advanced process control monitor (APCM) is adopted, which includes switching circuits, control circuits, detection circuits and auxiliary control circuits. By sequentially activate the switching device and provide equal or compensation voltages in its inactive state, the leakage current of the switching device is reduced.
It significantly reduces the total leakage current of the switching circuit, improves the efficiency and accuracy of the test device, and improves the reliability and efficiency of the test process.
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Figure CN120428071A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a test apparatus and an operation method thereof. Background Art
[0002] The semiconductor integrated circuit (IC) industry has been rapidly developing due to advances in IC materials and design. Each new generation of ICs is characterized by smaller and more complex circuits than the previous generation. During the manufacture of semiconductor devices, one or more test processes are typically involved, and on-chip structures are often utilized for testing purposes. Summary of the Invention
[0003] According to an embodiment of the present invention, a test apparatus includes: a plurality of devices under test (DUTs); and an advanced process control monitor (APCM), which includes: a switching circuit including a plurality of switching devices corresponding to the DUTs; a control circuit including a plurality of control devices corresponding to the switching devices and configured to sequentially activate one of the switching devices during a test process of the test apparatus; a detection circuit configured to provide a first power supply voltage to a first terminal of each of the plurality of switching devices; and an auxiliary control circuit configured to provide a second power supply voltage to a second terminal of each of the plurality of switching devices deactivated by the control circuit.
[0004] According to an embodiment of the present invention, a method includes: providing a test apparatus including a plurality of switching devices and a plurality of devices under test (DUTs); sequentially activating each of the switching devices of the test apparatus to test the corresponding DUT; and in response to a particular switching device not being activated, applying a first power supply voltage and a second power supply voltage to a first terminal and a second terminal of the particular switching device, respectively.
[0005] According to an embodiment of the present invention, a test apparatus includes: a plurality of devices under test (DUTs); and an advanced process control monitor (APCM), which includes: a switching circuit including a plurality of switching devices corresponding to the DUTs; a control circuit including a plurality of control devices corresponding to the switching devices and configured to sequentially activate one of the switching devices during a test process of the test apparatus; and a detection circuit configured to provide a first power supply voltage to a first terminal of each switching device and selectively provide a second power supply voltage to a second terminal of each switching device deactivated by the control circuit based on a selection signal from the control device corresponding to each switching device. Brief Description of the Drawings
[0006] As will be best understood from the following "Detailed Description" when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.
[0007] Figure 1 is a block diagram of a test device according to some embodiments of the present disclosure.
[0008] Figure 2 is to illustrate Figure 1 the connection between the DUT, the switch circuit, and the control circuit in the test device in
[0009] Figure 3A is a schematic diagram of a switch circuit according to some embodiments of the present disclosure.
[0010] Figure 3B is a schematic diagram of a control circuit according to some embodiments of the present disclosure.
[0011] Figure 3C is a waveform diagram of various signals within a control circuit according to some embodiments of the present disclosure.
[0012] Figure 3D is another schematic diagram of a control circuit according to some embodiments of the present disclosure.
[0013] Figure 3E is yet another schematic diagram of a control circuit according to some embodiments of the present disclosure.
[0014] Figure 4A is a cross-section of the deactivated first switch S1 in a switching device according to some embodiments of the present disclosure.
[0015] Figure 4B is another cross-section of the deactivated first switch S1 in a switching device according to some embodiments of the present disclosure.
[0016] Figure 4C is a cross-section of the activated first switch S1 in a switching device according to some embodiments of the present disclosure.
[0017] Figure 5A is a part of a schematic diagram of a switch circuit according to some embodiments of the present disclosure.
[0018] Figure 5B is a schematic diagram of a control circuit according to some embodiments of the present disclosure.
[0019] Figure 5C is Figure 5A a waveform diagram of various signals in the switch circuit in
[0020] Figure 6It is a flowchart of a method for operating a test device according to some embodiments of the present disclosure.
[0021] Figure 7 It is another flowchart of a method for operating a test device according to some embodiments of the present disclosure. Detailed Description
[0022] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first member above or on a second member may include embodiments in which the first and second members are formed in direct contact, and may also include embodiments in which additional members may be formed between the first and second members such that the first and second members may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.
[0023] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "under," "above," "over," "on," "upon," and the like may be used herein to describe the relationship of one element or member to another (some) element or member as illustrated in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatially relative descriptors used herein may be interpreted accordingly.
[0024] In addition, it will be understood that when an element is referred to as "connected to" or "coupled to" another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.
[0025] The embodiments or examples illustrated in the figures are disclosed using a specific language as follows. However, it will be understood that the embodiments and examples are not intended to be limiting. Consider any changes or modifications to the disclosed embodiments and any further applications of the principles disclosed herein, as would typically occur to one of ordinary skill in the relevant art.
[0026] In addition, it should be understood that only several processing steps and / or features of the device may be briefly described. Additionally, additional processing steps and / or features may be added, and certain of the following processing steps and / or features may be removed or altered while still implementing the claims. Therefore, it should be understood that the following description is only illustrative and is not intended to imply the need for one or more steps or features.
[0027] Additionally, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0028] Figure 1 is a block diagram of a test apparatus according to some embodiments of the present disclosure. Figure 2 illustrates Figure 1 the connection between the DUT, the switch circuit, and the control circuit in the test apparatus in
[0029] In some embodiments, the test apparatus 100 may include a plurality of devices under test (DUTs) 110, a switch circuit 130, a control circuit 140, a detection circuit 150, and an auxiliary control circuit 160. The switch circuit 130 and the control circuit 140 may be collectively referred to as an advanced process control monitor (APCM) 120. In some embodiments, the APMC 120 may also be referred to as a process control monitor (PCM) or a DUT selection circuit system.
[0030] Referring to Figure 2 , in some embodiments, the DUT 110 may include DUTs 1101 to 110N, which are different types of circuits designed to test semiconductor circuits or components fabricated on a semiconductor wafer. The switch circuit 130 may include a plurality of switching devices (e.g., Figure 2 the switching devices 1301 to 130N shown in Figure 2 ), which can be selectively activated and deactivated (e.g., turned on and off, or closed and opened). The first terminal of each switching device is coupled to a corresponding one of the terminals of the DUT 110. The switch circuit 130 is electrically coupled to the control circuit 140 and is controlled by the control circuit 140. The control circuit 140 may include a plurality of control devices (e.g., Figure 2 the control devices 1401 to 140N shown in
[0031] configured to selectively activate the switching devices. In some embodiments, the control circuit 140 may include a plurality of flip - flops as control devices. In an embodiment, the flip - flops include, but are not limited to, D flip - flops. In some embodiments, the flip - flops in the control circuit 140 may form a shift register. When a voltage pulse is applied to the control circuit 140, the voltage pulse may pass through the control devices 1401 to 140N (e.g., flip - flops) one by one in each clock cycle, allowing the control circuit 140 to activate the switching devices one by one, as shown in Figure 2 . Specific details of the control circuit 140 will be described later.
[0031] In some embodiments, the detection circuit 150 may be configured to provide a first power supply voltage (e.g., VDD1) to the second terminal of each switching device of the switch circuit 130 and detect the corresponding current (e.g., IDF )。
[0032] In some embodiments, the auxiliary control circuit 160 may be configured to selectively provide a second power supply voltage (e.g., VDD2) to the first terminal of each deactivated switch device in the switching circuit 130 based on selection signals from corresponding control devices for each switch device. In some embodiments, the first power supply voltage may be substantially equal to the second power supply voltage. In some embodiments, the first power supply voltage and the second power supply voltage may be slightly different due to process variations of the switch devices and the distance of the transmission path. More specifically, the second power supply voltage provided by the auxiliary control circuit 160 may be designed to eliminate the voltage difference between the first terminal and the second terminal of the deactivated switch device. In some embodiments, the first switch S1 and the second switch S2 of the switch devices 1301 to 130N may be implemented using P-type transistors, thereby reducing the leakage current of the deactivated switch devices.
[0033] In some embodiments, the auxiliary control circuit 160 may be integrated into the detection circuit 150 (not explicitly shown in the figure). Thus, the detection circuit 150 may be further configured to provide the first power supply voltage (e.g., VDD1) to the first terminal of each switch device and selectively provide the second power supply voltage (e.g., VDD2) to the second terminal of each switch device deactivated by the control circuit 140 based on selection signals from the control device corresponding to each switch device (e.g., one of the control devices 1401 to 140N).
[0034] Figure 3A is a schematic diagram of a switching circuit according to some embodiments of the present disclosure.
[0035] As Figure 3A depicted in, in some embodiments, each of the switch devices 1301 to 130N includes a first switch S1 and a second switch S2. For example, the first switch S1 and the second switch S2 of the switch device 1301 may be controlled by selection signals SEL1 and SEL1B (e.g., complementary to SEL1), respectively. The first switch S1 and the second switch S2 of the switch device 1302 may be controlled by selection signals SEL2 and SEL2B, respectively, and so on. In some embodiments, the selection signals SEL1 to SELN and SEL1B to SELNB may be generated by the control circuit 140. In some embodiments, the selection signals SEL1 to SELN may be generated by the control circuit 140, and the selection signals SEL1B and SELNB may be generated by the auxiliary control circuit 160.
[0036] In some embodiments, the first terminal (e.g., node N1) and the second terminal (e.g., node N2) of the first switch S1 in each of the switching devices 1301 to 130N may be coupled to the detection circuit 150 and a corresponding DUT (e.g., one of the DUTs 1101 to 110N), respectively. Additionally, the first terminal (e.g., node N3) and the second terminal (e.g., node N4) of the second switch S2 in each of the switching devices 1301 to 130N may be coupled to the auxiliary control circuit 160 and the second terminal (e.g., node N2) of the first switch S1.
[0037] In some embodiments, for each of the switching devices 1301 to 130N, one of the first switch S1 and the second switch S2 is activated (i.e., turned on or closed). Referring to the switching device 1301, the selection signals SEL1 and SEL1B are complementary. When the first switch S1 is activated based on the selection signal SEL1 (e.g., logic 1), the second switch S2 is deactivated based on the selection signal SEL1B (e.g., logic 0). Similarly, when the first switch S1 is deactivated based on the selection signal SEL1 (e.g., logic 0), the second switch S2 is activated based on the selection signal (e.g., logic 1). The first switch S1 and the second switch S2 in the other switching devices 1302 to 130N may operate in a similar manner.
[0038] In some embodiments, the first switch S1 and the second switch S2 of the switching device 1301 may be controlled by the selection signals SEL1B and SEL1, respectively. The first switch S1 and the second switch S2 of the switching device 1302 may be controlled by the selection signals SEL2B and SEL2, respectively, and so on. When the first switch S1 is activated based on the selection signal SEL1B (e.g., logic 1), the second switch S2 is deactivated based on the selection signal SEL1 (e.g., logic 0). Similarly, when the first switch S1 is deactivated based on the selection signal SEL1B (e.g., logic 0), the second switch S2 is activated based on the selection signal SEL1 (e.g., logic 1).
[0039] Figure 3B is a schematic diagram of a control circuit according to some embodiments of the present disclosure. Figure 3C is Figure 3B a waveform diagram of various signals within the control circuit in
[0040] Figure 1 The control circuit 140 shown in Figure 3BIt is implemented by the control circuit 140A shown in []. In some embodiments, the control circuit 140A may include multiple control devices 1401 to 140N (i.e., N control devices), and each of the control devices 1401 to 140N may be implemented using D flip - flops. Each of the control devices 1401 to 140N may store a logical state, such as logic 1 or logic 0. For example, each of the control devices 1401 to 140N may have a data input terminal D, a reset terminal RST, a clock input terminal CLK, a data output terminal Q, an inverted data output terminal QB, and a clock output terminal CLKo. For example, the output (Q) of the control device 1401 is the selection signal SEL1, and the inverted outputs (QB) of the control devices 1402 to 140N are the selection signals SEL2 to SELN respectively. Additionally, the selection signals SEL1 to SELN are respectively provided to the switching devices 1301 to 130N to control the corresponding first switches S1.
[0041] In some embodiments, the data input terminal D of the control device 1401 may receive an input data signal DIN, and the clock input terminal CLK may receive a clock signal CLOCK. The output signal at the data output terminal Q of the control device 1401 may be used as the selection signal SEL1. Additionally, the output signal at the inverted data output terminal QB of the control device 1401 may be provided to the data input terminal D of the control device 1402, and the output clock signal at the clock output terminal CLKo of the control device 1401 may be provided to the clock input terminal CLK of the control device 1402. Similarly, the output signal at the data output terminal Q of the control device 1402 may be provided to the data input terminal D of the control device 1403, and the output signal at the inverted data output terminal QB of the control device 1402 may be used as the selection signal SEL2, and so on. It should be noted that the output signal at the data output terminal Q of the Nth control device 140N may be used as a voltage signal VQ, and the voltage signal VQ may be used to report that the test processes of the DUTs 1101 to 110N have been successfully completed. Additionally, the reset terminals of the control devices 1401 to 140N may be electrically connected to a reset signal RESET for a global reset operation.
[0042] In some embodiments, each of the switching devices 1301 to 130N may include an inverter to convert the received selection signal (e.g., SELN or SELNB) into an inverted selection signal, so that the selection signal and the inverted selection signal may be respectively used to control the first switch S1 and the second switch S2 (vice versa).
[0043] Reference Figure 3C, in some embodiments, after the initialization of the ACPM 120, the control devices 1401 to 140N can be reset by a reset signal RESET in a low logic state (e.g., logic 0). At this time, the data output terminal Q and the inverted data output terminal QB of each of the control devices 1401 are reset to 0 and 1 respectively. After the cancellation establishment of the reset signal RESET (e.g., logic 1), an input data signal DIN (which can be a voltage pulse shorter than a clock cycle) is provided to the data input terminal D of the control device 1401. At time t1, at the rising edge of the clock signal CLOCK, the high logic state of the input data signal DIN is latched by the control device 1401, and the output signals at the data output terminal Q and the inverted data output terminal QB of the control device 1401 are in a high logic state and a low logic state respectively. Therefore, the output signal (e.g., SEL1) at the data output terminal Q of the control device 1401 can be used to activate the switching device 1301 within the time interval from time t1 to t2, as Figure 3A shown in.
[0044] At time t2, at the rising edge of the clock signal CLOCK, the low logic state at the inverted output terminal QB is latched by the control device 1402. The output signals at the output terminal Q and the inverted output terminal QB of the control device 1402 can be in a low logic state (e.g., logic 0) and a high logic state (e.g., logic 1) respectively. Therefore, the output signal (e.g., SEL2) at the inverted data output terminal QB of the control device 1402 can be used to activate the switching device 1302 within the time interval from time t2 to t3.
[0045] At time t3, at the rising edge of the clock signal CLOCK, the low logic state at the inverted output terminal QB is latched by the control device 1403. The output signals at the output terminal Q and the inverted output terminal QB of the control device 1403 can be in a low logic state (e.g., logic 0) and a high logic state (e.g., logic 1) respectively. Therefore, the output signal (e.g., SEL3) at the inverted data output terminal QB of the control device 1403 can be used to activate the switching device 1303 within the time interval from time t3 to t4.
[0046] At time t4, at the rising edge of the clock signal CLOCK, the low logic state at the inverted output terminal QB is latched by the control device 1404. The output signals at the output terminal Q and the inverted output terminal QB of the control device 1404 can be in a low logic state (e.g., logic 0) and a high logic state (e.g., logic 1), respectively. Thus, the output signal (e.g., SEL4) at the inverted data output terminal QB of the control device 1404 can be used to activate the switching device 1304 during the time interval from time t4 to t5. Additionally, the remaining control devices 1405 to 140N in the control circuit 140 can operate in a similar manner, allowing the control devices 1405 to 140N to activate the switching devices 1305 to 130N one by one in each clock cycle.
[0047] Figure 3D is another schematic diagram of a control circuit according to some embodiments of the present disclosure.
[0048] Figure 1 The control circuit 140 shown in Figure 3D can also be implemented using the control circuit 140B shown in Figure 3D The control circuit 140B shown in Figure 3B can be similar to the control circuit 140A shown in Figure 3D except that the clock output terminals of the control devices 1401 to 140N can be omitted, and the clock input terminals of the control devices 1401 to 140N can be connected to the clock signal CLOCK. In some embodiments, one or more clock buffers (e.g., clock buffers 301, 302, 303, etc.) can be inserted between the clock transmission paths from the control device 1401 to the control device 140N, as shown in
[0049] Figure 3E is yet another schematic diagram of a control circuit according to some embodiments of the present disclosure.
[0050] Figure 1 The control circuit 140 shown in Figure 3E can also be implemented using the control circuit 140C shown in Figure 3E The control circuit 140C shown in Figure 3B can be similar to the control circuit 140A shown in Figure 3EEach of the control devices 1401 to 140N therein can provide two selection signals that match each other. For example, the output signals at the data output terminal Q and the inverted data output terminal QB of the control device 1401 can be used as the selection signals SEL1 and SEL1B respectively. In addition, the output signals at the data output terminal Q and the inverted data output terminal QB of the control device 1401 can be used as the selection signals SEL2B and SEL2 respectively. Specifically, the first switch S1 and the second switch S2 in each of the switching devices 1301 to 130N can be controlled by the selection signals SELN and SELNB respectively (and vice versa), where N represents the corresponding number of each switching device.
[0051] Figure 4A is a cross-section of the deactivated first switch S1 in a switching device according to some embodiments of the present disclosure. Please refer to Figure 3A and Figure 4A .
[0052] In some embodiments, the switch S1 of each of the switching devices 1301 to 130N can be implemented using Figure 4A the transistor 400 shown in. The transistor 400 can include a substrate 416, well regions 410, 412, and 414, a gate dielectric 406, a gate electrode 408, and shallow trench isolation (STI) regions 402 and 404. The substrate 416 can be or include a semiconductor wafer, such as a silicon wafer. Alternatively, the wafer 416 can include other elemental semiconductors, such as germanium. The substrate 416 can also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. The substrate 416 can include alloy semiconductors, such as silicon germanium, germanium silicon carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the substrate 416 includes an N-type silicon wafer, which can be regarded as an N-type substrate. Alternatively, the substrate 416 can be an N-type well region formed on a P-type substrate.
[0053] In some embodiments, the well regions 410 and 412 can be P-type well regions. The well region 414 can be an N-type well region. The well region 410 can be regarded as the source terminal of the transistor 400, and the well region 414 can be regarded as the body (or bulk) terminal of the transistor 400. The well regions 410 and 414 are separated by the STI region 402. The transistor 400 can include a gate structure disposed on the substrate 416, and the gate structure can include a gate dielectric 406 and a gate electrode 408 disposed on the gate dielectric 406. The gate dielectric 406 includes a silicon dioxide layer formed by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes or a combination thereof. Alternatively, the gate dielectric 406 can include a high dielectric constant (high-k) material, silicon oxynitride, other suitable materials, or a combination thereof. The gate dielectric 406 can be a multi-layer of, for example, silicon dioxide and a high-k material.
[0054] The gate electrode 408 can be designed to couple to a metal interconnect and is placed overlying the gate dielectric 406. The gate electrode 408 can comprise doped polycrystalline silicon (polysilicon). Alternatively, the gate electrode 408 can comprise a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or a combination thereof. The gate electrode 408 can be formed by CVD, PVD, plating, and other acceptable processes. The gate electrode 408 can be multi-layered and formed by a multi-step process.
[0055] In some embodiments, the well region 414 (e.g., the body terminal) can be a highly doped N-type implant region (e.g., N+), and the well regions 410 and 412 (e.g., the source terminal and the drain terminal) can be highly doped P-type implant regions (e.g., P+). Additionally, another STI region 404 can be formed beside the well region 412.
[0056] In Figure 4A the configuration shown, the source terminal 410 and the body terminal 414 are electrically connected to a power supply voltage VDD1, the drain terminal 412 is connected to the voltage VN2 at the node N2 (shown in Figure 3A ), and the gate electrode 408 is electrically connected to a select signal (e.g., SEL1B). The voltage VN2 can be in the range from 0V to the first power supply voltage VDD1. When the select signal SEL1 is in a low logic state (e.g., logic 0), the select signal SEL1B is in a high logic state (e.g., logic 1), and thus the first power supply voltage VDD1 is provided to the gate electrode 408. Accordingly, the transistor 400 is deactivated (i.e., in the off state).
[0057] It should be noted that although the transistor 400 is deactivated, a leakage current referred to as the subthreshold current I sub (which is shown in Figure 4A as flowing from the source terminal 410 to the drain terminal 412) still exists because there is a voltage difference between the source terminal 410 (e.g., which is supplied with VDD1) and the drain terminal 412 (e.g., which is supplied with VN2). When the Figure 4A configuration shown is used for the first switch S1 of the switching devices 1301 to 130N, the total leakage current of the switching circuit 130 can be quite large because one of the switching devices 1301 to 130N is activated at a time during the test process.
[0058] Figure 4B is another cross-section of the deactivated first switch S1 in a switching device according to some embodiments of the present disclosure.
[0059] Figure 4BThe configuration of the transistor 400 shown in Figure 4A may be similar to the configuration shown in Figure 4B , except that the drain terminal 412 of the transistor 400 in sub is electrically connected to a second power supply voltage VDD2 (e.g., from an auxiliary control circuit 160), where the second power supply voltage VDD2 is substantially equal to the first power supply voltage VDD1. Since the voltage difference between the source terminal 410 and the drain terminal 412 is substantially equal to 0, the subthreshold current I from the source terminal 410 to the drain terminal 412 can be eliminated.
[0060] Figure 4C is a cross-section of the activated first switch S1 in the switching device according to some embodiments of the present disclosure.
[0061] As Figure 4C depicted in, the source terminal 410 and the body terminal 414 are electrically connected to the power supply voltage VDD1, the drain terminal 412 is connected to the voltage VN2 at the node N2 (shown in Figure 3A ), and the gate electrode 408 is electrically connected to a selection signal (e.g., SEL1B) at a low logic state (e.g., 0V). Therefore, the transistor 400 is activated (e.g., in the on state or the operating saturation region), and a conduction current (e.g., saturation current) I sat flows from the source terminal 410 to the drain terminal 412. It should be noted that when the transistor 400 is activated, the conduction current I sat and the subthreshold current I sub both flow from the source terminal 410 to the drain terminal 412.
[0062] Specifically, referring to Figure 3A , for the switching device 1301, the first switch S1 is activated and the second switch S2 is deactivated, resulting in a conduction current (e.g., Figure 4C the I shown in sat ) flowing through the first switch S1 (e.g., from the source terminal to the drain terminal and vice versa). Since the second switch S2 is deactivated, the second power supply voltage VDD2 is not provided to the drain terminal of the first switch (e.g., node N2), so there is a subthreshold current in the first switch S1. However, the subthreshold current can be ignored because it is relatively smaller than the saturation current I Figure 4C of the transistor 400 shown in sat . For each of the switching devices 1302 to 130N, the second power supply voltage VDD2 is provided to the second terminal near the corresponding DUT (e.g., 1102 to 110N), thereby eliminating the subthreshold current I subThus, the total leakage current of the switching circuit 130 can be significantly reduced. In some embodiments, the second switch S2 of each of the switching devices 1301 to 130N can be implemented using Figure 4A the transistor 400 shown in, and thus its details will not be repeated here.
[0063] Figure 5A is a part of the schematic diagram of the switching circuit according to some embodiments of the present disclosure. Figure 5B is a schematic diagram of the control circuit according to some embodiments of the present disclosure. Figure 5C is Figure 5A the waveform diagram of various signals in the switching circuit in.
[0064] For simplicity, in the Figure 5A embodiment of, the switching circuit 130 includes switching devices 1301 to 1309, and the DUT 110 includes DUTs 1101 to 1109 (i.e., N = 9). In some embodiments, the detection circuit 150 can detect the current I of each DUT (e.g., DUTs 1101 to 1109) DF , where the corresponding switching devices (e.g., switching devices 1301 to 1309) are activated during the testing process of the test device 100. The current I of each common DUT (e.g., DUTs 1101 and 1102) DF can vary. DUTs 1103 to 1109 (e.g., 7 DUTs) can be designed to provide dummy devices with a specific characteristic pattern, allowing the operator to check whether the test device 100 is operating normally based on the specific characteristic pattern. In some embodiments, each of DUTs 1103 to 1109 can be a transistor that provides a specially designed current. Here, it is assumed that L and H represent low current and high current respectively. Additionally, the states of the currents generated by DUTs 1103 to 1109 can be L, H, L, H, L, H, and L respectively.
[0065] Referring to Figure 5C , after the reset signal RESET is deasserted (e.g., logic 1), the testing process of the test device 100 starts. At time t1, the control device 1401 latches the input data signal DIN at the rising edge of the clock signal CLOCK. The behavior of the delay chain formed by the Figure 5B control devices 1401 to 1409 shown in can be referred to Figure 3B and Figure 3C embodiments of, and thus its details will not be repeated here. At time t3, the switching device 1303 is activated (e.g., the first switch is turned on and the second switch is turned off), and the detection circuit 150 can start detecting the low current I from time t3 DF(i.e., L). At time t4, the switching device 1304 is activated, and the detection circuit 150 can start detecting the high current I from time t4 DF (i.e., H). Similarly, the currents I detected by the detection circuit 150 at times t5, t6, t7, t8, and t9 DF can be in the states of L, H, L, H, and L, respectively. Specifically, the testing process of the test device 100 starts, and the detection circuit 150 detects a specific characteristic pattern (e.g., the pattern of the current I DF ) as L, H, L, H, L, H, L within a period of 7 clock cycles (e.g., from time t3 to t10) (including the clock cycle in which the voltage signal VQ is established (e.g., logic 1)). It should be noted that the specific characteristic pattern is not limited to the foregoing pattern, and the number of dummy devices can be adjusted according to actual requirements.
[0066] In some embodiments, an event may occur in the test device 100 that prevents the control circuit 140 from normally reporting the voltage signal VQ. In these cases, the operator of the test device 100 can evaluate the normal operation of the test device 100 by observing whether the test device 100 can generate a specific characteristic pattern (e.g., the pattern of the current I DF ). Therefore, the operator can evaluate the normal operation of the test device 100 through the reported voltage signal VQ or the specific characteristic pattern, thereby improving the reliability of the test device 100 and the efficiency of the testing process.
[0067] Figure 6 is a flowchart of a method for operating a test device according to some embodiments of the present disclosure. Please refer to Figure 1 、 Figure 2 and Figure 6 .
[0068] In operation 610, a test device (e.g., the test device 100 shown in Figure 1 ) including a plurality of switching devices (e.g., the switching devices 1301 to 130N of the switching circuit 130 shown in FIG. 3) and a plurality of devices under test (DUTs) is provided.
[0069] In operation 620, each of the switching devices of the test device is sequentially activated to test the corresponding DUT. For example, the activation of the switching devices 1301 to 130N can be controlled by the corresponding controller devices 1401 to 140N of the control circuit 140. The specific characteristics (e.g., the induced current I DF ) of each DUT can be detected when the corresponding switching circuit of each DUT is activated.
[0070] At operation 630, in response to a particular switching device not being activated, a first power supply voltage (e.g., VDD1) and a second power supply voltage (e.g., VDD2) are applied to a first terminal and a second terminal of a particular switching circuit. In some embodiments, the first power supply voltage VDD1 is substantially equal to the second power supply voltage VDD2. In some embodiments, the second power supply voltage VDD2 provided by the auxiliary control circuit 160 may be higher than the first power supply voltage VDD1 to compensate for the voltage drop caused by the transmission path from the auxiliary control circuit to the particular switching device. In some embodiments, each of the switching circuits may be implemented using a P-type transistor, such as Figures 4A to 4C the transistor 400 shown in. When the transistor 400 is turned off, substantially the same power supply voltage may be applied to the source terminal and the drain terminal of the transistor 400, thereby eliminating the sub-threshold current I from the source terminal and the drain terminal of the transistor 400 sub .
[0071] At operation 640, in response to a particular switching circuit being activated, a power supply voltage and a voltage from a DUT corresponding to the particular switching device are applied to the first terminal and the second terminal of the particular switching device, respectively. In some embodiments, when a particular switching circuit (e.g., a P-type transistor) is activated, a conduction current (e.g., a saturation current I sat ) may flow from the source terminal to the drain terminal. At this time, the sub-threshold current I from the source terminal to the drain terminal sub still exists, but may be ignored because it is relatively smaller than the saturation current I sat .
[0072] Figure 7 is another flowchart of a method for operating a test device according to some embodiments of the present disclosure. Please refer to Figure 1 , Figure 5A and Figure 5C .
[0073] At operation 710, a plurality of devices under test (DUTs) in a test device are provided.
[0074] At operation 720, each of a plurality of switching devices corresponding to the DUTs is sequentially activated during a test process of the test device. For example, the activation of the switching devices 1301 to 130N may be controlled by the corresponding control devices 1401 to 140N of the control circuit 140. A specific characteristic (e.g., an induced current I DF ) of each DUT may be detected when the corresponding switching circuit of each DUT is activated.
[0075] At operation 730, a feature pattern formed by a specific feature of each DUT in the first part of the DUT is detected by a detection circuit of the test device. For example, the first part of the DUT can be a dummy device (e.g., Figure 5A DUTs 1103 to 1109 in
[0076] attached to a normal DUT in test device 100), and each of the dummy devices can have a specific feature (e.g., generating a low current or a high current). The detection circuit 150 can detect the feature pattern formed by the specific feature of each DUT in the first part. Figure 5A and Figure 5C the L, H, L, H, L, H, L pattern of the current IDF shown in
[0077] One aspect of the present disclosure provides a test device that includes a plurality of devices under test (DUTs) and an advanced process control monitor (APCM). The APCM includes a switching circuit, a control circuit, a detection circuit, and an auxiliary control circuit. The switching circuit includes a plurality of switching devices corresponding to the DUTs. The control circuit includes a plurality of control devices corresponding to the switching devices and is configured to sequentially activate one of the switching devices during a test process of the test device. The detection circuit is configured to provide a first power supply voltage to a first terminal of each switching device. The auxiliary control circuit is configured to provide a second power supply voltage to a second terminal of each switching device deactivated by the control circuit.
[0078] Another aspect of the present disclosure provides a method that includes the steps of: providing a test device that includes a plurality of switching devices and a plurality of devices under test (DUTs); sequentially activating each of the switching devices of the test device to test a corresponding DUT; and in response to a specific switching device not being activated, applying a first power supply voltage and a second power supply voltage to a first terminal and a second terminal of the specific switching device, respectively.
[0079] Another aspect of the present disclosure provides a test device, which includes a plurality of devices under test (DUTs) and an advanced process control monitor (APCM). The APCM includes a switching circuit, a control circuit, and a detection circuit. The switching circuit includes a plurality of switching devices corresponding to the DUTs. The control circuit includes a plurality of control devices corresponding to the switching devices, and is configured to sequentially activate one of the switching devices during the test process of the test device. The detection circuit is configured to provide a first power supply voltage to a first terminal of each switching device, and selectively provide a second power supply voltage to a second terminal of each switching device deactivated by the control circuit based on a selection signal from the control device corresponding to each switching device.
[0080] The methods and features of the present disclosure have been fully described in the provided examples and descriptions. It should be understood that any modification or change is intended to be covered within the scope of protection of the present disclosure without departing from the spirit of the present disclosure.
[0081] Furthermore, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in this specification. As will be readily understood by those skilled in the art, current existing or yet-to-be-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be utilized in accordance with the present disclosure.
[0082] Therefore, the appended claims are intended to include processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope. Additionally, each claim constitutes a separate embodiment, and combinations of various claims and embodiments are within the scope of the present disclosure.
[0083] Symbol Explanation
[0084] 100: Test device
[0085] 110: Devices under test (DUT)
[0086] 120: Advanced process control monitor (APCM)
[0087] 130: Switching circuit
[0088] 140: Control circuit
[0089] 140A: Control circuit
[0090] 140B: Control circuit
[0091] 150: Detection circuit
[0092] 160: Auxiliary control circuit
[0093] 301: Clock buffer
[0094] 302: Clock buffer
[0095] 303: Clock buffer
[0096] 400: Transistor
[0097] 402: Shallow trench isolation (STI) region
[0098] 404: Shallow trench isolation (STI) region
[0099] 406: Gate dielectric
[0100] 408: Gate electrode
[0101] 410: Well region / source terminal
[0102] 412: Well region / drain terminal
[0103] 414: Well region / bulk terminal
[0104] 416: Substrate
[0105] 600: Process
[0106] 610: Operation
[0107] 620: Operation
[0108] 630: Operation
[0109] 640: Operation
[0110] 700: Process
[0111] 710: Operation
[0112] 720: Operation
[0113] 730: Operation
[0114] 740: Operation
[0115] 1101 to 110N: Device under test (DUT)
[0116] 1301 to 130N: Switching device
[0117] 1401 to 140N: Control device
[0118] CLK: Clock input terminal
[0119] CLKo: Clock output terminal
[0120] CLOCK: Clock signal
[0121] D: Data input terminal
[0122] DIN: Input data signal
[0123] I DF : Current
[0124] I sat : Conducting current / saturation current
[0125] I sub : Sub - threshold current
[0126] N1: Node
[0127] N2: Node
[0128] N3: Node
[0129] N4: Node
[0130] Q: Data output terminal
[0131] QB: Inverted data output terminal
[0132] RESET: Reset signal
[0133] RST: Reset terminal
[0134] S1: First switch
[0135] S2: Second switch
[0136] SEL1B to SELNB: Selection signal
[0137] SEL1 to SELN: Selection signal
[0138] VDD1: Power supply voltage
[0139] VDD2: Second power supply voltage
[0140] VN2: Voltage
[0141] VQ: Voltage signal.
Claims
1. A testing device comprising: Multiple devices under test (DUTs); and Advanced Process Control Monitor (APCM), which includes: a switching circuit comprising a plurality of switching devices corresponding to the DUT; a control circuit comprising a plurality of control devices corresponding to the switching devices and configured to sequentially activate one of the switching devices during a test process of the test apparatus; a detection circuit configured to provide a first supply voltage to a first terminal of each of the plurality of switching devices; and An auxiliary control circuit is configured to provide a second supply voltage to a second terminal of each of the plurality of switching devices deactivated by the control circuit. 2 . The test apparatus according to claim 1 , wherein the first power supply voltage is substantially equal to the second power supply voltage. 3 . The test apparatus according to claim 1 , wherein the second power supply voltage is higher than the first power supply voltage to compensate for a voltage drop caused by a transmission path from the auxiliary control circuit to each deactivated switching device. 4 . The test apparatus according to claim 1 , wherein each of the control devices comprises a D flip-flop, and the control devices are connected in series. The test apparatus according to claim 1 , wherein each of the switching devices comprises a P-type transistor. 6 . The test apparatus according to claim 1 , wherein the DUT comprises a first portion and a second portion, and each DUT in the second portion is a dummy device having specific features, and the specific features of each DUT in the second portion form a specific feature pattern.
7. A method for operating a test device, the method comprising: Providing a test device including a plurality of switching devices and a plurality of devices under test (DUTs); sequentially activating each of the switching devices of the test apparatus to test the corresponding DUT; and In response to the particular switching device being deactivated, a first power supply voltage and a second power supply voltage are applied to the first terminal and the second terminal of the particular switching device, respectively. The method of claim 7 , wherein the first supply voltage is substantially equal to the second supply voltage.
9. A testing device comprising: Multiple devices under test (DUTs); and Advanced Process Control Monitor (APCM), which includes: a switching circuit comprising a plurality of switching devices corresponding to the DUT; a control circuit comprising a plurality of control devices corresponding to the switching devices and configured to sequentially activate one of the switching devices during a test process of the test apparatus; and A detection circuit is configured to provide a first supply voltage to a first terminal of each switching device and selectively provide a second supply voltage to a second terminal of each switching device deactivated by the control circuit based on a selection signal from the control device corresponding to each switching device.
10. The test apparatus of claim 9, wherein the first power supply voltage is substantially equal to the second power supply voltage.