Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises a plurality of data lines which extend along a first direction and are arranged along a second direction, a plurality of gate lines which extend along the second direction and are arranged along the first direction, and a plurality of pixel units which are arranged in an array, and each pixel unit comprises a dark fringe region; the display panel further comprises a first common electrode, a second common electrode and a third common electrode. The orthographic projection of the first common electrode is at least partially overlapped with the orthographic projection of the pixel electrode in each pixel unit, the second common electrode extends in the first direction, and the orthographic projection of the second common electrode is at least partially overlapped with the orthographic projection of each data line, so that the capacitance of the data lines and the c-com electrodes and the capacitance of the data lines to the pixel electrodes can be reduced; horizontal and vertical crosstalk is improved; the orthographic projection of the third common electrode is located in the dark fringe area of each pixel unit, so that the storage capacitance between the pixel electrode and the common electrode is increased, the voltage retention rate is remarkably improved, and ghost shadows are avoided.

Description

Technical Field

[0001] The present invention belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] In liquid crystal display (LCD) technology, multi-domain pixel designs, such as 4-Domain and 8-Domain, are used to improve viewing angle uniformity and reduce color shift in display panels. In this type of structure, the storage capacitor (cst) between the pixel electrode and the common electrode (v-com) is crucial for maintaining pixel electrode voltage stability. However, existing technologies generally use a single common electrode, and due to aperture restrictions, the overlap area between the pixel electrode and the common electrode is limited, resulting in a small cst capacitance value. This, in turn, reduces pixel voltage stability and makes it prone to image sticking during display.

[0003] In addition, due to the large parasitic capacitance (cdc) between the data line and the opposite common electrode (c-com), the c-com voltage is easily coupled by the display data signal, resulting in horizontal crosstalk on the display panel; at the same time, the capacitance (cdp) between the data line and the pixel electrode is large, and the voltage of the pixel electrode will be coupled with the data voltage. Specifically, in the 4-Domain structure, it manifests as a single coupling, while in the 8-domain structure, it manifests as a dual coupling of the main pixel (Cdp-main) and the sub-pixel (Cdp-sub), both of which will cause the voltage of the pixel electrode to fluctuate with the display data signal and cause vertical crosstalk. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a display panel and a display device. The technical problem to be solved by the present invention is achieved through the following technical solutions: In a first aspect, the present invention provides a display panel comprising: a plurality of data lines extending along a first direction and arranged along a second direction, a plurality of gate lines extending along the second direction and arranged along the first direction, and a plurality of pixel units arranged in an array, each of the pixel units comprising a dark stripe region; The display panel also includes a first common electrode, a second common electrode and a third common electrode; wherein, in a direction perpendicular to the plane of the display panel, the orthographic projection of the first common electrode at least partially overlaps with the orthographic projection of the pixel electrode in each pixel unit, the second common electrode extends along the first direction, and its orthographic projection at least partially overlaps with the orthographic projection of each data line, and the orthographic projection of the third common electrode is respectively located in the dark line area of each pixel unit.

[0005] In one embodiment of the present invention, in the second direction, the width of the third common electrode is equal to or smaller than the width of the dark line area.

[0006] In one embodiment of the present invention, the first common electrode, the second common electrode, and the third common electrode are connected to different common electrode signals.

[0007] In one embodiment of the present invention, an array substrate is further included, and the array substrate includes: Glass substrate; a first metal layer located on one side of the glass substrate, a second metal layer located on a side of the first metal layer away from the glass substrate, an indium tin oxide (ITO) layer located on a side of the second metal layer away from the glass substrate, a first insulating layer located between the first metal layer and the second metal layer, and a second insulating layer located between the second metal layer and the ITO layer; The first common electrode and the gate line are located in a first metal layer, the third common electrode and the data line are located in a second metal layer, and the second common electrode and the pixel electrode are located in the ITO layer.

[0008] In one embodiment of the present invention, a plurality of data lines and a plurality of gate lines intersect to define a plurality of pixel units, and each of the pixel units is divided into four liquid crystal matching areas by a dark pattern area; The dark line area is cross-shaped, including a first dark line area extending along a first direction and a second dark line area extending along a second direction; in a direction perpendicular to the plane where the display panel is located, the positive projection of the third common electrode overlaps with the first dark line area, or is located within the first dark line area.

[0009] In one embodiment of the present invention, each of the pixel units includes a main pixel and a sub-pixel in the first direction, the main pixel and the sub-pixel in the pixel electrode correspond to the main pixel electrode and the sub-pixel electrode, respectively, the gate line is located between the main pixel and the sub-pixel in the same row of pixel units, the dark pattern area includes a main dark pattern area and a sub-dark pattern area, the main pixel is divided into four liquid crystal coordination areas by the main dark pattern area, and the sub-pixel is divided into four liquid crystal coordination areas by the sub-dark pattern area; The main dark pattern area and the sub-dark pattern area are both cross-shaped, the main dark pattern area includes a first main dark pattern area extending along a first direction and a second main dark pattern area extending along a second direction, and the sub-dark pattern area includes a first sub-dark pattern area extending along the first direction and a second sub-dark pattern area extending along the second direction; In a direction perpendicular to the plane of the display panel, the orthographic projection of the third common electrode overlaps with the first main dark line area and the first sub-dark line area, or is located within the first main dark line area and the first sub-dark line area.

[0010] In one embodiment of the present invention, each of the pixel units further includes: a first thin film transistor TFT1, a second thin film transistor TFT2 and a third thin film transistor TFT3; wherein, The gates of TFT1, TFT2 and TFT3 are connected to the gate line corresponding to the row of the pixel unit, the drains of TFT1 and TFT2 are connected to the data line corresponding to the column of the pixel unit, the source of TFT1 is connected to the main pixel electrode, the source of TFT2 is connected to the sub-pixel electrode, the source of TFT3 is connected to the third common electrode, and the drain of TFT3 is connected to the sub-pixel electrode.

[0011] In a second aspect, the present invention further provides a display device comprising the display panel as described in the first aspect.

[0012] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention provides a display panel and a display device, which introduce a third common electrode vcom3 into the dark stripe area of each pixel unit, and make the positive projection of each third common electrode vcom3 located in the dark stripe area of each pixel unit in a direction perpendicular to the plane where the display panel is located, thereby increasing the storage capacitance between the pixel electrode and the common electrode, can more effectively store charge, counteract leakage current after the thin film transistor is turned off, significantly improve voltage holding rate, and avoid the occurrence of afterimage.

[0013] (2) The present invention also introduces a second common electrode vcom2. Each second common electrode vcom2 extends along the first direction, and its orthographic projection at least partially overlaps with the orthographic projection of each data line. This can reduce the capacitance Cdc between the data line DL and the c-com electrode of the opposite plate, thereby reducing the coupling of the data line DL to the c-com electrode, alleviating horizontal crosstalk, and at the same time reducing the capacitance Cdp of the data line DL to the pixel electrode, thereby reducing the coupling of the data line DL to the pixel electrode and improving vertical crosstalk.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention; Figure 2 This is a partial schematic diagram of a display area in a display panel provided by an embodiment of the present invention; Figure 3 is another partial schematic diagram of a display area in a display panel provided by an embodiment of the present invention; Figure 4 yes Figure 2 Schematic diagram of the circuit of the pixel unit in the 4-Domain pixel structure shown; Figure 5 yes Figure 3 Schematic diagram of the circuit of the pixel unit in the 8-Domain pixel structure shown; Figure 6 1 is a schematic diagram of a film layer of an array substrate at the AA' cross section provided by an embodiment of the present invention; Figure 7 2 is a schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0017] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figures 2 and 3 FIG is a partial schematic diagram of a display area in a display panel provided by an embodiment of the present invention. Figures 1-3 An embodiment of the present invention provides a display panel 100, comprising: a plurality of data lines DL extending along a first direction x and arranged along a second direction y, a plurality of gate lines GL extending along the second direction y and arranged along the first direction x, and a plurality of pixel units 1 arranged in an array, each pixel unit 1 including a dark stripe region 2; The display panel 100 also includes a first common electrode vcom1, multiple second common electrodes vcom2 and multiple third common electrodes vcom3; wherein, in a direction perpendicular to the plane of the display panel 100, the orthographic projection of the first common electrode vcom1 at least partially overlaps with the orthographic projection of the pixel electrode in each pixel unit 1, the second common electrode vcom2 extends along the first direction, and its orthographic projection at least partially overlaps with the orthographic projection of each data line DL, and the orthographic projection of the third common electrode vcom3 is respectively located in the dark line area 2 of each pixel unit 1.

[0018] Specifically, Figure 1 The display panel 100 shown includes a display area and a non-display area. The non-display area can be located outside the display area. The display area includes multiple data lines DL and multiple gate lines GL. The multiple data lines DL extend along a first direction x and are arranged along a second direction y. The multiple gate lines GL extend along the second direction y and are arranged along the first direction x. The first direction x intersects with the second direction y. Multiple pixel units 1 are arranged in the display area in the form of an array.

[0019] It should be noted that Figure 1 It is only used to illustrate the display area of the display panel 100 and does not constitute a limitation on the shape or structure of the display panel 100. For example, in some other embodiments of the present application, the display panel 100 may be of an irregular shape, and the non-display area may only surround part of the display area.

[0020] Furthermore, please combine Figures 2 and 3, the display panel 100 further includes a first common electrode vcom1 , a second common electrode vcom2 and a third common electrode vcom3 .

[0021] For example, in a direction perpendicular to the plane of the display panel 100, the orthographic projection of the first common electrode vcom1 at least partially overlaps with the orthographic projection of the pixel electrode in each pixel unit 1. In the prior art, each pixel unit 1 includes only one common electrode. In a direction perpendicular to the plane of the display panel 100, the orthographic projection of the common electrode partially overlaps with the orthographic projection of the pixel electrode. However, considering the aperture ratio of the display panel 100, the amount of overlap between the two is limited, and therefore the storage capacitance (cst) formed is also limited. This results in insufficient ability to stabilize the pixel voltage, causing display image sticking. To address this issue, this embodiment introduces a third common electrode vcom3 in the dark stripe region 2 of each pixel unit 1. In a direction perpendicular to the plane of the display panel 100, the orthographic projection of the third common electrode vcom3 is located within the dark stripe region 2 of each pixel unit 1. This design increases the storage capacitance between the pixel electrode and the common electrode, allowing for more effective charge storage, counteracting leakage current after the thin-film transistor is turned off, significantly improving voltage holding ratio, and avoiding image sticking.

[0022] It should be noted that the first common electrode vcom1 includes an opening at each pixel electrode. That is, the orthographic projection of the first common electrode vcom1 actually only overlaps with the periphery of the orthographic projection of each pixel electrode. In addition, this embodiment also introduces a second common electrode vcom2. The second common electrode vcom2 extends along the first direction, and its orthographic projection at least partially overlaps with the orthographic projection of each data line DL.

[0023] Optionally, in the second direction y, the width of the third common electrode vcom3 is equal to or smaller than the width of the dark line region 2 , so as to ensure the aperture ratio of the display panel 100 .

[0024] The display panel 100 may adopt a multi-domain pixel structure, such as Figure 2 The 4-Domain pixel structure shown is Figure 3 In the 8-Domain pixel structure shown, a dark stripe region 2 is formed at the domain boundary in each pixel unit 1.

[0025] For more details, please see Figure 2 Taking the 4-Domain pixel structure as an example, multiple data lines DL and multiple gate lines GL intersect to define multiple pixel units 1, and each pixel unit 1 is divided into four liquid crystal matching areas by the dark pattern area 2; The dark line area 2 is cross-shaped, including a first dark line area 21 extending along the first direction and a second dark line area 22 extending along the second direction; in a direction perpendicular to the plane of the display panel 100, the orthographic projection of the third common electrode vcom3 overlaps with the first dark line area 21, or is located within the first dark line area 21.

[0026] Figure 4 yes Figure 2 The circuit diagram of the pixel unit in the 4-Domain pixel structure shown in the figure, wherein Clc (Liquid Crystal Capacitance) represents a liquid crystal capacitor, whose upper and lower electrodes are respectively a pixel electrode and a c-com electrode to the plate, Cst1 represents a first storage capacitor, whose upper and lower electrodes are respectively a pixel electrode and a first common electrode vcom1, Cst2 represents a second storage capacitor, whose upper and lower electrodes are respectively a pixel electrode and a third common electrode vcom3, Cdp refers to the capacitance of the data line DL to the pixel electrode, and Cda refers to the capacitance of the data line DL to the second common electrode vcom2. In the display panel 100, each pixel unit 1 also includes: a thin film transistor (TFT), please combine Figure 2 and Figure 4 The gate of the thin film transistor is connected to the gate line GL, the drain is connected to the data line, and the source is connected to the pixel electrode. In addition, an 8-Domain pixel structure can also be used. Please continue to refer to Figure 3 Each pixel unit 1 includes a main pixel 11 and a sub-pixel 12 in the first direction. The main pixel 11 and the sub-pixel 12 in the pixel electrodes correspond to the main pixel 11 electrode and the sub-pixel 12 electrode, respectively. The gate line GL is located between the main pixel 11 and the sub-pixel 12 in the same row of pixel units 1. The dark pattern area 2 includes a main dark pattern area 21' and a sub-dark pattern area 22'. The main pixel 11 is divided into four liquid crystal coordination areas by the main dark pattern area 21', and the sub-pixel 12 is divided into four liquid crystal coordination areas by the sub-dark pattern area 22'. The main dark pattern area 21' and the sub-dark pattern area 22' are both cross-shaped. The main dark pattern area 21' includes a first main dark pattern area 21a extending along the first direction and a second main dark pattern area 21b extending along the second direction. The sub-dark pattern area 22' includes a first sub-dark pattern area 22a extending along the first direction and a second sub-dark pattern area 22b extending along the second direction. In a direction perpendicular to the plane of the display panel 100 , the orthographic projection of the third common electrode vcom3 overlaps with the first main dark line area 21 a and the first sub dark line area 21 b , or is located within the first main dark line area 21 a and the first sub dark line area 21 b .

[0027] Figure 5 yes Figure 3The circuit diagram of the pixel unit in the 8-Domain pixel structure shown in the figure, wherein Clc-main and Clc-sub are liquid crystal capacitors, the upper and lower electrodes of Clc-main are the main pixel electrode and the c-com electrode of the opposite plate, respectively, the upper and lower electrodes of the storage capacitor Cst1-main are the main pixel electrode and the first common electrode vcom1, respectively, the upper and lower electrodes of the storage capacitor Cst2-main are the main pixel electrode and the third common electrode vcom3, respectively, Cdp-main refers to the capacitance of the data line DL to the main pixel electrode, the upper and lower electrodes of Clc-sub are the sub-pixel electrode and the c-com electrode of the opposite plate, the upper and lower electrodes of the storage capacitor Cst1-cub are the sub-pixel electrode and the first common electrode vcom1, respectively, the upper and lower electrodes of the storage capacitor Cst2-sub are the sub-pixel electrode and the third common electrode vcom3, respectively, and Cdp-sub refers to the capacitance of the data line DL to the sub-pixel electrode. For further information, please refer to Figure 3 and Figure 5 In the 8-Domain pixel structure, each pixel unit 1 further includes: a first thin film transistor TFT1, a second thin film transistor TFT2 and a third thin film transistor TFT3; wherein, The gates of TFT1, TFT2 and TFT3 are connected to the gate line GL corresponding to the row where the pixel unit 1 is located, the drains of TFT1 and TFT2 are connected to the data line DL corresponding to the column where the pixel unit 1 is located, the source of TFT1 is connected to the main pixel electrode, the source of TFT2 is connected to the sub-pixel electrode, the source of TFT3 is connected to the third common electrode vcom3, and the drain of TFT3 is connected to the sub-pixel electrode.

[0028] Optionally, the first common electrode vcom1, the second common electrode vcom2 and the third common electrode vcom3 are connected to different common electrode signals, wherein the first common electrode vcom1 is used to provide a storage voltage, the second common electrode vcom2 is used to shield the data line DL signal, and keep the voltage difference between the second common electrode vcom2 and the c-com electrode as small as possible, thereby minimizing the dark state brightness and improving the contrast. The third common electrode vcom3 provides a storage voltage in the 4-domain and 8-domain pixel structures, and can also provide the TFT3 divided voltage in the 8-Domain pixel structure, thereby individually adjusting the color deviation to meet customer needs.

[0029] Figure 6 Schematic diagram of the basic film layer of the array provided by the embodiment of the present invention. In this embodiment, the display panel 100 further includes an array substrate 3, such as Figure 6 The array substrate 3 includes: Glass substrate; A first metal layer M1 located on one side of the glass substrate, a second metal layer M2 located on a side of the first metal layer M1 away from the glass substrate, an indium tin oxide (ITO) layer located on a side of the second metal layer M2 away from the glass substrate, a first insulating layer located between the first metal layer M1 and the second metal layer M2, and a second insulating layer located between the second metal layer M2 and the ITO layer; The first common electrode vcom1 and the gate line GL are located in the first metal layer, the third common electrode vcom3 and the data line DL are located in the second metal layer, and the second common electrode vcom2 and the pixel electrode are located in the ITO layer.

[0030] It should be understood that the display panel 100 includes an array substrate 3 and a color film substrate arranged opposite to the array substrate 3. Since the orthographic projection of the second common electrode vcom2 overlaps with the orthographic projection of the data line DL, and the second common electrode vcom2 is located in the ITO layer and the data line DL is located in the second metal layer, it is equivalent to adding a second common electrode vcom2 between the data line DL and the opposite plate c-com electrode, shielding the electric field between the data line and the opposite plate c-com electrode, so as to reduce the capacitance Cdc of the data line DL and the opposite plate c-com electrode, thereby reducing the coupling of the data line DL to the c-com electrode, reducing the horizontal crosstalk, and at the same time reducing the capacitance Cdp of the data line DL to the pixel electrode, so as to reduce the coupling of the data line DL to the pixel electrode and improve the vertical crosstalk.

[0031] In addition, in this embodiment, the second insulating layer between the second metal layer M2 and the ITO layer may be one layer or multiple layers. Exemplarily, the multiple second insulating layers include but are not limited to a color layer, a PFA layer, and a passivation layer.

[0032] Figure 7 Schematic diagram of the structure of the display device provided by the embodiment of the present invention. Figure 7 As shown, an embodiment of the present invention further provides a display device 200 , comprising the above-mentioned display panel 100 . Figure 7 This embodiment uses a mobile phone as an example to illustrate the display device 200. It is understood that the display device 200 provided in the embodiment of the present invention can be other display devices 200 with display functions, such as smart watches, computers, televisions, and vehicle-mounted display devices, and the present invention does not specifically limit this. The display device 200 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention. For details, please refer to the detailed description of the display panel 100 in the above embodiments, and this embodiment will not be repeated here.

[0033] It can be seen from the above embodiments that the beneficial effects of the present invention are: (1) The present invention provides a display panel and a display device, which introduce a third common electrode vcom3 into the dark stripe area of each pixel unit, and make the positive projection of each third common electrode vcom3 located in the dark stripe area of each pixel unit in a direction perpendicular to the plane where the display panel is located, thereby increasing the storage capacitance between the pixel electrode and the common electrode without reducing the aperture ratio, and can more effectively store charge to counteract the leakage current after the thin film transistor is turned off, significantly improve the voltage holding ratio, and avoid the occurrence of afterimages.

[0034] (2) The present invention also introduces a second common electrode vcom2. Each second common electrode vcom2 extends along the first direction, and its orthographic projection at least partially overlaps with the orthographic projection of each data line. This can reduce the capacitance Cdc between the data line DL and the c-com electrode of the opposite plate, thereby reducing the coupling of the data line DL to the c-com electrode, alleviating horizontal crosstalk, and at the same time reducing the capacitance Cdp of the data line DL to the pixel electrode, thereby reducing the coupling of the data line DL to the pixel electrode and improving vertical crosstalk.

[0035] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0036] Descriptions with reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0037] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: a plurality of data lines extending along a first direction and arranged along a second direction, a plurality of gate lines extending along the second direction and arranged along the first direction, and a plurality of pixel units arranged in an array, each of the pixel units including a dark stripe region; The display panel also includes a first common electrode, a second common electrode and a third common electrode; wherein, in a direction perpendicular to the plane of the display panel, the orthographic projection of the first common electrode at least partially overlaps with the orthographic projection of the pixel electrode in each pixel unit, the second common electrode extends along the first direction, and its orthographic projection at least partially overlaps with the orthographic projection of each data line, and the orthographic projection of the third common electrode is respectively located in the dark line area of each pixel unit.

2. The display panel according to claim 1, wherein: In the second direction, the width of the third common electrode is equal to or smaller than the width of the dark line area.

3. The display panel according to claim 2, wherein: The first common electrode, the second common electrode, and the third common electrode are connected to different common electrode signals.

4. The display panel according to claim 3, wherein: The array substrate further comprises: Glass substrate; a first metal layer located on one side of the glass substrate, a second metal layer located on a side of the first metal layer away from the glass substrate, an indium tin oxide (ITO) layer located on a side of the second metal layer away from the glass substrate, a first insulating layer located between the first metal layer and the second metal layer, and a second insulating layer located between the second metal layer and the ITO layer; The first common electrode and the gate line are located in a first metal layer, the third common electrode and the data line are located in a second metal layer, and the second common electrode and the pixel electrode are located in the ITO layer.

5. The display panel according to claim 4, wherein: A plurality of data lines and a plurality of gate lines intersect to define a plurality of pixel units, and each of the pixel units is divided into four liquid crystal matching areas by a dark pattern area; The dark line area is cross-shaped, including a first dark line area extending along a first direction and a second dark line area extending along a second direction; in a direction perpendicular to the plane where the display panel is located, the positive projection of the third common electrode overlaps with the first dark line area, or is located within the first dark line area.

6. The display panel according to claim 4, wherein: Each of the pixel units includes a main pixel and a sub-pixel in a first direction, the main pixel and the sub-pixel in the pixel electrode correspond to the main pixel electrode and the sub-pixel electrode respectively, the gate line is located between the main pixel and the sub-pixel in the same row of pixel units, the dark pattern area includes a main dark pattern area and a sub-dark pattern area, the main pixel is divided into four liquid crystal coordination areas by the main dark pattern area, and the sub-pixel is divided into four liquid crystal coordination areas by the sub-dark pattern area; The main dark pattern area and the sub-dark pattern area are both cross-shaped, the main dark pattern area includes a first main dark pattern area extending along a first direction and a second main dark pattern area extending along a second direction, and the sub-dark pattern area includes a first sub-dark pattern area extending along the first direction and a second sub-dark pattern area extending along the second direction; In a direction perpendicular to the plane of the display panel, the orthographic projection of the third common electrode overlaps with the first main dark line area and the first sub-dark line area, or is located within the first main dark line area and the first sub-dark line area.

7. The display panel according to claim 4, wherein: Each of the pixel units further includes: a first thin film transistor TFT1, a second thin film transistor TFT2 and a third thin film transistor TFT3; wherein, The gates of TFT1, TFT2 and TFT3 are connected to the gate line corresponding to the row of the pixel unit, the drains of TFT1 and TFT2 are connected to the data line corresponding to the column of the pixel unit, the source of TFT1 is connected to the main pixel electrode, the source of TFT2 is connected to the sub-pixel electrode, the source of TFT3 is connected to the third common electrode, and the drain of TFT3 is connected to the sub-pixel electrode.

8. A display device, characterized in that: The device comprises a display panel as claimed in any one of claims 1 to 7.

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