PLC instruction system

Abstract

The invention provides a PLC instruction system, which relates to the technical field of programmable logic controllers and comprises an instruction actuator, a register and a memory mechanism. The instruction executor is used for executing instructions stored in a program block, accessing a register and a memory mechanism according to the instructions, and interacting in the PLC instruction system through the instructions stored in the program block; the register is used for storing a bit logic result which runs at present; and the memory mechanism is used for storing data and is accessed by a program. According to the instruction executor, the internal formats of the PLC instruction system are unified through the instructions stored in the program block, the access register and the memory mechanism, the effect of unifying the formats is achieved, and the problem that the PLC instruction system is not unified in the related technology is solved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of programmable logic controllers, and in particular to a PLC instruction system. Background Art

[0002] Currently, there are numerous Programmable Logic Controller (PLC) products on the market. Although the programming languages of various PLC products are basically the same, each company designs its own PLC instruction system, resulting in inconsistent internal instruction systems.

[0003] With regard to the problem of inconsistent PLC instruction systems in related technologies, no effective technical solution has yet been proposed. Summary of the Invention

[0004] The main purpose of the present disclosure is to provide a PLC instruction system to solve the problem of inconsistent PLC instruction systems in related technologies.

[0005] To achieve the above-mentioned object, a first aspect of the present disclosure provides a PLC instruction system, including an instruction executor, a register, and a memory mechanism; The instruction executor is used to execute the instructions stored in the program block, access registers and memory mechanisms according to the instructions, and interact within the PLC instruction system through the instructions stored in the program block; The register is used to store the bit logic result of the current operation; The memory mechanism is used to store data and is accessed by programs.

[0006] Optionally, the memory mechanism includes a global memory and a local memory; The global memory acts globally and is accessible to all programs; The local memory acts on the memory area used within the program, including temporary variable memory, anonymous variable memory, parameter block memory and pointer memory.

[0007] Optionally, the instruction includes an operation code and a plurality of operands; The operation code is used to represent a function or a type of function, and the format of the operation code determines the number of the operands.

[0008] Furthermore, the operand includes a plurality of prefix modifications and real data; Each prefix modification is 8 bits, the upper 3 bits of the prefix modification are used to identify the type of the operand, and the lower 5 bits of the prefix modification are determined by the operand; The value and number of bytes of the actual data are determined by the value of the prefix modification in the operand.

[0009] Furthermore, the instruction also includes an opcode and a modifier; The operation subcode is used to indicate a specific function in a class of functions indicated by the current operation code.

[0010] Optionally, the program blocks include system organization blocks, system functions, system function blocks, user functions, user function blocks and user organization blocks; The system function, system function block, user function and user function block are used to be called by the user, prepare local block memory for the function through function preparation instructions, pass input parameters, enter the function after preparation is ready and the input parameters are passed, execute the operation corresponding to the function, obtain output parameters, and release the local block memory prepared for the function.

[0011] Furthermore, the instruction executor includes an execution instruction set; The execution instruction set is used to represent the instructions contained in the instruction executor.

[0012] Furthermore, the execution instruction set includes system instructions, the system functions, system function blocks, user functions and user function blocks; The system instructions, system functions and system function blocks are defined within the PLC instruction system, and the user functions and user function blocks are defined by the user.

[0013] Furthermore, the system instructions, system functions and system function blocks are designed from statements or instructions in the PLC programming language; The system function block is used to represent statements that require a local block in the PLC programming language.

[0014] Optionally, the system function is also used to design a jump instruction suitable for the ENO mechanism, and judge whether the current instruction block executes a jump according to the RLO value. If the RLO is 0, it directly jumps to the label and runs other instructions. If the RLO is 1, no jump occurs, and the next instruction is directly run to perform the program block access operation.

[0015] The PLC instruction system provided in the embodiments of the present disclosure includes an instruction executor, registers, and a memory mechanism. The instruction executor is used to execute instructions stored in a program block, access the registers and memory mechanism based on the instructions, and interact within the PLC instruction system through the instructions stored in the program block. The registers are used to store the bit logic results of the current operation; the memory mechanism is used to store data and is accessed by the program. The instruction executor accesses the registers and memory mechanism through the instructions stored in the program block, thus unifying the format within the PLC instruction system. This has the effect of unifying the format and solves the problem of inconsistent PLC instruction systems in related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related technologies, the following briefly introduces the drawings required for use in the specific embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 This is an architectural diagram of the PLC instruction system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0019] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatus.

[0020] Furthermore, the terms "installed," "disposed," "provided with," "connected," "connected," and "socketed" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0021] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] Currently, there are numerous Programmable Logic Controller (PLC) products on the market. PLC instructions are the machine instructions used by PLCs. Although the programming languages of various PLC products are basically the same, each company designs its own PLC instruction system, resulting in inconsistent internal instruction systems.

[0023] In order to solve the above problems, the present disclosure provides a PLC instruction system, such as Figure 1 As shown, the PLC instruction system includes an instruction executor, registers and memory mechanisms; The instruction executor is used to execute the instructions stored in the program block, access registers and memory structures according to the instructions, and interact within the PLC instruction system through the instructions stored in the program block; the instructions stored in the program block are read and executed by the instruction executor; A register is used to store the bit logic result of the current operation. PLC programming languages include ladder diagram language, instruction list language, function block diagram language, structured text language, etc. This disclosure uses ladder diagram language as an example to explain the technical solution. Based on the characteristics of ladder diagram language, a 1-bit logic operation result (Result of Logic Operation, abbreviated as RLO) register is designed to store the bit logic result of the current operation. In addition, required registers can be added as needed, and corresponding instructions can be added to the program block to access the registers.

[0024] Memory is a structure used to store data and accessed by programs.

[0025] In the embodiment of the present disclosure, the instruction executor accesses registers and memory structures through instructions stored in the program block, unifies the format within the PLC instruction system, has the function of unifying the format, and solves the problem of inconsistent PLC instruction systems in related technologies.

[0026] In an optional embodiment of the present disclosure, the memory mechanism includes a global memory and a local memory; Global memory acts globally and is accessible to all programs. All programs can access global memory, such as input I, output Q, bit memory M, data block DB, etc. Local memory acts on the memory area used within the program, including temporary variable memory, anonymous variable memory, parameter block memory, and pointer memory. Local memory is the memory area used by the program itself, namely temporary variable memory L, anonymous variable memory A, parameter block memory ARG, and pointer memory PTR; among them, temporary variable memory L is a user-defined temporary variable area that the user can monitor and force; anonymous variable memory A is a variable area generated on demand during compilation, which is invisible to the user and cannot be monitored and forced; parameter block memory ARG is an area where users define input parameters and output parameters; pointer memory PTR is an area where non-user-declared pointers are stored. For example, if an input parameter defines a relatively large variable, the compiler will recognize it as a pointer value, and the variable is in the pointer memory area.

[0027] In an optional embodiment of the present disclosure, an instruction includes an opcode and multiple operands; the operands have various categories and can be constants, variables, expressions, or function return values; the opcode is 8 bits, the operand is 8N bits, and N is a natural number; An opcode represents a function or a class of functions. The format of the opcode determines the number of operands. For example, if the opcode is addition, three operands are required: addend, addend, and sum.

[0028] In an optional embodiment of the present disclosure, the instruction further includes an operand code and a modifier; the operand code is 8 bits and the modifier is 8N bits; The operation subcode is used to indicate a specific function within a class of functions indicated by the current operation code.

[0029] For example, an instruction may include an opcode, an opcode, modifiers, and m operands (m>1). The specific format is shown in Table 1 below: Table 1

[0030] The embodiments of the present disclosure provide a specific format of instructions, which can unify the instruction format.

[0031] In an optional embodiment of the present disclosure, the operand includes a plurality of prefix modifications and real data; Each prefix modification is 8 bits. The upper 3 bits of the prefix modification are used to identify the type of operand, and the lower 5 bits of the prefix modification are determined by the operand. A total of 8 types of operands can be defined by prefix modification. The actual data value and number of bytes are determined by the prefix value of the operand. The actual data is 8N bits.

[0032] For example, an operand may include n prefix modifications (n>1) and actual data. The specific format is shown in Table 2 below: Table 2

[0033] Taking a constant operand as an example, assuming the category code of the constant operand is 0x0, the format definition of the prefix-modified lower 5 bits is shown in Table 3 below: Table 3

[0034] Among them, the value starting with 0x is a hexadecimal integer constant; the above constant operands are flexible and variable, which can reduce the number of bytes of the generated bytecode, and the embodiment of the present disclosure provides a specific format of operands and prefix modifications, which can unify the operand format and prefix modification format.

[0035] In an optional embodiment of the present disclosure, a program block includes a system organization block, a system function, a system function block, a user function, a user function block, and a user organization block; a program unit (POU) of a PLC instruction system can be divided into a system organization block (SOB), a system function (SFC), a system function block (SFB), a user function (UFC), a user function block (UFB), and a user organization block (UOB); System functions, system function blocks, user functions, and user function blocks are used to be called by users. They prepare local block memory for the function through function preparation instructions, pass input parameters, enter the function after preparation is ready and input parameters are passed, execute the corresponding operations of the function, obtain output parameters, and release the local block memory prepared for the function.

[0036] Except for the system organization block (SOB) and user organization block (UOB), other blocks can be called by users. The calling process is as follows: Function preparation instructions: such as sfc, sfb, ufc, ufb, etc. These instructions will create program block frames to prepare for passing parameters; Parameter passing instructions: such as push, pushb, pushw, pushd, pushq, etc.; Execute instruction: when ready and parameters are passed, execute the program block, call, etc. Get output parameters: such as pop, popb, popw, popd, popq, etc.; Release the local block memory prepared for the program: end.

[0037] When calling, first prepare the local block memory for the program to be called through the function preparation instructions sfc, sfb, ufc, ufb, etc., then pass the parameters, execute the called program, obtain the parameters to be output, and finally release the local block memory prepared for the program; for the calling process of different blocks in the program block, the operations performed are the same, but the input parameters, output parameters or offset data are different, and the calling method is highly scalable.

[0038] For example, suppose a system function (SFC) declared as (Input bool in, Inout bool inout, Output int out) is called, and its number is 0. The pseudo code description of its call is as follows: sfc 0 / / Prepare local block memory such as parameter block for function number 0 push true,0 / / Push true to the input parameter in, 0 represents the offset of the parameter in push bvar,1 / / Push bvar to the input parameter inout, 1 represents the offset of inout enter / / Enter the function and perform the corresponding operations pop 1,bvar / / Get the parameter value and save it to parameter bvar, 1 represents the offset of inout pop 2,tvar / / Get the parameter value and store it in variable tvar, 2 represents the offset of out end / / Release the local block memory prepared for the function In an optional embodiment of the present disclosure, the instruction executor includes executing an instruction set; The execution instruction set is used to represent the instructions contained in the instruction executor.

[0039] In an optional embodiment of the present disclosure, the execution instruction set includes system instructions, system functions, system function blocks, user functions and user function blocks; the execution instruction set can be divided into system instructions (INS), system functions (SFC), system function blocks (SFB), user functions (UFC) and user function blocks (UFB); System instructions, system functions, and system function blocks are defined within the PLC instruction system, while user functions and user function blocks are user-defined. The PLC instruction system supports data types including basic types, arrays, pointers, system types (SDTs), and user types (UDTs). The execution instruction set provided by the disclosed embodiments can provide a reliable reference for designing specific instruction sets and is highly scalable.

[0040] In an optional embodiment of the present disclosure, the system instructions, system functions and system function blocks are designed from statements or instructions in a PLC programming language; System function blocks are used to represent statements that require local blocks in PLC programming languages.

[0041] Statements or instructions in PLC programming languages can be designed with different formats and data types depending on the operation. If an operation requires a local block to store information for user access, it can be designed as a system function block; if an operation requires a large number of parameters, it can be designed as a system function; if an operation requires fewer parameters, it can be designed as a system instruction. Taking ladder logic as an example, a normally open contact can be designed as a system instruction, a counter can be designed as a system function block, and a timer can be designed as a corresponding instruction to operate the DB instance defined by the timer.

[0042] In an optional embodiment of the present disclosure, the system function is also used to design a jump instruction suitable for the ENO mechanism, and determines whether the current instruction block executes a jump based on the RLO value. If the RLO is 0, it jumps directly to the label and executes other instructions. If the RLO is 1, no jump occurs, and the next instruction is executed directly to perform the program block access operation.

[0043] The ENO (enable output) mechanism in Siemens PLCs determines whether the current instruction block is executed based on the value of the RLO. Therefore, a jump instruction is designed specifically for the ENO mechanism, such as the instruction jen offset. The pseudo code is as follows: jen L100 / / Perform EN conditional judgment to determine whether to jump to the last line label sfc 1, / / Prepare local block memory such as parameter block for function number 1 push true,0 / / Push true to in, 0 represents the offset of in push bvar,1 / / Push bvar to inout, 1 represents the offset of inout enter / / Enter the function and perform the corresponding operations pop 1,bvar / / Get the inout value to bvar, 1 represents the offset of inout pop 2,tvar / / Get the out value and save it to tvar, 2 represents the offset of out end / / Release the local block memory prepared for the function L100: / / label When the instruction executor executes to jen, if the RLO is 0, it jumps directly to the label L100 and runs other instructions; if the RLO is 1, no jump occurs and the next instruction is run directly to perform the program block access operation.

[0044] For some instructions, there are versions that support and do not support the EN / ENO (enable input / enable output) mechanism.

[0045] Combined with the functions of PLC programming language, specific instruction design can be carried out; for example, for normally open contacts, there are three corresponding instructions, namely LD, A, and O in the STL language, among which LD stands for Load, which is used for normally closed contacts, A stands for And and normally closed, which is used for normally closed contacts in series, and O stands for Or or normally closed, which is used for normally closed contacts in parallel.

[0046] The disclosed embodiments can provide a reliable reference for designing specific instruction sets, can be combined with the functions of the PLC programming language to design specific instructions, and have high scalability.

[0047] From the above description, it can be seen that the present disclosure achieves the following technical effects: The instruction executor in the present disclosure accesses registers and memory structures through instructions stored in program blocks, unifies the internal format of the PLC instruction system, has the function of unifying the format, and solves the problem of inconsistent PLC instruction systems in related technologies. Compared with the related art, the present disclosure can unify the instruction format, operand format and prefix modification format; This disclosure provides a reliable reference for designing specific instruction sets and has high scalability.

[0048] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0049] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A PLC instruction system, characterized in that: Includes instruction execution unit, registers and memory mechanism; The instruction executor is used to execute the instructions stored in the program block, access registers and memory mechanisms according to the instructions, and interact within the PLC instruction system through the instructions stored in the program block; The register is used to store the bit logic result of the current operation; The memory mechanism is used to store data and is accessed by programs.

2. The PLC instruction system according to claim 1, characterized in that: The memory mechanism includes a global memory and a local memory; The global memory acts globally and is accessible to all programs; The local memory acts on the memory area used within the program, including temporary variable memory, anonymous variable memory, parameter block memory and pointer memory.

3. The PLC instruction system according to claim 1, characterized in that: The instruction includes an operation code and a plurality of operands; The operation code is used to represent a function or a type of function, and the format of the operation code determines the number of the operands.

4. The PLC instruction system according to claim 3, characterized in that: The operand includes multiple prefix modifications and real data; Each prefix modification is 8 bits, the upper 3 bits of the prefix modification are used to identify the type of the operand, and the lower 5 bits of the prefix modification are determined by the operand; The value and number of bytes of the actual data are determined by the value of the prefix modification in the operand.

5. The PLC instruction system according to claim 3, characterized in that: The instruction also includes an opcode and modifiers; The operation subcode is used to indicate a specific function in a class of functions indicated by the current operation code.

6. The PLC instruction system according to claim 1, characterized in that: The program blocks include system organization blocks, system functions, system function blocks, user functions, user function blocks and user organization blocks; The system function, system function block, user function and user function block are used to be called by the user, prepare local block memory for the function through function preparation instructions, pass input parameters, enter the function after preparation is ready and the input parameters are passed, execute the operation corresponding to the function, obtain output parameters, and release the local block memory prepared for the function.

7. The PLC instruction system according to claim 6, characterized in that: The instruction executor includes an execution instruction set; The execution instruction set is used to represent the instructions contained in the instruction executor.

8. The PLC instruction system according to claim 7, characterized in that: The execution instruction set includes system instructions, the system function, the system function block, the user function and the user function block; The system instructions, system functions and system function blocks are defined within the PLC instruction system, and the user functions and user function blocks are defined by the user.

9. The PLC instruction system according to claim 8, characterized in that: The system instructions, system functions and system function blocks are designed by statements or instructions in the PLC programming language; The system function block is used to represent statements that require a local block in the PLC programming language.

10. The PLC instruction system according to claim 6, characterized in that: The system function is also used to design a jump instruction suitable for the ENO mechanism. It determines whether the current instruction block executes a jump based on the RLO value. If the RLO is 0, it directly jumps to the label and executes other instructions. If the RLO is 1, no jump occurs and the next instruction is directly executed to perform the program block access operation.

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