Microprocessor architecture and voltage regulation method

Abstract

The invention relates to the technical field of chips, and discloses a microprocessor architecture and a voltage regulation method, the microprocessor architecture adopts a modular hierarchical design, and a processor core converts an external voltage regulation request into a standardized voltage regulation task parameter after receiving the external voltage regulation request. And the voltage control module receives the voltage regulation task parameters issued by the processor core, and dynamically determines an unoccupied target core unit in the at least one voltage regulation core unit. And configuring an effective communication path between the peripheral control module and the power management module through the target core unit, so that the power management module executes a voltage regulation task corresponding to the voltage regulation task parameter. Therefore, the voltage regulation task executed by the processor core in the related technology is unloaded to the voltage control module, and computing resources occupied by the voltage regulation task on the processor core are reduced.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a microprocessor architecture and a voltage regulation method. Background Art

[0002] As application scenarios become more complex, system-on-chip (SOC) devices need to handle a variety of peripheral operation tasks, such as voltage regulation and temperature monitoring. In related centralized architectures, the processor core is mainly used to control peripheral units to perform peripheral operation tasks.

[0003] However, the computing resources occupied by voltage regulation tasks on the processor core will affect the performance of the processor core. Therefore, it is urgent to propose a new microprocessor architecture. Summary of the Invention

[0004] The present application provides a microprocessor architecture and a voltage regulation method, which solves the technical problem that voltage regulation operation tasks affect the performance of the processor core, and achieves the technical effect of unloading the voltage regulation load of the processor core.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, an embodiment of the present application provides a microprocessor architecture, which includes a processor core, a voltage control module, and a peripheral control module, wherein the voltage control module includes at least one voltage regulation core unit, and the peripheral control module is correspondingly connected to a power management module;

[0007] The voltage control module is configured to receive the voltage regulation task parameters issued by the processor core, and configure the path of the peripheral control module to be connected to the power management module through the target core unit in the at least one voltage regulation core unit, so that the power management module performs the voltage regulation task corresponding to the voltage regulation task parameters; wherein, the voltage regulation task parameters are obtained by converting the voltage regulation request received by the processor core.

[0008] The microprocessor architecture proposed in the embodiment of the present application adopts a modular layered design. After the processor core receives an external voltage regulation request, it converts it into standardized voltage regulation task parameters. The voltage control module receives the voltage regulation task parameters issued by the processor core, and the voltage control module dynamically determines an unoccupied target core unit in at least one voltage regulation core unit. The effective communication path between the peripheral control module and the power management module is configured through the target core unit, so that the power management module executes the voltage regulation task corresponding to the voltage regulation task parameters. At this point, the voltage regulation task performed by the processor core in the related technology is unloaded to the voltage control module, reducing the computing resources occupied by the voltage regulation task on the processor core, and achieving the technical effect of unloading the voltage regulation load of the processor core.

[0009] Optionally, the voltage regulation task parameters correspond to multiple voltage regulation tasks; the target core unit is connected to a path configured with the peripheral control module and multiple target power management units in the power management module, so that the multiple target power management units execute the multiple voltage regulation tasks in parallel. The voltage control module enables the parallel execution of multiple voltage regulation tasks, thereby reducing the time consumption of voltage regulation operations and improving the performance of the processor core.

[0010] Optionally, the voltage control module further includes a task allocation unit; the number of the voltage regulation core units is multiple, and the task allocation unit is connected to each of the voltage regulation core units. The task allocation unit is configured to allocate the multiple voltage regulation tasks to the multiple target core units in the multiple voltage regulation core units upon receiving the voltage regulation task parameters; wherein the multiple target core units are respectively configured to connect the paths of the peripheral control module to the multiple target power management units. The task allocation unit allocates the multiple voltage regulation tasks to the multiple target core units, and the multiple voltage regulation tasks are processed in parallel through the multiple target core units, thereby reducing processing time. Compared with serial voltage regulation, the processing efficiency of parallel voltage regulation is improved to a certain extent.

[0011] Optionally, the voltage regulation task parameters include an operation type parameter; if the operation type parameter is equal to a first preset value, the voltage regulation task is to perform voltage regulation on the target voltage domain corresponding to the voltage regulation task; if the operation type parameter is equal to a second preset value, the voltage regulation task is to perform a power-on operation on the target voltage domain; if the operation type parameter is equal to a third preset value, the voltage regulation task is to perform a power-off operation on the target voltage domain.

[0012] Optionally, the task allocating unit is further configured to interrupt the previous voltage regulation task using the voltage regulation task parameters corresponding to the current voltage regulation task if the target voltage domains corresponding to the current voltage regulation task and the previous voltage regulation task are consistent.

[0013] Optionally, there are multiple voltage regulation core units, and the voltage control module further includes a storage unit, a storage access arbitration unit, and a storage interface control unit; the storage access arbitration unit is connected to each of the multiple voltage regulation core units and is configured to arbitrate access requests from the target core unit to the storage unit; the storage interface control unit is connected to the storage access arbitration unit and is configured to control access operations to the storage unit based on the arbitrated access requests. By implementing an arbitration mechanism by providing storage access arbitration units connected to each of the multiple voltage regulation core units and providing a storage interface control unit connected to the storage access arbitration units, arbitration decisions can be mapped to physical read and write operations, thereby meeting the timing requirements of the voltage regulation task.

[0014] Optionally, the voltage control module also includes a bus allocation unit and a register configuration unit; the bus allocation unit is connected to the storage access arbitration unit and the register configuration unit respectively, and is configured to route external input to the storage access arbitration unit or the register configuration unit; the register configuration unit is connected to the bus allocation unit and the voltage regulation core unit respectively, and is configured to issue commands through a configuration register to pass the voltage regulation task parameters to the target core unit.

[0015] Optionally, there are multiple voltage regulating core units, and the voltage control module further includes an AXI bus master unit. The AXI bus master unit is connected to each of the multiple voltage regulating core units and is configured to arbitrate AXI read and write requests from the target core unit, generate a voltage regulation sequence that complies with the AXI protocol, and send the sequence to the peripheral control module. The AXI bus master unit arbitrates read and write requests, optimizes bus resource allocation, prevents timing confusion caused by competition among multiple voltage regulating core units, and generates a voltage regulation sequence that complies with the AXI protocol through protocol conversion, thereby achieving protocol compatibility with different peripheral control modules.

[0016] Optionally, the voltage control module is provided with an APB interface, an AXI interface and an interrupt interface; the APB interface is configured to access registers within the voltage control module, or to perform initialization operations on the storage unit of the voltage control module when powered on; the AXI interface is configured to access the storage unit of the processor core and transmit a voltage adjustment sequence to the peripheral control module; wherein, the voltage adjustment sequence is used to instruct the power management module to execute the voltage adjustment task; the interrupt interface is configured to report the execution status of the voltage adjustment task to the processor core. The reliable loading of the voltage adjustment task parameters is ensured through the APB interface. The standardization and batching of voltage adjustment operations are achieved through the AXI interface. Real-time status feedback and rapid response are achieved through the interrupt interface.

[0017] In a second aspect, an embodiment of the present application provides a voltage regulation method, which is applied to a microprocessor architecture, wherein the microprocessor architecture includes a processor core, a voltage control module and a peripheral control module, wherein the voltage control module includes at least one voltage regulation core unit, and the peripheral control module is correspondingly connected to a power management module; the method includes: receiving the voltage regulation task parameters issued by the processor core through the voltage control module; wherein the voltage regulation task parameters are obtained by converting the voltage regulation request received by the processor core; and configuring the path of the peripheral control module to be connected to the power management module through the target core unit in the at least one voltage regulation core unit, so that the power management module performs the voltage regulation task corresponding to the voltage regulation task parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1a A framework diagram of a microprocessor architecture provided for an example scenario of this application;

[0020] Figure 1b A framework diagram of a microprocessor architecture provided for an example scenario of this application;

[0021] Figure 1c A schematic diagram of the process of the voltage control module performing parallel voltage regulation tasks provided for the example scenario of this application;

[0022] Figure 2 A framework diagram of the microprocessor architecture provided in an embodiment of the present application;

[0023] Figure 3 A framework diagram of a voltage control module provided in one embodiment of the present application;

[0024] Figure 4 A framework diagram of a voltage control module provided in yet another embodiment of the present application;

[0025] Figure 5 A framework diagram of a voltage control module provided in another embodiment of the present application;

[0026] Figure 6 A framework diagram of a voltage control module provided in an embodiment of the present application;

[0027] Figure 7 A framework diagram of a voltage control module provided in an embodiment of the present application;

[0028] Figure 8 A schematic diagram of a flow chart of a voltage regulation method provided in an embodiment of the present application;

[0029] Figure 9 A schematic diagram of a flow chart of a voltage control module provided in an embodiment of the present application;

[0030] Figure 10 A framework diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0032] In SOC design, as chip integration and performance continue to improve, chip power consumption has become a key indicator affecting chip performance. Chip power consumption is proportional to the square of voltage. Reducing voltage can significantly reduce chip power consumption, so voltage regulation must be tailored to the actual operating conditions of the SOC. Voltage regulation requires precise control. If the main processor core is responsible for both computing tasks and voltage regulation, the overall performance and efficiency of the chip will be affected. Therefore, by assigning voltage regulation to a separate processor core, interference with other tasks can be avoided, ensuring the accuracy and independence of the voltage regulation process. As can be seen, voltage regulation is performed by a separate, dedicated processor core that is separate from the main processor core or other core circuits.

[0033] In the voltage regulation process of related technologies, the dedicated processor core is used to complete the voltage regulation operation. On the one hand, this dedicated processor core occupies a large chip area; on the other hand, this dedicated processor core adopts a serial voltage regulation method, which is a time-consuming process and will affect the performance of the processor core to a certain extent.

[0034] Therefore, an embodiment of the present application provides a new microprocessor architecture that offloads the voltage regulation work of the processor core to hardware execution. Specifically, a voltage control module is introduced into the microprocessor architecture. The voltage control module is used in the voltage regulation scenario. When the processor core receives a voltage regulation request, the processor core converts the voltage regulation request to obtain voltage regulation task parameters. The processor core sends the converted voltage regulation task parameters to the voltage control module, so that the voltage control module parses the voltage regulation task parameters and configures the path of the peripheral control module to be connected to the power management module based on the parsing results. Furthermore, the power management module executes the voltage regulation task corresponding to the voltage regulation task parameters to complete the voltage regulation. At this point, it is possible to offload the voltage regulation load handled by the processor core in the related technology to the voltage control module.

[0035] According to an embodiment of the present application, a scenario example of a microprocessor architecture is provided. Figure 1aThe microprocessor architecture includes a processor core 110, a voltage control module 120, a first peripheral controller 130, and a second peripheral controller 140. The first peripheral controller 130 is connected to a first power management unit 150 and a second power management unit 160. The second peripheral controller 140 is connected to a third power management unit 170. The first power management unit 150, the second power management unit 160, and the third power management unit 170 can each be a power management integrated circuit (PMIC). The microprocessor architecture is provided with different voltage domains to meet the power requirements of different parts. Each voltage domain is usually controlled by an independent power management unit.

[0036] When the processor core 110 receives an external voltage regulation request, the processor core 110 converts the voltage regulation request into a custom parameter to obtain a voltage regulation task parameter. The processor core 110 transmits the voltage regulation task parameter to the voltage control module 120. After receiving the voltage regulation task parameter, the voltage control module 120 searches for the instruction function, executes it, searches the parameter table, and searches the voltage conversion table to obtain a voltage regulation sequence, and configures the communication path between the peripheral controller and the corresponding power management unit, and sends the voltage regulation sequence to the corresponding power management unit through the configured communication path. The power management unit performs voltage regulation according to the voltage regulation sequence. At this point, the voltage regulation task of the processor core is offloaded by the introduced hardware (voltage control module), and the voltage control module has a smaller size than the processor core.

[0037] In this scenario, the microprocessor architecture is configured with multiple voltage domains, and the voltage regulation task parameters correspond to the first voltage regulation task and the second voltage regulation task. Figure 1b , the voltage control module 120 includes multiple voltage regulation core units 122. When receiving the voltage regulation task parameters, it is necessary to determine two idle target core units among the multiple voltage regulation core units 122. The communication path between the first peripheral controller 130 and the first power management unit 150 is configured through one of the two target core units, so that the first power management unit 150 performs the first voltage regulation task. At the same time, the communication path between the second peripheral controller 140 and the second power management unit 160 is configured through another one of the multiple target core units, so that the second power management unit 160 and the first power management unit 150 perform the second voltage regulation task in parallel. At this point, parallel voltage regulation can be achieved through the multiple voltage regulation core units in the voltage control module 120, which reduces the debugging time and improves the processor core performance.

[0038] The following describes how the voltage control module in this scenario implements parallel voltage regulation. The voltage control module includes a task allocation unit, a first target core unit, a second target core unit, a first peripheral controller, and a second peripheral controller. The first peripheral controller is connected to the first power management unit. The second peripheral controller is connected to the second power management unit. The processor core receives the voltage regulation request, parses the request, and obtains the voltage regulation task parameters. Figure 1c , the processor core sends the voltage regulation task parameters to the voltage control module. The task allocation unit receives the voltage regulation task parameters. The voltage regulation task parameters correspond to a first voltage regulation task and a second voltage regulation task. The task allocation unit distributes the tasks fairly. The first voltage regulation task is allocated to the first target core unit, and the second voltage regulation task is allocated to the second target core unit. The first target core unit configures a path between the first peripheral controller and the first power management unit, and calculates a voltage regulation sequence. The first target core unit sends the first voltage regulation sequence to the first peripheral controller, and the first peripheral controller sends the first voltage regulation sequence to the first power management unit. The first power management unit performs a voltage regulation operation based on the first voltage regulation sequence. At the same time, the second target core unit configures a path between the second peripheral controller and the second power management unit, and calculates a second voltage regulation sequence. The second peripheral controller sends the second voltage regulation sequence to the second power management unit, and the second power management unit performs a voltage regulation operation based on the second voltage regulation sequence.

[0039] It should be noted that, in addition to the voltage regulation function implemented in the above scenario example, other functions are also included. If the peripheral controller supports the I2C protocol, the microprocessor architecture can operate other slave devices that support the I2C protocol. Specifically, an embodiment of the present application also provides a microprocessor architecture, which includes a processor core and a peripheral control module. The peripheral control module may include a task allocation unit and a plurality of core execution units respectively connected to the task allocation unit. The processor core is configured to convert the peripheral operation request into an operation task parameter and send the operation task parameter to the peripheral control module. The task allocation unit is configured to, upon receiving the operation task parameter, allocate the plurality of peripheral operation tasks corresponding to the operation task parameter to a plurality of idle target core units in the plurality of core execution units; wherein each target core unit is configured to configure the path of the target peripheral controller to be connected to the corresponding target peripheral device based on the interconnection topology of the system on chip, so that each target peripheral device executes the peripheral operation task in parallel.

[0040] According to an embodiment of the present application, a microprocessor architecture is provided. Figure 2The microprocessor architecture includes a processor core 110, a voltage control module 120, and a peripheral control module 210. The voltage control module 120 includes at least one voltage regulation core unit 122, and the peripheral control module 210 is connected to a power management module 220.

[0041] The voltage control module 120 is configured to receive voltage regulation task parameters issued by the processor core 110 and, through a target core unit in at least one voltage regulation core unit, configure the path of the peripheral control module 210 to communicate with the power management module 220, so that the power management module 220 executes the voltage regulation task corresponding to the voltage regulation task parameters. The voltage regulation task parameters are obtained by converting the voltage regulation request received by the processor core 110.

[0042] In this embodiment, the microprocessor architecture can be viewed as a hardware system architecture that integrates a processor core, a voltage control module, and a peripheral control module. The processor core can be understood as an independent execution unit within the processor, that is, a core unit that executes independently within the processor. The voltage control module can be a hardware logic unit responsible for dynamically adjusting the power output, which includes at least one voltage regulation core unit. Each voltage regulation core unit corresponds to an independent power domain control channel. The peripheral control module can be a controller that manages peripheral interface communications and is physically connected to the power management module. For example, the peripheral control module can include an I2C controller or an SPI controller. The power management module is a hardware unit responsible for performing voltage regulation tasks.

[0043] In this embodiment, the voltage regulation request may be a voltage regulation requirement triggered by an external event or module (such as a temperature sensor, a power management unit PMU). When the device enters low power mode, the PMU sends a voltage reduction request to the system. The voltage regulation task parameters can be understood as voltage regulation parameters that meet the preset standard definition. It should be noted that the hardware-driven voltage regulation request in this embodiment is different from the software-driven frequency regulation request from the application processor (AP) domain. In SOC design, the frequency regulation request from the AP domain generally refers to the application processor domain dynamically requesting to change its processor frequency (or clock frequency) according to the needs of the current workload to achieve more efficient performance and power consumption management.

[0044] Specifically, the processor core is configured to receive a voltage regulation request, convert the voltage regulation request, obtain voltage regulation task parameters, and send the voltage regulation task parameters to the voltage control module. The voltage control module receives the voltage regulation task parameters sent by the processor core, and the voltage control module includes at least one voltage regulation core unit. Based on the voltage regulation task parameters, an idle target core unit is determined in at least one voltage regulation core unit, and the path of the peripheral control module configured by the target core unit is connected to the power management module to establish a communication path between the peripheral control module and the power management module, so that the power management module executes the voltage regulation task corresponding to the voltage regulation task parameters. In one embodiment, the target core unit is configured to calculate a voltage regulation sequence and send the calculated voltage regulation sequence to the power management module through the established communication path. Further, the target core unit is configured to calculate based on the target voltage included in the voltage regulation task parameters to obtain a voltage regulation sequence.

[0045] In some embodiments, the voltage regulation task parameters may include a target voltage of a target voltage domain. The target voltage domain is the voltage domain in which voltage regulation is required. The target core unit is configured to obtain a current voltage of the target voltage domain and determine a voltage encoding value of the current voltage and a voltage encoding value of the target voltage. Furthermore, a voltage regulation sequence is calculated based on the voltage encoding value of the current voltage and the voltage encoding value of the target voltage, and the voltage regulation sequence is sent to the peripheral control module so that the power management module executes the voltage regulation task.

[0046] In some embodiments, the voltage regulation task parameters may further include a voltage domain identifier of the target voltage domain. The target core unit is further configured to determine a corresponding target voltage domain from the plurality of voltage domains based on the voltage domain identifier, so as to connect a path of the peripheral control module to a power management module corresponding to the target voltage domain, thereby enabling the power management module corresponding to the target voltage domain to perform the voltage regulation task.

[0047] In some embodiments, the voltage regulation task parameters may further include an operation type parameter. If the operation type parameter is equal to a first preset value, the voltage regulation task is to regulate the voltage of the target voltage domain corresponding to the voltage regulation task. If the operation type parameter is equal to a second preset value, the voltage regulation task is to power on the target voltage domain. If the operation type parameter is equal to a third preset value, the voltage regulation task is to power off the target voltage domain.

[0048] The voltage regulation task parameters may refer to a standardized set of parameters generated by the processor core based on a received voltage regulation request, including an operation type parameter used to define specific voltage regulation behavior. The operation type parameter may refer to a classification identification parameter used to distinguish the execution mode of the voltage regulation task. The operation type parameter has three preset values: a first preset value, a second preset value, and a third preset value.

[0049] In this embodiment, the first preset value is used to trigger dynamic voltage regulation of the target voltage domain. The voltage regulation task corresponds to the target voltage domain. If the operation type parameter is equal to the first preset value, the voltage regulation task is to perform voltage regulation on the target voltage domain. Specifically, the target core unit sends a voltage regulation sequence to the peripheral controller, which sends the voltage regulation sequence to the PMIC, which executes the voltage regulation sequence.

[0050] In this embodiment, the second preset value is a preset coded value used to identify a power-on operation. If the operation type parameter is equal to the second preset value, the voltage regulation task is to perform a power-on operation on the target voltage domain. Specifically, the target core unit sends the power-on sequence to the peripheral controller, which sends the power-on sequence to the PMIC, which executes the power-on sequence. The target core unit checks that the power-on operation is complete, and the task ends.

[0051] In this embodiment, the third preset value is a preset coded value used to identify a power-off operation. If the operation type parameter is equal to the third preset value, the voltage regulation task is to power off the target voltage domain. Specifically, the target core unit sends a power-off sequence to the peripheral controller, which in turn sends the power-off sequence to the PMIC. The PMIC executes the power-off sequence, completing the power-off task.

[0052] The microprocessor architecture in the above embodiment adopts a modular layered design. After the processor core receives an external voltage regulation request, it converts it into standardized voltage regulation task parameters. The voltage control module receives the voltage regulation task parameters sent by the processor core, and the voltage control module dynamically determines an unoccupied target core unit in at least one voltage regulation core unit. An effective communication path between the peripheral control module and the power management module is configured through the target core unit, so that the power management module executes the voltage regulation task corresponding to the voltage regulation task parameters. At this point, the voltage regulation task performed by the processor core in the related art is offloaded to the voltage control module, reducing the computing resources occupied by the voltage regulation task on the processor core; further, since the voltage control module is small in size, it is conducive to reducing the chip size.

[0053] In some embodiments, the voltage regulation task parameter corresponds to multiple voltage regulation tasks. The target core unit configures the peripheral control module path and the multiple target power management units in the power management module to conduct, so that the multiple target power management units execute multiple voltage regulation tasks in parallel.

[0054] Among them, the multiple voltage regulation tasks corresponding to the voltage regulation task parameters may refer to multiple independent voltage regulation operations that need to be executed in parallel within the same time period. The target core unit may be a hardware logic unit in the voltage control module that is responsible for calculating the voltage regulation sequence and configuring the communication path. The target core unit dynamically binds the corresponding peripheral controller according to the voltage regulation task parameters and the topological interconnection structure corresponding to the microprocessor architecture, so that the peripheral controller is connected to the multiple target power management units in the power management module. The path for configuring the peripheral control module may be to establish an independent physical or logical communication link for each target power management unit selected for the target core unit. The multiple target power management units in the power management module may be PMICs selected to execute multiple voltage regulation tasks in parallel.

[0055] In some cases, as mentioned above, dedicated processor cores employ serial voltage regulation. This process is time-consuming and can affect the performance of the processor core to a certain extent. Therefore, to reduce the time consumed by serial voltage regulation, in this embodiment, the path configured through the target core unit to the peripheral control module is connected to each target power management unit in the power management module, establishing a communication path between the peripheral control module and each target power management unit, allowing each target power management unit to execute multiple voltage regulation tasks in parallel. Thus, the voltage control module enables the parallel execution of multiple voltage regulation tasks, reducing the time consumed by voltage regulation operations and improving the performance of the processor core.

[0056] In some embodiments, see Figure 3 The voltage control module further includes a task allocation unit 310. There are multiple voltage regulation core units 122, and the task allocation unit 310 is connected to each voltage regulation core unit 122. The task allocation unit 310 is configured to, upon receiving voltage regulation task parameters, allocate multiple voltage regulation tasks to multiple target core units in the multiple voltage regulation core units 122. The multiple target core units are each configured to connect pathways of the peripheral control module to the multiple target power management units.

[0057] In this embodiment, since the voltage control module includes multiple voltage regulation core units, each operating independently, timing conflicts caused by task preemption are avoided. The task allocation unit is directly connected to each voltage regulation core unit via a hardware bus, allowing for fair allocation of voltage regulation tasks to multiple voltage regulation core units.

[0058] The task allocation unit can be a dedicated hardware unit within the voltage control module, configured to dynamically allocate voltage regulation task parameters to multiple voltage regulation core units. The multiple voltage regulation core units can refer to parallel hardware processing units within the voltage control module, each of which can independently control a peripheral controller path. The target core unit can refer to the voltage regulation core unit selected by the task allocation unit.

[0059] Specifically, the voltage control module includes multiple voltage regulation core units, and the voltage control module also includes a task allocation unit, which is connected to each voltage regulation core unit. The processor core sends voltage regulation task parameters to the voltage control module, and receives the voltage regulation task parameters through the task allocation unit. The voltage regulation task parameters correspond to multiple voltage regulation tasks, and the task allocation unit allocates the multiple voltage regulation tasks to multiple target core units among the multiple voltage regulation core units. Each target core unit is configured to connect the path of the peripheral control module to the corresponding target power management unit. For example, when a parameter set containing three voltage regulation tasks is received, the task allocation unit fairly distributes the three voltage regulation tasks to the corresponding three target core units.

[0060] In some embodiments, the task allocation unit is further configured to interrupt the previous voltage regulation task using the voltage regulation task parameters corresponding to the current voltage regulation task if the target voltage domains corresponding to the current voltage regulation task and the previous voltage regulation task are consistent.

[0061] Specifically, the task allocation unit receives new voltage regulation task parameters, and the new voltage regulation task parameters correspond to the current voltage regulation task. The current voltage regulation task is recorded as the new voltage regulation task, and the previous voltage regulation task before the current voltage regulation task is recorded as the old voltage regulation task. Because the voltage regulation task parameters include a voltage domain identifier, it is determined based on the voltage domain identifier whether the target voltage domain corresponding to the current voltage regulation task is consistent with the target voltage domain corresponding to the previous voltage regulation task. If they are consistent, the process of the previous voltage regulation task is interrupted using the new voltage regulation task parameters. For example, the previous voltage regulation task is to configure voltage domain 1 and is assigned to the target core unit vc_core0 for execution. At this time, the new voltage regulation task is also to configure voltage domain 1. Then the target object of the new voltage regulation task is consistent with the target object of the old task and will be replaced.

[0062] Furthermore, the target core unit checks whether the target voltage of the target voltage domain has changed. If it is detected that the target voltage of the target voltage domain has changed, a new voltage adjustment sequence is calculated based on the voltage code value of the current voltage of the target voltage domain and the voltage code value of the changed target voltage.

[0063] In the above embodiment, the task allocation unit allocates multiple voltage regulation tasks to multiple target core units, and multiple target core units are used to realize parallel processing of multiple voltage regulation tasks, thereby reducing processing time. Compared with serial voltage regulation, the processing efficiency of parallel voltage regulation is improved to a certain extent.

[0064] In some embodiments, see Figure 4The number of voltage regulation core units is multiple. The voltage control module 120 further includes a storage unit (not shown), a storage access arbitration unit 420, and a storage interface control unit 430. The storage access arbitration unit 420 is connected to each of the multiple voltage regulation core units 122 and is configured to arbitrate access requests from target core units to the storage units. The storage interface control unit 430 is connected to the storage access arbitration unit and is configured to control access operations to the storage units based on the arbitrated access requests.

[0065] The voltage regulation core unit is an independent hardware logic unit in the voltage control module 122 that performs voltage regulation-related operations. Multiple voltage regulation core units are provided to enable parallel task processing. For example, each voltage regulation core unit can independently configure the communication parameters of the peripheral controller and control the voltage output of a power management unit. The storage unit can store the topology of the microprocessor architecture. The storage unit is a storage area associated with the storage interface control unit. The storage access arbitration unit can be a hardware arbiter within the voltage control module, connected to each voltage regulation core unit via an independent channel. For example, when the first and third voltage regulation core units simultaneously request to read data from the storage unit, the storage access arbitration unit allocates access rights based on a priority policy. For example, the request from the first voltage regulation core unit will be responded to immediately, while the request from the third voltage regulation core unit will need to be delayed to avoid access conflicts. The storage interface control unit can be a controller that manages the physical interface of the storage unit and is connected to the storage access arbitration unit via a control signal line.

[0066] Specifically, the voltage control module includes a storage unit, a storage access arbitration unit, a storage interface control unit, and multiple voltage regulation core units. The multiple voltage regulation core units are respectively connected to the storage access arbitration unit, and the storage access arbitration unit is connected to the storage interface control unit. The storage access arbitration unit arbitrates the access request of the target core unit to the storage unit. For example, the read instruction request generated by the voltage regulation core unit is arbitrated. After arbitration by the storage access arbitration unit, the storage unit is accessed based on the arbitrated access request, and the access operation to the storage unit is controlled by the storage interface control unit, such as implementing the control work of the APB interface and the voltage regulation core unit interface to the RAM interface.

[0067] Further, see Figure 5The voltage control module further includes a bus allocation unit 510 and a register configuration unit 520. The bus allocation unit 510 is connected to the memory access arbitration unit 420 and the register configuration unit 520, respectively, and is configured to route external input to the memory access arbitration unit 420 or the register configuration unit 520. The register configuration unit 520 is connected to the bus allocation unit 510 and the voltage regulation core unit 122, respectively, and is configured to issue commands through configuration registers to transmit voltage regulation task parameters to the target core unit.

[0068] In this embodiment, the voltage control module distributes instructions to each submodule via the bus distribution unit, and the voltage regulation core unit performs specific voltage regulation-related operations. The bus distribution unit is connected to the storage access arbitration unit and the register configuration unit respectively; the bus distribution unit is the signal routing hub within the voltage control module, responsible for classifying and directing external input instructions to the storage access arbitration unit or the register configuration unit. When the external input is a storage access request, the bus distribution unit routes it to the storage access arbitration unit via the APB bus; when the input is a register configuration instruction, it is transmitted to the register configuration unit via a dedicated channel. The bus distribution unit enables precise distribution of multi-source instructions.

[0069] In this embodiment, the register configuration unit is a hardware logic unit in the voltage control module responsible for parameter transmission. It is connected to the bus allocation unit and the voltage regulation core unit via a data bus. When the processor core issues voltage regulation task parameters, the register configuration unit writes these parameters to the target register and notifies the voltage regulation core unit via an interrupt signal to obtain the parameters. The register configuration unit ensures that the voltage regulation core unit can obtain the latest instructions.

[0070] In the above embodiment, an arbitration mechanism is implemented by setting a storage access arbitration unit connected to multiple voltage regulation core units respectively, and setting a storage interface control unit connected to the storage access arbitration unit, so that the arbitration decision can be mapped into physical read and write operations to meet the timing requirements of the voltage regulation task.

[0071] In some embodiments, see Figure 6 There are multiple voltage regulation core units 122, and the voltage control module further includes an AXI bus master unit 610. The AXI bus master unit 610 is connected to each of the multiple voltage regulation core units 122 and is configured to arbitrate AXI read and write requests from the target core unit, generate a voltage regulation sequence that complies with the AXI protocol, and send the sequence to the peripheral control module.

[0072] The AXI bus master unit can be a hardware controller responsible for bus communication management within the voltage control module, connecting to multiple voltage regulation core units via an AXI protocol interface. For example, when the first and third voltage regulation core units simultaneously initiate AXI read and write requests, the AXI bus master unit arbitrates the requests based on a priority strategy. By generating AXI-compliant voltage regulation sequences, it achieves protocol compatibility with different peripheral control modules.

[0073] Specifically, the voltage control module includes an AXI bus master unit connected to multiple voltage regulation core units. The AXI bus master unit is connected to a peripheral controller. The AXI bus master unit arbitrates AXI read and write requests from different voltage regulation core units. The AXI bus master unit includes protocol conversion logic that encodes the read and write requests from the voltage regulation core units into voltage regulation sequences that comply with the AXI protocol. The AXI bus master unit transmits the voltage regulation sequences that comply with the AXI protocol to the peripheral controller via the bus.

[0074] In the above embodiment, the AXI bus master unit arbitrates read and write requests, optimizes bus resource allocation, prevents timing confusion caused by competition among multiple voltage regulation core units, and generates a voltage regulation sequence that complies with the AXI protocol through protocol conversion, thereby achieving protocol compatibility with different peripheral control modules.

[0075] In some embodiments, the voltage control module is provided with an APB interface, an AXI interface, and an interrupt interface. The APB interface is configured to access registers within the voltage control module or to initialize the voltage control module's memory cells upon power-up. The AXI interface is configured to access the processor core's memory cells and transmit a voltage adjustment sequence to the peripheral control module. The voltage adjustment sequence is used to instruct the power management module to execute a voltage adjustment task. The interrupt interface is configured to report the execution status of the voltage adjustment task to the processor core.

[0076] The voltage control module is a hardware control unit that integrates the APB interface, AXI interface, and interrupt interface. It coordinates voltage regulation between the processor core and the power management module. The voltage control module initializes the storage unit through the APB interface, transmits the voltage regulation sequence through the AXI interface, and provides feedback on the voltage regulation status to the processor core through the interrupt interface.

[0077] Specifically, the APB interface is the voltage control module's low-bandwidth peripheral bus interface, used to access the module's internal registers and perform memory unit initialization operations. The AXI interface is the voltage control module's high-performance bus interface, used to access the processor core's memory units and transmit voltage regulation sequences. The interrupt interface is the voltage control module's event notification channel, used to report the execution status of voltage regulation tasks to the processor core.

[0078] In the above embodiment, the APB interface ensures reliable loading of voltage regulation task parameters, the AXI interface enables standardization and batching of voltage regulation operations, and the interrupt interface enables real-time status feedback and rapid response.

[0079] The following is a detailed introduction to the voltage control module provided in the embodiments of the present application. The main interfaces of the voltage control module include an APB interface, an AXI interface, and an interrupt interface. The APB interface is a slave interface with two main uses: one is for software to configure and access registers within the voltage control module; the other is that during power-on initialization, the software uses this interface to update the RAM within the voltage control module. The AXI interface is a master interface with two main uses: one is for accessing the RAM of the processor core, and the other is for accessing the peripheral controller. The interrupt interface is used to report the interrupt status to the processor core.

[0080] The voltage control module includes an AXI bus master unit, a bus allocation unit, a register configuration unit, a task allocation unit, multiple voltage regulation core units, a memory access arbitration unit, a memory interface control unit, and a clock reset module. The bus allocation unit is connected to the register configuration unit and the memory access arbitration unit, respectively. The register configuration unit is connected to the task allocation unit. The task allocation unit is connected to the multiple voltage regulation core units, respectively. The multiple voltage regulation core units are each connected to the AXI bus master unit.

[0081] See also Figure 7 , which exemplarily introduces the functions of each unit in the voltage control module. The voltage control module is denoted as VC. The voltage control module includes a clock reset module (clk_rst) for the clock reset signal used in the voltage control module.

[0082] The voltage control module includes a bus distribution unit (apb_dist) for routing the external input APB bus to the register module or RAM module of the voltage control module.

[0083] The voltage control module contains a register configuration unit (vc_reg). The software issues commands through the configuration register and accesses the register to obtain status information.

[0084] The voltage control module contains a task distribution unit (vc_dist); this unit is responsible for checking the voltage regulation commands issued by the software for each channel and implementing the distribution work to vc_core. At the same time, this module is also responsible for interrupting the repeated configuration of the same voltage domain.

[0085] The voltage control module contains at least one voltage regulation core unit (vc_core), which implements the voltage control module's main functions, including instruction acquisition, translation, and execution. A voltage control module can contain multiple vc_core modules to achieve parallel voltage regulation.

[0086] The voltage control module contains a storage access arbitration unit (sram_arb) that arbitrates the read instruction requests generated by each vc_core.

[0087] The voltage control module contains a storage interface control unit (sram_ctl), which mainly controls the apb interface and vc_core interface to the RAM interface.

[0088] The voltage control module contains an AXI bus master unit (axi_mstr), which is mainly responsible for read and write arbitration between each vc_core and ultimately generates an AXI interface.

[0089] In this embodiment, the voltage regulation task parameters are transferred by writing hardware registers. When the hardware receives the voltage regulation request, it will first pass the voltage control module to the task allocation unit, and the task allocation unit will pass the voltage regulation task parameters to the currently idle vc_core for execution. At the same time, the task allocation unit will determine whether the target voltage domain of this voltage regulation task is consistent. If consistent, the old voltage regulation task parameters will be interrupted by the new ones. After receiving the task parameters, vc_core will obtain data from the RAM inside the voltage control module according to the specific parameter content. vc_core will operate according to the parsed data content. When the operation target is a peripheral controller, the request, data, etc. will be sent to the AXI bus host unit, converted into an AXI protocol packet, and sent to the target peripheral controller.

[0090] When voltage regulation is performed, the processor core transmits voltage regulation task parameters to the voltage control module. The voltage regulation task parameters include the operation instruction opcode, the target voltage vol, and the voltage domain identifier of the target voltage domain. The operation instruction opcode means the specified operation type, and the voltage control module can determine the next operation behavior based on the operation instruction opcode. The specified operation types are divided into three types: voltage regulation operation, power-off operation, and power-on operation. Vol is the target voltage to be adjusted. Vol is valid only when the opcode indicates that the operation type is voltage regulation. The execution process in the voltage control module is described as an example. The execution process includes the following steps:

[0091] 1) After receiving the opcode, the voltage control module distributes the voltage regulation task to vc_core fairly.

[0092] 2) After vc_core receives the voltage regulation task, it starts executing it.

[0093] 3) vc_core obtains the topology stored in RAM and determines the peripheral controller to be operated and the target PMIC.

[0094] 4) vc_core configures the peripheral controller path to point to the target PMIC based on the obtained topology.

[0095] 5) vc_core determines the operation type based on the opcode. If it is a voltage regulation operation, execute step 6), if it is a power-off operation, execute step 16), and if it is a power-on operation, execute step 21).

[0096] 6) When the chip is set to multiple voltage domains, vc_core checks the target voltage domain to be operated currently. This check determines the target voltage domain that needs voltage regulation operation through opcode.

[0097] 7) vc_core obtains the current voltage of the target voltage domain and records it.

[0098] The current voltage corresponds to the actual voltage value and the PMIC voltage coding value.

[0099] 8) vc_core obtains the PMIC voltage code value corresponding to the target voltage by looking up a table or calculating.

[0100] 9) vc_core compares the PMIC voltage code value corresponding to the current voltage with the PMIC voltage code value corresponding to the target voltage, and determines whether the voltage is adjusted upward (boost operation) or downward (buck operation).

[0101] 10) vc_core gradually increases or decreases the voltage according to the predefined voltage adjustment granularity.

[0102] It should be noted that when the difference between the target voltage and the current voltage is smaller than the voltage adjustment granularity, the target voltage value is directly used.

[0103] 11) vc_core uses the voltage regulation value calculated in step 9 and the predefined voltage regulation sequence to operate the peripheral controller (the voltage regulation sequence is customized according to the PMIC)

[0104] 12) The peripheral controller sends the voltage adjustment sequence to the corresponding PMIC.

[0105] 13) The PMIC performs voltage regulation according to the voltage regulation sequence.

[0106] 14) vc_core checks whether the target voltage value of the current operating voltage domain has changed. If so, it jumps to step 8 to continue execution; otherwise, it ends execution.

[0107] 15) vc_core waits for the PMIC to complete this voltage regulation operation and determines whether the current voltage has reached the target voltage. If not, it jumps to step 10 to continue execution; if it has reached the target voltage, this voltage regulation operation ends.

[0108] 16) When the chip is set to multiple voltage domains, vc_core checks the target voltage domain to be operated currently.

[0109] 17) vc_core executes a predefined power-off sequence and sends the power-off sequence to the corresponding peripheral controller.

[0110] 18) The peripheral controller sends the power-off sequence to the PMIC.

[0111] 19) The PMIC performs a power-off sequence.

[0112] 20) The power-off task is completed.

[0113] 21) When the chip is set to multiple voltage domains, vc_core checks the target voltage domain to be operated currently.

[0114] 22) vc_core executes the predefined power-on sequence and sends the power-on sequence to the corresponding peripheral controller.

[0115] 23) The peripheral controller sends the power-off sequence to the PMIC.

[0116] 24) The PMIC performs a power-on sequence.

[0117] 25) vc_core checks that power is complete and the task is completed.

[0118] The present application provides a voltage regulation method, which is applied to a microprocessor architecture. The microprocessor architecture includes a processor core, a voltage control module, and a peripheral control module. The voltage control module includes at least one voltage regulation core unit, and the peripheral control module is connected to a power management module. Figure 8 , the voltage regulation method comprises the following steps:

[0119] S810: Receive voltage regulation task parameters sent by the processor core through the voltage control module.

[0120] The voltage regulation task parameters are obtained by converting the voltage regulation request received by the processor core.

[0121] S820: Connect the path of the peripheral control module to the power management module through the target core unit in at least one voltage regulation core unit, so that the power management module performs the voltage regulation task corresponding to the voltage regulation task parameter.

[0122] The present application provides a voltage regulation method, which is applied to a microprocessor architecture. The microprocessor architecture includes a processor core, a voltage control module, and a peripheral control module. The voltage control module includes at least one voltage regulation core unit, and the peripheral control module is connected to a power management module. Figure 9 , the voltage regulation method comprises the following steps:

[0123] S910: Receive a voltage adjustment request through a processor core.

[0124] S920: The processor verifies and converts the voltage regulation request to obtain voltage regulation task parameters.

[0125] S930: Send voltage regulation task parameters to the voltage control module.

[0126] The voltage regulation task parameter is used to instruct the voltage control module to connect the path of the peripheral control module to the power management module through the target core unit in at least one voltage regulation core unit, so that the power management module performs the voltage regulation task corresponding to the voltage regulation task parameter.

[0127] The further description of the above method embodiment is the same as the functional description of each module and unit in the above microprocessor architecture, and will not be repeated here.

[0128] See also Figure 10 , Figure 10 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 10 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 10 A processor 10 is taken as an example.

[0129] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0130] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0131] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0132] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0133] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

[0134] The architecture, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions.

[0135] For the convenience of description, the above devices are described as being divided into various units according to their functions. Of course, when implementing this application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0136] The present application is described with reference to flowcharts and / or block diagrams of methods, devices (systems) according to embodiments of the present application. Computer program instructions are provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce means for implementing the functions specified in one or more processes of the flowchart and / or one or more blocks of the block diagram.

[0137] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0138] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0139] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0140] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0141] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

[0142] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A microprocessor architecture, characterized in that The microprocessor architecture includes a processor core, a voltage control module and a peripheral control module, wherein the voltage control module includes at least one voltage regulation core unit, and the peripheral control module is correspondingly connected to a power management module; The voltage control module is configured to receive the voltage regulation task parameters issued by the processor core, and configure the path of the peripheral control module to be connected to the power management module through the target core unit in the at least one voltage regulation core unit, so that the power management module performs the voltage regulation task corresponding to the voltage regulation task parameters; wherein, the voltage regulation task parameters are obtained by converting the voltage regulation request received by the processor core.

2. The microprocessor architecture according to claim 1, wherein: The voltage regulation task parameters correspond to multiple voltage regulation tasks; The path through which the target core unit configures the peripheral control module is connected to multiple target power management units in the power management module, so that the multiple target power management units execute the multiple voltage regulation tasks in parallel.

3. The microprocessor architecture according to claim 2, wherein: The voltage control module further includes a task allocation unit; the number of the voltage regulation core units is multiple, and the task allocation unit is connected to each of the voltage regulation core units; The task allocation unit is configured to allocate the multiple voltage regulation tasks to multiple target core units among the multiple voltage regulation core units upon receiving the voltage regulation task parameters; wherein the multiple target core units are respectively configured to connect the paths of the peripheral control module to the multiple target power management units.

4. The microprocessor architecture according to claim 1, wherein: The voltage regulation task parameters include operation type parameters; If the operation type parameter is equal to a first preset value, the voltage regulation task is to perform voltage regulation on a target voltage domain corresponding to the voltage regulation task; If the operation type parameter is equal to a second preset value, the voltage regulation task is to perform a power-on operation on the target voltage domain; If the operation type parameter is equal to a third preset value, the voltage regulation task is to perform a power-off operation on the target voltage domain.

5. The microprocessor architecture according to claim 3, wherein: The task allocation unit is further configured to interrupt the previous voltage regulation task using the voltage regulation task parameters corresponding to the current voltage regulation task if the target voltage domains corresponding to the current voltage regulation task and the previous voltage regulation task are consistent.

6. The microprocessor architecture according to claim 1, wherein: There are multiple voltage regulation core units, and the voltage control module further includes a storage unit, a storage access arbitration unit, and a storage interface control unit; The storage access arbitration unit is connected to the plurality of voltage regulating core units respectively and is configured to arbitrate the access request of the target core unit to the storage unit; The storage interface control unit is connected to the storage access arbitration unit and is configured to control the access operation to the storage unit based on the arbitrated access request.

7. The microprocessor architecture according to claim 6, wherein: The voltage control module also includes a bus allocation unit and a register configuration unit; The bus allocation unit is connected to the memory access arbitration unit and the register configuration unit respectively, and is configured to route external input to the memory access arbitration unit or the register configuration unit; The register configuration unit is connected to the bus allocation unit and the voltage regulation core unit respectively, and is configured to issue a command through a configuration register to transfer the voltage regulation task parameters to the target core unit.

8. The microprocessor architecture according to claim 1, wherein: There are multiple voltage regulation core units, and the voltage control module further includes an AXI bus master unit; The AXI bus master unit is connected to multiple voltage regulation core units respectively, and is configured to arbitrate the AXI read and write requests of the target core unit, generate a voltage regulation sequence that complies with the AXI protocol, and send it to the peripheral control module.

9. The microprocessor architecture according to claim 1, wherein: The voltage control module is provided with an APB interface, an AXI interface and an interrupt interface; The APB interface is configured to access registers in the voltage control module or to initialize a storage unit of the voltage control module when powered on; The AXI interface is configured to access the storage unit of the processor core and transmit a voltage adjustment sequence to the peripheral control module; wherein the voltage adjustment sequence is used to instruct the power management module to perform the voltage adjustment task; The interrupt interface is configured to report the execution status of the voltage regulation task to the processor core.

10. A voltage regulation method, characterized in that: Applied to a microprocessor architecture, the microprocessor architecture includes a processor core, a voltage control module and a peripheral control module, the voltage control module includes at least one voltage regulation core unit, and the peripheral control module is correspondingly connected to a power management module; the method includes: Receiving, through the voltage control module, voltage regulation task parameters issued by the processor core; wherein the voltage regulation task parameters are obtained by converting the voltage regulation request received by the processor core; The target core unit in the at least one voltage regulating core unit configures a path of the peripheral control module to be connected to the power management module, so that the power management module executes the voltage regulating task corresponding to the voltage regulating task parameter.

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