Neuromorphic circuit, neural network architecture and signal processing method
Directly process the analog signal through the neuromorphic circuit, solving the complexity of analog signal processing process and conversion errors, and achieving efficient signal processing.
Patent Information
- Application Number
- CN202510277819.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-08-05
AI Technical Summary
The prior art requires analog-to-digital conversion and digital-to-analog conversion when processing analog signals, resulting in complex processes and introducing conversion errors and signal delays.
Neuromorphic circuits, including matrix circuits, aggregation modules and activation modules, directly process the analog signal, and control the adjustment method of the matrix circuit through the controller, eliminating the analog-to-digital conversion process.
Improves the efficiency of signal processing, reduces conversion error and signal delay.
Smart Images
Figure CN120430359A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of neural network technology, and in particular to a neuromorphic circuit, a neural network architecture, and a signal processing method. Background Art
[0002] In the field of neural network technology, field programmable gate arrays (FPGAs) are commonly used as programmable logic devices to provide hardware support for signal processing. FPGAs are programmable logic chips that can perform general functions, meaning they can be programmed to perform certain logic processing functions.
[0003] However, when processing analog signals, it's necessary to first perform analog-to-digital conversion on the analog signal. This involves converting the analog signal into a digital signal, processing the digital signal through an FPGA chip, and then performing digital-to-analog conversion on the processed signal to obtain the analog signal. This signal conversion process is complex and introduces conversion errors and signal delays. Summary of the Invention
[0004] The main purpose of this application is to provide a neuromorphic circuit, a neural network architecture and a signal processing method, aiming to solve the technical problems that the signal conversion process is relatively complex and introduces conversion errors and signal delays.
[0005] To achieve the above objectives, the present application provides a neuromorphic circuit, which includes a matrix circuit, an aggregation module, and an activation module. The neuromorphic circuit is also electrically connected to an external controller;
[0006] The input end of the matrix circuit serves as the input end of the neuromorphic circuit, the output end of the matrix circuit is electrically connected to the input end of the aggregation module, the output end of the aggregation module is electrically connected to the input end of the activation module, and the output end of the activation module serves as the output end of the neuromorphic circuit;
[0007] The matrix circuit is used to adjust the received analog signal and transmit the adjusted analog signal to the aggregation module;
[0008] The aggregation module is used to perform a pooling operation on the received analog signal and transmit the processed analog signal to the activation module;
[0009] The activation module is used to rectify the received analog signal and output the processed analog signal;
[0010] The controller is used to control the adjustment method of the matrix circuit on the analog signal.
[0011] Optionally, the matrix circuit includes a plurality of resistance bridge modules, and adjacent resistance bridge modules are electrically connected.
[0012] Optionally, the resistance bridge module includes multiple resistance bridges, and the multiple resistance bridges are connected in series.
[0013] Optionally, the resistance bridge includes a resistor, a first transistor and a second transistor;
[0014] The first end of the resistor and the first end of the first transistor are electrically connected via a first node, and the first node serves as an input end of the resistance bridge;
[0015] The second end of the resistor is electrically connected to the first end of the second transistor;
[0016] The second end of the first transistor and the second end of the second transistor are electrically connected via a second node, and the second node serves as an output end of the resistance bridge.
[0017] Optionally, the resistance bridge module includes a first resistance bridge and a plurality of second resistance bridges;
[0018] The first transistor and the second transistor in the first resistance bridge are turned on when receiving a high level signal from the controller, and the resistors in the first resistance bridge are connected in parallel with the resistors in the plurality of second resistance bridges.
[0019] Optionally, the resistance bridge module includes a first resistance bridge and a plurality of second resistance bridges;
[0020] The first transistor and the second transistor in the first resistance bridge are turned off when receiving the low level signal sent by the controller, and the resistors in the first resistance bridge are disconnected from the resistors in the plurality of second resistance bridges.
[0021] In addition, to achieve the above objectives, the present application also provides a neural network architecture, which includes a neuromorphic circuit, and multiple neuromorphic circuits are connected in series.
[0022] Optionally, the neural network architecture further comprises a controller;
[0023] The controller is electrically connected to each neuromorphic circuit.
[0024] Optionally, the neural network architecture further comprises a digital-to-analog converter and an analog-to-digital converter;
[0025] The output terminal of the digital-to-analog converter is electrically connected to the input terminals of the plurality of neuromorphic circuits, and the input terminal of the analog-to-digital converter is electrically connected to the output terminals of the plurality of neuromorphic circuits;
[0026] The digital-to-analog converter is configured to convert the received digital signal into an analog signal and transmit the analog signal to the plurality of neuromorphic circuits;
[0027] The analog-to-digital converter is used to convert the analog signals output by the multiple neuromorphic circuits into digital signals.
[0028] In addition, to achieve the above objectives, the present application also provides a signal processing method, including:
[0029] Receive analog signals;
[0030] Sending the analog signal to a neural network architecture, and processing the analog signal by the neural network architecture;
[0031] The neuromorphic circuit in the neural network architecture adjusts the analog signal based on a received control signal, and the control signal is a signal sent by a controller in the neural network architecture.
[0032] Compared with the prior art, the embodiments of the present application have the following beneficial effects:
[0033] Embodiments of the present application provide a neuromorphic circuit, a neural network architecture, and a signal processing method. The neuromorphic circuit includes a matrix circuit, an aggregation module, and an activation module. The neuromorphic circuit is also electrically connected to an external controller. The input of the matrix circuit serves as the input of the neuromorphic circuit, the output of the matrix circuit is electrically connected to the input of the aggregation module, the output of the aggregation module is electrically connected to the input of the activation module, and the output of the activation module serves as the output of the neuromorphic circuit. The neuromorphic circuit in the embodiment of the present application can directly process analog signals without analog-to-digital conversion, thereby improving signal processing efficiency and reducing conversion errors that occur during signal processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the solutions in this application, a brief introduction will be given below to the drawings required for use in the description of the embodiments of this application. Obviously, the drawings described below are some embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0035] Figure 1 is a schematic diagram of the structure of the neuromorphic circuit provided in an embodiment of the present application;
[0036] Figure 2 Schematic diagram of the structure of the matrix circuit provided by the embodiment of the present application;
[0037] Figure 3This is one of the structural diagrams of the resistance bridge provided in the embodiment of the present application;
[0038] Figure 4 This is the second structural diagram of the resistance bridge provided in the embodiment of the present application;
[0039] Figure 5 It is a structural diagram of the neural network architecture provided in the embodiment of the present application;
[0040] Figure 6 This is a flowchart of a signal processing method provided in an embodiment of the present application.
[0041] Description of reference numerals:
[0042] 100, neuromorphic circuit; 110, matrix circuit; 120, aggregation module; 130, activation circuit; 111, resistance bridge module; T 1A , the first transistor; T 1B , the second transistor; T 2A , the third transistor; T 2B , the fourth transistor; T 3A , the fifth transistor; T 3B , the sixth transistor; T 4A , the seventh transistor; T 4B , the eighth transistor; T 5A , the ninth transistor; T 5B , transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; Q1, first resistor bridge; Q2, second resistor bridge; J1, controller; T1, first node; T2, second node. DETAILED DESCRIPTION
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.
[0044] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0045] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.
[0046] See also Figure 1 , Figure 1 Schematic diagram of the structure of the neuromorphic circuit provided by the embodiment of the present application. Figure 1 As shown, the neuromorphic circuit includes a matrix circuit 110, an aggregation module 120 and an activation module 130. The neuromorphic circuit is also electrically connected to an external controller. The input end of the matrix circuit 110 serves as the input end of the neuromorphic circuit, the output end of the matrix circuit 110 is electrically connected to the input end of the aggregation module 120, the output end of the aggregation module 120 is electrically connected to the input end of the activation module 130, and the output end of the activation module 130 serves as the output end of the neuromorphic circuit.
[0047] In an optional embodiment, the aggregation module 120 is a temporal information aggregation (TIA) module. The TIA module effectively extracts potential multi-scale temporal information from the feature map by continuously temporally pooling the feature map using various pooling windows. In an optional embodiment, the activation module 130 applies a ReLu activation function to rectify the received analog signal.
[0048] The working principle of the neuromorphic circuit provided in the embodiment of the present application is as follows: the matrix circuit 110 is used to adjust the received analog signal and transmit the adjusted analog signal to the aggregation module 120; the aggregation module 120 is used to perform a pooling operation on the received analog signal and transmit the processed analog signal to the activation module 130; the activation module 130 is used to rectify the received analog signal and output the processed analog signal; the controller is used to control the adjustment method of the analog signal by the matrix circuit 110.
[0049] The neuromorphic circuit in the embodiment of the present application can directly process analog signals without performing analog-to-digital conversion on the analog signals, thereby improving the efficiency of signal processing and reducing conversion errors in the signal processing process.
[0050] Optionally, the matrix circuit includes a plurality of resistance bridge modules, and adjacent resistance bridge modules are electrically connected.
[0051] Optionally, the resistance bridge module includes multiple resistance bridges, and the multiple resistance bridges are connected in series.
[0052] See also Figure 2 ,like Figure 2 As shown, the matrix circuit 110 includes a plurality of resistance bridge 111 modules, and each resistance bridge 111 module includes a plurality of resistance bridges 111. Adjacent resistance bridge 111 modules are electrically connected, and the plurality of resistance bridges 111 are connected in series.
[0053] It should be noted that the resistance bridge 111 is a measurement and sensing circuit widely used in circuits, and is used to accurately measure resistance values, detect resistance changes, or serve as a sensor signal processing circuit.
[0054] The rectangular circuit in this embodiment includes multiple resistance bridge 111 modules, which are composed of multiple resistance bridges 111. The controller that controls the opening and closing of the internal transistors of each resistance bridge 111 is connected to the serial bus to assist the controller in unified control of the entire neuromorphic circuit.
[0055] See also Figure 3 , optionally, the resistance bridge includes a resistor, a first transistor and a second transistor;
[0056] The first end of the resistor and the first end of the first transistor are electrically connected via a first node T1, and the first node T1 serves as an input end of the resistance bridge;
[0057] The second end of the resistor is electrically connected to the first end of the second transistor;
[0058] The second end of the first transistor and the second end of the second transistor are electrically connected via a second node T2, and the second node T2 serves as the output end of the resistance bridge.
[0059] See also Figure 3 , Figure 3 The resistor bridge shown includes a resistor, a first transistor T 1A and the second transistor T 1B ,exist Figure 3 The middle resistance bridge is also connected to the controller J1 for communication.
[0060] Optionally, the resistance bridge module includes a first resistance bridge and a plurality of second resistance bridges;
[0061] The first transistor and the second transistor in the first resistance bridge are turned on when receiving a high level signal from the controller, and the resistors in the first resistance bridge are connected in parallel with the resistors in the plurality of second resistance bridges.
[0062] Optionally, the resistance bridge module includes a first resistance bridge and a plurality of second resistance bridges;
[0063] The first transistor and the second transistor in the first resistance bridge are turned off when receiving the low level signal sent by the controller, and the resistors in the first resistance bridge are disconnected from the resistors in the plurality of second resistance bridges.
[0064] It should be noted that, for the first resistance bridge, when both the first triode and the second triode receive a high-level signal from the controller, the first triode and the second triode are turned on, and the resistors in the first resistance bridge are connected in parallel with the resistors in the plurality of second resistance bridges. When both the first triode and the second triode receive a low-level signal from the controller, the first triode and the second triode are turned off, and the resistors in the first resistance bridge are disconnected from the resistors in the plurality of second resistance bridges.
[0065] See also Figure 4 ,like Figure 4 As shown, the resistance bridge module includes one first resistance bridge Q1 and four second resistance bridges Q2.
[0066] exist Figure 4 In the resistance bridge module shown, if the second transistor T 1B , the fourth transistor T 3A 、The sixth transistor T 3B 、The eighth transistor T 4B and the thirteenth transistor T 5B After receiving the low level signal sent by the controller, the first transistor T 1A , the third transistor T 2A 、The fifth transistor T 3A 、The seventh transistor T 4A And the ninth transistor T 5A When receiving the high level signal sent by the controller, the second transistor T 1B , the fourth transistor T 3A 、The sixth transistor T 3B 、The eighth transistor T 4B and the thirteenth transistor T 5B Cut-off, the first transistor T 1A , the third transistor T 2A 、The fifth transistor T 3A 、The seventh transistor T 4A And the ninth transistor T 5AIn this case, only the first resistor R1 is connected to the circuit, and the equivalent resistance of the resistance bridge module is the first resistor R1.
[0067] exist Figure 4 In the resistance bridge module shown, if the first transistor T 1A , the second transistor T 1B , the third transistor T 2A , the fourth transistor T 2B 、The fifth transistor T 3A 、The sixth transistor T 3B 、The seventh transistor T 4A And the ninth transistor T 5A After receiving the high level signal from the controller, the eighth transistor T 4B and the thirteenth transistor T 5B When receiving the low level signal sent by the controller, the first transistor T 1A , the second transistor T 1B , the third transistor T 2A , the fourth transistor T 2B 、The fifth transistor T 3A 、The sixth transistor T 3B 、The seventh transistor T 4A And the ninth transistor T 5A The eighth transistor T is turned on. 4B and the thirteenth transistor T 5B In this case, only the first resistor R1, the second resistor R2 and the third resistor R3 are connected to the circuit, and the equivalent resistance of the resistance bridge module is the first resistor R1, the second resistor R2 and the third resistor R3 in parallel.
[0068] for Figure 4 The resistance bridge module shown can also send different level signals to each transistor through the controller to adjust the resistance value of the resistance bridge module. The combination results of the equivalent resistance of the resistance bridge module are shown in Table 1 below:
[0069] Table 1:
[0070]
[0071]
[0072] In this embodiment, the controller controls the conduction and cutoff of each transistor in the resistance bridge module, so that the resistors form different series and parallel relationships, thereby changing the equivalent resistance of the resistance bridge.
[0073] The resistance bridge provided in the embodiment of the present application adopts an electronically controlled variable resistance element, which significantly improves the adjustment speed and accuracy. The resistance bridge provided in the embodiment of the present application can automatically adjust the resistance value according to the level signal sent by the controller, achieving a higher level of automation. The resistance bridge provided in the embodiment of the present application is composed of one resistor and two transistors, realizing a modular and integrated design. The resistance bridge provided in the embodiment of the present application can be coordinated with other resistance bridges to achieve a variety of resistance combinations, thereby greatly improving the adjustment range and flexibility of the resistance bridge and meeting more diverse application needs.
[0074] See also Figure 5 , Figure 5 This is a schematic diagram of the structure of the neural network architecture provided in the embodiment of this application. Figure 5 As shown, the neural network architecture provided by the embodiment of the present application includes a plurality of neuromorphic circuits 100 as described above, and the plurality of neuromorphic circuits 100 are connected in series.
[0075] In the embodiment of the present application, in a real-time and dynamic environment, the neural network architecture provided by the embodiment of the present application significantly reduces the signal processing delay, eliminates the processes such as timing analysis and logic unit configuration, improves design efficiency and reliability, reduces power consumption, and has a higher energy efficiency ratio.
[0076] Optionally, the neural network architecture further includes a controller J1;
[0077] The controller J1 is electrically connected to each neuromorphic circuit 100 .
[0078] like Figure 5 As shown, the neural network architecture further includes a controller J1, which is electrically connected to each neuromorphic circuit 100. In the embodiment of the present application, the core of the neural network architecture is to control the neuromorphic circuit 100 through the controller J1 and adjust the resistance value via the serial bus.
[0079] Optionally, the neural network architecture further comprises a digital-to-analog converter and an analog-to-digital converter;
[0080] The output terminal of the digital-to-analog converter is electrically connected to the input terminals of the multiple neuromorphic circuits 100 , and the input terminal of the analog-to-digital converter is electrically connected to the output terminals of the multiple neuromorphic circuits 100 .
[0081] like Figure 5 As shown, the neural network architecture provided in the embodiment of the present application also includes a digital-to-analog converter and an analog-to-digital converter. The digital-to-analog converter is used to convert the received digital signal into an analog signal and transmit the analog signal to the multiple neuromorphic circuits 100; the analog-to-digital converter is used to convert the analog signal output by the multiple neuromorphic circuits 100 into a digital signal.
[0082] In this embodiment, by setting a digital-to-analog converter and an analog-to-digital converter in the neural network architecture, when the neural network architecture receives a digital signal, the digital signal is converted into an analog signal through the digital-to-analog converter, and then the analog signal is processed; the analog signal is converted into a digital signal through the analog-to-digital converter, and then the processed digital signal is output, thereby realizing joint work with other digital chip devices.
[0083] See also Figure 6 , Figure 6 This is a flow chart of the signal processing method provided by the embodiment of the present application. Figure 6 As shown, the signal processing method provided in the embodiment of the present application includes:
[0084] S610: Receive an analog signal.
[0085] S620, sending the analog signal to a neural network architecture, and processing the analog signal through the neural network architecture; wherein the neuromorphic circuit in the neural network architecture adjusts the analog signal based on a received control signal, and the control signal is a signal sent by a controller in the neural network architecture.
[0086] It should be noted that the signal processing method provided in the embodiment of the present application is applied to a neural network architecture.
[0087] In this embodiment, when an analog signal is received, the analog signal is sent to the neural network architecture. The controller in the neural network architecture sends a control signal to the neuromorphic circuit in the neural network architecture through a pre-written program, and the neuromorphic circuit adjusts the analog signal based on the received control signal.
[0088] The neuromorphic circuit in the embodiment of the present application can directly process analog signals without performing analog-to-digital conversion on the analog signals, thereby improving the efficiency of signal processing and reducing conversion errors in the signal processing process.
[0089] Obviously, the embodiments described above are only some of the embodiments of the present application, rather than all of the embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned specific embodiments, or to make equivalent replacements for some of the technical features therein. Any equivalent structure made using the contents of the present application specification and the accompanying drawings, directly or indirectly used in other related technical fields, is also within the scope of patent protection of the present application.
Claims
1. A neuromorphic circuit, characterized in that The neuromorphic circuit includes a matrix circuit, an aggregation module, and an activation module, and the neuromorphic circuit is also electrically connected to an external controller; The input end of the matrix circuit serves as the input end of the neuromorphic circuit, the output end of the matrix circuit is electrically connected to the input end of the aggregation module, the output end of the aggregation module is electrically connected to the input end of the activation module, and the output end of the activation module serves as the output end of the neuromorphic circuit; The matrix circuit is used to adjust the received analog signal and transmit the adjusted analog signal to the aggregation module; The aggregation module is used to perform a pooling operation on the received analog signal and transmit the processed analog signal to the activation module; The activation module is used to rectify the received analog signal and output the processed analog signal; The controller is used to control the adjustment method of the matrix circuit on the analog signal.
2. The neuromorphic circuit according to claim 1, wherein The matrix circuit includes a plurality of resistance bridge modules, and adjacent resistance bridge modules are electrically connected.
3. The neuromorphic circuit according to claim 2, wherein: The resistance bridge module includes a plurality of resistance bridges, and the plurality of resistance bridges are connected in series.
4. The neuromorphic circuit according to claim 3, wherein: The resistance bridge includes a resistor, a first transistor and a second transistor; The first end of the resistor and the first end of the first transistor are electrically connected via a first node, and the first node serves as an input end of the resistance bridge; The second end of the resistor is electrically connected to the first end of the second transistor; The second end of the first transistor and the second end of the second transistor are electrically connected via a second node, and the second node serves as an output end of the resistance bridge.
5. The neuromorphic circuit according to claim 3, wherein: The resistance bridge module includes a first resistance bridge and a plurality of second resistance bridges; The first transistor and the second transistor in the first resistance bridge are turned on when receiving a high level signal from the controller, and the resistors in the first resistance bridge are connected in parallel with the resistors in the plurality of second resistance bridges.
6. The neuromorphic circuit according to claim 3, wherein: The resistance bridge module includes a first resistance bridge and a plurality of second resistance bridges; The first transistor and the second transistor in the first resistance bridge are turned off when receiving the low level signal sent by the controller, and the resistors in the first resistance bridge are disconnected from the resistors in the plurality of second resistance bridges.
7. A neural network architecture, characterized in that The neural network architecture includes a plurality of neuromorphic circuits according to any one of claims 1 to 6, and the plurality of neuromorphic circuits are connected in series.
8. The neural network architecture according to claim 7, characterized in that The neural network architecture also includes a controller; The controller is electrically connected to each neuromorphic circuit.
9. The neural network architecture according to claim 7, characterized in that The neural network architecture also includes a digital-to-analog converter and an analog-to-digital converter; The output terminal of the digital-to-analog converter is electrically connected to the input terminals of the plurality of neuromorphic circuits, and the input terminal of the analog-to-digital converter is electrically connected to the output terminals of the plurality of neuromorphic circuits; The digital-to-analog converter is configured to convert the received digital signal into an analog signal and transmit the analog signal to the plurality of neuromorphic circuits; The analog-to-digital converter is used to convert the analog signals output by the multiple neuromorphic circuits into digital signals.
10. A signal processing method, characterized in that: include: Receive analog signals; Sending the analog signal to a neural network architecture according to any one of claims 7 to 9, and processing the analog signal by the neural network architecture; The neuromorphic circuit in the neural network architecture adjusts the analog signal based on a received control signal, and the control signal is a signal sent by a controller in the neural network architecture.