Memory device with memory output masking mechanism
Through the memory output masking mechanism, the memory circuit is controlled to open and close and bypass, solving the problem that unknown state affects the test when the memory circuit is closed, and achieving efficient test path delay fault detection.
Patent Information
- Application Number
- CN202410153159.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-04
- Publication Date
- 2025-08-05
AI Technical Summary
The prior art cannot effectively test the path delay fault between the memory and the external functional circuit, and the output of an unknown state when the memory circuit is turned off, resulting in an increase in the test complexity and reducing the test efficiency.
The memory output masking mechanism is adopted to control the opening and closing of the memory circuit through the masking circuit and the masking control circuit, and bypass it during testing to avoid the unknown state affecting the test results.
Effectively test path delay faults between memory and external functional circuits, reduce test complexity, improve test efficiency, and reduce test time and sample number.
Smart Images
Figure CN120431985A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to memory technology, and more particularly to a memory device having a memory output masking mechanism. Background Art
[0002] After an integrated circuit is manufactured, an automatic test pattern generation (ATPG) tool is used to generate scan test patterns with high error coverage, and the scan test is performed through a scan chain to preliminarily exclude chips with defects in logic circuits such as, but not limited to, stuck-at faults and delay faults. In addition, in order to exclude chips with defective memories, a built-in self-test (BIST) circuit of the memory circuit is used to test the memory.
[0003] However, the above test methods cannot test delay faults on the path between the external functional circuit and the memory, and a mechanism that can keep the memory circuit activated and test the path between the external functional circuit and the memory is required. However, some test patterns will cause the memory circuit to shut down and result in unknown state outputs during the above test mechanism, thereby increasing the test operation complexity and reducing the test efficiency. Summary of the Invention
[0004] In view of the problems of the prior art, an object of the present invention is to provide a memory device having a memory output masking mechanism to improve the prior art.
[0005] An object of the present invention is to provide a memory device having a memory output masking mechanism, comprising: a memory block, a masking circuit, and a masking control circuit. The memory block includes: a memory circuit and a memory bypass circuit. The memory circuit is configured to be controlled by an actual drive signal, to be activated when the actual drive signal is in an enabling state, to be turned off when the actual drive signal is in a disabling state, and to receive an access signal and operate accordingly to generate a data output signal when activated. The memory bypass circuit is configured to be controlled by an actual mode control signal, to output the data output signal as an output signal when the actual mode control signal is in a non-bypass state, and to output the access signal and the actual drive signal as an output signal when the actual mode control signal is in a bypass state. The masking circuit is configured to receive a drive signal and a mode control signal, and to generate an actual drive signal and an actual mode control signal under the control of a masking control signal, wherein when the masking control signal is in a masking state, the actual drive signal is in a disabling state, and the actual mode control signal is in a bypass state. The masking control circuit is configured to receive and output a masking control signal.
[0006] The features, implementation, and effects of this case will be described in detail with reference to the preferred embodiments in conjunction with the drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 Showing a block diagram of a memory device having a memory output masking mechanism in an embodiment of the present invention;
[0008] Figures 2A to 2E Respectively showing schematic diagrams of the operation of the memory device in different modes in an embodiment of the present invention;
[0009] Figure 3 Showing a block diagram of the masking circuit and the masking control circuit in an embodiment of the present invention; and
[0010] Figure 4 Showing a block diagram of a memory device having a memory output masking mechanism in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0011] An object of the present invention is to provide a memory device having a memory output masking mechanism. By setting the masking circuit and the masking control signal in the masking state, the memory circuit is turned off, and at the same time, the memory circuit is bypassed, avoiding the influence of the unknown state output by the memory circuit when it is turned off on the test result.
[0012] Please refer to Figure 1 . Figure 1FIG. 0 shows a block diagram of a memory device 100 having a memory output masking mechanism according to an embodiment of the present invention. The memory device 100 includes: a memory block 110, an input multiplexer 115, a built-in self-test control circuit 120, a mode selection circuit 125, a masking circuit 130, and a masking control circuit 135.
[0013] The memory block 110 includes: a memory circuit 140 and a memory bypass circuit 145.
[0014] In one embodiment, the memory circuit 140 is a static random access memory (SRAM), and is configured to be controlled by an actual drive signal MA, and to be activated when the actual drive signal MA is in an enabled state, and to be deactivated when the actual drive signal MA is in a disabled state. In one embodiment, the enabled state of the actual drive signal MA is a high state, and the disabled state of the actual drive signal MA is a low state.
[0015] The memory circuit 140 is further configured to operate based on an access signal AS received when activated and generate a data output signal DO. In one embodiment, the access signal AS may include, for example, but not limited to, an input data signal, an address signal, a write enable signal, a read enable signal, or other signals (not shown) for accessing the memory circuit 140. In one embodiment, the memory circuit 140 may receive the above signals through different input terminals. The present invention is not limited thereto.
[0016] The memory bypass circuit 145 is controlled by an actual mode control signal AM, and outputs the data output signal DO as an output signal OS when the actual mode control signal AM is in a non-bypass state, and outputs the access signal AS and the actual drive signal MA as the output signal OS when the actual mode control signal AM is in a bypass state. In one embodiment, the non-bypass state of the actual mode control signal AM is a low state, and the bypass state of the actual mode control signal AM is a high state.
[0017] In one embodiment, the memory bypass circuit 145 includes a bit compression circuit 150 and a multiplexer 155.
[0018] The bit compression circuit 150 may include, for example, but not limited to, at least one exclusive or (XOR) gate, configured to compress the access signal AS and the actual drive signal MA to generate a compression signal CS. In one embodiment, the bit compression circuit 150 compresses the access signal AS and the actual drive signal MA into a compression signal CS having the same number of bits as the data output signal DO.
[0019] In a numerical example, when the data output signal DO is an 8-bit signal, the bit compression circuit 150 can compress a total of 13-bit access signal AS and the actual drive signal MA into an 8-bit compressed signal CS. It should be noted that the above number of bits is only an example. The present invention is not limited thereto.
[0020] The multiplexer 155 is configured to output the data output signal DO as the output signal OS when the actual mode control signal AM is in the non-bypass state, and bypass the memory circuit 140 when the actual mode control signal AM is in the bypass state, and output the compressed signal CS (i.e., the compressed access signal AS and the actual drive signal MA) as the output signal OS.
[0021] In one embodiment, the non-bypass state of the actual mode control signal AM is a low state, and the bypass state of the actual mode control signal AM is a high state. In Figure 1 it, the high state is represented as 1 and the low state is represented as 0, marked on the side where the multiplexer 155 receives the data output signal DO and the compressed signal CS, to indicate the selection made by the input multiplexer 115 according to the state of the actual mode control signal AM.
[0022] The input multiplexer 115 is configured to receive a set of first access signals AC1 and a first drive signal DR1 from an external circuit (not shown), and receive a set of second access signals AC2 and a second drive signal DR2 from the built-in self-test control circuit 120.
[0023] The input multiplexer 115 is further configured to receive the built-in self-test mode control signal BM, and operate according to the non-built-in self-test mode state and the built-in self-test mode state of the built-in self-test mode control signal BM.
[0024] When the built-in self-test mode control signal BM is in the non-built-in self-test mode state, the memory device 100 operates in the non-built-in self-test mode, and the non-built-in self-test mode is one of the functional mode, the scan test mode, and the full-speed test mode. At this time, the input multiplexer 115 selects the first access signal AC1 to output as the access signal AS, and selects the first drive signal DR1 to output as the drive signal ME.
[0025] When the built-in self-test mode control signal BM is in the built-in self-test mode state, the memory device 100 operates in the built-in self-test mode. At this time, the input multiplexer 115 selects the second access signal AC2 to output as the access signal AS, and selects the second drive signal DR2 to output as the drive signal ME. Among them, the built-in self-test mode state corresponds to the built-in self-test mode.
[0026] In one embodiment, the non-built-in self-test mode state of the built-in self-test mode control signal BM is in the low state, and the non-built-in self-test mode state of the built-in self-test mode control signal BM is in the high state. In Figure 1 it, in the form where the high state is 1 and the low state is 0, it is marked on the side where the input multiplexer 115 receives the first access signal AC1 and the second access signal AC2, to indicate the selection made by the input multiplexer 115 according to the state of the built-in self-test mode control signal BM.
[0027] The mode selection circuit 125 is configured to receive the scan test mode control signal SC and the full-speed test mode control signal AT, and accordingly generate the mode control signal MO.
[0028] In one embodiment, when the scan test mode control signal SC is in the scan test mode state and the full-speed test mode control signal AT is in the non-full-speed test mode state, the memory device 100 operates in the scan test mode (which belongs to the non-built-in self-test mode). At this time, the mode selection circuit 125 makes the mode control signal MO in the bypass state.
[0029] In one embodiment, when the scan test mode control signal SC is in the scan test mode state and the full-speed test mode control signal AT is in the full-speed test mode state, the memory device 100 operates in the full-speed test mode (which belongs to the non-built-in self-test mode). At this time, the mode selection circuit 125 makes the mode control signal MO in the non-bypass state.
[0030] In one embodiment, when the scan test mode control signal SC is in the non-scan test mode state and the full-speed test mode control signal AT is in the non-full-speed test mode state, the memory device 100 operates in the functional mode (which belongs to the non-built-in self-test mode), or operates in the built-in self-test mode. At this time, the mode selection circuit 125 makes the mode control signal MO in the non-bypass state.
[0031] In practice, the mode selection circuit 125 can be implemented by a combination of logic circuits. In one embodiment, as Figure 1 shown, the mode selection circuit 125 includes an AND gate 160 and an inverter 165. The AND gate 160 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is configured to receive the scan test mode control signal SC, the second input terminal is configured to receive the test mode control signal AT through the inverter 165, and the output terminal is configured to generate the mode control signal MO.
[0032] Under such a combination of logic circuits, the scan test mode state, the full-speed test mode state, and the bypass state are respectively configured as the high state, where the non-scan test mode state, the non-full-speed test mode state, and the non-bypass state are respectively configured as the low state.Figure 1 Among them, these states are marked beside each signal in the form that the high state is 1 and the low state is 0.
[0033] The masking circuit 130 is configured to receive the drive signal ME and the mode control signal MO, and is controlled by the masking control signal MK to generate the actual drive signal MA and the actual mode control signal AM according to the state of the masking control signal MK. The masking control circuit 135 is configured to receive and output the masking control signal MK to the masking circuit 130 to achieve the effect of controlling the masking circuit 130.
[0034] More specifically, when the masking control signal MK is in the masking state, the masking circuit 130 makes the actual drive signal MA in the disabled state and makes the actual mode control signal AM in the bypass state.
[0035] At this time, the memory circuit 140 will be turned off, and the memory bypass circuit 145 will bypass the memory circuit 140 to output the compression signal CS as the output signal OS.
[0036] When the masking control signal MK is in the non-masking state, the masking circuit 130 outputs the drive signal ME as the actual drive signal MA and outputs the mode control signal MO as the actual mode control signal AM.
[0037] At this time, the memory circuit 140 will determine whether to be turned on or off according to the state of the drive signal ME. In one embodiment, the first drive signal DR1 received by the input multiplexer 115 from an external circuit and the second drive signal DR2 received from the built-in self-test control circuit respectively have the disabled state or the enabled state. Therefore, the drive signal ME output by the input multiplexer 115 according to one of the first drive signal DR1 and the second drive signal DR2 also has the disabled state or the enabled state, and the memory circuit 140 determines whether to be turned on or off based on this.
[0038] On the other hand, the memory bypass circuit 145 will determine whether to perform bypass according to the state of the mode control signal MO. As described above, the scan test mode control signal SC and the full-speed test mode control signal AT received by the mode selection circuit 125 will determine whether the mode control signal MO is in the bypass state or the non-bypass state, and then the memory bypass circuit 145 determines whether to bypass the memory circuit 140 based on this.
[0039] The following will describe the operation mode of the memory device 100 according to the masking control signal MK output by the masking control circuit 135 in different modes.
[0040] Please refer to Figures 2A to 2E . Figures 2A to 2ESchematically show the operations of the memory device 100 in different modes in an embodiment of the present invention. In these diagrams, signals not selected by each multiplexer in the memory device 100 are shown as dashed lines, and the high and low states of each signal are marked. The masked state and the unmasked state of the masking control signal MK are marked as 1 and 0, respectively.
[0041] Figure 2A Corresponds to the operation of the memory device 100 in the functional mode and the masking control signal MK in the unmasked state.
[0042] The input multiplexer 115 selects the first access signal AC1 and the first drive signal DR1 as the access signal AS and the drive signal ME according to the built-in self-test mode control signal BM in the non-built-in self-test mode state. At this time, the first access signal AC1 and the first drive signal DR1 can be generated by the real functional circuit.
[0043] The masking circuit 130 outputs the drive signal ME as the actual drive signal MA according to the masking control signal MK in the unmasked state, so that the memory circuit 140 receives the access signal AS and the actual drive signal MA to generate the data output signal DO.
[0044] The mode selection circuit 125 makes the mode control signal MO in the non-bypass state according to the scan test mode control signal SC in the non-scan test mode state and the full-speed test mode control signal AT in the non-full-speed test mode state.
[0045] The masking circuit 130 outputs the mode control signal MO as the actual mode control signal AM according to the masking control signal MK in the unmasked state, so that the multiplexer 155 does not bypass the memory circuit 140 according to the actual mode control signal AM in the non-bypass state, and outputs the data output signal DO as the output signal OS. At this time, the output signal OS can be received by another external functional circuit.
[0046] Figure 2B Corresponds to the operation of the memory device 100 in the built-in self-test mode and the masking control signal MK in the unmasked state.
[0047] The input multiplexer 115 selects the second access signal AC2 and the second drive signal DR2 as the access signal AS and the drive signal ME according to the built-in self-test mode control signal BM in the built-in self-test mode state. At this time, the second access signal AC2 and the second drive signal DR2 can be generated by the built-in self-test control circuit 120.
[0048] The masking circuit 130 outputs the drive signal ME as the actual drive signal MA according to the masking control signal MK in the unmasked state, so that the memory circuit 140 receives the access signal AS and the actual drive signal MA to generate the data output signal DO.
[0049] The mode selection circuit 125 makes the mode control signal MO in the non-bypass state according to the scan test mode control signal SC in the non-scan test mode state and the full-speed test mode control signal AT in the non-full-speed test mode state.
[0050] The masking circuit 130 outputs the mode control signal MO as the actual mode control signal AM according to the masking control signal MK in the unmasked state, so that the multiplexer 155 does not bypass the memory circuit 140 according to the actual mode control signal AM in the non-bypass state, but outputs the data output signal DO as the output signal OS. At this time, the output signal OS can be fed back to the built-in self-test control circuit 120 for evaluation.
[0051] Figure 2C This corresponds to the operating condition of the memory device 100 in the scan test mode and the masking control signal MK in the unmasked state.
[0052] The input multiplexer 115 can selectively select the first access signal AC1 and the first drive signal DR1 according to the built-in self-test mode control signal BM in the non-built-in self-test mode state, or select the second access signal AC2 and the second drive signal DR2 according to the built-in self-test mode control signal BM in the built-in self-test mode state as the access signal AS and the drive signal ME. In this example, the input multiplexer 115 selects the first access signal AC1 and the first drive signal DR1 as the access signal AS and the drive signal ME according to the built-in self-test mode control signal BM in the non-built-in self-test mode state as an example. At this time, the first access signal AC1 and the first drive signal DR1 can be generated by, for example, but not limited to, an automatic test pattern generation tool.
[0053] The masking circuit 130 outputs the drive signal ME as the actual drive signal MA according to the masking control signal MK in the unmasked state, so that the memory circuit 140 receives the access signal AS and the actual drive signal MA to generate the data output signal DO.
[0054] The mode selection circuit 125 makes the mode control signal MO in the bypass state according to the scan test mode control signal SC in the scan test mode state and the full-speed test mode control signal AT in the non-full-speed test mode state.
[0055] The masking circuit 130 outputs the mode control signal MO as the actual mode control signal AM according to the masking control signal MK in the unmasked state, causing the multiplexer 155 to bypass the memory circuit 140 according to the actual mode control signal AM in the bypass state and output the compressed signal CS as the output signal OS. At this time, the output signal OS can be received by an external circuit related to the scan chain for subsequent evaluation.
[0056] Figure 2D This corresponds to the operating condition of the memory device 100 in the full-speed test mode and the masking control signal MK being in the unmasked state.
[0057] The input multiplexer 115 selects the first access signal AC1 and the first drive signal DR1 as the access signal AS and the drive signal ME according to the built-in self-test mode control signal BM in the non-built-in self-test mode state. At this time, the first access signal AC1 and the first drive signal DR1 can be generated by, for example, but not limited to, an automatic test pattern generation tool.
[0058] The masking circuit 130 outputs the drive signal ME as the actual drive signal MA according to the masking control signal MK in the unmasked state, causing the memory circuit 140 to receive the access signal AS and the actual drive signal MA and generate a data output signal DO.
[0059] The mode selection circuit 125 makes the mode control signal MO in the non-bypass state according to the scan test mode control signal SC in the scan test mode state and the full-speed test mode control signal AT in the full-speed test mode state.
[0060] The masking circuit 130 outputs the mode control signal MO as the actual mode control signal AM according to the masking control signal MK in the unmasked state, causing the multiplexer 155 not to bypass the memory circuit 140 according to the actual mode control signal AM in the non-bypass state and output the data output signal DO as the output signal OS. At this time, the output signal OS can be received by an external circuit related to the scan chain for subsequent evaluation.
[0061] From Figure 2D it can be seen that in the full-speed test mode, the operation of the memory circuit 140 is closest to the functional mode, and it is possible to detect, for example, but not limited to, transition delay faults in the timing between the memory circuit 140 and the external circuit (i.e., the source of the first access signal AC1 and the first drive signal DR1).
[0062] In some applications, the memory circuit 140 in full-speed test mode may need to be turned off. However, turning off the memory circuit 140 will cause the data output signal DO and the output signal OS based on which it is output to be in an unknown state, thereby increasing the computational complexity of the debugging tool, not only reducing the debugging efficiency, but also increasing the computational time, decreasing the test coverage, and requiring more test pattern counts to debug.
[0063] Figure 2E This corresponds to the operating condition of the memory device 100 in full-speed test mode and the masking control signal MK being in the masked state.
[0064] The input multiplexer 115 will select the first access signal AC1 and the first drive signal DR1 as the access signal AS and the drive signal ME according to the built-in self-test mode control signal BM in the non-built-in self-test mode state. The masking circuit 130 will make the actual drive signal MA in the disabled state according to the masking control signal MK in the masked state.
[0065] The mode selection circuit 125 makes the mode control signal MO in the non-bypass state according to the scan test mode control signal SC in the scan test mode state and the full-speed test mode control signal AT in the full-speed test mode state. The masking circuit 130 makes the actual mode control signal AM in the bypass state according to the masking control signal MK in the masked state, causing the multiplexer 155 to bypass the memory circuit 140 according to the bypass state of the actual mode control signal AM, and outputting the compressed signal CS as the output signal OS.
[0066] The memory device 100 can, through the setting of the masking circuit 130, turn off the memory circuit 140 in full-speed test mode through the masking control signal MK in the masked state, and at the same time bypass the memory circuit 140 to avoid the unknown state output by the memory circuit 140 when it is turned off from affecting the test results.
[0067] It should be noted that in other modes, the memory device 100 can also, when there is a masking requirement, achieve the effect of masking the unknown state output by the memory circuit 140 when it is turned off through the masking circuit 130. The present invention is not limited to this.
[0068] In practice, the masking circuit 130 can be implemented by a combination of logic circuits, and the masking control circuit 135 can be implemented by a register. The implementation methods of one of the masking circuit 130 and the masking control circuit 135 will be described below.
[0069] Please refer to Figure 3 . Figure 3The block diagrams of the masking circuit 130 and the masking control circuit 135 in an embodiment of the present invention are shown. The masking circuit 130 includes: a drive control circuit 300 and a bypass control circuit 310.
[0070] The drive control circuit 300 is configured to receive a drive signal ME and a masking control signal MK, and accordingly generate an actual drive signal MA to Figure 1 the memory circuit 140.
[0071] In this embodiment, the drive control circuit 300 includes an AND gate 320 and an inverter 330. The AND gate 320 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is configured to receive the drive signal ME, the second input terminal is configured to receive the masking control signal MK through the inverter 330, and the output terminal is configured to generate the actual drive signal MA.
[0072] The bypass control circuit 310 is configured to receive a mode control signal MO and a masking control signal MK, and accordingly generate an actual mode control signal AM to Figure 1 the memory bypass circuit 145. The bypass control circuit 310 includes an OR gate 340. The OR gate 340 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is configured to receive the masking control signal MK, the second input terminal is configured to receive the mode control signal MO, and the output terminal is configured to generate the actual mode control signal AM.
[0073] Therefore, when the masking control signal MK is in the masking state and the masking state is high, the AND gate 320 of the drive control circuit 300 receives the drive signal ME and the inverted masking control signal MK which is low. Regardless of the state of the drive signal ME, the drive control circuit 300 will generate an actual drive signal MA which is low (corresponding to the disabled state).
[0074] On the other hand, when the masking control signal MK is in the masking state and the masking state is high, the OR gate 340 of the bypass control circuit 310 receives the mode control signal MO and the masking control signal MK which is high. Regardless of the state of the mode control signal MO, the drive control circuit 300 will generate an actual mode control signal AM which is high (corresponding to the non-bypass state).
[0075] In an embodiment, the masking control circuit 135 is a masking control register disposed in a scan chain, and as Figure 3 shown, includes: a data input terminal D, a data output terminal Q, a scan input terminal SI, a scan enable terminal SE, and a clock receiving terminal CK.
[0076] The data output terminal Q is electrically coupled to the data input terminal D. The scan enable terminal SE is configured to receive a scan enable signal ES. The scan input terminal SI is electrically coupled to a scan chain (not shown in the figure). The clock receiving terminal CK is configured to receive a clock signal CL and operate based thereon.
[0077] The scan input terminal SI is configured to receive a masking control signal MK when the scan enable terminal SE receives the scan enable signal ES in the scan enable state, and output the masking control signal MK at the data output terminal Q. When the scan enable terminal SE receives the scan enable signal ES in the non-scan enable state, the data input terminal D receives the masking control signal MK output from the data output terminal Q to maintain the state of the masking control signal MK.
[0078] Please refer to Figure 4 . Figure 4 FIG. shows a block diagram of a memory device 400 having a memory output masking mechanism according to an embodiment of the present invention.
[0079] The memory device 400 includes Figure 1 an input multiplexer 115, a built-in self-test control circuit 120, a mode selection circuit 125, and a masking control circuit 135 in
[0080] The memory device 400 further includes N Figure 1 memory blocks 110 and circuit blocks CB1 to CB N each including a masking circuit 130, and only the structure of the circuit block CB1 is shown in detail in Figure 4 . Therefore, the memory device 400 actually includes N memory blocks 110 and N masking circuits 130 that correspond to each other, where N is an integer greater than 1.
[0081] The N circuit blocks CB1 to CB N are actually electrically coupled to the N input multiplexers 115 in a one-to-one relationship. However, to avoid making the diagram too complex, the connection lines between each circuit block CB1 to CB N and each input multiplexer 115 are not shown in Figure 4 . Different groups of circuit blocks and input multiplexers can share the built-in self-test control circuit 120, the mode selection circuit 125, and the masking control circuit 135, so that the N circuit blocks CB1 to CB N receive signals from the built-in self-test control circuit 120, the mode selection circuit 125, and the masking control circuit 135 through the corresponding N input multiplexers 115. The connection manner and the corresponding operation manner of each group of circuit blocks and multiplexers to the built-in self-test control circuit 120, the mode selection circuit 125, and the masking control circuit 135 are the same asFigure 1 The same, no longer repeated here.
[0082] With such a configuration, the N shielding circuits 130 can receive a common shielding control signal MK from a shielding control circuit 135, so as to achieve simultaneous control of the memory circuits (not shown) in the plurality of memory blocks 110. Figure 4 This configuration can significantly save circuit area when the memory device 400 has multiple memory blocks and can flexibly operate the memory blocks.
[0083] It should be noted that the above implementation is merely an example. In other embodiments, those skilled in the art may make modifications without departing from the spirit of the present invention. For example, the signal states in the above embodiment are merely examples; in practice, the configurations may be reversed depending on requirements. Furthermore, the logic circuit combinations may vary depending on the signal state configurations without affecting the functionality of the memory device. The present invention is not limited to specific signal state configurations or logic circuit combinations.
[0084] In summary, the memory device with a memory output masking mechanism in the present invention can shut down the memory circuit by configuring a masking circuit and a masking control signal in a masking state, and simultaneously bypass the memory circuit to prevent the unknown state output by the memory circuit when it is turned off from affecting the test results.
[0085] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art may modify the technical features of this case based on the explicit or implicit content of this case. All such modifications may fall within the scope of the patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.
[0086]
Explanation of symbols
[0087] 100: Memory device
[0088] 110: memory block
[0089] 115: Input multiplexer
[0090] 120: Built-in self-test control circuit
[0091] 125: Mode selection circuit
[0092] 130: Shielding circuit
[0093] 135: Shielding control circuit
[0094] 140: memory circuit
[0095] 145: Memory bypass circuit
[0096] 150: Bit compression circuit
[0097] 155: Multiplexer
[0098] 160: AND gate
[0099] 165: Inverter
[0100] 300: Drive control circuit
[0101] 310: Bypass control circuit
[0102] 320: AND gate
[0103] 330: Inverter
[0104] 340: OR gate
[0105] 400: Memory device
[0106] AC1: First access signal
[0107] AC2: Second access signal
[0108] AM: Actual mode control signal
[0109] AS: Access signal
[0110] AT: Full-speed test mode control signal
[0111] BM: Built-in self-test mode control signal
[0112] CB1~CB N : Circuit block
[0113] CK: Clock receiving end
[0114] CL: Clock signal
[0115] CS: Compression signal
[0116] D: Data input terminal
[0117] DO: Data output signal
[0118] DR1: First drive signal
[0119] DR2: Second drive signal
[0120] ES: Scan enable signal
[0121] MA: Actual drive signal
[0122] MK: Mask control signal
[0123] MO: Mode control signal
[0124] OS: Output signal
[0125] Q: Data output terminal
[0126] SC: Scan test mode control signal
[0127] SE: Scan enable terminal
[0128] SI: Scan input terminal
Claims
1. A memory device having a memory output masking mechanism, comprising: A memory block comprising: A memory circuit configured to be controlled by an actual driving signal, to be activated when the actual driving signal is in an enabled state, and to be disabled when the actual driving signal is in a disabled state, and to receive an access signal when activated to operate and generate a data output signal; as well as a memory bypass circuit configured to be controlled by an actual mode control signal to output the data output signal as an output signal when the actual mode control signal is in a non-bypass state, and to output the access signal and the actual drive signal as the output signal when the actual mode control signal is in a bypass state; a mask circuit configured to receive a driving signal and a mode control signal and be controlled by a mask control signal to generate the actual driving signal and the actual mode control signal, wherein when the mask control signal is in a mask state, the actual driving signal is in the disabled state and the actual mode control signal is in the bypass state; and A shading control circuit is configured to receive and output the shading control signal. 2 . The memory device according to claim 1 , wherein when the mask control signal is in a non-masking state, the mask circuit outputs the driving signal as the actual driving signal and outputs the mode control signal as the actual mode control signal.
3. The memory device according to claim 2 , wherein the shielding circuit comprises a driving control circuit, and the driving control circuit comprises an AND gate and an inverter, the AND gate comprising: a first input terminal configured to receive the driving signal; a second input terminal configured to receive the shielding control signal through the inverter; and An output terminal is configured to generate the actual driving signal.
4. The memory device according to claim 2 , further comprising a built-in self-test (BIST) control circuit and an input multiplexer, the input multiplexer configured to receive a first driving signal from a functional circuit and a second driving signal from the BIST control circuit, the first driving signal and the second driving signal respectively having the disabled state or the enabled state, and the BIST control circuit and the input multiplexer further configured to receive a built-in self-test (BIST) mode control signal; When the built-in self-test mode control signal is in a non-built-in self-test mode state, the built-in self-test control circuit is disabled and the input multiplexer selects the first driving signal to be output as the driving signal, wherein the non-built-in self-test mode state corresponds to a non-built-in self-test mode, and the non-built-in self-test mode is one of a functional mode, a scan test mode, and a full-speed test mode; and When the BIST control signal is in a BIST mode state, the BIST control circuit is enabled and the input multiplexer selects the second driving signal to be output as the driving signal, wherein the BIST mode state corresponds to a BIST mode.
5. The memory device of claim 4 , wherein the input multiplexer is further configured to receive a first access signal from the functional circuit and a second access signal from the built-in self-test control circuit; When the built-in self-test mode control signal is in the non-built-in self-test mode state, the input multiplexer selects the first access signal to be output as the access signal; When the built-in self-test mode control signal is in the built-in self-test mode state, the input multiplexer selects the second access signal to be output as the access signal.
6. The memory device of claim 2 , wherein the shielding circuit comprises a bypass control circuit, and the bypass control circuit comprises an OR gate, the OR gate comprising: a first input terminal configured to receive the shielding control signal; a second input terminal configured to receive the mode control signal; and An output terminal is configured to generate the actual mode control signal.
7. The memory device according to claim 2, further comprising a mode selection circuit configured to receive a scan test mode control signal and a full-speed test mode control signal and generate the mode control signal accordingly; wherein when the scan test mode control signal is in a scan test mode state and the full-speed test mode control signal is in a non-full-speed test mode state, the mode selection circuit places the mode control signal in the bypass state; When the scan test mode control signal is in a scan test mode state and the full-speed test mode control signal is in a full-speed test mode state, the mode selection circuit places the mode control signal in the non-bypass state; and When the scan test mode control signal is in the non-scan test mode state and the full-speed test mode control signal is in the non-full-speed test mode state, the mode selection circuit places the mode control signal in the non-bypass state.
8. The memory device according to claim 7, wherein the mode selection circuit comprises an AND gate and an inverter, the AND gate comprising: a first input terminal configured to receive the scan test mode control signal; a second input terminal configured to receive the full-speed test mode control signal through the inverter; and An output terminal is configured to generate the mode control signal, wherein the scan test mode state, the full-speed test mode state and the bypass state are respectively a high state, and the non-scan test mode state, the non-full-speed test mode state and the non-bypass state are respectively a low state.
9. The memory device according to claim 1 , wherein the memory bypass circuit comprises: a one-bit compression circuit configured to compress the access signal and the actual driving signal to generate a compressed signal; and A multiplexer is configured to output the data output signal as the output signal when the actual mode control signal is in the non-bypass state, and to output the compressed signal as the output signal when the actual mode control signal is in the bypass state. 10 . The memory device according to claim 1 , wherein the number of the memory blocks and the shielding circuits is N and corresponds to each other, and the N shielding circuits receive the shielding control signal from one shielding control circuit, and N is an integer greater than 1.