Semiconductor integrated circuit and manufacturing method thereof

Abstract

The invention provides a semiconductor integrated circuit and a manufacturing method thereof, and the manufacturing method comprises the steps: firstly depositing a stress dielectric layer with the stress opposite to that of a topmost metal layer after the topmost metal layer is deposited and before the topmost metal layer is etched, enabling the warping degree of a wafer substrate to be reduced to a required range, and enabling the warping degree of the wafer substrate to be reduced to a required range; according to the invention, the risk that the wafer cannot be grabbed by a photoetching machine or the wafer falls off and is broken in the process of grabbing the wafer due to the overlarge warping degree of the wafer substrate can be avoided, and the adverse problem that the photoresist is too thick to topple over or the thickness of the photoresist is insufficient when the topmost metal layer is etched can be solved. According to the semiconductor integrated circuit, the stress dielectric layer is arranged between the topmost metal layer and the passivation layer, the wafer warping degree is within the required range, the sealing performance at the vertex angle of the contact pad is good, and the circuit yield and reliability are high.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor integrated circuit and a manufacturing method thereof. Background Art

[0002] In the manufacturing of semiconductor integrated circuits, various semiconductor device structures (such as the source, drain, and gate of a transistor) are typically fabricated on a wafer substrate. Metal interconnect structures (including multiple metal interconnect layers in a stacked structure and conductive vias connecting two metal interconnect layers) are then fabricated above to enable signal transmission between the semiconductor device structures. Certain circuits with high performance requirements (such as mixed-signal circuits, analog circuits, and radio frequency circuits) require a thicker top metal layer (UTM), or even an ultra-thick metal layer (UTM), to reduce the resistance of the metal lines, withstand higher currents, and improve the quality factor of the inductor. These layers can be, for example, thicker than 3μm.

[0003] The manufacturing method of these semiconductor integrated circuits with a relatively thick (or ultra-thick) top metal layer generally includes: after manufacturing the front-end device and the metal interconnection structure below the top metal layer in the substrate 100, depositing a sufficiently thick top metal layer 101, coating a photoresist layer on the top metal layer 101, and performing photolithography on the photoresist layer to form a patterned photoresist 102, such as Figure 1 With the patterned photoresist 102 as a mask (ie, under the shielding of the patterned photoresist 102), the top metal layer 101 is etched to form a desired pattern in the top metal layer 101, as shown in FIG. Figure 1 After that, the patterned photoresist 102 is removed and a silicon nitride (SiN) layer is deposited as a passivation layer 103 to obtain a better sealing effect, and the passivation layer 103 is further etched to open the exposed top metal layer 101 to form a contact pad 101a, as shown in FIG. Figure 1 As shown in (C).

[0004] The above-mentioned prior art has the following problems:

[0005] 1. Due to the large difference in thermal expansion coefficients between metal and dielectric materials, tension is easily generated during the manufacturing process of the metal interconnect structure, causing wafer warpage. After the top metal layer (Top Metal) 101 is grown, the wafer warpage will increase significantly. Excessive wafer warpage will have a serious impact on the subsequent lithography process, which may cause distortion of the lithography pattern structure and reduce the yield. It may also cause the subsequent lithography machine to be sensitive and unable to grasp the wafer, or increase the risk of the wafer falling and breaking during the wafer grasping process.

[0006] 2. The thicker the top metal layer 101 is, the longer it takes to etch it, and the thicker the photoresist layer coated thereon must be. In this way, the patterned photoresist 102 used as a mask will not be over-etched during the long etching time of the top metal layer 101, thereby ensuring the integrity of the etched pattern of the top metal layer 101. However, if the thickness of the coated photoresist layer is too high, the patterned photoresist 102 formed after photolithography is prone to tipping over. If a thinner photoresist is used to prevent the photoresist from tipping over, the top metal layer 101 will not be adequately etched or the etched pattern will be distorted due to insufficient shielding of the patterned photoresist 102 after photolithography. Figure 2 As shown, this will lead to a short circuit problem.

[0007] 3. The thermal expansion coefficients of the silicon nitride (SiN) deposited on the top metal layer as the passivation layer 103 do not match those of the top metal layer, resulting in poor adhesion between the two. When the passivation layer 103 is etched open to form the contact pad 101a, the SiN on both sides of the top of the contact pad 101a easily cracks with the top metal layer 101, resulting in poor sealing. Summary of the Invention

[0008] The purpose of the present invention is to provide a semiconductor integrated circuit and a manufacturing method thereof, which can solve the problems of wafer warping caused by the top metal layer being too thick and the top metal layer etching pattern distortion caused by insufficient photoresist shielding, so as to improve the circuit yield and reliability.

[0009] To achieve the above object, the present invention provides a method for manufacturing a semiconductor integrated circuit, comprising:

[0010] Providing a wafer substrate that has been processed accordingly, and depositing a topmost metal layer on the wafer substrate;

[0011] Covering the topmost metal layer with a corresponding stress dielectric layer, wherein the stress of the stress dielectric layer is opposite to the stress of the topmost metal layer, so that the warpage of the wafer substrate is reduced to a required range;

[0012] coating a photoresist layer on the stressed dielectric layer, and performing photolithography on the photoresist layer to form a patterned photoresist;

[0013] Using the patterned photoresist as a mask, etching the stressed dielectric layer to the top surface of the topmost metal layer;

[0014] removing the patterned photoresist and etching the topmost metal layer using the stressed dielectric layer as a mask to form a desired pattern in the topmost metal layer;

[0015] The patterned photoresist is removed.

[0016] Optionally, the material of the stress dielectric layer includes at least one of undoped or doped silicate glass, tetraethyl orthosilicate, and low-temperature silicon oxide formed in a temperature range of 0 to 500° C.

[0017] Optionally, the stress of the stress medium layer is compressive stress, and the magnitude thereof is -200 MPa to -1000 MPa.

[0018] Optionally, front-end devices and front-end metal interconnection structures are formed in the wafer substrate, the front-end devices include at least one of MOS transistors, capacitors, resistors, inductors, diodes, and triodes, and the front-end metal interconnection structure includes an interlayer dielectric layer, a multilayer metal interconnection layer formed in the interlayer dielectric layer, a conductive through-hole electrically connecting two corresponding metal interconnection layers in the multilayer metal interconnection layer, a contact hole connecting the multilayer metal interconnection layer and the front-end device, and a top conductive through-hole connecting the multilayer metal interconnection layer and the topmost metal layer.

[0019] Optionally, each metal interconnect layer is a copper interconnect layer, and the topmost metal layer includes copper, copper alloy, aluminum or aluminum alloy.

[0020] Optionally, after forming the desired pattern in the topmost metal layer, the manufacturing method further comprises:

[0021] depositing a passivation layer on the stressed dielectric layer, the topmost metal layer, and the wafer substrate;

[0022] Etching the passivation layer and the stress dielectric layer to form an opening exposing a portion of the top metal layer, wherein the top metal layer exposed by the opening serves as a contact pad;

[0023] A corresponding metallization connection process is performed on the contact pad and the passivation layer to achieve connection between the contact pad and an external electrical structure.

[0024] Optionally, the stress medium layer remains on the bottom sidewall of each opening.

[0025] Optionally, the passivation layer includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0026] Based on the same inventive concept, the present invention further provides a semiconductor integrated circuit, comprising:

[0027] Wafer substrates that have been processed accordingly;

[0028] a topmost metal layer formed on the wafer substrate and having a desired pattern;

[0029] a stressed dielectric layer formed on a portion of the top surface of the topmost metal layer, and having a stress opposite to that of the topmost metal layer, so as to reduce the warpage of the wafer substrate to a required range;

[0030] A passivation layer is formed on the stress dielectric layer, the top metal layer and the wafer substrate and has corresponding openings. The openings penetrate the passivation layer and the stress dielectric layer and expose a portion of the top metal layer to form contact pads.

[0031] Optionally, the semiconductor integrated circuit further includes at least one of the following features:

[0032] (1) The material of the stress dielectric layer includes at least one of undoped or doped silicate glass, tetraethyl orthosilicate, and low-temperature silicon oxide formed in a temperature range of 0 to 500° C.;

[0033] (2) The stress of the stress medium layer is compressive stress, and the magnitude is -200 MPa to -1000 MPa;

[0034] (3) A front-end device and a front-end metal interconnect structure are formed in the wafer substrate, wherein the front-end device includes at least one of a MOS transistor, a capacitor, a resistor, an inductor, a diode, and a triode, and the front-end metal interconnect structure includes an interlayer dielectric layer, a multilayer metal interconnect layer formed in the interlayer dielectric layer, a conductive via electrically connecting two corresponding metal interconnect layers in the multilayer metal interconnect layer, a contact hole connecting the multilayer metal interconnect layer and the front-end device, and a top conductive via connecting the multilayer metal interconnect layer and the topmost metal layer;

[0035] (4) Each metal interconnect layer in the wafer substrate is a copper interconnect layer, and the top metal layer includes copper, copper alloy, aluminum or aluminum alloy;

[0036] (5) The stress dielectric layer is retained on the bottom sidewall of each opening;

[0037] (6) The passivation layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride;

[0038] (7) A metallized connection structure formed on the contact pad and the passivation layer to achieve connection between the contact pad and an external electrical structure.

[0039] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0040] 1. The manufacturing method of the present invention deposits a stress dielectric layer having a stress opposite to that of the top metal layer after the top metal layer is deposited and before the top metal layer is etched, so that the warpage of the wafer substrate is reduced to a required range. On the one hand, this is beneficial to the normal grasping of the wafer substrate by the subsequent photolithography machine, avoiding the risk of the photolithography machine being unable to grasp the wafer or increasing the risk of the wafer falling and breaking during the grasping process due to excessive warpage of the wafer substrate. On the other hand, the etching between the stress dielectric layer and the photoresist is relatively large, and the stress dielectric layer can be used as a hard mask layer (hardmask) for etching the top metal layer, which is beneficial to reducing the coating thickness of the photoresist, solving the adverse problems caused by the overly thick photoresist or the insufficient thickness of the photoresist during the etching of the top metal layer, thereby improving the circuit yield and reliability. In addition, due to the presence of the stress dielectric layer, on the one hand, the passivation layer is not easily cracked when etching open the passivation layer to form the contact pad. On the other hand, the stress dielectric layer can be retained above the top corner of the formed contact pad, achieving a good adhesion effect at the top corner of the contact pad and ensuring the sealing at the top corner of the contact pad.

[0041] 2. The semiconductor integrated circuit of the present invention has a stress dielectric layer between the top metal layer and the passivation layer. On the one hand, the stress of the stress dielectric layer can be used to reduce the warpage of the semiconductor integrated circuit wafer to a required range by taking advantage of the fact that the stress of the stress dielectric layer is opposite to the stress of the top metal layer. On the other hand, the stress dielectric layer can be used to alleviate the mismatch in thermal expansion coefficients between the top metal layer and the passivation layer, thereby avoiding cracking of the passivation layer. In addition, the stress dielectric layer retained above the top corners of the contact pads achieves a good adhesion effect at the top corners of the contact pads, ensuring the sealing at the top corners of the contact pads, thereby improving the circuit yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0043] Figure 1 Schematic diagram of wafer warpage caused by excessive thickness of the top metal layer.

[0044] Figure 2 This is an electron microscope scan image showing the top metal layer with distorted etching patterns due to insufficient shielding by the photoresist above.

[0045] Figure 3 The flowchart of the method for manufacturing a semiconductor integrated circuit according to one embodiment of the present invention is shown.

[0046] Figures 4A to 4D It is a schematic cross-sectional view of a circuit structure in a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] The technical solutions proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0049] Please refer to Figure 3 The present invention provides a method for manufacturing a semiconductor integrated circuit, comprising the following steps:

[0050] S1, providing a wafer substrate that has been processed accordingly, and depositing a topmost metal layer on the wafer substrate;

[0051] S2, covering the topmost metal layer with a corresponding stress dielectric layer, wherein the stress of the stress dielectric layer is opposite to the stress of the topmost metal layer, so that the warpage of the wafer substrate is reduced to a required range;

[0052] S3, coating a photoresist layer on the stressed dielectric layer, and performing photolithography on the photoresist layer to form a patterned photoresist;

[0053] S4, using the patterned photoresist as a mask, etching the stressed dielectric layer to the top surface of the topmost metal layer;

[0054] S5, removing the patterned photoresist, and etching the topmost metal layer using the stressed dielectric layer as a mask to form a desired pattern in the topmost metal layer;

[0055] S6, removing the patterned photoresist.

[0056] In step S1, please refer to Figure 4A A wafer substrate 200 that has undergone front-end device processing and front-end metal interconnect structure processing is provided. The wafer substrate 200 includes a base 200a (made of any suitable semiconductor material, such as silicon, silicon-on-insulator, silicon germanium, silicon carbide, or gallium arsenide). The corresponding front-end devices are formed on the base 200a and may include any one or more active devices, such as MOS transistors 202, diodes, and triodes, and may also include any one or more passive devices, such as capacitors, resistors, and inductors. The front-end metal interconnect structure is formed above the layer where the front-end devices are located. It may include an interlayer dielectric layer 203x (typically formed by stacking multiple intermetallic dielectric layers), multiple metal interconnect layers Mx formed in the interlayer dielectric layer 203x (i.e., from the bottom metal interconnect layer M1 to the next top metal layer below the top metal layer to be formed), conductive vias Vx (also known as conductive plugs) electrically connecting two corresponding metal interconnect layers in the multilayer metal interconnect layer, and contact holes CT (also known as contact plugs) connecting the multilayer metal interconnect layers (e.g., the bottom metal interconnect layer M1) and the front-end devices (e.g., the source, drain, or gate of a MOS transistor). The number of metal interconnect layers Mx can be two, three, four, five, six, or more, depending on the specific circuit design requirements, which is not specifically limited in the present invention.

[0057] As an example, the front-end device formed in the wafer substrate 200 of this embodiment includes multiple MOS transistors 202, and a device isolation structure (for example, a shallow trench isolation structure) 201 for defining the active area (not shown) of each MOS transistor 202 is formed in the substrate 200a. At the same time, a well region 200b is formed in the active area of each MOS transistor 202 (wherein the well region 200b corresponding to the NMOS transistor is a P-type well region, and the well region 200b corresponding to the PMOS transistor is an N-type well region). Each MOS transistor 202 includes: a gate structure formed on its active area (unmarked, including a gate oxide layer and a gate stacked in sequence on the substrate), a sidewall (unmarked) formed on the sidewall of the gate structure, and a source region and a drain region formed in the well region 200b on both sides of the gate structure. The bottom-layer interlayer dielectric layer in the front-end metal interconnection structure buries each MOS transistor 202 and has a flat upper surface. The front-end metal interconnection structure not only includes the interlayer dielectric layer 203x, the contact hole CT, the multi-layer metal interconnection layer Mx, and the conductive via Vx, but also includes the top conductive via TV. The top conductive via TV is used to electrically connect the multi-layer metal interconnection layer (for example, the sub-top metal layer therein) and the top-layer metal layer 204 to be formed. Among them, the interlayer dielectric layer 203x can be formed by at least one of silicon dioxide, silicon nitride, undoped silicate glass (USG), fluorinated silicate glass (FSG), low-k (dielectric constant k is less than 3.8, for example) dielectric materials, etc.; the material of the contact hole CT can be any suitable material such as tungsten, tungsten alloy, copper or copper alloy; each layer of metal interconnection layer Mx and the corresponding conductive through hole Vx can be formed by a single damascene and / or dual damascene process, and the material of each layer of metal interconnection layer Mx and the corresponding conductive through hole Vx can be copper or copper alloy (that is, each layer of metal interconnection layer Mx is a copper interconnection layer), and the thickness of each layer of metal interconnection layer Mx can be in the range of 10000 to 10000. the following.

[0058] In step S1, please continue to refer to Figure 4A A top metal layer 204 of a desired thickness may be deposited on the wafer substrate 200 by any suitable process such as physical vapor deposition (PVD) or electroplating. As an example, the thickness of the top metal layer 204 is 1 μm to 10 μm, such as 3 μm or 5 μm.

[0059] Optionally, the topmost metal layer 204 may include a bottom metal diffusion barrier layer (not shown), a metal material layer (not shown), and a top metal diffusion barrier layer (not shown). The metal material layer in the topmost metal layer 204 may include any suitable metal material, such as copper, a copper alloy, aluminum, or an aluminum alloy. The bottom metal diffusion barrier layer and the top metal diffusion barrier layer may be made of the same material or different materials, for example, at least one selected from titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), tungsten nitride (WN), and the like.

[0060] Among them, due to the large difference in thermal expansion coefficient between the top metal layer 204 and the interlayer dielectric layer below it, corresponding stress will be generated during the deposition process of the top metal layer 204, and as the deposition thickness of the top metal layer 204 increases, the stress caused by the top metal layer 204 will also gradually increase. Therefore, after the top metal layer 204 is grown, the warping of the wafer substrate 200 will usually increase significantly.

[0061] In step S2, please continue to refer to Figure 4A , a stress dielectric layer 205 of corresponding thickness can be deposited on the top metal layer 204 through any suitable deposition process such as atmospheric pressure chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The stress of the stress dielectric layer 205 is opposite to the stress of the top metal layer 204, thereby reducing the warpage of the wafer substrate 200 to a required range, thereby ensuring that the subsequent photolithography machine can normally grasp the wafer substrate 200, and avoiding the problem of photolithography machine grasping error and the risk of the wafer falling and breaking during the process of grasping the wafer substrate 200.

[0062] It should be understood that the material of the stress dielectric layer 205 can be any suitable material that can reduce the warpage of the wafer substrate 200 and enhance the adhesion between the subsequently formed passivation layer and the top metal layer 204, and will not bring other adverse effects to the manufacture and performance of the semiconductor integrated circuit. The present invention does not make any specific limitations on this.

[0063] As an example, the material of the stress dielectric layer 205 formed in this step S2 includes an oxide, which oxide includes, for example, at least one of doped or undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), and low-temperature silicon oxide formed in a temperature range of 0 to 500° C. (for example, below 100° C., below 200° C., below 300° C., or below 400° C.).

[0064] As an example, the stress of the stress dielectric layer 205 formed in step S2 is compressive stress, and the magnitude thereof is -200 MPa to -1000 MPa (eg, -300 MPa, -400 MPa, -500 MPa, -600 MPa, -700 MPa, -800 MPa, -900 MPa).

[0065] Among them, when depositing low-temperature silicon oxide to form the stress dielectric layer 205 in the temperature range of 0 to 500° C. (for example, 0 to 300° C.), it also has the following advantages: (1) the process is simple and low-cost, and it can generate sufficient compressive stress or pressure to offset the stress of the top metal layer 204, thereby achieving the desired effect of reducing the warpage of the wafer substrate 200; (2) the process temperature for forming the stress dielectric layer 205 is low, which will not have an adverse effect on the film layer and structure below the stress dielectric layer 205; (3) the formation of the stress dielectric layer 205 can better alleviate the difference in thermal expansion coefficient between the subsequently formed passivation layer and the top metal layer 204, so that in the subsequent process of etching open the passivation layer to form the contact pad, the passivation layers on both sides of the top of the contact pad are not likely to crack with the top metal layer, thereby ensuring the sealing.

[0066] In step S3, please continue to refer to Figure 4A A photoresist layer can be coated on the stressed dielectric layer 205 by spin coating or other methods, and the photoresist layer is subjected to a series of photolithography processes such as exposure and development to form a patterned photoresist 206. The photolithography pattern in the patterned photoresist 206 is used to define the required pattern in the topmost metal layer 204.

[0067] It should be understood that, since the stress dielectric layer 205 is formed on the topmost metal layer 204 in step S2, on the one hand, the compressive stress generated by the stress dielectric layer 205 can control the wafer warpage within the required range, so that the wafer warpage will not have a serious adverse effect on the photolithography process in step S3, thereby avoiding the distortion of the photolithographic pattern structure and the reduction of the yield in the patterned photoresist 206; on the other hand, the stress dielectric layer 205 can subsequently serve as a hard mask layer (hardmask) for etching the topmost metal layer 204, so that the coating thickness of the photoresist layer can be reduced in step S3, the coating time can be shortened, the photolithography cost can be reduced, and the photolithography effect can be improved. Furthermore, it can avoid the problems in the prior art of the photoresist being too thick and tilting and the photoresist being too thin and insufficient shielding when etching the topmost metal layer 204.

[0068] In step S4, please refer to Figure 4B Using the patterned photoresist 206 as a mask, the stressed dielectric layer 205 is etched by any suitable etching process until the top surface of the topmost metal layer 204 is exposed, thereby transferring the pattern in the patterned photoresist 206 to the stressed dielectric layer 205 .

[0069] In step S5, please refer to Figure 4B and Figure 4C First, the patterned photoresist 206 is removed by any suitable stripping process such as dry stripping or wet stripping; then, the top metal layer 204 is etched using the stressed dielectric layer 205 as a mask until the top surface of the interlayer dielectric layer below the top metal layer 204 or the top surface of the top conductive via TV is exposed, thereby forming a desired pattern (which may include a groove pattern or a through-hole pattern or a combination pattern of grooves and through-holes, etc.) in the top metal layer 204.

[0070] In this step S5, since the stressed dielectric layer 205 is used as a hard mask layer (hardmask) for etching the top metal layer 204, it is possible to ensure that the top metal layer 204 is fully and reliably blocked and etched, thereby ensuring the accuracy of the pattern formed in the top metal layer 204, thereby improving the circuit yield and reliability.

[0071] After the etching of the topmost metal layer 204 is completed, the manufacturing method of this embodiment may proceed to the subsequent corresponding steps.

[0072] As an example, please refer to Figure 3 The manufacturing method of this embodiment, after completing the above step S5, further includes:

[0073] S6, depositing a passivation layer on the stressed dielectric layer, the topmost metal layer and the wafer substrate;

[0074] S7, etching the passivation layer and the stressed dielectric layer to form an opening exposing a portion of the top metal layer, wherein the top metal layer exposed by the opening serves as a contact pad;

[0075] S8, performing corresponding metallization connection processes on the contact pad and the passivation layer to achieve connection between the contact pad and an external electrical structure.

[0076] In step S6, please refer to Figure 4D The passivation layer 207 can be deposited by any suitable deposition process, such as high-density plasma (HDP) chemical vapor deposition (CVD). The deposited passivation layer 207 can at least cover the sidewalls and bottom surface of the gap between the topmost metal layer 204 and the stressed dielectric layer 205, as well as the top surface of the stressed dielectric layer 205. In one example, the passivation layer 207 can completely fill the gap between the topmost metal layer 204 and the stressed dielectric layer 205 and bury the top surface of the stressed dielectric layer 205 therein. The top surface of the passivation layer 207 can be further planarized by a chemical mechanical polishing (CMP) process, so that the top surface is flat, thereby facilitating the implementation of subsequent processes.

[0077] The passivation layer 207 can be formed of any suitable dielectric material and can be a single layer or a stack of multiple layers, which is not specifically limited in the present invention. As an example, the passivation layer 207 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and polyimide. For example, the passivation layer 207 is a silicon nitride layer, or the passivation layer 207 is a composite structure such as an ON structure or an ONO structure formed by alternating layers of silicon oxide (O) and silicon nitride (N).

[0078] In step S7, please refer to Figure 4D First, a patterned photoresist layer (not shown) is formed through a series of photolithography processes, including photoresist coating, exposure, and development, to define the pattern of the contact pads. Then, using this patterned photoresist layer as a mask, the passivation layer 207 and the stressed dielectric layer 205 are etched until a plurality of openings (not labeled) are formed that expose a portion of the top surface of the topmost metal layer 204. Each opening exposes the topmost metal layer 204 as a contact pad 204a. The remaining patterned photoresist layer on the passivation layer 207 is then removed.

[0079] In step S7, on the one hand, in the process of etching and opening the passivation layer 207 and the stress dielectric layer 205 above the top of the contact pad 204a, the stress dielectric layer 205 can alleviate the problem of thermal expansion coefficient mismatch between the top metal layer 204 and the passivation layer 207, thereby avoiding the problem of cracking of the passivation layer 207 at the top corner of the contact pad 204a when the passivation layer 207 is etched and opened; on the other hand, after the passivation layer 207 and the stress dielectric layer 205 above the top of the contact pad 204a are etched and opened to form the contact pad 204a, the top corner of the contact pad 204a (such as Figure 4D The corresponding stressed dielectric layer 205 can be retained (i.e., remains) on the sidewalls of the opening (shown by the dotted circle in FIG). This allows the top corners of contact pad 204a to adhere to passivation layer 207 through stressed dielectric layer 205, achieving good adhesion at the top corners of contact pad 204a and ensuring sealing at the top corners of contact pad 204a. This prevents unnecessary corrosion at the top corners of the contact pad during subsequent removal of the remaining photoresist on the passivation layer and subsequent packaging processes, thereby ensuring circuit reliability and sealing. In this case, the top sidewalls of the opening for exposing contact pad 204a are the sidewalls of passivation layer 207, and the bottom sidewalls are the sidewalls of stressed dielectric layer 205.

[0080] In step S8, a corresponding metallization connection structure (not shown) is formed on the contact pad 204a and the surrounding passivation layer 207 through a suitable metallization connection process (e.g., a rewiring process, a ball implantation process, or a wire bonding process). The metallization connection structure connects the contact pad 204a to an external electrical structure. The metallization connection structure can be any suitable structure, such as a wire lead or a solder ball, and the external electrical structure can be any suitable structure, such as a PCB board or a functional module.

[0081] In summary, the semiconductor integrated circuit manufacturing method of this embodiment deposits a stress dielectric layer after depositing the top metal layer and before etching the top metal layer, thereby reducing the warpage of the wafer substrate to the required range. This facilitates the normal gripping of the wafer substrate by the subsequent photolithography machine, avoiding the risk of the photolithography machine being unable to grip the wafer or increasing the risk of the wafer falling and breaking during the gripping process due to excessive warpage of the wafer substrate. Furthermore, the etching between the stress dielectric layer and the photoresist is relatively large, and the stress dielectric layer can serve as a hard mask layer for etching the top metal layer. This helps reduce the coating thickness of the photoresist, solving the adverse problems caused by excessive photoresist tipping or insufficient photoresist thickness during etching of the top metal layer, thereby improving circuit yield and reliability. Furthermore, the presence of the stress dielectric layer makes the passivation layer less susceptible to cracking when etching the passivation layer to form the contact pad. Furthermore, the stress dielectric layer can be retained above the top corners of the formed contact pads, achieving good adhesion at the top corners of the contact pads and ensuring sealing at the top corners of the contact pads. The method for manufacturing a semiconductor integrated circuit of this embodiment can be applied to the manufacture of any semiconductor integrated circuit having a relatively thick or ultra-thick topmost metal layer.

[0082] Based on the same invention concept, please refer to Figure 4D An embodiment of the present invention further provides a semiconductor integrated circuit, which is preferably formed using the semiconductor integrated circuit manufacturing method of the present invention. The semiconductor integrated circuit includes: a wafer substrate 200 that has been processed accordingly, and a top metal layer 204, a stress dielectric layer 205, and a passivation layer 207 stacked in sequence.

[0083] The wafer substrate 200 may have undergone front-end device processing and front-end metal interconnection structure processing, and includes a base 200a, front-end devices formed on the base 200a, and a front-end metal interconnection structure formed above the layer where the front-end devices are located. The specific structures of the base 200a, the front-end devices, and the front-end metal interconnection structure can be found in the corresponding contents of step S1 above and will not be repeated here.

[0084] Illustratively, a front-end device and a front-end metal interconnect structure are formed in a wafer substrate 200, wherein the front-end device includes at least one of a MOS transistor, a capacitor, a resistor, an inductor, a diode, and a triode. The front-end metal interconnect structure includes an interlayer dielectric layer 203x, a multilayer metal interconnect layer Mx formed in the interlayer dielectric layer 203x, a conductive via Vx electrically connecting two corresponding metal interconnect layers in the multilayer metal interconnect layer Mx, a contact hole CT connecting the multilayer metal interconnect layer Mx and the front-end device, and a top conductive via TV connecting the multilayer metal interconnect layer Mx and the topmost metal layer 204. Optionally, each metal interconnect layer in the multilayer metal interconnect layer Mx is a copper interconnect layer.

[0085] The top metal layer 204 is formed on the wafer substrate 200 and has a desired pattern. Optionally, the top metal layer 204 includes metal materials such as copper, copper alloy, aluminum, or aluminum alloy.

[0086] The stressed dielectric layer 205 is formed on a portion of the top surface of the topmost metal layer 204, and the stress generated by the stressed dielectric layer 205 is opposite to the stress generated by the topmost metal layer 204, thereby reducing the warpage of the wafer substrate 200 to a desired range. As an example, the material of the stressed dielectric layer 205 includes at least one of undoped or doped silicate glass, tetraethyl orthosilicate, and low-temperature silicon oxide formed in a temperature range of 0 to 500° C. (e.g., below 100° C., below 200° C., below 300° C., or below 400° C.).

[0087] Optionally, the compressive stress generated by the stress dielectric layer 205 is -200 MPa to -1000 MPa (eg, -300 MPa, -400 MPa, -500 MPa, -600 MPa, -700 MPa, -800 MPa, -900 MPa).

[0088] The passivation layer 207 is formed on the stress dielectric layer 205, the top metal layer 204, and the wafer substrate 200 where the top metal layer 204 protrudes, and has corresponding multiple openings (not marked). Each opening penetrates the passivation layer 207 and the stress dielectric layer 205 and exposes a portion of the top surface of the top metal layer 204 to form a contact pad 204a.

[0089] Optionally, a stress dielectric layer 205 is retained on the bottom sidewalls of each opening so that the top corners of the contact pad 204a are still adhered to the passivation layer 207 through the stress dielectric layer 205, thereby achieving a good adhesion effect at the top corners of the contact pad 204a and ensuring the sealing of the top corners of the contact pad 204a.

[0090] Optionally, the material of the passivation layer 207 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and polyimide. The passivation layer 207 is silicon nitride to simplify the process and reduce the cost.

[0091] Optionally, the semiconductor integrated circuit of this embodiment further includes a metallized connection structure (not shown) formed on the contact pad 104a and the passivation layer 207 to connect the contact pad 207 to an external electrical structure. The metallized connection structure can be any suitable structure such as a lead or a solder ball, and the external electrical structure can be any suitable structure such as a PCB board or a functional module, which is not specifically limited in the present invention.

[0092] In the semiconductor integrated circuit of this embodiment, a stress dielectric layer is provided between the topmost metal layer and the passivation layer. This stress dielectric layer, having a stress opposite to that of the topmost metal layer, can be used to reduce the warpage of the semiconductor integrated circuit wafer to within a desired range. Furthermore, the stress dielectric layer can be used to alleviate the mismatch in thermal expansion coefficients between the topmost metal layer and the passivation layer, thereby preventing cracking of the passivation layer. Furthermore, the stress dielectric layer retained above the top corners of the contact pads achieves excellent adhesion at the top corners of the contact pads, ensuring sealing at the top corners of the contact pads, thereby improving circuit yield and reliability.

[0093] The semiconductor integrated circuit of this embodiment can be a memory circuit (such as random access memory RAM, dynamic random access memory DRAM, static random access memory SRAM, read-only memory ROM, etc.), a logic device circuit (such as programmable logic array PLA, application-specific integrated circuit ASIC, etc.), or a corresponding chip or circuit module of an electronic product (such as a personal computer, a portable computer, a game console, a cellular phone, a personal digital assistant, a video camera, a digital camera, a mobile phone, etc., especially a radio frequency electronic product).

[0094] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor integrated circuit, characterized in that: include: Providing a wafer substrate that has been processed accordingly, and depositing a topmost metal layer on the wafer substrate; Covering the topmost metal layer with a corresponding stress dielectric layer, wherein the stress of the stress dielectric layer is opposite to the stress of the topmost metal layer, so that the warpage of the wafer substrate is reduced to a required range; coating a photoresist layer on the stressed dielectric layer, and performing photolithography on the photoresist layer to form a patterned photoresist; Using the patterned photoresist as a mask, etching the stressed dielectric layer to the top surface of the topmost metal layer; The patterned photoresist is removed, and the topmost metal layer is etched using the stressed dielectric layer as a mask to form a desired pattern in the topmost metal layer.

2. The manufacturing method according to claim 1, wherein The material of the stress dielectric layer includes at least one of undoped or doped silicate glass, tetraethyl orthosilicate, and low-temperature silicon oxide formed in a temperature range of 0 to 500°C.

3. The manufacturing method according to claim 1, wherein: The stress of the stress medium layer is compressive stress, and the stress magnitude is -200 MPa to -1000 MPa.

4. The manufacturing method according to claim 1, wherein: Front-end devices and front-end metal interconnection structures are formed in the wafer substrate, wherein the front-end devices include at least one of MOS transistors, capacitors, resistors, inductors, diodes, and triodes, and the front-end metal interconnection structure includes an interlayer dielectric layer, a multilayer metal interconnection layer formed in the interlayer dielectric layer, a conductive via electrically connecting corresponding two metal interconnection layers in the multilayer metal interconnection layer, a contact hole connecting the multilayer metal interconnection layer and the front-end device, and a top conductive via connecting the multilayer metal interconnection layer and the topmost metal layer.

5. The manufacturing method according to claim 4, wherein: Each metal interconnect layer is a copper interconnect layer, and the top metal layer includes copper, copper alloy, aluminum or aluminum alloy.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that After forming a desired pattern in the topmost metal layer, the method further comprises: depositing a passivation layer on the stressed dielectric layer, the topmost metal layer, and the wafer substrate; Etching the passivation layer and the stress dielectric layer to form an opening exposing a portion of the top metal layer, wherein the top metal layer exposed by the opening serves as a contact pad; A corresponding metallization connection process is performed on the contact pad and the passivation layer to achieve connection between the contact pad and an external electrical structure.

7. The manufacturing method according to claim 6, wherein: The stress medium layer is retained on the bottom sidewall of each opening.

8. The manufacturing method according to claim 6, wherein: The passivation layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride and polyimide.

9. A semiconductor integrated circuit, characterized in that: include: Wafer substrates that have been processed accordingly; a topmost metal layer formed on the wafer substrate and having a desired pattern; a stressed dielectric layer formed on the topmost metal layer and having a stress opposite to that of the topmost metal layer, so as to reduce the warpage of the wafer substrate to a required range; A passivation layer is formed on the stress dielectric layer, the top metal layer and the wafer substrate and has corresponding openings. The openings penetrate the passivation layer and the stress dielectric layer and expose a portion of the top metal layer to form a contact pad.

10. The semiconductor integrated circuit according to claim 9, wherein: It also includes at least one of the following features: (1) The material of the stress dielectric layer includes at least one of undoped or doped silicate glass, tetraethyl orthosilicate, and low-temperature silicon oxide formed in a temperature range of 0 to 500° C.; (2) The stress of the stress medium layer is compressive stress, and the magnitude is -200 MPa to -1000 MPa; (3) A front-end device and a front-end metal interconnect structure are formed in the wafer substrate, wherein the front-end device includes at least one of a MOS transistor, a capacitor, a resistor, an inductor, a diode, and a triode, and the front-end metal interconnect structure includes an interlayer dielectric layer, a multilayer metal interconnect layer formed in the interlayer dielectric layer, a conductive via electrically connecting two corresponding metal interconnect layers in the multilayer metal interconnect layer, a contact hole connecting the multilayer metal interconnect layer and the front-end device, and a top conductive via connecting the multilayer metal interconnect layer and the topmost metal layer; (4) Each metal interconnect layer in the wafer substrate is a copper interconnect layer, and the top metal layer includes copper, copper alloy, aluminum or aluminum alloy; (5) The stress dielectric layer is retained on the bottom sidewall of each opening; (6) The passivation layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride and polyimide; (7) A metallized connection structure formed on the contact pad and the passivation layer to achieve connection between the contact pad and an external electrical structure.

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