Chip heat recovery device and preparation method thereof

Abstract

The present application provides a chip heat recovery device and its preparation method, belonging to the field of semiconductor technology. The chip heat recovery device comprises a heat-conducting layer, a thermoelectric material layer, a PN junction array layer, and an output layer, stacked sequentially on the back of the chip. The heat-conducting layer is used to conduct heat from the chip to the thermoelectric material layer, and the thermoelectric material layer is used to convert heat into electrical energy. The PN junction array layer includes a plurality of electrically isolated vertical PN junction units, each of which is used to conduct electricity under the action of the electrical energy of the thermoelectric material layer. The output layer includes a conductive unit connected to each vertical PN junction unit and electrically isolated from each other, and the conductive unit is used to output the current of each vertical PN junction unit. The chip heat recovery device of the present application is a passive heat recovery device that can effectively recover and utilize chip heat.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip heat recovery device and a preparation method thereof. Background Art

[0002] With the advancement of chip manufacturing technology, high-computing-power chips have become a key development direction in the semiconductor industry. However, high computing speeds also generate high heat. In the field of semiconductor power research, high-voltage devices such as high-voltage fast charging are currently a hot topic. Both high-computing-power and high-voltage chips generate more heat than traditional chips. Currently, research on chips focuses on heat dissipation, with little coverage of heat recovery.

[0003] Existing research on semiconductor chip heat management primarily focuses on heat dissipation technology. The principle involves digging heat dissipation holes in the silicon chip and using piezoelectric materials to generate high-frequency vibrations to activate and remove the heat source from the holes. Cooling air is introduced through one side, and the heat source is discharged through the other side, thereby reducing the chip temperature. Alternatively, channels are designed to allow cooling water to flow through the chip, allowing the cooling water to remove heat from the chip. However, existing technologies lack designs for chip heat recovery, resulting in chip heat being dissipated rather than utilized. Summary of the Invention

[0004] An object of the first aspect of the present invention is to provide a chip heat recovery device that can effectively recover and utilize chip heat.

[0005] Another object of the present invention is to reduce energy waste.

[0006] An object of the second aspect of the present invention is to provide a method for preparing the above-mentioned chip heat recovery device.

[0007] An embodiment of the present invention provides a chip heat recovery device, comprising a heat-conducting layer, a thermoelectric material layer, a PN junction array layer, and an output layer stacked in sequence on the back side of the chip, wherein the heat-conducting layer is used to conduct the heat of the chip to the thermoelectric material layer, and the thermoelectric material layer is used to convert the heat into electrical energy. The PN junction array layer includes a plurality of electrically isolated vertical PN junction units, each of which is used to conduct under the action of the electrical energy of the thermoelectric material layer. The output layer includes a conductive unit connected to each of the vertical PN junction units and electrically isolated from each other, and the conductive unit is used to output the current of each of the vertical PN junction units.

[0008] Furthermore, the heat-conducting layer covers the entire back surface of the chip and has a thermal conductivity greater than 100 W / m·K.

[0009] Furthermore, the material of the heat conducting layer includes one or more of SiC, GaN and AlN.

[0010] Furthermore, the thermoelectric material layer is made of bismuth telluride-based material.

[0011] Furthermore, the forward turn-on voltage of the vertical PN junction unit is any value between 0.2V and 1V.

[0012] In particular, an embodiment of the present invention further provides a method for preparing any of the above-mentioned chip heat recovery devices, comprising:

[0013] S10, providing a substrate, and preparing the PN junction array layer on the substrate;

[0014] S20, forming a thermoelectric material layer on a side of the PN junction array layer facing away from the substrate;

[0015] S30, forming a heat-conducting layer on a side of the thermoelectric material layer away from the PN junction array layer to form a first structure;

[0016] S40, inverting the first structure and removing the substrate bottom material until the PN junction array layer is exposed;

[0017] S50 , forming the output layer on the PN junction array layer.

[0018] Furthermore, step S10 includes:

[0019] Performing N-type ion implantation in the middle region of the substrate to form an N-type layer region;

[0020] Performing P-type ion implantation in the upper region of the substrate to form a P-type layer region in contact with the N-type layer region;

[0021] performing an annealing process on the substrate;

[0022] forming a plurality of first isolation trenches spaced apart in a horizontal direction on the substrate, each of the first isolation trenches passing through the P-type layer region and the N-type layer region;

[0023] An isolation material is deposited on the surface of the substrate to fill the first isolation trench, and a planarization process is performed until the surface of the P-type layer region to form a first isolation structure.

[0024] Furthermore, step S50 includes:

[0025] forming a first isolation layer, a protective layer and a photoresist layer in sequence on the PN junction array layer;

[0026] Photolithography, etching, and resist stripping are performed to form second isolation structures that are in contact with and correspond to each of the first isolation structures, and electrode trenches are formed between each of the second isolation structures;

[0027] A conductive structure is formed in the electrode groove.

[0028] Furthermore, after the step of forming a conductive structure in the electrode groove, the method further includes:

[0029] A pad layer is formed on the surface of the conductive structure. The pad layer includes a plurality of electrically isolated pads. Each pad contacts the conductive structure in each electrode groove.

[0030] Furthermore, after step S30, the following steps are included:

[0031] The heat-conducting layer is bonded to the back side of the chip to be cooled.

[0032] According to one aspect of the present invention, a chip heat recovery device is provided that effectively recovers chip heat and converts the heat into electrical energy for output, thereby achieving chip heat recovery and utilization. Furthermore, this device is a passive heat recovery device that does not require external power to recycle chip waste heat, thus saving energy.

[0033] Furthermore, in the chip heat recovery device, a vertical PN junction unit is set on the back of the chip. This vertical arrangement can locally have a high density of PN junction devices on the back of the chip, thereby achieving large current output and meeting large current usage scenarios.

[0034] According to the second aspect of the present invention, the present application also provides a method for preparing a chip heat recovery device. This method is highly compatible with existing semiconductor process technologies and is easy to implement. Combined with relatively mature thermoelectric materials, heat is converted into current through thermoelectric materials, thereby realizing the integration of a heat recovery device on the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 2 is a schematic structural diagram of a chip heat recovery device according to an embodiment of the present invention;

[0036] Figure 2 is a flow chart of a preparation method according to one embodiment of the present invention;

[0037] Figure 3 Schematic diagram of the steps of a preparation method according to one embodiment of the present invention.

[0038] Reference numerals:

[0039] 100-chip heat recovery device, 10-thermal conductive layer, 20-thermoelectric material layer, 30-PN junction array layer, 31-vertical PN junction unit, 40-output layer, 41-conductive unit, 200-chip, 300-external device, 310-interface, 1-substrate, 2-N-type layer region, 3-P-type layer region, 4-first photoresist mask, 5-through hole, 6-first isolation groove, 7-isolation material layer, 8-first isolation structure, 9-first isolation layer, 11-protective layer, 12-photoresist layer, 13-second photoresist mask, 14-second isolation groove, 15-electrode groove, 16-conductive material, 17-conductive structure, 18-pad, 19-package protection layer, 24-pad structure, 21-connection layer, 22-metal layer, 23-anti-reflection layer. DETAILED DESCRIPTION

[0040] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0041] It should be noted that when a component is referred to as being "fixed to" or "disposed on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may be a central component at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in the specification of this application are for illustrative purposes only and do not represent the only implementation method.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0043] In this application, unless otherwise expressly specified or limited, a first feature being “above” or “below” a second feature may mean that the first feature is directly in contact with the second feature, or that the first feature and the second feature are indirectly in contact through an intermediate medium. Furthermore, a first feature being “above,” “above,” or “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below,” “below,” or “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0044] Unless otherwise defined, all technical and scientific terms used in the specification of this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in the specification of this application includes any and all combinations of one or more of the relevant listed items.

[0045] Figure 1 FIG. 1 is a schematic structural diagram of a chip heat recovery device 100 according to an embodiment of the present invention. Figure 1 As shown, in one embodiment, a chip heat recovery device 100 includes a thermal conductive layer 10, a thermoelectric material layer 20, a PN junction array layer 30, and an output layer 40 stacked sequentially on the back side of a chip 200. The thermal conductive layer 10 is used to conduct heat from the chip 200 to the thermoelectric material layer 20, which is used to convert the heat into electrical energy. The PN junction array layer 30 includes a plurality of electrically isolated vertical PN junction units 31, for example, each vertical PN junction unit 31 is separated by an isolation structure made of silicon dioxide or silicon nitride. Each vertical PN junction unit 31 is used to conduct electricity under the action of the electrical energy of the thermoelectric material layer 20. The output layer 40 includes conductive units 41 connected to each vertical PN junction unit 31 and electrically isolated from each other. The conductive units 41 are used to output the current of each vertical PN junction unit 31.

[0046] The chip heat recovery device can be attached, welded, or connected to the back of chip 200 via a bonding process. Chip 200 is a chip that dissipates a lot of heat during operation, such as a high-computing chip, a chip equipped with certain high-voltage power devices (such as high-voltage fast charging), or a chip with high-temperature components such as a CPU, GPU, or TPU. To improve heat dissipation, in some embodiments, the chip can be thinned.

[0047] When the chip heat recovery device is in operation, the thermal conductive layer 10 transfers heat from the chip 200 to the thermoelectric material layer 20. The thermoelectric material layer 20, heated, generates a voltage that effectively conducts each vertical PN junction unit 31. The current from each vertical PN junction unit 31 is output through the conductive units 41 of the output layer 40. The output end of each conductive unit 41 can be connected to an external charging port 310. The charging port 310 can also be connected to some modulation circuit, such as a rectifier circuit, to achieve stable power output and power the external device 300, which can be a battery, thereby recovering and utilizing the chip heat. In this embodiment, the conductive unit 41 can include a first conductive layer, for example, made of copper, aluminum, gold, titanium, or an alloy. The conductive unit 41 can also be a composite structure, for example, comprising a first conductive layer, a connecting layer, and a second conductive layer. The second conductive layer can be made of aluminum, a commonly used pad material, to facilitate subsequent wire bonding or flip-chip packaging. The connecting layer is used to improve the connection stability between the two conductive materials, and can be made of, for example, Ti / TiN.

[0048] The chip heat recovery device of the present application is a passive heat recovery device that can recycle chip waste heat without the need for external power supply, thereby saving energy.

[0049] The forward turn-on voltage of the vertical PN junction unit 31 is adjusted by doping and / or modulation, for example, by ion implantation and annealing of the Ge substrate material to modulate the forward turn-on voltage to a value between 0.2V and 1V. By selecting the material of the thermoelectric material layer 20, a voltage sufficient to turn on each vertical PN junction unit 31 can be generated under a preset temperature. For example, a bismuth telluride-based material can be used to prepare the thermoelectric material layer 20. The bismuth telluride-based material can be a bismuth telluride superlattice material, a nanocomposite material of bismuth telluride and other materials (such as carbon nanotubes or graphene), a bismuth-antimony (Bi-Sb) alloy, a silicon-germanium (SiGe) alloy, or a tellurium-lead alloy. Generally, a voltage of 0.5V to 1V can be achieved when heated.

[0050] To more efficiently conduct heat away from chip 200, thermal conductive layer 10 can be made of a wide-bandgap semiconductor material with high thermal conductivity. In one embodiment, the thermal conductivity is greater than 100 W / m·K. For example, thermal conductive layer 10 can be made of one or more of SiC, GaN, and AlN, thereby conducting heat quickly and efficiently. Furthermore, thermal conductive layer 10 is spread across the entire backside of chip 200, ensuring a larger contact area and allowing for greater heat dissipation.

[0051] In some application scenarios, in order to achieve better heat dissipation effect, holes are opened on the back of the chip 200 to be cooled. At this time, these openings are in direct contact with the chip heat recovery device 100. When the thermal and electrical effects are superimposed, leakage may occur. The thermal conductive layer 10 is made of wide bandgap semiconductor material so that it can not only play a role in heat conduction, but also suppress the leakage current of the chip.

[0052] Figure 2 Flowchart of a preparation method according to one embodiment of the present invention. Figure 3 This application also provides a method for preparing the chip heat recovery device 100 in the above embodiment. Figure 2 As shown, in one embodiment, the preparation method includes the following steps:

[0053] S10, providing a substrate 1, and preparing a PN junction array layer 30 on the substrate 1;

[0054] S20, forming a thermoelectric material layer 20 on a side of the PN junction array layer 30 facing away from the substrate 1;

[0055] S30, forming a heat conducting layer 10 on a side of the thermoelectric material layer 20 away from the PN junction array layer 30, to form a first structure;

[0056] S40, inverting the first structure and removing the bottom surface material of the substrate 1 until the PN junction array layer 30 is exposed;

[0057] S50 , forming an output layer 40 on the PN junction array layer 30 .

[0058] In one embodiment, Figure 3 As shown, step S10 includes:

[0059] S11, providing a substrate 1;

[0060] In this embodiment, Figure 3 As shown in a, a P-type germanium (Ge) substrate is first provided. In other embodiments, the substrate 1 may also be an undoped single crystal germanium substrate, or a doped / undoped silicon substrate, which is not limited here.

[0061] S12, performing N-type ion implantation in the middle region of the substrate 1 to form an N-type layer region 2;

[0062] S13, performing P-type ion implantation in the upper region of the substrate 1 to form a P-type layer region 3 in contact with the N-type layer region 2;

[0063] In this embodiment, the N-type layer region 2 (eg, Figure 3 b) and P-type layer region 3 (such as Figure 3In other embodiments, the N-type layer region 2 and the P-type layer region 3 may be formed by, for example, a diffusion process or an epitaxial process, which is not limited here.

[0064] The ion implantation process used in this embodiment can precisely control the implantation energy and doping dose, conveniently adjust the penetration depth and doping concentration of the impurity ions, and thus prepare a high-performance vertical PN junction unit 31 , which is more in line with the design requirements of device miniaturization.

[0065] It should be noted that the middle region in step S12 refers to a region that is at a certain distance from the bottom and surface of the substrate 1 , and the upper region is the region between the middle region and the surface of the substrate 1 .

[0066] Step S14, performing annealing treatment on the substrate 1;

[0067] The annealing process may be rapid thermal annealing or furnace high temperature annealing, etc. By performing the annealing process on the substrate 1, lattice damage can be repaired and impurity ions can be activated.

[0068] Step S15 , forming a plurality of first isolation trenches 6 spaced apart in a horizontal direction on the substrate 1 , each isolation trench passing through the P-type layer region 3 and the N-type layer region 2 ;

[0069] Specifically, a first photoresist layer 12 is formed on the surface of the substrate 1 by a spin coating process; the first photoresist layer 12 is then patterned (including exposure, development, etc.) to form a first photoresist mask 4. Figure 3 As shown in d; then use the photoresist mask as an etching mask, through the etching process, etch the P-type layer region 3 and the N-type layer region 2 in sequence, and stop at a position at a certain distance from the bottom surface of the substrate 1 to form a through hole 5. The result is as shown in Figure 3 As shown in e.

[0070] The etching process of this step can generally adopt a dry etching process. After forming the through hole 5, the substrate 1 is subjected to a degumming process to remove the first photoresist mask 4 remaining on the surface and to a cleaning process to obtain the first isolation groove 6. The result is as follows: Figure 3 As shown in f.

[0071] In step S16 , an isolation material is deposited on the surface of the substrate 1 to fill the first isolation trench 6 , and a planarization process is performed until the surface of the P-type layer region 3 is reached to form a first isolation structure 8 .

[0072] like Figure 3 As shown in g and h in FIG, an isolation material is deposited on the surface of the substrate 1 through a deposition process to fill the first isolation trench 6 , and then a planarization process is performed until the upper surface of the P-type layer region 3 .

[0073] Specifically, the isolation material is first deposited on the surface of the substrate 1 by a plasma enhanced vapor deposition process, the isolation material fills the first isolation groove 6 and forms an isolation material layer 7 on the surface of the substrate 1. Figure 3 Then, a chemical mechanical polishing (CMP) process is performed on the surface of the substrate 1 to remove excess isolation material until the surface of the P-type layer region 3 is reached, as shown in FIG. Figure 3 Thus, a PN junction array structure consisting of a plurality of vertical PN junction units 31 is prepared in the substrate 1, forming a PN junction array layer 30.

[0074] In this embodiment, the isolation material is silicon oxide. In other embodiments, the isolation material may also be silicon nitride. In other embodiments, other deposition processes may be used to form the isolation material layer 7, such as chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy.

[0075] In step S20, refer to Figure 3 As shown in FIG. 1 , in this embodiment, a thermoelectric material is deposited on the surface of the P-type layer region 3 by a magnetron sputtering process to form a thermoelectric material layer 20 .

[0076] In order to make the formation process of the passive heat recovery device compatible with the integrated circuit process, in this embodiment, a magnetron sputtering process is used to form the thermoelectric material layer 20; in other embodiments, other physical deposition processes can also be selected according to actual conditions.

[0077] In step S30, refer to Figure 3 As shown in FIG. 1 , in this embodiment, a heat-conducting material is deposited on the surface of the thermoelectric material layer 20 by a chemical vapor deposition process to form a heat-conducting layer 10 . The heat-conducting layer 10 is used to contact the back surface of the chip 200 .

[0078] Before step S40, the method further includes:

[0079] Step S35 , bonding the heat conducting layer 10 to the back surface of the chip 200 to be cooled.

[0080] In order to better dissipate the heat of the chip, it is necessary to ensure that the chip 200 and the surface of the passive heat recovery device, that is, the surface of the heat conducting layer 10, are well bonded. This can be achieved by, for example, soldering or bonding. If necessary, the chip 200 can also be thinned as needed to accelerate heat dissipation. In this embodiment, the chip 200 and the passive heat recovery device are bonded by a thermal compression bonding process. The result is shown in FIG. Figure 3 As shown in k.

[0081] In step S40, Figure 3As shown in FIG1, the first structure is flipped over so that the bottom surface of the substrate 1 faces upward; then chemical mechanical polishing is performed to remove part of the material on the bottom surface of the substrate 1, and then cleaning is performed to expose the PN junction array layer 30. The result is shown in FIG1. Figure 3 As shown in m.

[0082] Step S50 of forming the output layer 40 includes:

[0083] Step S51 , forming a first isolation layer 9 , a protection layer 11 and a photoresist layer 12 in sequence on the PN junction array layer 30 ;

[0084] Step S52 , photolithography, etching, and resist stripping are performed to form second isolation structures that contact and correspond to each first isolation structure 8 , and electrode trenches 15 are formed between each second isolation structure;

[0085] Step S53, forming a conductive structure 17 in the electrode groove 15;

[0086] Specifically, an isolation material, a protective material and a photoresist are sequentially deposited on the PN junction array layer 30 to form a Figure 3 The first isolation layer 9, protective layer 11 and photoresist layer 12 shown in FIG. 1 can be made of commonly used isolation materials such as silicon oxide or silicon nitride. The material of the protective layer 11 can be silicon nitride, silicon oxide, etc., which controls the end position of the pattern transfer to prevent the photoresist from damaging the underlying structure during etching or stripping. The photoresist layer 12 is then photolithographically processed to form a second photoresist mask 13. The result is shown in FIG. Figure 3 Then the protective layer 11 and the first isolation layer 9 are etched to form a second isolation groove 14. Figure 3 Finally, the photoresist is removed and wet cleaning is performed to remove the residual photoresist and etching residues to form the electrode groove 15. Figure 3 As shown in q in FIG, the structure after the electrode groove 15 is completed is referred to as the second structure.

[0087] In this embodiment, the conductive material 16 is copper, and its formation process includes: depositing a barrier layer and a copper seed layer on the surface of the electrode groove 15 provided in the second structure in sequence, and then depositing copper metal through an electrochemical plating process to fill the electrode groove 15. The result is as follows: Figure 3 Finally, by chemical mechanical polishing, the excess copper material, copper seed layer and barrier layer on the surface of the second structure are removed to obtain a conductive structure 17. Figure 3 As shown in s in FIG, the structure after the conductive structure 17 is formed is referred to as the third structure. In this embodiment, the conductive structure 17 is the conductive unit 41 mentioned above.

[0088] After step S53, the method further includes:

[0089] In step S54 , a pad layer is formed on the surface of the conductive structure 17 . The pad layer includes a plurality of electrically isolated pads 18 . Each pad 18 contacts the conductive structure 17 in each electrode groove 15 .

[0090] Step S54, the pad-out process, electrically connects the internal conductive structure 17 to the topmost pads 18 through the pad layer, ensuring good solderability or bonding (e.g., aluminum wire bonding) for subsequent package connection. In this embodiment, the pads 18 are made of aluminum. In this embodiment, the conductive structure 17 and pads 18 constitute the aforementioned conductive unit 41.

[0091] Generally, the process of the pad lead-out process is: depositing a connection layer 21, a metal layer 22 and an anti-reflection layer 23 on the surface of the third structure in sequence. In this embodiment, the material of the connection layer is Ti / TiN, the material of the metal layer is Al, and the material of the anti-reflection layer is Ti / TiN. The connection layer 21 is used to increase the interface bonding force between the metal layer 22 and the conductive structure 17, play a role in increasing adhesion, and can also prevent copper elements from diffusing into the aluminum layer and affecting the structural stability of the metal layer 22. The anti-reflection layer 23 can protect the metal layer 22 during the photolithography process. The anti-reflection layer 23 can also reduce the reflectivity and avoid the problem of reduced photolithography accuracy caused by the reflection of the metal layer 22 during photolithography; then, a pad structure 24 for connecting to the conductive structure 17 is formed through photolithography and etching processes, and degumming and cleaning are performed. The results are as shown in FIG. Figure 3 Finally, an oxide layer and a nitride layer are deposited in sequence. In this embodiment, the oxide layer material is SiO2, and the nitride layer material is SiN. Then, photolithography, etching, degumming, cleaning and other steps are performed to form a packaging protection layer 19 and expose the metal layer 22. The result is as shown in FIG. Figure 3 As shown in u in the figure, each pad 18 is isolated and the surface area of ​​the product where no pad 18 is set is protected.

[0092] In another embodiment, step S35 may also be performed after forming the pad 18 , which is not limited here.

[0093] The above-described embodiments merely illustrate several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A chip heat recovery device, characterized in that: It includes a heat-conducting layer, a thermoelectric material layer, a PN junction array layer and an output layer stacked in sequence on the back side of the chip, wherein the heat-conducting layer is used to conduct the heat of the chip to the thermoelectric material layer, and the thermoelectric material layer is used to convert the heat into electrical energy. The PN junction array layer includes a plurality of electrically isolated vertical PN junction units, each of which is used to conduct under the action of the electrical energy of the thermoelectric material layer. The output layer includes a conductive unit connected to each of the vertical PN junction units and electrically isolated from each other, and the conductive unit is used to output the current of each vertical PN junction unit.

2. The chip heat recovery device according to claim 1, characterized in that: The heat-conducting layer covers the entire back surface of the chip and has a thermal conductivity greater than 100 W / m·K.

3. The chip heat recovery device according to claim 1, characterized in that: The material of the heat conducting layer includes one or more of SiC, GaN and AlN.

4. The chip heat recovery device according to claim 1, characterized in that: The thermoelectric material layer adopts bismuth telluride-based material.

5. The chip heat recovery device according to claim 1, characterized in that: The forward turn-on voltage of the vertical PN junction unit is any value between 0.2V and 1V.

6. A method for preparing the chip heat recovery device according to any one of claims 1 to 5, characterized in that: include: S10, providing a substrate, and preparing the PN junction array layer on the substrate; S20, forming a thermoelectric material layer on a side of the PN junction array layer facing away from the substrate; S30, forming a heat-conducting layer on a side of the thermoelectric material layer away from the PN junction array layer to form a first structure; S40, inverting the first structure and removing the substrate bottom material until the PN junction array layer is exposed; S50 , forming the output layer on the PN junction array layer.

7. The preparation method according to claim 6, characterized in that Step S10 includes: Performing N-type ion implantation in the middle region of the substrate to form an N-type layer region; Performing P-type ion implantation in the upper region of the substrate to form a P-type layer region in contact with the N-type layer region; performing an annealing process on the substrate; forming a plurality of first isolation trenches spaced apart in a horizontal direction on the substrate, each of the first isolation trenches passing through the P-type layer region and the N-type layer region; An isolation material is deposited on the surface of the substrate to fill the first isolation trench, and a planarization process is performed until the surface of the P-type layer region to form a first isolation structure.

8. The preparation method according to claim 7, characterized in that Step S50 includes: forming a first isolation layer, a protective layer and a photoresist layer in sequence on the PN junction array layer; Photolithography, etching, and resist stripping are performed to form second isolation structures that are in contact with and correspond to each of the first isolation structures, and electrode trenches are formed between each of the second isolation structures; A conductive structure is formed in the electrode groove.

9. The preparation method according to claim 8, characterized in that After the step of forming a conductive structure in the electrode groove, the method further includes: A pad layer is formed on the surface of the conductive structure. The pad layer includes a plurality of electrically isolated pads. Each pad contacts the conductive structure in each electrode groove.

10. The preparation method according to any one of claims 6 to 9, characterized in that: Step S30 and subsequent steps include: The heat-conducting layer is bonded to the back side of the chip to be cooled.

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