Charging and discharging circuit, charging and discharging method, display screen and electronic equipment

Abstract

The invention discloses a charging and discharging circuit, a charging and discharging method, a display screen and electronic equipment, and belongs to the technical field of display. The charging and discharging circuit comprises at least one load capacitor, at least one preprocessing circuit, a current mirror circuit, a compensation circuit and at least one switching circuit. Each preprocessing circuit is correspondingly connected with a load capacitor, the preprocessing circuit can adjust the voltage of the corresponding load capacitor to a reference voltage, the current mirroring circuit can mirror a reference current source and output the reference current source through at least one branch, and each output branch is connected between the preprocessing circuit and the load capacitor through a switching circuit. The compensation circuit can compensate the charging or discharging time of the load capacitor, and the switching circuit can control the charging or discharging time of the load capacitor. According to the array substrate, all column load capacitors can be charged or discharged in a short time, meanwhile, charging and discharging are compensated, the difference between different pixel columns can be compensated, and the image display quality is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a charge and discharge circuit, a charge and discharge method based on the charge and discharge circuit, a display screen having the charge and discharge circuit, and an electronic device having the display screen. Background Art

[0002] Display screens are increasingly used as interfaces for human-computer interaction, encompassing a wide range of applications, including but not limited to smartphones, tablets, laptops, televisions, and desktop monitors. In a display screen, each pixel unit corresponds to a pixel circuit. This circuit is located at the intersection of scan lines (row-wise, supplying control signals) and data lines (column-wise, supplying data signals) to drive the corresponding pixel unit to display an image. During image display, the capacitors in the pixel circuits need to be charged so that they can control the light-emitting element during the light-emitting phase.

[0003] With the continuous development of display technology, the resolution and refresh rate of display screens are also constantly increasing. For example, some displays have a resolution of 4K and a refresh rate of 120Hz. However, as the resolution and refresh rate of display screens continue to increase, the number of pixel units increases dramatically. Some displays need to charge the capacitors of the pixel circuits corresponding to all pixel units in a time as short as a few microseconds. How to charge the capacitors in all pixel circuits in such a short time so that the capacitor voltage meets actual usage requirements is an urgent problem that needs to be solved.

[0004] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0005] An object of the present invention is to provide a charge and discharge circuit that can charge or discharge capacitors in all column pixel circuits in a short time, so that the voltage of the capacitors meets actual usage requirements.

[0006] Another object of the present invention is to provide a charging and discharging method, which can charge or discharge the capacitors in all column pixel circuits in a short time, so that the voltage of the capacitors meets actual usage requirements.

[0007] Another object of the present invention is to provide a display screen and an electronic device, which can charge or discharge the capacitors in all column pixel circuits in a short time so that the voltage of the capacitors meets actual usage requirements.

[0008] To achieve the above object, an embodiment of the present invention provides a charge and discharge circuit, comprising

[0009] at least one load capacitor;

[0010] at least one pre-processing circuit, each of the pre-processing circuits corresponding to one of the load capacitors, the pre-processing circuit being connected to the corresponding load capacitor to form a connection point, the pre-processing circuit being configured to adjust the voltage of the corresponding load capacitor to a reference voltage value;

[0011] a current mirror circuit, the current mirror circuit being configured to mirror a reference current source and output the current through at least one output branch, each output branch corresponding to one of the connection points;

[0012] At least one switching circuit, each switching circuit corresponds to one output branch, each output branch is connected to the corresponding connection point through the corresponding switching circuit, and the switching circuit is used to control the charging or discharging time of the load capacitance.

[0013] In one or more embodiments of the present invention, each of the pre-processing circuits is controlled by a same control signal to adjust the voltage of the corresponding load capacitor to a reference voltage value.

[0014] In one or more embodiments of the present invention, each switch circuit is controlled to be turned on or off by a different control signal.

[0015] In one or more embodiments of the present invention, the pre-processing circuit includes

[0016] Reference voltage source;

[0017] The first MOS transistor has a source terminal connected to a reference voltage source, a drain terminal connected to the load capacitor to form the connection point, and a gate terminal connected to a control signal.

[0018] In one or more embodiments of the present invention, the current mirror circuit includes

[0019] The second MOS transistor has a drain terminal connected to a reference current source, a source terminal connected to a voltage source or ground, and a gate terminal connected to a drain terminal;

[0020] At least one third MOS transistor, each third MOS transistor has a drain terminal serving as an output branch, a source terminal commonly connected to a voltage source or ground, and a gate terminal connected to the gate terminal of the second MOS transistor.

[0021] In one or more embodiments of the present invention, the second MOS transistor and the third MOS transistor are PMOS transistors or NMOS transistors.

[0022] In one or more embodiments of the present invention, the switching circuit includes

[0023] The fourth MOS transistor has a source terminal connected to the output branch, a drain terminal connected to the connection point, and a gate terminal connected to the control signal.

[0024] In one or more embodiments of the present invention, the compensation circuit includes

[0025] Detection resistor;

[0026] A plurality of calibration circuits, each corresponding to a pixel column, and each calibration circuit is connected to a voltage source or ground via a detection resistor to form a detection point, each calibration circuit is used to receive pixel data and convert the corresponding pixel data into a reference current and a calibration current and input them into the detection resistor;

[0027] At least one detection circuit is used to obtain a reference voltage and a calibration voltage at a detection point according to a reference current and a calibration current, respectively, and adjust pixel data according to the reference voltage and the calibration voltage.

[0028] In one or more embodiments of the present invention, all pixel columns share a detection circuit.

[0029] In one or more embodiments of the present invention, the calibration circuit includes

[0030] a fifth MOS transistor, connected in series with the detection resistor between the voltage source and the ground;

[0031] a first switch, one end of which is connected to a reference voltage, and an opposite end of which is connected to a gate terminal of a fifth MOS transistor;

[0032] a second switch, one end of which is connected to the data voltage of the pixel column, and the opposite end of which is connected to the gate end of the fifth MOS transistor;

[0033] a third switch, one end of which is connected to a voltage source, and an opposite end of which is connected to a gate terminal of the fifth MOS transistor;

[0034] The switch control circuit is connected to the first switch, the second switch and the third switch, and is used to control the first switch, the second switch and the third switch to be closed or opened according to the pixel data.

[0035] In one or more embodiments of the present invention, the switch control circuit is a logic circuit composed of gate-level circuits, whose inputs are calibration_mode0, calibration_mode1 and data[M], and whose outputs are Q1, Q2, and Q3. Q1, Q2, and Q3 respectively control the closing or opening of the first switch, the second switch, and the third switch, wherein calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit value of the grayscale value corresponding to the pixel column.

[0036] In one or more embodiments of the present invention, the switching circuit controls the charging or discharging time of the load capacitor including:

[0037] During charging or discharging, the M-bit counter counts from 0 to 2. M -1 counts the charging or discharging time, and when the counter counts from zero to the grayscale value corresponding to a column of pixels, the switch circuit corresponding to the column of pixels is disconnected, M is the color depth of the display, and M is an integer greater than 0.

[0038] In one or more embodiments of the present invention, the current of each output branch is the same as or proportional to a reference current source.

[0039] An embodiment of the present invention provides a charge and discharge method, comprising:

[0040] Each pre-processing circuit adjusts the voltage of the corresponding load capacitor to a reference voltage value;

[0041] The current mirror circuit mirrors the reference current source and outputs the current through at least one output branch to charge or discharge the load capacitor;

[0042] The compensation circuit compensates for the charging or discharging time of the load capacitance;

[0043] The switching circuit controls the charging or discharging time of the load capacitor.

[0044] In one or more embodiments of the present invention, the charging or discharging time is compensated by the following steps:

[0045] Selecting a reference voltage from the ramp voltage;

[0046] Discharging each pixel column from the maximum value of the ramp voltage, or charging each pixel column from the minimum value of the ramp voltage, and determining the pixel column with the slowest discharge or charge;

[0047] Performing time calibration on the pixel column that discharges or charges the slowest, and determining time offset values corresponding to the remaining pixel columns based on the time of the pixel column that discharges or charges the slowest;

[0048] The actual charging or discharging time is obtained by subtracting the corresponding time offset from the discharge or charging time of each pixel column.

[0049] In one or more embodiments of the present invention, selecting a reference voltage from the ramp voltage includes:

[0050] During discharge, a voltage close to the minimum value of the ramp voltage is selected as the reference voltage. During charge, a voltage close to the maximum value of the ramp voltage is selected as the reference voltage. M is the color depth of the display.

[0051] In one or more embodiments of the present invention, the time calibration of the slowest discharging pixel column includes:

[0052] (a) Discharge all pixel columns for a discharge time of

[0053] (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles;

[0054] (b) Determine the pixel column with the slowest discharge and discharge the pixel column simultaneously by adjusting the reference current source of the current mirror circuit. The discharge time is

[0055] (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles;

[0056] (c) Determine whether the data voltage of the pixel column is the same as the reference voltage. If they are the same, the discharge time of the pixel column with the slowest discharge is (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles, otherwise, continue to adjust the reference current source and discharge (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles until the data voltage is the same as the reference voltage,

[0057] Among them, M is the color depth of the display, V H Maximum ramp voltage, V L is the minimum value of the ramp voltage, V cal is the reference voltage.

[0058] In one or more embodiments of the present invention, the time calibration of the slowest charging pixel column includes:

[0059] (a) Charge all pixel columns, the charging time is

[0060] (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles;

[0061] (b) Determine the pixel column with the slowest charging time and charge the pixel column simultaneously by adjusting the reference current source of the current mirror circuit. The charging time is

[0062] (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles;

[0063] (c) Determine whether the data voltage of the pixel column is the same as the reference voltage. If they are the same, the charging time of the slowest charging pixel column is (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles, otherwise, continue to adjust the reference current source and charge (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles until the data voltage is the same as the reference voltage,

[0064] Among them, M is the color depth of the display, V H Maximum ramp voltage, V L is the minimum value of the ramp voltage, V cal is the reference voltage.

[0065] In one or more embodiments of the present invention, the time offset value is obtained by the following steps:

[0066] (a) Based on the time it takes for the pixel column that discharges or charges the slowest to discharge or charge to the reference voltage, determine the time it takes for the pixel column that discharges or charges the slowest to go from the maximum value of the ramp voltage to the minimum value or from the minimum value of the ramp voltage to the maximum value.

[0067] T max *P w =T' max *P w *(2 M -1) / G cal

[0068] The time taken by the remaining pixel columns to change from the maximum value to the minimum value of the ramp voltage or from the minimum value to the maximum value of the ramp voltage is

[0069] T k *P w =T' k *P w *(2 M -1) / Gcal

[0070] (b) The remaining pixel columns are related to the pixel column with the slowest discharge or charge. Cycle offset value for

[0071] △T k =(T' max -T' k )*(2 M -1) / G cal

[0072] (c) determining the time offset value of each pixel column by the cycle number offset value and the cycle time length of each pixel column,

[0073] Where T is the number of clock cycles, P w is the clock cycle length, M is the display color depth, G cal is the grayscale value corresponding to the reference voltage Vcal.

[0074] An embodiment of the present invention provides a display screen including the above-mentioned charging and discharging circuit.

[0075] An embodiment of the present invention provides an electronic device including the display screen described above.

[0076] Compared to existing technologies, the present invention can rapidly charge or discharge the capacitors of all pixel circuits in each column, ensuring that the capacitor voltages meet actual usage requirements. Furthermore, the capacitors in each column of pixel circuits are independently controlled with constant current during charging or discharging, preventing cross-column interference. Furthermore, by compensating for charging and discharging, differences between pixel columns can be compensated, improving image display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 is a schematic structural diagram of a charge and discharge circuit according to one embodiment of the present invention;

[0078] Figure 2 is a circuit diagram of a charge and discharge circuit according to one embodiment of the present invention;

[0079] Figure 3 is a circuit diagram of a charge and discharge circuit according to another embodiment of the present invention;

[0080] Figure 4 is a circuit diagram of a charge and discharge time control circuit according to an embodiment of the present invention;

[0081] Figure 5 is a schematic diagram of the structure of a compensation circuit according to an embodiment of the present invention;

[0082] Figure 6is a circuit diagram of a compensation circuit according to an embodiment of the present invention;

[0083] Figure 7 is a compensation circuit diagram according to another embodiment of the present invention;

[0084] Figure 8 is a schematic diagram of a ramp voltage according to an embodiment of the present invention;

[0085] Figure 9 FIG. 4 is a schematic diagram of a ramp voltage according to another embodiment of the present invention. DETAILED DESCRIPTION

[0086] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0087] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0088] like Figures 1 to 4 As shown, a charging and discharging circuit according to a preferred embodiment of the present invention can quickly charge or discharge the capacitors of all pixel circuits in each column so that the voltage of the capacitors meets the actual usage requirements, and the capacitors of the pixel circuits in each column are independent of each other and do not interfere with each other during charging or discharging.

[0089] Specifically, combined Figures 1 to 7 As shown, the charge-discharge circuit includes at least one load capacitor, at least one pre-processing circuit 10, a current mirror circuit 20, a compensation circuit, and at least one switch circuit 30. The load capacitor is used to store charge. The load capacitor here is the equivalent load capacitor of all pixel circuits in each column. Therefore, the number of load capacitors can be determined according to the number of columns.

[0090] The preprocessing circuit 10 corresponds to the load capacitor one-to-one, that is, each preprocessing circuit 10 corresponds to a load capacitor, and the preprocessing circuit 10 is connected to the corresponding load capacitor to form a connection point A. The preprocessing circuit 10 can adjust the voltage value of the load capacitor to a preset value, such as by charging the load capacitor to adjust the voltage value of the load capacitor to a preset value, or by discharging the load capacitor to adjust the voltage value of the load capacitor to a preset value, which can be selected according to actual needs.

[0091] The current mirror circuit 20 is used to mirror a reference current source and output it through at least one output branch to provide a current proportional to the reference current source. The output branches correspond one-to-one with the connection point A, or one-to-one with the load capacitor. The ratio includes, but is not limited to, 1:1 and can be adjusted based on actual needs.

[0092] The compensation circuit is used to compensate for the charging or discharging time of the capacitor of each pixel column, so as to compensate for the difference between different pixel columns and improve the display effect.

[0093] The switch circuits 30 correspond one-to-one with the output branches. Each output branch is connected to the corresponding connection point A via a corresponding switch circuit 30. That is, the switch circuit 30 is connected between the connection point A and the output branch. The switch circuit 30 can control the charge or discharge time of the load capacitor so that the voltage value of the load capacitor reaches the actual desired voltage value. The charge or discharge time here refers to the time it takes for the load capacitor to reach the actual desired voltage value from the current voltage value.

[0094] In a specific implementation, the pre-processing circuit 10 first charges or discharges the corresponding load capacitor to make its voltage reach a preset value, and the switch circuit 30 is in a disconnected state during the process of the pre-processing circuit 10 charging or discharging the load capacitor.

[0095] When the voltage across the load capacitor reaches a preset value, current mirror circuit 20 begins operating, mirroring the reference current source and outputting a current proportional to the reference current source through the output branch. Simultaneously, switch circuit 30 is closed. Due to the current flowing through the output branch, the voltage across the load capacitor continuously decreases or increases from the preset value, effectively discharging or charging the load capacitor.

[0096] When the charge or discharge time of the load capacitor is reached, the switch circuit 30 is in the off state. At this time, there is no current in the loop, so the voltage of the load capacitor no longer drops or rises. At this time, the voltage value of the load capacitor is the required voltage value.

[0097] Combine Figure 2 and Figure 3 As shown, the preprocessing circuit 10 includes a reference voltage source and a first MOS transistor. The gate terminal of the first MOS transistor is connected to a control signal, the source terminal is connected to the reference voltage source, and the drain terminal is connected to a corresponding load capacitor, forming a connection point A. In a specific implementation, the control signal controls the first MOS transistor to conduct, electrically connecting the reference voltage source and the load capacitor. The voltage value of the load capacitor can then be adjusted to the same voltage value as the reference voltage source by charging or discharging.

[0098] In this embodiment, all pre-processing circuits 10 are controlled by the same control signal, so that the pre-processing circuit 10 adjusts the voltage value of the corresponding load capacitor to a preset value, such as Figure 2 As shown, the gate terminals of all first MOS transistors are controlled by the control signal S0. Of course, in other embodiments, they can also be controlled individually, which can be selected according to actual needs.

[0099] Combine Figure 2 and Figure 3 As shown, the current mirror circuit 20 includes a second MOS transistor and at least one third MOS transistor. The drain terminal of each second MOS transistor is connected to a reference current source, the source terminal is connected to a voltage source or ground, and the gate terminal is connected to the drain terminal. The drain terminal of each third MOS transistor serves as an output branch for the output current. The source terminal is commonly connected to a voltage source or ground, and the gate terminal is connected to the gate terminal of each second MOS transistor. The second MOS transistor and a third MOS transistor can form a basic current mirror to mirror the reference current source to the corresponding output branch.

[0100] In this embodiment, the second MOS transistor and the third MOS transistor are either PMOS transistors or NMOS transistors, and can be selected according to actual needs.

[0101] Combine Figure 2 and Figure 3 As shown, the switch circuit 30 includes a fourth MOS transistor, which can be either a PMOS transistor or an NMOS transistor. The source terminal of the fourth MOS transistor is connected to the corresponding output branch, the drain terminal is connected to the corresponding connection point A, and the gate terminal is connected to the control signal. In a specific implementation, the control signal turns on the fourth MOS transistor, thereby forming a loop between the output branch and the corresponding load capacitor. This generates a current in the loop, and the voltage value of the load capacitor changes over time.

[0102] In this embodiment, each switch circuit 30 is controlled by a different control signal, that is, each switch circuit 30 is controlled by a corresponding control signal. Figure 2 and Figure 3 As shown, each fourth MOS transistor is controlled by a different control signal. By controlling the switch circuit 30 by different control signals, the charging or discharging time of each load capacitor can be controlled individually.

[0103] Combined with 5~ Figure 7 As shown, the compensation circuit includes a detection resistor, several calibration circuits, and at least one detection circuit. Each calibration circuit is connected to a voltage source or ground (GND) through a detection resistor to form a detection point. Each calibration circuit is used to receive Pixel dataThe corresponding pixel data is converted into reference current and calibration current, which are input into the detection resistor. The detection circuit is used to obtain the reference data voltage and calibration data voltage at the detection point based on the reference current and calibration current, respectively, and adjust the pixel data accordingly. The pixel data here is grayscale value data. For example, for a display with a color depth of 10, the calibration circuit receives pixel data such as 10'h200, etc.

[0104] In a specific implementation, first, the compensation circuit receives an entire row of pixel data, wherein the highest bit of the pixel data of the first pixel column is configured as 1, and each bit of the pixel data of other columns is configured as 0, and the detection circuit obtains the reference voltage Ref_Vdata generated by the calibration circuit corresponding to the first pixel column through the detection resistor; thereafter, an entire row of pixel data is sent again, wherein the highest bit of the pixel data of the second pixel column is configured as 1, and each bit of the pixel data of other columns is configured as 0, and the detection circuit obtains the reference voltage Ref_Vdata generated by the calibration circuit of the second pixel column through the detection resistor; by repeating the above process, the reference voltage Ref_Vdata corresponding to all pixel columns can be obtained.

[0105] Finally, the compensation circuit receives an entire row of pixel data, where the pixel data for column 1 is 10'h300 and the data for all other columns is 10'h000. The detection circuit obtains the calibration voltage Cal_Vdata generated by the calibration circuit corresponding to the first pixel column through the detection resistor. At the same time, the calibration voltage Cal_Vdata is compared with the obtained reference voltage Ref_Vdata. If the calibration voltage Cal_Vdata is greater than the reference voltage Ref_Vdata, the pixel data for column 1 is subtracted by one. If the calibration voltage Cal_Vdata is less than the reference voltage Ref_Vdata, the pixel data for column 1 is incremented by one. This process repeats until the calibration voltage Cal_Vdata and the reference voltage Ref_Vdata are equal. At this point, the received pixel data for column 1 is the number of clock cycles required for pixel column 1 to reach the reference voltage.

[0106] Repeating the above process can obtain the number of clock cycles required for each pixel column to reach the reference voltage.

[0107] After the number of clock cycles is obtained, the time required for each pixel column to reach the reference voltage can be obtained using it, that is, the product of the number of clocks and the length of the clock cycle is the time.

[0108] In this embodiment, all pixel columns share one detection circuit. Of course, in other embodiments, a corresponding detection circuit may be independently provided for each pixel column, and the configuration may be performed according to actual needs.

[0109] Combine Figure 6 and Figure 7 As shown, the calibration circuit includes a fifth MOS transistor T, a first switch K1, a second switch K2 and a third switch K3. The fifth MOS transistor T and the detection resistor R are connected in series to the voltage source V H Between the first switch K1 and the ground (GND), one end of the first switch K1 is connected to the calibration voltage Vcal, and the opposite end is connected to the gate end of the fifth MOS transistor T. One end of the second switch K2 is connected to the pixel column data signal V data , the opposite end is connected to the gate end of the fifth MOS tube T, and one end of the third switch K3 is connected to the reference voltage source V H , the opposite end is the gate end of the fifth MOS tube T.

[0110] In a specific implementation, when performing the first step of calibration, the first switch K1 is closed, the second switch K2 and the third switch K3 are opened, so that the reference voltage V cal can be input into the calibration circuit; when performing the second step of calibration, the first switch K1 and the third switch K3 are disconnected, and the second switch K2 is closed, so that the data voltage Vdata can be input into the calibration circuit.

[0111] In this embodiment, the first switch K1, the second switch K2, and the third switch K3 can be controlled to be on or off by the switch control circuit (Control) shown in the figure. The switch control circuit here is a simple logic circuit composed of gate-level circuits. Its inputs are calibration_mode0, calibration_mode1, and data[M], and its outputs are Q1, Q2, and Q3. Q1, Q2, and Q3 can respectively control the closing or opening of the first switch K1, the second switch K2, and the third switch K3. Among them, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the most significant bit of the grayscale value of the pixel column (M is the color depth of the grayscale).

[0112]

[0113] Furthermore, the following takes the case where the color depth is 10 and the first pixel column is compensated as an example to describe in detail how the compensation circuit performs compensation.

[0114] First, calibration_mode0 and calibration_mode1 are configured to 1 and 0 respectively. Then, a whole row of pixel data is received, where the pixel data of the first column is 10'h200 (the highest bit must be 1), and the pixel data of other columns are 10'h000. Under the control of the switch control circuit (Control), the first switch K1 corresponding to the first pixel column is closed, the second switch K2 and the third switch K3 are opened, and the gate terminal of the fifth MOS transistor T is connected to the reference voltage V cal , at this time the reference voltage V cal A current I1 will be generated from the source terminal S to the drain terminal D of the fifth MOS transistor T, and the current I1 will flow through the resistor R. Since the data [M] corresponding to other pixel columns is 0, the third switch K3 is closed, the first switch K1 and the second switch K2 are open, and the fifth MOS transistor T does not generate current. Therefore, only the current I1 flows through the detection resistor R. At this time, the voltage detected by the detection circuit at the detection point P represents the reference voltage V cal The converted data is Ref_Vdata corresponding to the first pixel column.

[0115] Next, calibration_mode0 and calibration_mode1 are configured to 0 and 1, respectively. Next, a full row of pixel data is received, where the pixel data for the first column is 10'h300 and the pixel data for the other columns is 10'h000. Under the control of the switch control circuit (Control), the second switch K2 is closed, the first switch K1 and the third switch K3 are opened, and the gate terminal of the fifth MOS transistor T is connected to the data voltage Vdata. The voltage of the data voltage Vdata depends on the pixel data input for the first pixel column. At this time, the data voltage Vdata generates a current I1' from the source terminal S to the drain terminal D of the fifth MOS transistor T, which flows through the detection resistor R. Since the data [M] corresponding to the other pixel columns is 0, the third switch K3 is closed, the first switch K1 and the second switch K2 are opened, and the fifth MOS transistor T does not generate current. Therefore, only current I1' flows through the detection resistor R. At this point, the detection circuit detects that the voltage at the detection point P represents the data voltage Vdata for the first pixel column. The converted data is the Cal_Vdata corresponding to the first pixel column.

[0116] Finally, it is determined whether the voltage Cal_Vdata is the same as Ref_Vdata, and the pixel data is adjusted based on the determination result. That is, if the voltage Cal_Vdata is greater than Ref_Vdata, the pixel data input to the first pixel column is reduced by one; if the voltage Cal_Vdata is less than Ref_Vdata, the pixel data input to the first pixel column is increased by one.

[0117] The above process is repeated until the voltage Cal_Vdata is the same as Ref_Vdata. At this time, the pixel data (i.e., grayscale value data) of the first pixel column is the number of clock cycles required for the first pixel column to reach the reference voltage, which can be used to obtain the time required for each pixel column to reach the reference voltage.

[0118] In this embodiment, an M-bit counter is used to count from 0 to 2 M -1 is used to count the charging or discharging time, and M is an integer greater than 0. Figure 4 As shown, when the counter counts from 0 to the grayscale value corresponding to a certain column of pixels (the grayscale value is the value that has been compensated by the above-mentioned pixel compensation circuit), the fourth MOS tube in the switch circuit corresponding to the pixel in this column is controlled to be disconnected by the corresponding control signal. At this time, the loop is disconnected, and no current flows, thereby stopping the discharge of the load capacitor and keeping the voltage of the load capacitor constant.

[0119] The following describes the charge and discharge circuit of the present invention in detail by taking two embodiments as examples.

[0120] Example 1

[0121] like Figure 2 As shown, the charge and discharge circuit includes n pre-processing circuits 10, n switching circuits 30, and a current mirror circuit 20 with n output branches. The first MOS transistor in the pre-processing circuit 10 is a PMOS transistor, the second and third MOS transistors in the current mirror circuit 20 are both NMOS transistors, and the fourth MOS transistor in the switching circuit 30 is an NMOS transistor. The source terminal of each first MOS transistor (denoted as T11 to Tn1) is connected to a reference voltage source V H , the drain end is connected to the corresponding load capacitor (denoted as C1~Cn) and forms a connection point A, the gate end is connected to the control signal S0; the drain end of the second MOS tube (denoted as T0) is connected to the reference current source I bias , the source terminal is grounded, and the gate terminal is connected to the drain terminal; the drain terminal of each third MOS tube (denoted as T13 to Tn3) serves as an output branch, the source terminal is grounded, and the gate terminal is connected to the gate terminal of the second MOS tube; the source terminal of each fourth MOS tube (denoted as T12 to Tn2) is connected to the drain terminal of the corresponding third MOS tube, the drain terminal is connected to the connection point A, and the gate terminal is connected to the corresponding control signal.

[0122] In a specific implementation, after a row starts, the control signal S0 controls all first MOS transistors (T11 to Tn1) to be turned on. At the same time, the control signal Sn controls the corresponding fourth MOS transistor Tn to be turned off. For example, the control signal S1 controls the fourth MOS transistor T1 to be turned off. At this time, the voltage values of all load capacitors (C1 to Cn) are increased to the high voltage reference voltage value V H .

[0123] Furthermore, the control signal S0 controls all the first MOS transistors to turn off, and at the same time, the control signal Sn controls the corresponding fourth MOS transistor Tn to turn on, and the charge-discharge circuit starts to discharge. At this time, the current mirror circuit 20 can mirror a current I in each output branch, and the current I is equal to the reference current source I bias In specific implementation, the width-to-length ratio of the second MOS transistor and the third MOS transistor can be adjusted to control the current I and the current I bias The proportional relationship can be used to select the appropriate current according to actual needs.

[0124] The discharge time of the load capacitor can be further controlled by counting, such as using an M-bit counter from 0 to 2 M -1 is used to count the discharge time, and M is an integer greater than 0. Figure 4 As shown, when the counter counts from 0 to the grayscale value corresponding to a column of pixels (this grayscale value is the value compensated by the above-mentioned pixel compensation circuit), the fourth MOS transistor in the switch circuit corresponding to the pixels in this column is controlled to disconnect by the corresponding control signal. At this time, the circuit is disconnected, no current flows, and the discharge of the load capacitor stops, and the voltage of the load capacitor is fixed. The voltage at this time is the voltage corresponding to the grayscale value of this column of pixels, and this voltage will be stored by the load capacitor. When the load capacitors of all columns are discharged, they will be written into the pixel driver circuit of a row.

[0125] Example 2

[0126] like Figure 3 As shown, the difference from the first embodiment is that the first MOS transistor of the pre-processing circuit 10 is an NMOS transistor, the second MOS transistor and the third MOS transistor in the current mirror circuit 20 are both PMOS transistors, and the fourth MOS transistor in the switch circuit 30 is a PMOS transistor. The source terminal of each first MOS transistor is connected to the reference voltage source V L , the drain end is connected to the load capacitor and forms a connection point A, the gate end is connected to the control signal S0; the drain end of the second MOS tube is connected to the reference current source I bias , the source terminal is connected to the voltage VDD, and the gate terminal is connected to the drain terminal; the drain terminal of each third MOS tube serves as an output branch, the source terminal is connected to the voltage VDD, and the gate terminal is connected to the gate terminal of the second MOS tube; the source terminal of each fourth MOS tube is connected to the drain terminal of the third MOS tube, the drain terminal is connected to the connection point A, and the gate terminal is connected to the corresponding control signal.

[0127] In a specific implementation, after a row of time starts, the control signal S0 controls all first MOS transistors to be turned on, and at the same time, the control signal Sn controls the corresponding fourth MOS transistor Tn to be turned off. At this time, the voltage values of all load capacitors are adjusted to the low voltage reference voltage value V L .

[0128] Furthermore, control signal S0 turns off all first MOS transistors, while control signal Sn turns on the corresponding fourth MOS transistors Tn, and the charge-discharge circuit begins charging. At this point, current mirror circuit 20 can mirror a current in each output branch that is proportional to the reference current source.

[0129] The charging time of the load capacitor can be further controlled by counting, such as using an M-bit counter from 0 to 2 M -1 is used to count the charging time, and M is an integer greater than 0. Figure 4 As shown, when the counter counts from 0 to the grayscale value corresponding to a certain column of pixels (this grayscale value is the value compensated by the above-mentioned pixel compensation circuit), the fourth MOS transistor in the switch circuit corresponding to this column is controlled to disconnect by the corresponding control signal. At this time, the circuit is disconnected, and no current flows, thereby stopping the charging of the load capacitor, and the voltage of the load capacitor is fixed. The voltage at this time is the voltage corresponding to the grayscale value of the pixels in this column, and this voltage is stored by the load capacitor. When the load capacitors of all columns are fully charged, they are written into the pixel driver circuit of a certain row.

[0130] In this embodiment, the compensation circuit can realize the compensation for charging and discharging through the above-mentioned specific circuit. Of course, in other embodiments, the compensation circuit can also compensate for the charging and discharging time in the following manner.

[0131] Specifically, first, a calibration voltage is selected from the ramp voltage;

[0132] Secondly, each pixel column is discharged from the maximum value of the ramp voltage, or each pixel column is charged from the minimum value of the ramp voltage, and the pixel column with the slowest discharge or charge is determined;

[0133] Thirdly, calibrate the pixel column that discharges or charges the slowest, and determine the time offset values corresponding to the remaining pixel columns based on the pixel column that discharges or charges the slowest;

[0134] Finally, the discharge or charge time of each pixel column minus the corresponding time offset value is the actual charge or discharge time.

[0135] The following describes in detail how to perform compensation using the discharge and charge processes.

[0136] (1) Discharge process

[0137] like Figure 8 The figure shows a schematic diagram of a ramp voltage, which can be expressed by the following formula:

[0138] V out =V H -(IL / C L )*t,

[0139] Where t is T*P W , T is the number of clock cycles, ranging from 0 to 2 M -1, P W is the cycle time length; C L is the load capacitance; I L is the pixel column discharge current; V out is the display pixel data voltage.

[0140] In a specific implementation, the pre-processing circuit 10 first adjusts each load capacitor to a preset value, that is, to a voltage V H In order to realize the compensation of the discharge process, the present invention firstly H and V L Select a reference voltage V cal Here the reference voltage V cal It can be selected by the following method: Set the voltage V L to V H The voltage between the two M , corresponding to pixel grayscale value 2 M -1 to 0, where V H The corresponding pixel minimum gray value is 0, V L The maximum grayscale value of the corresponding pixel is 2 M -1.

[0141] In this embodiment, in order to achieve better calibration accuracy and reuse the Latch circuit, and to ensure that the maximum difference of all pixel columns can be covered, the reference voltage V cal It is preferred to select a voltage close to V L point.

[0142] Furthermore, when the reference voltage V cal After that, all pixel columns are discharged, and the discharge time is (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles. When the discharge time is over, the pixel column with the slowest discharge is determined. In specific implementation, the pixel column with the slowest discharge can be determined by a detection circuit, such as the detection circuit determining whether the pixel column has discharged to the reference voltage V cal , to determine whether it is the slowest discharging pixel column, etc.

[0143] After determining the pixel column with the slowest discharge, the reference current source I bias, by changing the reference current source I bias To change the current mirrored by the current mirror circuit 20 in the pixel column, and at the same time, discharge the pixel column, the discharge time is (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles. At the same time, the data voltage V data Is it consistent with the reference voltage V cal If the data voltage V data With the reference voltage V cal If the same, the calibration is completed, the current reference current source I bias is the reference current source after calibration. At this time, the current reference current source I bias The configuration parameters are stored to facilitate subsequent use of the reference current source I bias Calibrate other pixel columns. If the data voltage V data With the reference voltage V cal If they are not the same, then continue to adjust the reference current source I of the current mirror circuit 20. bias , until it is discharged (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles when the data voltage V data With the reference voltage V cal same.

[0144] Furthermore, after calibrating the pixel column with the slowest discharge time, the time offset values corresponding to the remaining pixel columns are determined based on the discharge time of the pixel column with the slowest discharge time. In specific implementation, the time offset values corresponding to the remaining pixel columns can be obtained as follows:

[0145] From the above, we can know and combine Figure 8 As shown, the pixel column with the slowest discharge voltage is V H Discharge to V cal Time taken T' max *P w , then the pixel column changes from voltage V H Discharge to V L The time taken is T max *P w =T' max *P w *(2 M -1) / G cal , which can be achieved through Figure 8 The similar triangle relationship shown in the figure is deduced, where G calis the voltage V cal The corresponding pixel grayscale value.

[0146] Among the remaining pixel columns, the first pixel column is from voltage V H Discharge to V cal The time taken is T'1*P w , then the first pixel column is from the voltage V H Discharge to V L The time taken is T1*P w =T'1*P w *(2 M -1) / G cal .

[0147] By (T max *P w -T1*P w ) / P w , the clock cycle offset value Offset corresponding to the first pixel column is obtained as:

[0148] △T1=(T' max -T'1)*(2 M -1) / G cal ;

[0149] Furthermore, the second pixel column corresponds to Clock cycle offset value Offset is:

[0150] △T2=(T' max -T'2)*(2 M -1) / G cal ;

[0151] By analogy, any pixel column k in other pixel columns corresponds to Clock cycle offset value Offset values are:

[0152] △T k =(T' max -T' k )*(2 M -1) / G cal .

[0153] Since the gray value G of the pixel point on any pixel column k k and the maximum gray value is G k / (2 M -1)=t k0 / t k , where G k is the grayscale value of the pixel on any pixel column k, t k0 is a pixel point G on any pixel column k k The corresponding discharge time.

[0154] Therefore, the clock cycle offset value Offset corresponding to any pixel point on any pixel column k is:

[0155] △T k0 / △T k =t k0 / t k =G k / (2 M -1).

[0156] If the external input display signal grayscale of the k-th pixel column is G k When , the corresponding discharge time clock cycle number (Clock Cycle) is

[0157] G k / (2 M -1)*(T' max *(2 M -1) / G cal -△T k ).

[0158] After determining the clock cycle offset value Offset corresponding to any pixel point on any pixel column k, the clock cycle length Pw can be further used to determine the time offset value corresponding to any pixel point on any pixel column k.

[0159] In specific implementation, the clock cycle offset value Offset of the slowest discharging pixel column is usually set to 0, and the offset values Offset corresponding to the remaining pixel columns can be stored in a corresponding storage medium for subsequent use.

[0160] In this embodiment, the grayscale value G of a pixel on any pixel column k is k and the maximum gray value is G k / (2 M -1)=t k0 / t k Can be obtained by combining Figure 8 As shown, for any pixel point on pixel column k, the corresponding gray value formula G k =(2 M -1)*(I k / C k )*t k0 / (V H -V L ). For any pixel column k (I k / C k ) is a fixed value, (2 M -1) and (V H -V L ) is a constant, G k and t k0Is proportional, for any two pixels on the pixel column corresponding to the gray value G k1 and G k2 , all have G k1 / G k2 =t k1 / t k2 ; Therefore, the pixel point G on any pixel column k k and the maximum gray value is G k / (2 M -1)=t k0 / t k Among them, I k is the actual charging current of any pixel column k, C k is the actual load capacitance of any pixel column k.

[0161] (2) Charging process

[0162] like Figure 9 The figure shows a schematic diagram of a ramp voltage, which can be expressed by the following formula:

[0163] V out =V L +(I L / C L )*t,

[0164] Where t is T*P W , T is the number of clock cycles, ranging from 0 to 2 M -1, P W is the cycle time length; C L is the load capacitance; I L is the pixel column discharge current; V out is the display pixel data voltage.

[0165] In a specific implementation, the pre-processing circuit 10 first adjusts each load capacitor to a preset value, that is, to a voltage V L In order to realize the compensation of the charging process, the present invention firstly increases the voltage V H and V L Select a reference voltage V cal Here the reference voltage V cal It can be selected by the following method: Set the voltage V L to V H The voltage between the two M , corresponding to pixel grayscale value 2 M -1 to 0, where V L The corresponding pixel minimum gray value is 0, V H The maximum grayscale value of the corresponding pixel is 2 M -1.

[0166] In this embodiment, in order to achieve better calibration accuracy and reuse the Latch circuit, and to ensure that the maximum difference of all pixel columns can be covered, the reference voltage V cal It is preferred to select a voltage close to V H point.

[0167] Furthermore, when the reference voltage V cal After that, all pixel columns are charged, and the charging time is (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles. When the charging time is over, the pixel column with the slowest charging is determined. In a specific implementation, the pixel column with the slowest charging can be determined by a detection circuit, such as a detection circuit that determines whether the pixel column is charged to a reference voltage V cal , to determine whether it is the slowest charging pixel column, etc.

[0168] Furthermore, after determining the pixel column with the slowest charging speed, the reference current source I of the current mirror circuit 20 is adjusted. bias , by changing the reference current source I bias To change the current mirrored by the current mirror circuit 20 in the pixel column, and at the same time, charge the pixel column, the charging time is (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles. At the same time, the data voltage V data Is it consistent with the reference voltage V cal If the data voltage V data With the reference voltage V cal The same, the current reference current source I bias is the reference current source after calibration. At this time, the current reference current source I bias The configuration parameters are stored to facilitate subsequent use of the reference current source I bias Calibrate other pixel columns. If the data voltage V data With the reference voltage V cal If they are not the same, then continue to adjust the reference current source I of the current mirror circuit 20. bias , until it is charging (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles when the data voltage V data With the reference voltage Vcal same.

[0169] Furthermore, after calibrating the pixel column with the slowest charging time, the time offset values corresponding to the remaining pixel columns are determined based on the charging time of the pixel column with the slowest charging time. In specific implementation, the time offset values corresponding to the remaining pixel columns can be obtained as follows:

[0170] From the above, we can know and combine Figure 9 As shown, the slowest charging pixel column starts from voltage V L Charge to V cal Time taken T' max *P w , then the pixel column changes from voltage V L Charging V H The time taken is T max *P w =T' max *P w *(2 M -1) / G cal , which can be achieved through Figure 9 The similar triangle relationship shown in the figure is deduced, where G cal is the voltage V cal The corresponding pixel grayscale value.

[0171] In the remaining pixel columns, the first pixel column is from the voltage V L Charge to V cal The time taken is T'1*P w , then the first pixel column voltage V L Charging V H The time taken to reach is T1*P w =T'1*P w *(2 M -1) / G cal .

[0172] By (T max *P w -T1*P w ) / P w , the clock cycle offset value Offset corresponding to the first pixel column is obtained as:

[0173] △T1=(T' max -T'1)*(2 M -1) / G cal ;

[0174] Furthermore, the clock cycle offset value Offset corresponding to the second pixel column is:

[0175] △T2=(T' max -T'2)*(2M -1) / G cal ;

[0176] By analogy, the clock cycle offset value Offset corresponding to any pixel column k in other pixel columns is:

[0177] △T k =(T' max -T' k )*(2 M -1) / G cal .

[0178] Since the gray value G of the pixel point on any pixel column k k and the maximum gray value is G k / (2 M -1)=t k0 / t k , where G k is the grayscale value of the pixel on any pixel column k, t k0 is a pixel point G on any pixel column k k The corresponding charging time.

[0179] Therefore, the clock cycle offset value Offset corresponding to any pixel point on any pixel column k is:

[0180] △T k0 / △T k =t k0 / t k =G k / (2 M -1).

[0181] After determining the clock cycle offset value Offset corresponding to any pixel point on any pixel column k, the clock cycle length Pw can be further used to determine the time offset value corresponding to any pixel point on any pixel column k.

[0182] In this embodiment, the grayscale value G of a pixel on any pixel column k is k and the maximum gray value is G k / (2 M -1)=t k0 / t k Can be obtained by combining Figure 9 As shown, for any pixel point on pixel column k, the corresponding gray value formula G k =(2 M -1)*(I k / C k )*t k0 / (V H -V L ). For any pixel column k (Ik / C k ) is a fixed value, (2 M -1) and (V H -V L ) is a constant, G k and t k0 Is proportional, for any two pixels on the pixel column corresponding to the gray value G k1 and G k2 , all have G k1 / G k2 =t k1 / t k2 ; Therefore, the pixel point G on any pixel column k k and the maximum gray value is G k / (2 M -1)=t k0 / t k Among them, I k is the actual charging current of any pixel column k, C k is the actual load capacitance of any pixel column k.

[0183] The present invention also discloses a display screen having the aforementioned charge-discharge circuit, capable of charging or discharging the load capacitors in all columns of pixel circuits in the same row, ensuring that the voltage value of the load capacitors meets actual usage requirements, and that the load capacitors in each column of pixel circuits charge or discharge independently and do not interfere with each other. Such display screens include, but are not limited to, OLED / LED / LCD displays.

[0184] The present invention also discloses an electronic device having the aforementioned display screen, which is capable of quickly charging or discharging the load capacitors in all columns of pixel circuits in the same row, ensuring that the voltage of the load capacitors meets actual usage requirements, and the load capacitors in each column of pixel circuits are charged or discharged independently and without interfering with each other. The electronic devices described herein include, but are not limited to, smartphones, tablet computers, laptop computers, televisions, and desktop monitors.

[0185] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A charge and discharge circuit, characterized in that: include at least one load capacitor; at least one pre-processing circuit, each of the pre-processing circuits corresponding to one of the load capacitors, the pre-processing circuit being connected to the corresponding load capacitor to form a connection point, the pre-processing circuit being configured to adjust the voltage of the corresponding load capacitor to a reference voltage value; a current mirror circuit, the current mirror circuit being configured to mirror a reference current source and output the current through at least one output branch, each output branch corresponding to one of the connection points; A compensation circuit for compensating for the charging or discharging time of the load capacitance; At least one switching circuit, each switching circuit corresponds to one output branch, each output branch is connected to the corresponding connection point through the corresponding switching circuit, and the switching circuit is used to control the charging or discharging time of the load capacitance.

2. The charge and discharge circuit according to claim 1, wherein: Each of the pre-processing circuits is controlled by the same control signal to adjust the voltage of the corresponding load capacitor to a reference voltage value.

3. The charge and discharge circuit according to claim 1, wherein: Each switch circuit is turned on or off by a different control signal.

4. The charge and discharge circuit according to claim 1, wherein: The pre-processing circuit includes a reference voltage source; The first MOS transistor has a source terminal connected to a reference voltage source, a drain terminal connected to the load capacitor to form the connection point, and a gate terminal connected to a control signal.

5. The charge and discharge circuit according to claim 1, wherein: The current mirror circuit includes a second MOS transistor, a drain terminal connected to a reference current source, a source terminal connected to a voltage source or ground, and a gate terminal connected to a drain terminal; At least one third MOS transistor, each third MOS transistor has a drain terminal serving as an output branch, a source terminal commonly connected to a voltage source or ground, and a gate terminal connected to the gate terminal of the second MOS transistor.

6. The charge and discharge circuit according to claim 5, wherein: The second MOS transistor and the third MOS transistor are PMOS transistors or NMOS transistors.

7. The charge and discharge circuit according to claim 1, wherein: The switching circuit includes The fourth MOS transistor has a source terminal connected to the output branch, a drain terminal connected to the connection point, and a gate terminal connected to the control signal.

8. The charge and discharge circuit according to claim 1, wherein: The compensation circuit includes Detection resistor; A plurality of calibration circuits, each corresponding to a pixel column, and each calibration circuit is connected to a voltage source or ground via a detection resistor to form a detection point, each calibration circuit is used to receive pixel data and convert the corresponding pixel data into a reference current and a calibration current and input them into the detection resistor; At least one detection circuit is used to obtain a reference voltage and a calibration voltage at a detection point according to a reference current and a calibration current, respectively, and adjust pixel data according to the reference voltage and the calibration voltage.

9. The charge and discharge circuit according to claim 8, wherein: All pixel columns share a detection circuit.

10. The charge and discharge circuit according to claim 8, wherein: The calibration circuit includes a fifth MOS transistor connected in series with the detection resistor between the voltage source and the ground; a first switch, one end of which is connected to a reference voltage, and an opposite end of which is connected to a gate terminal of a fifth MOS transistor; A second switch, one end of which is connected to the data voltage of the pixel column, and the opposite end of which is connected to the gate end of the fifth MOS transistor; a third switch, one end of which is connected to the voltage source, and an opposite end of which is connected to the gate terminal of the fifth MOS transistor; The switch control circuit is connected to the first switch, the second switch and the third switch, and is used to control the first switch, the second switch and the third switch to be closed or opened according to the pixel data.

11. The charge and discharge circuit according to claim 10, wherein: The switch control circuit is a logic circuit composed of gate-level circuits, with inputs of calibration_mode0, calibration_mode1 and data[M], and outputs Q1, Q2, and Q3. Q1, Q2, and Q3 respectively control the closing or opening of the first switch, the second switch, and the third switch. Among them, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit value of the grayscale value corresponding to the pixel column.

12. The charge and discharge circuit according to claim 1, wherein: The switching circuit controls the charging or discharging time of the load capacitor including: During charging or discharging, the M-bit counter counts from 0 to 2. M -1 counts the charging or discharging time, and when the counter counts from zero to the grayscale value corresponding to a column of pixels, the switch circuit corresponding to the column of pixels is disconnected, M is the color depth of the display, and M is an integer greater than 0.

13. The charge and discharge circuit according to claim 1, wherein: The current of each output branch is the same as or proportional to the reference current source.

14. A charging and discharging method based on the charging and discharging circuit according to claim 1, characterized in that: include Each pre-processing circuit adjusts the voltage of the corresponding load capacitor to a reference voltage value; The current mirror circuit mirrors the reference current source and outputs the current through at least one output branch to charge or discharge the load capacitor; The compensation circuit compensates for the charging or discharging time of the load capacitance; The switching circuit controls the charging or discharging time of the load capacitor.

15. The charge-discharge method of the charge-discharge circuit according to claim 14, wherein: The charging or discharging time is compensated by the following steps: Selecting a reference voltage from the ramp voltage; Discharging each pixel column from the maximum value of the ramp voltage, or charging each pixel column from the minimum value of the ramp voltage, and determining the pixel column with the slowest discharge or charge; Performing time calibration on the pixel column that discharges or charges the slowest, and determining time offset values corresponding to the remaining pixel columns based on the time of the pixel column that discharges or charges the slowest; The actual charging or discharging time is obtained by subtracting the corresponding time offset from the discharge or charging time of each pixel column.

16. The charge and discharge method according to claim 15, wherein: Selecting a reference voltage from the ramp voltage includes Divide the ramp voltage evenly into 2 M share; During discharge, a voltage close to the minimum value of the ramp voltage is selected as the reference voltage. During charge, a voltage close to the maximum value of the ramp voltage is selected as the reference voltage. M is the color depth of the display.

17. The charge-discharge method according to claim 10, wherein: The time calibration of the slowest discharging pixel column includes: (a) Discharge all pixel columns for a discharge time of (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles; (b) Determine the pixel column with the slowest discharge and discharge the pixel column simultaneously by adjusting the reference current source of the current mirror circuit. The discharge time is (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles; (c) Determine whether the data voltage of the pixel column is the same as the reference voltage. If they are the same, the discharge time of the pixel column with the slowest discharge is (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles, otherwise, continue to adjust the reference current source and charge (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles until the data voltage is the same as the reference voltage, Among them, M is the color depth of the display, V H Maximum ramp voltage, V L is the minimum value of the ramp voltage, V cal is the reference voltage.

18. The charge and discharge method according to claim 10, wherein: The time calibration of the slowest charging pixel column includes (a) Charge all pixel columns, the charging time is (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles; (b) Determine the pixel column with the slowest charging time and charge the pixel column simultaneously by adjusting the reference current source of the current mirror circuit. The charging time is (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles; (c) Determine whether the data voltage of the pixel column is the same as the reference voltage. If they are the same, the charging time of the slowest charging pixel column is (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles, otherwise, continue to adjust the reference current source and charge (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles until the data voltage is the same as the reference voltage, Among them, M is the color depth of the display, V H Maximum ramp voltage, V L is the minimum value of the ramp voltage, V cal is the reference voltage.

19. The charge and discharge method according to claim 10, wherein: The time offset value is obtained by the following steps: (a) Based on the time it takes for the pixel column that discharges or charges the slowest to discharge or charge to the reference voltage, determine the time it takes for the pixel column that discharges or charges the slowest to go from the maximum value of the ramp voltage to the minimum value or from the minimum value of the ramp voltage to the maximum value. T max *P w =T' max *P w *(2 M -1) / G cal The time taken by the remaining pixel columns to change from the maximum value to the minimum value of the ramp voltage or from the minimum value to the maximum value of the ramp voltage is T k *P w =T' k *P w *(2 M -1) / G cal (b) The remaining pixel columns are related to the pixel column with the slowest discharge or charge. Cycle offset value is △T k =(T' max -T' k )*(2 M -1) / G cal (c) determining the time offset value of each pixel column by the cycle number offset value and the cycle time length of each pixel column, Where T is the number of clock cycles, P w is the clock cycle length, M is the display color depth, G cal is the grayscale value corresponding to the reference voltage Vcal.

20. A display screen, characterized in that: The charging and discharging circuit comprises the charging and discharging circuit according to any one of claims 1 to 13.

21. An electronic device, characterized in that: Including the display screen according to claim 20.

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