Power amplifier, radio frequency chip and base station

Abstract

The invention provides a power amplifier, a radio frequency chip and a base station, and relates to the technical field of power amplifiers. The problem that the complexity of a power amplifier circuit is aggravated is solved. The power amplifier comprises a mean value tube, a first peak value tube and a second peak value tube, a first impedance inverter circuit is arranged between the output end of the mean value tube and the output end of the first peak value tube, and a second impedance inverter circuit is arranged between the output end of the first peak value tube and the output end of the second peak value tube. The first impedance inverter circuit and the second impedance inverter circuit are opposite in phase and identical in phase compensation angle.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of power amplifiers, and in particular to a power amplifier, a radio frequency chip, and a base station. Background Art

[0002] In modern wireless communication systems, power amplifiers (PAs) play a crucial role, amplifying the low-power signal from the modulator to the high-power signal required to drive the antenna and transmit over long distances. PAs must be highly efficient, linear, and broadband to ensure effective signal transmission and good communication quality.

[0003] Currently, the structure of power amplifiers is developing towards multi-channel, and the multi-channel structure will increase the complexity of the circuit. Summary of the Invention

[0004] Embodiments of the present application provide a power amplifier, a radio frequency chip, and a base station, which are used to improve the problem of increasing complexity of power amplifier circuits.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In the first aspect, the present application provides a power amplifier comprising: an averaging tube, a first peak tube and a second peak tube, a first impedance inverter circuit being arranged between the output end of the averaging tube and the output end of the first peak tube, a second impedance inverter circuit being arranged between the output end of the first peak tube and the output end of the second peak tube, the first impedance inverter circuit and the second impedance inverter circuit having opposite phases and the same phase compensation angles.

[0007] The power amplifier provided in the present application arranges a first impedance inverter circuit and a second impedance inverter circuit with opposite phases but the same phase compensation angle between the averaging tube, the first peak tube, and the second peak tube, so that the phases of the signals at the combining point can be consistent, and there is no need to add an additional phase compensation circuit to the input end of the second peak tube. Compared with traditional power amplifiers, while achieving the same effect, the number of phase compensation circuits is reduced, the circuit area of the power amplifier is further reduced, and the reliability and stability of the system are improved due to the reduction in the number of components in the power amplifier.

[0008] In a possible implementation, the power amplifier further includes a phase compensation circuit connected to the input end of the first peak transistor. The phase compensation circuit and the second impedance inverter circuit have opposite phases and the same phase compensation angle.

[0009] The power amplifier provided in the present application can be provided with a phase compensation circuit at the input end of the first peak tube in order to ensure phase consistency of the various signals at the combining point, with a phase compensation circuit having an opposite phase and the same phase compensation angle as the second impedance inverter circuit. Ensuring phase consistency of the various signals at the combining point can ensure that the phases of different signals remain synchronized when combined, preventing interference or distortion caused by phase differences. Achieving phase consistency through a phase compensation circuit can not only improve the performance and stability of the system, but also effectively reduce energy waste, enabling the power amplifier to operate in a more efficient manner, thereby better meeting the needs of practical applications.

[0010] In a possible implementation, the power amplifier further includes a third peak transistor, and a third impedance inverter circuit is provided between the output end of the third peak transistor and the output end of the second peak transistor.

[0011] In a possible embodiment, the power amplifier also includes multiple third peak tubes, wherein a third impedance inverter circuit is arranged between the output end of one third peak tube and the output end of the second peak tube, and a third impedance inverter circuit is arranged between the output ends of any two cascaded third peak tubes.

[0012] In a possible implementation manner, at least two adjacent third impedance inverter circuits have opposite phases and the same phase compensation angles.

[0013] In a possible implementation manner, any two adjacent third impedance inverter circuits have the same phase and the same phase compensation angle.

[0014] In a possible implementation, the first impedance inverter circuit is a high-pass circuit, and the second impedance inverter circuit is a low-pass circuit.

[0015] In the power amplifier provided in the present application, the first impedance inversion circuit is a high-pass circuit. The high-pass circuit has a good suppression effect on low-frequency signals, which is beneficial to improving broadband linearity. It can also enable the averaging tube and the first peak tube to achieve different leakage voltage power supply. The peak tube allows a higher leakage voltage power supply and can provide greater output power during the signal peak period. Therefore, better broadband characteristics can be obtained when processing high-frequency signals.

[0016] In one possible embodiment, the high-pass circuit includes: a first inductor, a second inductor, and a first capacitor, wherein the first end of the first inductor and the first end of the first capacitor are connected to the input end of the high-pass circuit, the first end of the second inductor and the second end of the first capacitor are connected to the output end of the high-pass circuit, and the second end of the first inductor and the second end of the second inductor are connected to the ground end.

[0017] In one possible embodiment, the low-pass circuit includes: a second capacitor, a third capacitor, and a third inductor, the first end of the second capacitor and the first end of the third inductor are connected to the input end of the low-pass circuit, the first end of the third capacitor and the second end of the third inductor are connected to the output end of the low-pass circuit, and the second end of the second capacitor and the second end of the third capacitor are connected to the ground end.

[0018] In a second aspect, the present application provides a radio frequency chip, comprising: a substrate and a power amplifier, wherein the power amplifier is arranged on the substrate, and the power amplifier is the power amplifier of the aforementioned first aspect.

[0019] In a third aspect, the present application provides a base station, comprising: a baseband processing circuit and a radio frequency front-end circuit, the baseband processing circuit is connected to the radio frequency front-end circuit, the radio frequency front-end circuit includes a power amplifier, and the power amplifier is the power amplifier of the first aspect mentioned above.

[0020] The technical effects of the second to third aspects refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0022] Figure 2 A power-efficiency matching curve diagram of a power amplifier provided in an embodiment of the present application;

[0023] Figure 3 A schematic structural diagram of a power amplifier provided in an embodiment of the present application;

[0024] Figure 4 A circuit diagram of an impedance inversion circuit provided in an embodiment of the present application;

[0025] Figure 5 A circuit diagram of another impedance inversion circuit provided in an embodiment of the present application;

[0026] Figure 6 A circuit diagram of another impedance inversion circuit provided in an embodiment of the present application;

[0027] Figure 7 Another structural diagram of a power amplifier provided in an embodiment of the present application;

[0028] Figure 8 A circuit diagram of another impedance inversion circuit provided in an embodiment of the present application;

[0029] Figure 9 A circuit diagram of another impedance inversion circuit provided in an embodiment of the present application;

[0030] Figure 10 A power-efficiency matching curve diagram of another power amplifier provided in an embodiment of the present application;

[0031] Figure 11 Another structural diagram of a power amplifier provided in an embodiment of the present application;

[0032] Figure 12 A circuit diagram of another impedance inversion circuit provided in an embodiment of the present application;

[0033] Figure 13 Another structural diagram of a power amplifier provided in an embodiment of the present application;

[0034] Figure 14 A circuit diagram of another impedance inversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and claims of the present application, the singular expressions "a", "a", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0037] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more. For example, "plurality of processing units" refers to two or more processing units.

[0038] Furthermore, in the embodiments of the present application, "upper," "lower," "left," and "right" are not limited to being defined relative to the orientation of the components schematically shown in the drawings. It should be understood that these directional terms can be relative concepts. They are used for relative description and clarification, and may change accordingly based on changes in the orientation of the components in the drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity, and the dimensional ratios between the components in the drawings do not reflect the actual dimensional ratios.

[0039] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "electrical connection" can mean direct electrical connection or indirect electrical connection through an intermediate medium.

[0040] In the embodiments of the present application, the term "module" generally refers to a functional structure divided according to logic. The "module" can be implemented by pure hardware or a combination of hardware and software. In the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, B exists alone, and A and B exist at the same time.

[0041] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0042] The technical solution of the present application can be applied to various communication devices including power amplifiers. The communication device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted. It can also be deployed on the water (such as a ship, etc.). It can also be deployed in the air (such as on an airplane, balloon, and satellite, etc.). For example, the communication device can be a base station, which includes a baseband processing circuit and a radio frequency front-end circuit.

[0043] Figure 1 A schematic diagram of the structure of a radio frequency front-end circuit provided in an embodiment of the present application.

[0044] Typically, the RF front-end circuit includes but is not limited to a RF switch, a duplexer, a filter, a power amplifier circuit (PA), a low noise amplifier (LNA), etc. For example, Figure 1As shown, the RF front-end circuit may include: a RF switch, a duplexer, a filter, a power amplifier, and a low-noise amplifier.

[0045] The RF front-end circuit may include a transmitting channel and a receiving channel, the transmitting channel includes a power amplifier and a transmitting channel filter, the RF output end of the power amplifier is coupled to the input end of the transmitting channel filter, the receiving channel includes a low-noise amplifier and a receiving channel filter, the output end of the receiving channel filter is coupled to the RF input end of the low-noise amplifier.

[0046] The duplexer is responsible for duplex switching of the frequency division duplex system and filtering of RF signals in the receiving channel / transmitting channel, while the RF switch is responsible for switching between the receiving channel and the transmitting channel.

[0047] The baseband signal is transmitted by the transceiver to the transmit channel, which amplifies the received RF signal and outputs it to the antenna for transmission. The power amplifier amplifies the RF signal in the transmit channel, while the transmit channel filter filters it.

[0048] It should be explained that when an electronic device includes multiple antennas, one antenna may correspond to one power amplifier, one antenna may correspond to multiple power amplifiers, or multiple antennas may share one power amplifier. The application scenarios in the relevant technologies are all applicable to the embodiments of this application.

[0049] The receiving channel receives the RF signal from the antenna, and the RF signal is amplified by the receiving channel and output, and transmitted to the baseband through the transceiver. The low noise amplifier is responsible for amplifying the RF signal of the receiving channel, and the receiving channel filter is responsible for filtering the RF signal of the receiving channel. In addition, the antenna frequency applicable to the embodiment of the present application may include sub6G bands and other frequency bands with relatively high bandwidth requirements. Of course, it can also be applicable to other frequency bands such as sub3G bands, WIFI bands (such as 2.4G bands, 5G bands, and 6G bands).

[0050] Modern wireless communication systems typically employ modulated signals with a high peak-to-average power ratio (PAPR) to improve the utilization of scarce spectrum resources. This signal processing method allows the system to more efficiently utilize spectrum, increase data rates, and meet growing communication demands. In communication architectures, power amplifiers are primarily located in the downlink, transmitting signals from the base station to the end device. During this process, the signal generated by the base station undergoes a series of processing steps, including modulation and mixing, before ultimately being amplified by the power amplifier. The power amplifier plays a critical role in the downlink, providing sufficient power to ensure efficient transmission of communication signals to the end device, thereby achieving a reliable communication connection. However, in practical applications, in most scenarios, the end device traffic load is low, resulting in the power amplifier often operating in a power-backed state far exceeding the signal's peak-to-average power ratio. In this state, the power amplifier's efficiency is relatively low, resulting in high operating power consumption for the entire circuit. Therefore, optimizing the efficiency and performance of the power amplifier is crucial for the performance and energy efficiency of the entire wireless communication system.

[0051] For example, see Figure 2 , Figure 2 The dashed curve in the figure represents the theoretical efficiency curve for a traditional Class B power amplifier. As can be seen, as the power back-off level increases, the amplifier's efficiency gradually decreases. Power back-off refers to the difference between the amplifier's current power and its maximum power. Therefore, when the amplifier is in power back-off, its efficiency is also relatively low. For high peak-to-average power ratio signals, when power back-off is large, only a small amount of DC energy in the amplifier is converted into RF energy, and the remaining energy is almost entirely converted into heat.

[0052] In one possible implementation, a Doherty (DHT) power amplifier can be used to improve the efficiency of the power amplifier during power back-off. A DHT power amplifier can include two amplifiers with different power levels: a main amplifier and an auxiliary amplifier. The main amplifier handles the majority of the system signal power, while the auxiliary amplifier handles high peak power. This division of labor enables the DHT power amplifier to maintain relatively high operating efficiency even at high power back-off levels.

[0053] For example, see Figure 2 , Figure 2The solid line curve in the figure is the theoretical efficiency curve of a two-way symmetrical DHT power amplifier. It can be seen that the two-way symmetrical DHT power amplifier has two efficiency peaks, occurring at the peak power point and at 6dB back-off. Compared with traditional Class B power amplifiers, the two-way symmetrical DHT power amplifier has a significant efficiency improvement, especially in the high power output range (0 to -6dB). However, when the output power is 12dB back-off, the efficiency of the two-way symmetrical DHT power amplifier drops from a maximum of 78.5% to around 40%. If the output power is further reduced to the low power output range (-20dB to -12dB), the efficiency of the two-way symmetrical DHT power amplifier will drop even further.

[0054] To improve the efficiency of the DHT power amplifier in the low-power output range and reduce the power consumption of the base station equipment, in one possible implementation, a DHT power amplifier with a multi-channel structure can be configured. Due to the presence of multiple efficiency peaks, the efficiency of the DHT power amplifier in the low-power output range can be effectively improved.

[0055] As DHT power amplifiers develop towards multi-channel structures, the circuit area of DHT power amplifiers continues to increase, and the number of components also continues to increase. Therefore, while ensuring high efficiency of DHT power amplifiers, simplifying the structure of DHT power amplifiers and reducing the number of components are the optimization directions of DHT power amplifiers.

[0056] In a possible implementation, the embodiment of the present application provides a DHT power amplifier, including a main power amplifier circuit and an auxiliary power amplifier circuit. Figure 3 , Figure 3 Figure 2 shows a schematic diagram of the circuit structure of a three-way DHT power amplifier. It includes a power divider 301 at the input end. This device splits one input signal into two or more equal or unequal outputs. It can also combine multiple signal energies into one output, also known as a combiner. The amplifier circuit also includes a main power amplifier circuit and two auxiliary power amplifier circuits: a first auxiliary power amplifier circuit and a second auxiliary power amplifier circuit. The main power amplifier circuit includes an averaging transistor 302 and a first impedance inverter circuit 303. The first auxiliary power amplifier circuit, cascaded with the main power amplifier circuit, includes a first phase compensation circuit 304, a first peak transistor 305, and a second impedance inverter circuit 306. The second auxiliary power amplifier circuit, cascaded with the first auxiliary power amplifier circuit, includes a second peak transistor 308 and a second phase compensation circuit 307. The output of the second peak transistor 308 is also connected to a load terminal 309. The averaging transistor 302 can be biased in Class AB or Class B, while the first peak transistor 305 and the second peak transistor 308 can be biased in Class C.

[0057] To ensure that the signals from the different paths of the power amplifier are combined in phase before entering the load, a phase compensation circuit is required at the input of the peak transistor. To maintain high efficiency at different power output levels and ensure impedance matching between the input and output ports, the DHT power amplifier is equipped with an impedance inverter circuit. This circuit dynamically changes the load impedance of the power amplifier, allowing it to maintain high efficiency at low power output. At low power output, typically only the main power amplifier circuit is active, while the auxiliary power amplifier circuits are in a low-power state or turned off. The impedance inverter circuit dynamically adjusts the load impedance of the main amplifier according to the output power requirement to match the optimal efficiency point for the current operating state. As a result, the main amplifier can operate at high efficiency even at low power output, thereby improving the efficiency of the entire DHT power amplifier.

[0058] Continue reading Figure 3 The first phase compensation circuit 304, the second phase compensation circuit 307, the first impedance inverter circuit 303, and the second impedance inverter circuit 306 can all be implemented by wires. For example, the signal compensation line length of the first phase compensation circuit 304 can be λ / 4, the signal compensation line length of the second phase compensation circuit 307 can be λ / 2, and the signal compensation line lengths of the first impedance inverter circuit 303 and the second impedance inverter circuit 306 can be λ / 4, where λ is the wavelength.

[0059] In order to reduce the overall circuit area of the DHT power amplifier and save manufacturing costs, the implementation of the impedance inversion circuit can be optimized. In one possible implementation, the impedance inversion circuit can be implemented using electronic components. The first impedance inversion circuit 303 and the second impedance inversion circuit 306 can be -90° impedance inversion circuits, which delay the phase of the input signal by 90°. Figure 4 The -90° impedance inverter circuit includes capacitors C1 and C2, and an inductor L. This is a low-pass circuit, allowing low-frequency signals to pass while blocking high-frequency signals. Inductors have a limited current capacity, so in high-power scenarios, they may not meet the power requirements of a DHT power amplifier. In low-power scenarios, existing process conditions may not be able to meet the requirements for a large inductor.

[0060] In one possible implementation, a multi-stage impedance inverter circuit can be used to implement large inductance. Figure 5 , Figure 5 for Figure 4 The schematic diagram of the third-order implementation of the impedance inverter circuit is shown in Figure 1. The original first-order structure is split into a three-order structure, where capacitor C1, capacitor C2 and inductor L a It is a first-order structure, capacitor C2, capacitor C3 and inductor Lb It is a second-order structure, with capacitors C3, C4 and inductor L c It is a third-order structure.

[0061] See Figure 6 , Figure 6 for Figure 3 In the schematic diagram of the circuit topology of the first impedance inverter circuit 303 and the second impedance inverter circuit 306, it can be seen that an inductor L1 is connected in series between the output end (a) of the averaging tube and the output end (b) of the first peak tube, and an inductor L2 is connected in series between the output end (b) of the first peak tube and the output end (c) of the second peak tube, that is, the devices between any power tubes are inductors. Because the inductor does not have the characteristic of blocking DC, the voltage of the power tubes at both ends of the inductor is the same, so it is impossible to achieve different leakage voltage power supply for the power amplifier circuit and the auxiliary power amplifier circuit. And as the DHT power amplifier develops towards a multi-channel structure, each additional channel will increase an impedance inverter circuit and a phase compensation circuit.

[0062] See Figure 7 The power amplifier provided in this application is described. The power amplifier may include an averaging tube 701, a first peaking tube 704, and a second peaking tube 706. A first impedance inverter circuit 702 is provided between the output end (a) of the averaging tube 701 and the output end (b) of the first peaking tube 704, and a second impedance inverter circuit 705 is provided between the output end (b) of the first peaking tube 704 and the output end (c) of the second peaking tube 706. The first impedance inverter circuit 702 and the second impedance inverter circuit 705 have opposite phases and the same phase compensation angle. For example, the first impedance inverter circuit 702 may be a +90° impedance inverter circuit, and the second impedance inverter circuit 705 may be a -90° impedance inverter circuit.

[0063] The first impedance inverter circuit 702 and the second impedance inverter circuit 705 can form a left-handed topology combiner. The left-handed topology combiner can be a three-port combiner, whose three ports can be port a connected to the averaging tube, port b connected to the output end of the first peak tube 704, and port c connected to the output end of the second peak tube 706.

[0064] compared to Figure 3The three-way DHT power amplifier of this embodiment simplifies the phase compensation circuit of the entire power amplifier due to the optimization of the impedance inversion circuit. That is, the input end of the second peak tube 706 no longer needs to add a phase compensation circuit, which is equivalent to reducing two 90° phase compensation circuits. Therefore, the area of the entire circuit can be significantly reduced. By optimizing the impedance inversion circuit and then simplifying the phase compensation circuit, the power amplifier of this embodiment can reduce the circuit area of the entire power amplifier while ensuring performance, thereby reducing production costs and circuit complexity. And because the number of devices in the power amplifier is reduced, the reliability and stability of the entire power amplifier are improved. It should be noted that the above Figure 7 The power amplifier structure shown is not only applicable to a three-way DHT power amplifier, but also to the first three-way structure of a multi-way DHT power amplifier.

[0065] To ensure the stability of the power amplifier, the phases of the signals at the combining point must be consistent. In one possible implementation, the power amplifier further includes a phase compensation circuit connected to the input of the first peak transistor. The phase compensation circuit and the second impedance inverter circuit have opposite phases and the same phase compensation angle.

[0066] Continue reading Figure 7 A first phase compensation circuit 703 is further provided between the power divider and the first peak transistor 704. The first phase compensation circuit 703 and the second impedance inverter circuit 705 have opposite phases and the same phase compensation angle. For example, the first phase compensation circuit 703 may be a +90° impedance inverter circuit, and the second impedance inverter circuit 705 may be a -90° impedance inverter circuit.

[0067] exist Figure 7 In the power amplifier shown, the input signal is split into three signals by a power divider. The first signal is amplified by an averaging transistor 701 and then passes through a +90° impedance inverter circuit. The second signal passes through a +90° phase compensation circuit and is amplified by a first peak transistor 704. These two signals are combined at the output of the first peak transistor 704 and then pass through a -90° impedance inverter circuit. The third signal is amplified by a second peak transistor 706 and then merges with the first two signals at the output point, entering the load terminal 707.

[0068] In order to improve the broadband linearity of the power amplifier, in a possible implementation, the first impedance inverter circuit is a high-pass circuit, and the second impedance inverter circuit is a low-pass circuit.

[0069] A high-pass circuit allows high-frequency signals to pass while suppressing low-frequency signals. This characteristic allows the high-pass circuit to effectively suppress low-frequency voltage broadband signals, thereby improving the broadband linearity of the entire power amplifier. Broadband linearity refers to the ability of the power amplifier to maintain the original characteristics of the signal and avoid signal distortion when processing broadband signals. In wireless communication systems, signal transmission is often subject to various interferences such as noise and attenuation. These interferences can cause signal quality to degrade and affect communication performance. Setting the first impedance inverter circuit as a high-pass circuit can effectively reduce these interferences, allowing the signal to remain purer during transmission.

[0070] In a possible implementation, the specific circuit structure of the high-pass circuit can be as follows: Figure 8 As shown, the circuit includes: a first inductor (L1), a second inductor (L2), and a first capacitor (C). The first end of the first inductor (L1) and the first end of the first capacitor (C) are connected to the input end (a) of the high-pass circuit, the first end of the second inductor (L2) and the second end of the first capacitor (C) are connected to the output end (b) of the high-pass circuit, and the second end of the first inductor (L1) and the second end of the second inductor (L2) are connected to the ground end.

[0071] The specific circuit structure of the low-pass circuit can be as follows Figure 4 As shown, it includes: a second capacitor (C1), a third capacitor (C2) and a third inductor (L). The first end of the second capacitor (C1) and the first end of the third inductor (L) are connected to the input end of the low-pass circuit, the first end of the third capacitor (C2) and the second end of the third inductor (L) are connected to the output end of the low-pass circuit, and the second end of the second capacitor (C1) and the second end of the third capacitor (C2) are connected to the ground end.

[0072] Figure 9 for Figure 7 The circuit topology diagram of the first impedance inverter circuit 702 and the second impedance inverter circuit 705 is shown in FIG. Figure 9 In Figure A, a capacitor C1 is connected in series between the output end (a) of the averaging tube and the output end (b) of the first peak tube, while an inductor L3 is connected in series between the output end (b) of the first peak tube and the output end (c) of the second peak tube. Since the capacitor has the characteristic of blocking DC, the voltages of the power tubes at both ends of the capacitor C can be different, that is, the output end (a) of the averaging tube and the output end (b) of the first peak tube can be powered by different leakage voltages, while the peak tube allows for higher leakage voltage power supply, which can provide greater output power during the signal peak period, so better broadband characteristics can be obtained when processing high-frequency signals. In practical applications, due to Figure 9 The inductor L2 and capacitor C2 in Figure A will resonate and there will be two situations. Figure 9In Figure B, the first case is that only the original inductor L2 remains, and the other capacitors and inductors remain unchanged. Figure 9 In Figure C, the second case is that only the original capacitor C2 remains, and the other capacitors and inductors remain unchanged.

[0073] The following will be combined Figure 10 , the working process of the DHT power amplifier provided in the embodiment of the present application under different working scenarios is described, see Figure 10 In low-power scenarios, the input signal is small, and only the averaging tube power amplifier operates in a high-efficiency state. The other power tubes are not turned on, and the output power is more than 12dB backed off compared to full power. In medium-power scenarios, the input power continues to increase, the first peak tube turns on, and works with the averaging tube in Doherty mode until both power amplifiers reach maximum power at the same time. At this time, the power amplifier output power is more than 9dB backed off compared to full power. In high-power scenarios, the input power further increases, the second peak tube turns on, and forms a three-way DHT structure with the averaging tube and the first peak tube respectively, until the averaging tube power amplifier and the two peak tube power amplifiers reach maximum power output. At this time, the power amplifier output power reaches maximum power and maintains high efficiency.

[0074] For other path structures of a multi-channel DHT power amplifier, various implementations are possible. In one possible implementation, the multi-channel DHT power amplifier may include one or more third peak transistors. For example, when the DHT power amplifier includes N third peak transistors, a third impedance inverter circuit numbered 1 is provided between the third peak transistor numbered 1 and the second peak transistor, and a third impedance inverter circuit numbered N is provided between the third peak transistor numbered N-1 and the third peak transistor numbered N. When multiple third impedance inverter circuits are present, any third impedance inverter circuit can be a high-pass circuit or a low-pass circuit.

[0075] For example, see Figure 11, exemplified by a five-way DHT power amplifier, comprising an averaging transistor 1101, a first peak transistor 1104, a second peak transistor 1106, and two adjacent third peak transistors, namely, third peak transistor 1109 and third peak transistor 1112. A first impedance inverter circuit 1102 is provided between the output end (a) of averaging transistor 1101 and the output end (b) of first peak transistor 1104, and a second impedance inverter circuit 1105 is provided between the output end (b) of first peak transistor 1104 and the output end (c) of second peak transistor 1106. A phase compensation circuit 1103 is provided at the input end of the second peak transistor 1106. A third impedance inverter circuit 1107 is provided between the output end (d) of the third peak transistor 1109 and the output end (c) of the second peak transistor 1106. A third impedance inverter circuit 1110 is also provided between the output end (d) of the third peak transistor 1109 and the output end (e) of the third peak transistor 1112. A phase compensation circuit 1108 is provided at the input end of the third peak transistor 1109, and a phase compensation circuit 1111 is provided at the input end of the third peak transistor 1112. The output end (e) of the third peak transistor 1112 is also connected to the load end 1113. The cascaded third impedance inverter circuits 1107 and 1110 have the same phase and the same phase compensation angle. For example, the third impedance inverter circuit 1107 can be a -90° impedance inverter circuit, and the third impedance inverter circuit 1110 can be a -90° impedance inverter circuit. Figure 12 for Figure 11 The circuit topology diagram of the third impedance inverter circuit 1107 and the third impedance inverter circuit 1110 is shown in FIG. Figure 12 An inductor L4 is connected in series between the output end (c) of the second peak tube 1106 and the output end (d) of the third peak tube 1109, and an inductor L5 is connected in series between the output end (d) of the third peak tube 1109 and the output end (e) of the third peak tube 1112, that is, the devices connected between the third peak tubes are all inductors.

[0076] See Figure 13The power amplifier includes an averaging transistor 1301, a first peak transistor 1304, a second peak transistor 1306, and two adjacent third peak transistors, namely, a third peak transistor 1309 and a third peak transistor 1311. A first impedance inverter circuit 1302 is provided between the output end (a) of the averaging transistor 1301 and the output end (b) of the first peak transistor 1304, and a second impedance inverter circuit 1305 is provided between the output end (b) of the first peak transistor 1304 and the output end (c) of the second peak transistor 1306. The input end of the second peak transistor 1306 is provided with a phase compensation circuit 1303. A third impedance inverter circuit 1307 is provided between the output end (d) of the third peak transistor 1309 and the output end (c) of the second peak transistor 1306. A third impedance inverter circuit 1310 is also provided between the output end (d) of the third peak transistor 1309 and the output end (e) of the third peak transistor 1311. The input end of the third peak transistor 1309 is provided with a phase compensation circuit 1308, while the input end of the third peak transistor 1311 is not provided with a phase compensation circuit. The cascaded third impedance inverter circuits 1307 and 1310 have opposite phases and the same phase compensation angle. For example, the third impedance inverter circuit 1307 can be a +90° impedance inverter circuit, and the third impedance inverter circuit 1310 can be a -90° impedance inverter circuit. The output end (e) of the third peak transistor 1311 is also connected to the load end 1312. Figure 14 for Figure 13 The circuit topology diagram of the third impedance inverter circuit 1307 and the third impedance inverter circuit 1310 is shown in FIG. Figure 14 A capacitor C4 is connected in series between the output end (c) of the second peak tube 1306 and the output end (d) of the third peak tube 1309, and an inductor L6 is connected in series between the output end (d) of the third peak tube 1309 and the output end (e) of the third peak tube 1311, that is, the devices connected between the third peak tubes are inductors and capacitors that appear alternately.

[0077] It can be seen that when the devices connected between the third peak transistors are alternately inductors and capacitors, compared to when the devices connected between the third peak transistors are all inductors, one phase compensation circuit can be saved for every two third peak transistors.

[0078] The present application also provides a radio frequency chip, including: a substrate and a power amplifier, wherein the power amplifier is arranged on the substrate, and the power amplifier is the power amplifier provided in the aforementioned embodiment.

[0079] In the several embodiments provided herein, it should be understood that the control and memory of the provided electronic device may be implemented in other ways. For example, the division of a module is merely a logical functional division, and in actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0080] It should be noted that the above description uses the example of a power amplifier circuit in which some components are located in the power amplifier chip and some components are located on the substrate. Of course, all components in the power amplifier circuit provided in the embodiment of the present application may also be provided in the power amplifier chip. Alternatively, some components may be located in the power amplifier chip and some components may be located on the substrate, but the components located in the power amplifier chip may differ from those illustrated in the above embodiment. The embodiment of the present application does not limit the layout of components in the power amplifier circuit, and the illustration in the embodiment is merely an illustration.

[0081] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A power amplifier, characterized in that: include: Average value tube, first peak value tube and second peak value tube; A first impedance inverter circuit is provided between the output end of the averaging tube and the output end of the first peak tube; A second impedance inverter circuit is provided between the output end of the first peak transistor and the output end of the second peak transistor; The first impedance inverter circuit and the second impedance inverter circuit have opposite phases and the same phase compensation angle.

2. The power amplifier according to claim 1, wherein: The power amplifier further includes a phase compensation circuit connected to the input end of the first peak tube. The phase of the phase compensation circuit and the second impedance inverter circuit are opposite in phase and have the same phase compensation angle.

3. The power amplifier according to claim 2, wherein: The power amplifier further includes a third peak transistor, and a third impedance inverter circuit is provided between the output end of the third peak transistor and the output end of the second peak transistor.

4. The power amplifier according to claim 2, wherein: The power amplifier also includes multiple third peak tubes, wherein a third impedance inverter circuit is arranged between the output end of one of the third peak tubes and the output end of the second peak tube, and the third impedance inverter circuit is arranged between the output ends of any two cascaded third peak tubes.

5. The power amplifier according to claim 4, wherein: Any two adjacent third impedance inverter circuits have the same phase and the same phase compensation angle.

6. The power amplifier according to claim 4, wherein: At least two adjacent third impedance inverter circuits have opposite phases and the same phase compensation angle.

7. The power amplifier according to claim 1, wherein: The first impedance inverter circuit is a high-pass circuit, and the second impedance inverter circuit is a low-pass circuit.

8. The power amplifier according to claim 7, wherein: The high-pass circuit includes: a first inductor, a second inductor and a first capacitor; The first end of the first inductor and the first end of the first capacitor are connected to the input end of the high-pass circuit, the first end of the second inductor and the second end of the first capacitor are connected to the output end of the high-pass circuit, and the second end of the first inductor and the second end of the second inductor are connected to the ground end.

9. The power amplifier according to claim 7, wherein: The low-pass circuit includes: a second capacitor, a third capacitor and a third inductor; The first end of the second capacitor and the first end of the third inductor are connected to the input end of the low-pass circuit, the first end of the third capacitor and the second end of the third inductor are connected to the output end of the low-pass circuit, and the second end of the second capacitor and the second end of the third capacitor are connected to the ground end.

10. A radio frequency chip, characterized in that: include: A substrate and a power amplifier, wherein the power amplifier is arranged on the substrate, wherein the power amplifier is the power amplifier according to any one of claims 1 to 9.

11. A base station, characterized in that: include: A baseband processing circuit and a radio frequency front-end circuit, wherein the baseband processing circuit is connected to the radio frequency front-end circuit, and the radio frequency front-end circuit includes a power amplifier, and the power amplifier is the power amplifier according to any one of claims 1 to 9.

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