Eight-phase clock circuit and delay method

Abstract

The invention relates to an eight-phase clock circuit, which comprises a four-phase clock generation circuit, an eight-phase clock generation circuit and an eight-phase clock delay circuit, and is characterized in that the four-phase clock generation circuit is used for generating an orthogonal four-phase clock; the eight-phase clock generation circuit comprises first to fourth phase interpolators, and is used for performing interpolation between adjacent phases through the first to fourth phase interpolators based on the four-phase clock as input to generate an initial eight-phase clock; the eight-phase clock delay circuit comprises a fifth phase interpolator to an eighth phase interpolator, and is used for carrying out interpolation between adjacent phases through the fifth phase interpolator to the eighth phase interpolator based on the initial eight-phase clock as input to generate a delayed eight-phase clock. Therefore, the problems that the PVT characteristic of the circuit is poor and a plurality of frequency dividers are needed during high-speed clock input are solved. The PVT performance of the circuit during high-speed clock input is improved, and the circuit structure is simplified.

Description

Technical Field

[0001] The present invention relates to the field of circuit technologies, and particularly to an eight-phase clock circuit and a delay method. Background Art

[0002] With the rapid development of Internet technologies and multimedia, to adapt to the explosive growth of bandwidth requirements and meet protocol requirements, the data rate of high-speed serial interface circuits must increase accordingly. To increase the single-channel data rate, in addition to doubling the clock operating frequency, multi-phase clocks are another necessary means.

[0003] In related technologies, there are usually two methods for generating multi-phase clocks: (1) an open-loop circuit structure based on a delay line or an inverter chain, and (2) a structure based on a frequency divider.

[0004] However, in related technologies: (1) For the open-loop circuit structure based on a delay line or an inverter chain, due to the large delay of the delay unit, the circuit (Process Voltage Temperature, PVT) characteristics are poor, the resolution is poor, and the resolution is different under different PVTs; (2) For the structure based on a frequency divider, if an eight-phase clock circuit is generated with differential clocks, the frequency divider needs to be used for frequency division twice, and the frequency requirement of the input clock is 4 times that of the highest-speed clock. When the highest-speed clock is relatively fast, this method cannot be used to achieve it, which urgently needs to be solved. Summary of the Invention

[0005] The present invention provides an eight-phase clock circuit and a delay method to solve the problems in related technologies that the circuit PVT characteristics are poor and multiple frequency dividers are required when a high-speed clock is input, improve the PVT performance of the circuit when a high-speed clock is input, and simplify the circuit structure.

[0006] In a first aspect embodiment of the present invention, an eight-phase clock circuit is provided, including: a four-phase clock generation circuit, an eight-phase clock generation circuit, and an eight-phase clock delay circuit. Among them, the four-phase clock generation circuit is used to generate orthogonal four-phase clocks; the eight-phase clock generation circuit includes first to fourth phase interpolators, and is used to generate initial eight-phase clocks by performing interpolation between adjacent phases respectively based on the four-phase clocks through the first to fourth phase interpolators; the eight-phase clock delay circuit includes fifth to eighth phase interpolators, and is used to generate delayed eight-phase clocks by performing interpolation between adjacent phases respectively based on the initial eight-phase clocks through the fifth to eighth phase interpolators.

[0007] Further, in some embodiments, the eight-phase clock circuit further includes: a clock output circuit, which is used to process the delayed eight-phase clocks and output the processed results.

[0008] Further, in some embodiments, the clock output circuit includes: a high-speed clock frequency division circuit, a duty cycle correction circuit, a quadrature correction circuit, and a transceiver circuit. The high-speed clock frequency division circuit is configured to generate a four-phase 1 / 4-speed clock based on the delayed eight-phase clock. The duty cycle correction circuit is configured to perform duty cycle correction on the four-phase 1 / 4-speed clock to obtain a four-phase clock with corrected duty cycle. The quadrature correction circuit is configured to perform quadrature correction on the four-phase clock with corrected duty cycle to obtain a four-phase clock with corrected quadrature. The clock output circuit is configured to output the four-phase clock with corrected quadrature.

[0009] Further, in some embodiments, the four-phase clock generation circuit includes: a buffer register and a frequency divider. The buffer register is configured to store and register the input clock. The frequency divider is configured to generate the orthogonal four-phase clock from the input clock stored in the buffer register.

[0010] Further, in some embodiments, the input clock of the four-phase clock generation circuit is a 32 GHz differential clock.

[0011] Further, in some embodiments,

[0012] The control code of the first phase interpolator is the same as that of the third phase interpolator, and the control code of the second phase interpolator is the same as that of the fourth phase interpolator.

[0013] Further, in some embodiments, the control codes of the fifth to eighth phase interpolators are all the same.

[0014] According to the eight-phase clock circuit provided by the embodiments of the present invention, an orthogonal four-phase clock is generated by the four-phase clock generation circuit, and an initial eight-phase clock is generated by the eight-phase clock generation circuit, and then a delayed eight-phase clock is generated by the eight-phase clock delay circuit, which solves the problems of poor PVT characteristics of the circuit and the need for multiple frequency dividers when a high-speed clock is input. The PVT performance of the circuit when a high-speed clock is input is improved, and the circuit structure is simplified.

[0015] An embodiment of the second aspect of the present invention provides a delay method based on an eight-phase clock circuit, using the eight-phase clock circuit as described in any one of the above. The method includes: generating an orthogonal four-phase clock by the four-phase clock generation circuit; generating an initial eight-phase clock by the eight-phase clock generation circuit including the first to fourth phase interpolators, based on the four-phase clock as an input, and performing interpolation between adjacent phases by the first to fourth phase interpolators respectively; generating a delayed eight-phase clock by the eight-phase clock delay circuit including the fifth to eighth phase interpolators, based on the initial eight-phase clock as an input, and performing interpolation between adjacent phases by the fifth to eighth phase interpolators respectively.

[0016] Further, in some embodiments, the delayed eight-phase clock is processed by a clock output circuit, and the processed result is output.

[0017] Further, in some embodiments, the eight-phase clock output circuit is configured to implement the transmission and reception functions of a clock signal based on the delayed eight-phase clock, including: generating a four-phase 1 / 4-speed clock based on the delayed eight-phase clock through a high-speed clock frequency division circuit; performing duty cycle correction on the four-phase 1 / 4-speed clock through a duty cycle correction circuit to obtain a four-phase clock after duty cycle correction; performing quadrature correction on the four-phase clock after duty cycle correction through the quadrature correction circuit to obtain a four-phase clock after quadrature correction. The four-phase clock after quadrature correction is output through the clock output circuit.

[0018] According to the delay method based on an eight-phase clock circuit provided by an embodiment of the present invention, an orthogonal four-phase clock is generated by a four-phase clock generation circuit, an initial eight-phase clock is generated by an eight-phase clock generation circuit, and then a delayed eight-phase clock is generated by an eight-phase clock delay circuit, solving the problems of poor PVT characteristics of the circuit and the need for multiple frequency dividers when a high-speed clock is input. The PVT performance of the circuit when a high-speed clock is input is improved, and the circuit structure is simplified.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0021] Figure 1 FIG. [FIG. NUMBER] is a schematic block diagram of an eight-phase clock circuit provided according to an embodiment of the present invention;

[0022] Figure 2 FIG. [FIG. NUMBER] is a schematic structural diagram of an eight-phase clock circuit provided according to a specific embodiment of the present invention;

[0023] Figure 3 FIG. [FIG. NUMBER] is a schematic diagram of a high-speed clock frequency division circuit provided according to a specific embodiment of the present invention;

[0024] Figure 4 FIG. [FIG. NUMBER] is a schematic structural diagram of an interpolator circuit provided according to a specific embodiment of the present invention;

[0025] Figure 5 FIG. [FIG. NUMBER] is a schematic diagram of a simulation result waveform provided according to a specific embodiment of the present invention;

[0026] Please note that the specific figure numbers in the translated text are replaced with placeholders "[FIG. NUMBER]" as the original figure numbers are not provided in the given text. You may need to substitute the actual figure numbers according to the specific content in the original patent document.Figure 6 A flowchart of a delay method based on an eight-phase clock circuit according to an embodiment of the present invention. Detailed implementation manners

[0027] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present invention, and should not be construed as a limitation to the present invention.

[0028] The eight-phase clock circuit and the delay method according to the embodiments of the present invention will be described below. In view of the problems mentioned in the above background art that the circuit PVT characteristics are poor and multiple frequency dividers are required when a high-speed clock is input, the present invention provides an eight-phase clock circuit, which generates orthogonal four-phase clocks through a four-phase clock generation circuit, generates an initial eight-phase clock through an eight-phase clock generation circuit, and then generates a delayed eight-phase clock through an eight-phase clock delay circuit, thereby solving the problems that the circuit PVT characteristics are poor and multiple frequency dividers are required when a high-speed clock is input. The PVT performance of the circuit when a high-speed clock is input is improved, and the circuit structure is simplified.

[0029] Specifically, Figure 1 A schematic block diagram of an eight-phase clock circuit according to an embodiment of the present invention.

[0030] As Figure 1 shown, the eight-phase clock circuit 10 includes: a four-phase clock generation circuit 100, an eight-phase clock generation circuit 200, and an eight-phase clock delay circuit 300. Among them, the four-phase clock generation circuit 100 is used to generate orthogonal four-phase clocks; the eight-phase clock generation circuit 200 includes first to fourth phase interpolators, and is used to generate an initial eight-phase clock by interpolating between adjacent phases based on the four-phase clock as an input through the first to fourth phase interpolators respectively; the eight-phase clock delay circuit 300 includes fifth to eighth phase interpolators, and is used to generate a delayed eight-phase clock by interpolating between adjacent phases based on the initial eight-phase clock as an input through the fifth to eighth phase interpolators respectively.

[0031] Among them, the orthogonal four-phase clock is a clock signal with four-phase outputs and a 90-degree difference between each phase output; the phase interpolator takes the 4 orthogonal phases of the four-phase clock as inputs, utilizes the principle of an analog adder, and obtains multi-phase signals with different interpolation ratios by regulating the ratio of the tail currents of the differential pairs.

[0032] Among them, in some embodiments, the input clock of the four-phase clock generation circuit 100 is a 32 GHz differential clock.

[0033] As Figure 2 shown, Figure 2Schematic diagram of an eight-phase clock circuit structure provided according to a specific embodiment of the present invention. In this eight-phase clock circuit 20, the four-phase clock generation circuit 100 includes: a buffer register and a frequency divider. Among them, the buffer register is used to store and register the input clock; the frequency divider is used to generate four orthogonal-phase clocks from the input clock stored in the buffer register.

[0034] As a possible implementation, the angle of each phase of the 32 GHz differential clock signal is 0 degrees and 180 degrees. The 32 GHz differential clock signal is cached by the buffer register buffer and frequency-divided by the frequency divider divider to generate four natural orthogonal 16 GHz clocks. Among them, the angle of each phase of the orthogonal 16 GHz clocks is 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively.

[0035] Furthermore, in some embodiments, the eight-phase clock circuit 10 further includes: a clock output circuit 400. The clock output circuit is used to process the delayed eight-phase clock and output the processed result.

[0036] Among them, in some embodiments, the eight-phase clock output circuit 400 includes: a high-speed clock frequency divider circuit, a duty cycle correction circuit, an orthogonality correction circuit, and a transceiver circuit. Among them, the high-speed clock frequency divider circuit is used to generate a four-phase 1 / 4-speed clock; the duty cycle correction circuit is used to correct the duty cycle of the four-phase 1 / 4-speed clock to obtain a four-phase clock with a corrected duty cycle; the orthogonality correction circuit is used to correct the orthogonality of the four-phase clock with a corrected duty cycle to obtain a four-phase clock with a corrected orthogonality; the clock output circuit is used to output the four-phase clock with a corrected orthogonality.

[0037] As Figure 3 shown, Figure 3 Schematic diagram of a high-speed clock frequency divider circuit provided according to an embodiment of the present invention. The first stage of this high-speed clock CML frequency divider circuit is a CML Latch that is transparent to the low level of the clock, and the second stage is a CMLLatch that is transparent to the high level of the clock. Combined into a master-slave structure rising-edge-triggered CML DFF, and cross-coupling its output terminal with the input terminal, a clock frequency divider circuit is obtained. This frequency divider circuit outputs a four-phase 1 / 4-speed clock (16 GHz) and has good duty cycle and IQ phase accuracy.

[0038] As a possible implementation, the duty cycle correction circuit selects a (Digital Clock Correction, DCC) correction circuit. Through components such as digital logic and counters, it can accurately measure and adjust the duty cycle of the pulse signal, control the duty cycle error within a small range, and has good stability; the quadrature correction circuit selects a (Quadrature Error Correction, QEC) correction circuit. Through the built-in correction algorithm and circuit structure, it controls the amplitude difference and phase deviation of the quadrature signal within a very small range, thereby improving the accuracy and reliability of signal processing; the transceiver circuit is TX / RX, which is usually used to clearly distinguish the transmission direction of the signal, facilitating the connection and debugging of the device.

[0039] Further, in some embodiments, the control code of the first phase interpolator is the same as the control code of the third phase interpolator, and the control code of the second phase interpolator is the same as the control code of the fourth phase interpolator.

[0040] Among them, the control code of the first phase interpolator and the control code of the third phase interpolator are the first control code, the control code of the second phase interpolator and the control code of the fourth phase interpolator are the second control code. The first control code and the second control code are control instructions for interpolator output phases in the octal clock generation circuit 200. For example, if the second control code has a 45-degree phase delay relative to the first control code, then under the control of the second control code, the phase output of the interpolator has a 45-degree delay compared to the output of the interpolator under the control of the first control code; the interpolation control is a control method for phase control of the output of the interpolator according to a preset phase delay angle.

[0041] Figure 4 It is a schematic diagram of the interpolator circuit structure provided according to a specific embodiment of the present invention. Among them, in combination with Figure 2 And Figure 4, in some embodiments, the first interpolator PI1, the second interpolator PI2, the third interpolator PI3, and the fourth interpolator PI4 in the eight-phase clock generation circuit 200 adopt two sets of control codes, namely the first control code CTRL1 and the second control code CTRL2. Among them, the delay of the second control code CTRL2 is 45 degrees more than that of the first control code CTRL1. The first interpolator PI1 and the third interpolator PI3 are controlled by the first control code CTRL1, and the second interpolator PI2 and the fourth interpolator PI4 are controlled by the second control code CTRL2; the inputs of the first interpolator PI1 and the second interpolator PI2 are the 0-degree, 90-degree, 180-degree, and 270-degree clocks in sequence, and the inputs of the third interpolator PI3 and the fourth interpolator PI4 are the 90-degree, 180-degree, 270-degree, and 0-degree clocks in sequence; if the output of the first interpolator PI1 is the 0-degree / 180-degree clock, since the first interpolator PI1 is controlled by the first control code CTRL1 and the second interpolator PI2 is controlled by the second control code CTRL2, the output of the second interpolator PI2 is the 45-degree / 225-degree clock.

[0042] Furthermore, due to the different input connection methods of the third interpolator PI3, the 0-degree input of the third interpolator PI3 is connected to the 90-degree of the actual clock. Therefore, when controlled by the first control code CTRL1, the output of the third interpolator PI3 is the 90-degree / 270-degree clock. Similarly, since the third interpolator PI3 is controlled by the first control code CTRL1 and the fourth interpolator PI4 is controlled by the second control code CTRL2, the output of the fourth interpolator PI4 is the 135-degree / 315-degree clock.

[0043] Thus, when PVT changes, the first control code CTRL1 and the second control code CTRL2 can be changed to keep the delay of the second control code CTRL2 45 degrees more than that of the first control code CTRL1, and it divides the frequency one less time than the method based on the frequency divider. In the high-speed clock circuit, there is no need to double the frequency of the input clock. The schematic diagram of the simulation result waveform is as Figure 5 shown, where the eight-phase clock waveform schematic diagrams from top to bottom are the 0-degree, 45-degree, 90-degree, 135-degree, 180-degree, 225-degree, 270-degree, and 315-degree clock waveforms respectively.

[0044] Furthermore, in some embodiments, the control codes of the fifth to eighth phase interpolators are the same.

[0045] Among them, the control codes of the fifth to eighth phase interpolators are the third control code, and the third control code is a control instruction for controlling the output phase of the interpolator in the eight-phase clock delay circuit 300. For example, under the control of the third control code, the interpolator in the eight-phase clock delay circuit 300 does not change the relative phase but only changes the delay angle of the interpolator.

[0046] As a possible implementation method, the fifth interpolator PI5, the sixth interpolator PI6, the seventh interpolator PI7 and the eighth interpolator PI8 share the third control code CTRL, but the starting phases of the input orthogonal clocks are different. If the output of the first interpolator PI1 is a 0 degree / 180 degree clock, the input of the second interpolator PI2 is connected to 45 degrees of the actual clock, so the output of the second interpolator PI2 is a 45 degree / 225 degree clock. Similarly, the output of the third interpolator PI3 is a 90 degree / 270 degree clock, and the output of the fourth interpolator PI4 is a 135 degree / 315 degree clock. The input of the fifth interpolator PI5 is The angles of interest are 0 degrees, 90 degrees, 180 degrees and 270 degrees. Under the control of the third control code CTRL, the output of the fifth interpolator PI5 is 0 degrees and 180 degrees; the input of the sixth interpolator PI6 is 45 degrees, 135 degrees, 225 degrees and 315 degrees, and the output of the sixth interpolator PI6 is 45 degrees and 225 degrees; the input of the seventh interpolator PI7 is 90 degrees, 180 degrees, 270 degrees and 0 degrees, and the output of the seventh interpolator PI7 is 90 degrees and 270 degrees; the input of the eighth interpolator PI8 is 135 degrees, 225 degrees, 315 degrees and 45 degrees, and the output of the eighth interpolator PI8 is 135 degrees and 315 degrees.

[0047] Therefore, when the third control code CTRL changes, only the interpolator delay is changed, and the relative phases of the eight-phase clocks remain unchanged, thus achieving common delay control of the eight-phase clocks. Furthermore, PVT only affects the common delay of the eight-phase clocks and does not change the phase relationships of the eight-phase clocks, thus achieving a common delay output.

[0048] The eight-phase delay circuit provided by the embodiments of the present invention generates an orthogonal four-phase clock using a four-phase clock generation circuit, generates an initial eight-phase clock using an eight-phase clock generation circuit, and then generates a delayed eight-phase clock using an eight-phase clock delay circuit. This solves the problem of poor PVT characteristics of the circuit when high-speed clock input is used and requires multiple frequency dividers. This improves the circuit's PVT performance when high-speed clock input is used and simplifies the circuit structure.

[0049] Next, a delay method based on an eight-phase clock circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0050] Figure 6 The figure is a flow chart of a delay method based on an eight-phase clock circuit according to an embodiment of the present invention.

[0051] like Figure 6 As shown, the delay method based on the eight-phase clock circuit includes the following steps:

[0052] In step S601 , a four-phase clock generating circuit generates a four-phase clock having quadrature phases.

[0053] In step S602, an eight-phase clock generation circuit including first to fourth phase interpolators generates an initial eight-phase clock by taking a four-phase clock as an input and performing interpolation between adjacent phases through the first to fourth phase interpolators respectively.

[0054] In step S603, an eight-phase clock delay circuit including fifth to eighth phase interpolators generates a delayed eight-phase clock by taking the initial eight-phase clock as an input and performing interpolation between adjacent phases through the fifth to eighth phase interpolators respectively.

[0055] Further, in some embodiments, a clock output circuit processes the delayed eight-phase clock and outputs the processed result.

[0056] Further, in some embodiments, an eight-phase clock output circuit is used to implement the sending and receiving functions of a clock signal based on the delayed eight-phase clock, including: generating a four-phase 1 / 4-speed clock based on the delayed eight-phase clock through a high-speed clock frequency division circuit; performing duty cycle correction on the four-phase 1 / 4-speed clock through a duty cycle correction circuit; performing quadrature correction on the four-phase clock after duty cycle correction through a quadrature correction circuit to obtain a quadrature-corrected four-phase clock. The quadrature-corrected four-phase clock is output through a transceiver circuit.

[0057] It should be noted that the above explanation of the eight-phase clock circuit embodiment also applies to the delay method based on the eight-phase clock circuit of this embodiment, and will not be elaborated here.

[0058] According to the delay method based on the eight-phase clock circuit proposed by the embodiment of the present invention, an orthogonal four-phase clock is generated by a four-phase clock generation circuit, an initial eight-phase clock is generated by an eight-phase clock generation circuit, and then a delayed eight-phase clock is generated by an eight-phase clock delay circuit, solving the problems of poor PVT characteristics of the circuit and the need for multiple frequency dividers when a high-speed clock is input. The PVT performance of the circuit when a high-speed clock is input is improved, and the circuit structure is simplified.

[0059] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or N embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "N" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0061] Any process or method description in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more N executable instructions for implementing a customized logical function or process. The scope of the preferred embodiments of the present invention includes additional implementations where functions may be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0062] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0063] Those of ordinary skill in the art of the present technology can understand that all or part of the steps carried by the method of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

Claims

1. An eight-phase clock circuit, characterized in that: include: Four-phase clock generation circuit, eight-phase clock generation circuit and eight-phase clock delay circuit, wherein, The four-phase clock generating circuit is used to generate an orthogonal four-phase clock; The eight-phase clock generation circuit includes first to fourth phase interpolators, which are used to generate an initial eight-phase clock based on the four-phase clock as input and interpolate between adjacent phases through the first to fourth phase interpolators respectively; The eight-phase clock delay circuit includes fifth to eighth phase interpolators, which are used to interpolate between adjacent phases based on the initial eight-phase clock as input to generate a delayed eight-phase clock through the fifth to eighth phase interpolators.

2. The eight-phase clock circuit according to claim 1, wherein: Also includes: The clock output circuit is used to process the delayed eight-phase clock and output the processed result.

3. The eight-phase clock circuit according to claim 2, wherein: The clock output circuit includes: a high-speed clock frequency division circuit, a duty cycle correction circuit, an orthogonal correction circuit and a transceiver circuit, wherein: The high-speed clock frequency dividing circuit is used to generate a four-phase 1 / 4 speed clock based on the delayed eight-phase clock; The duty cycle correction circuit is used to perform duty cycle correction on the four-phase 1 / 4 speed clock to obtain a four-phase clock after duty cycle correction; The quadrature correction circuit is used to perform quadrature correction on the duty cycle-corrected four-phase clock to obtain a quadrature-corrected four-phase clock; The clock output circuit is used to output the quadrature-corrected four-phase clock.

4. The eight-phase clock circuit according to claim 1, wherein: The four-phase clock generating circuit includes a buffer register and a frequency divider, wherein: The buffer register is used to store the input clock; The frequency divider is used to generate the orthogonal four-phase clock by storing the input clock in the buffer register.

5. The eight-phase clock circuit according to claim 4, characterized in that: The input clock of the four-phase clock generation circuit is a 32 GHz differential clock.

6. The eight-phase clock circuit according to claim 1, wherein: The control code of the first phase interpolator is the same as the control code of the third phase interpolator, and the control code of the second phase interpolator is the same as the control code of the fourth phase interpolator.

7. The eight-phase clock circuit according to claim 1, wherein: The control codes of the fifth to eighth phase interpolators are all the same.

8. A delay method based on an eight-phase clock circuit, characterized in that: The eight-phase clock circuit according to any one of claims 1 to 7 is used, wherein the method comprises the following steps: Generate an orthogonal four-phase clock by the four-phase clock generating circuit; The eight-phase clock generating circuit including the first to fourth phase interpolators generates an initial eight-phase clock based on the four-phase clock as input and interpolating between adjacent phases through the first to fourth phase interpolators respectively; The eight-phase clock delay circuit including the fifth to eighth phase interpolators takes the initial eight-phase clock as input and interpolates between adjacent phases through the fifth to eighth phase interpolators to generate a delayed eight-phase clock.

9. The method according to claim 8, characterized in that The delay method based on the eight-phase clock circuit includes: The delayed eight-phase clock is processed by a clock output circuit, and the processed result is output.

10. The method according to claim 8, characterized in that An eight-phase clock output circuit is used to implement the sending and receiving functions of clock signals based on the delayed eight-phase clock, including: Generating a four-phase 1 / 4 speed clock based on the delayed eight-phase clock through a high-speed clock frequency dividing circuit; Performing duty cycle correction on the four-phase 1 / 4 speed clock by a duty cycle correction circuit to obtain a four-phase clock after duty cycle correction; Performing quadrature correction on the duty cycle-corrected four-phase clock by the quadrature correction circuit to obtain a quadrature-corrected four-phase clock; The quadrature-corrected four-phase clock is outputted through the clock output circuit.

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