Phase-locked loop and control method thereof, chip, communication system, electronic equipment and medium

Abstract

The invention relates to a phase-locked loop and a control method thereof, a chip, a communication system, electronic equipment and a medium, and the method comprises the steps: obtaining a first analog voltage signal outputted by a filter in the phase-locked loop, and adjusting a control bit value of a capacitor array of a voltage-controlled oscillator in the phase-locked loop according to the first analog voltage signal, therefore, the effective capacitance value of the capacitor array is changed, and the output frequency of the voltage-controlled oscillator is adjusted. According to the method, the linearity of the phase-locked loop is improved by adjusting the control bit value of the capacitor array, so that the stability of the output frequency of the voltage-controlled oscillator can be ensured.

Description

Technical Field

[0001] The present application relates to the technical field of phase-locked loops, and in particular to a phase-locked loop and a control method, chip, communication system, electronic device, and medium thereof. Background Art

[0002] In phase-locked loop (PLL) design, the voltage-controlled oscillator (VCO) is a core component that generates an output signal with adjustable frequency characteristics based on a received control voltage. Therefore, the performance of the VCO is directly related to the stability and reliability of the overall PLL system. However, in practical applications, environmental changes (such as temperature fluctuations) often cause control voltage offsets, resulting in poor PLL linearity and, consequently, affecting the stability of the VCO's output frequency. Summary of the Invention

[0003] This application provides a phase-locked loop and its control method, chip, communication system, electronic device, and medium. The technical solution of this application is as follows:

[0004] A first embodiment of the present application provides a phase-locked loop control method, including:

[0005] Acquire a first analog voltage signal output by a filter in the phase-locked loop;

[0006] According to the first analog voltage signal, the control bit value of the capacitor array of the voltage controlled oscillator in the phase-locked loop is adjusted to adjust the output frequency of the voltage controlled oscillator.

[0007] The second embodiment of the present application provides a phase-locked loop, comprising: a filter, a processing module and a voltage-controlled oscillator connected in sequence; wherein,

[0008] The filter is configured to output a first analog voltage signal;

[0009] The processing module is configured to receive the first analog voltage signal and adjust a control bit value of a capacitor array in the voltage-controlled oscillator according to the first analog voltage signal, so as to adjust an output frequency of the voltage-controlled oscillator.

[0010] A third embodiment of the present application provides a chip, including: a phase-locked loop as described above.

[0011] A fourth embodiment of the present application proposes a communication system, including: a phase-locked loop as described above.

[0012] The fifth aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the above method are implemented.

[0013] The sixth aspect embodiment of the present application proposes a non-temporary computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the steps of the above method when executed by a processor.

[0014] The seventh aspect of the present application provides a computer program product, including a computer program, which implements the steps of the above method when executed by a processor.

[0015] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:

[0016] The control method for a phase-locked loop (PLL) according to an embodiment of the present application first obtains a first analog voltage signal output by a filter in the PLL. Based on the first analog voltage signal, the control bit value of the capacitor array of a voltage-controlled oscillator in the PLL is adjusted to change the effective capacitance of the capacitor array, thereby adjusting the output frequency of the voltage-controlled oscillator. Thus, by adjusting the control bit value of the capacitor array, the method improves the linearity of the PLL circuit, thereby ensuring the stability of the output frequency of the voltage-controlled oscillator.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application, and do not constitute an improper limitation on the present application.

[0019] Figure 1 is a block diagram of a phase-locked loop according to an embodiment of the present application;

[0020] Figure 2 is a schematic structural diagram of a phase-locked loop according to an embodiment of the present application;

[0021] Figure 3 is a structural diagram of a voltage-controlled oscillator according to an embodiment of the present application;

[0022] Figure 4 is a flow chart of phase-locked loop control according to one embodiment of the present application;

[0023] Figure 5 is a schematic diagram of a communication system according to an embodiment of the present application;

[0024] Figure 6 is a flow chart of a phase-locked loop control method according to one embodiment of the present application;

[0025] Figure 7 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable ordinary people in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0027] It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0028] The following describes a phase-locked loop and its control method, chip, communication system, electronic device and medium according to embodiments of the present application with reference to the accompanying drawings.

[0029] Figure 1 is a schematic diagram of a phase-locked loop according to an embodiment of the present application.

[0030] like Figure 1 As shown, the phase-locked loop 100 of the embodiment of the present application includes: a filter 110, a processing module 120 and a voltage-controlled oscillator 130 connected in sequence.

[0031] The filter 110 is configured to output a first analog voltage signal, and the processing module 120 is configured to receive the first analog voltage signal and adjust the control bit value of the capacitor array in the voltage controlled oscillator 130 according to the first analog voltage signal to adjust the output frequency of the voltage controlled oscillator 130.

[0032] In this embodiment, after receiving the first analog voltage signal output by the filter 110, the processing module 120 first converts the first analog voltage signal into a corresponding digital signal, then determines the relationship between the voltage value represented by the digital signal and the set voltage range, and adjusts the control bit value of the capacitor array accordingly based on the determination result. Specifically, if the determination result indicates that the voltage value is greater than the upper limit of the set voltage range (e.g., Vdd / 2+5mV), the control bit value of the capacitor array is reduced to reduce the effective capacitance value of the voltage-controlled oscillator 130; if the determination result indicates that the voltage value is less than the lower limit of the set voltage range (e.g., Vdd / 2-5mV), the control bit value of the capacitor array is increased to increase the effective capacitance value of the voltage-controlled oscillator 130. Vdd is the power supply voltage of the charge pump.

[0033] Therefore, the phase-locked loop of the embodiment of the present application adjusts the control bit value of the capacitor array according to the first analog voltage signal at the output end of the filter to change the effective capacitance value of the capacitor array, thereby improving the linearity of the phase-locked loop and ensuring the stability of the output frequency of the voltage-controlled oscillator.

[0034] Figure 2 2 is a schematic structural diagram of a phase-locked loop according to an embodiment of the present application.

[0035] like Figure 2 As shown, the processing module 120 of the embodiment of the present application includes: an analog-to-digital conversion unit 121 and a digital signal processing unit 122. The analog-to-digital conversion unit 121 is used to convert the first analog voltage signal (ie Figure 2 The voltage at the midpoint 1) is converted into analog to digital to obtain a corresponding digital signal; the digital signal processing unit 122 is used to adjust the control bit value of the capacitor array accordingly according to the relationship between the voltage value represented by the digital signal and the set voltage range.

[0036] In this embodiment, after receiving the first analog voltage signal output by the filter 110, the processing module 120 first converts the first analog voltage signal into a corresponding digital signal through the analog-to-digital conversion unit 121, and sends the digital signal to the digital signal processing unit 122. The digital signal processing unit 122 determines the relationship between the voltage value represented by the digital signal and the set voltage range, and adjusts the control bit value of the capacitor array accordingly based on the determination result.

[0037] The digital signal processing unit 122 is configured to:

[0038] When the voltage value is greater than the upper limit of the set voltage range, reducing the control bit value of the capacitor array;

[0039] When the voltage value is less than the lower limit of the set voltage range, the control bit value of the capacitor array is increased.

[0040] In one embodiment of the present application, when the digital signal processing unit 122 is used to increase or decrease the control bit value of the capacitor array, it includes: increasing or decreasing the control bit value of the capacitor array until the adjusted voltage value falls within the set voltage range. For example, a binary search method is used to gradually increase or decrease the control bit value of the capacitor array until the adjusted voltage value falls within the set voltage range.

[0041] The binary search method is executed as follows:

[0042] Set the minimum value min and maximum value max of the control bit value of the capacitor array;

[0043] Take the middle value mid = (min + max) / 2 of the current search range and use it as the current control bit value;

[0044] Adjusting the switch state of the capacitor array according to the current control bit value to change the effective capacitance value of the capacitor array;

[0045] Measuring the first analog voltage signal output by the filter 110, and comparing the voltage value represented by the digital signal corresponding to the first analog voltage signal with the upper limit and lower limit of the set voltage range;

[0046] If the voltage value is less than the lower limit of the target voltage range, update min=mid+1, or if the voltage value is greater than the lower limit of the target voltage range, update max=mid-1, and continue the above search steps, gradually narrowing the search range until the voltage value falls within the target voltage range, then stop searching and confirm that the current control bit value is the target control bit value.

[0047] Therefore, the phase-locked loop of the embodiment of the present application uses a binary search method to adjust the voltage value represented by the digital signal corresponding to the first analog voltage signal output by the filter to the target voltage range, significantly improving the linearity of the phase-locked loop. In this state, the phase-locked loop 100 can provide a stable frequency output while also significantly improving its noise and spurious performance.

[0048] In one embodiment of the present application, before performing analog-to-digital conversion on the first analog voltage signal, the analog-to-digital conversion unit 121 is further configured to obtain a second analog voltage signal (i.e., Figure 2 The voltage at the midpoint 2 is obtained, and it is determined whether the second analog voltage signal matches the first analog voltage signal. If the second analog voltage signal is consistent with the first analog voltage signal, analog-to-digital conversion is performed on the first analog voltage signal.

[0049] The analog-to-digital converter 121 can be an analog-to-digital converter with a bandwidth of 1 MHz or greater. The high bandwidth of the analog-to-digital converter ensures that it can keep up with voltage fluctuations while meeting the voltage accuracy required for calibration, such as 5 mV. To achieve this voltage accuracy requirement, an analog-to-digital converter with 8 significant bits can be used.

[0050] Figure 3 1 is a schematic structural diagram of a voltage-controlled oscillator according to an embodiment of the present application.

[0051] like Figure 3 As shown, the capacitor array in the voltage-controlled oscillator 130 of the embodiment of the present application includes: a plurality of capacitor units connected in parallel, each capacitor unit including at least one switch and at least one capacitor connected in series. For example, each capacitor unit includes one switch and two capacitors connected in series.

[0052] The processing module 120 is used to adjust the control bit value of the capacitor array in the voltage-controlled oscillator 130 by controlling the switch state of each capacitor unit to change the effective capacitance value of the capacitor array.

[0053] Figure 3 The illustrated voltage-controlled oscillator 130 does not rely on a large-scale varactor array structure. By reducing the equivalent parasitic capacitance of the entire voltage-controlled oscillator 130 at high frequencies, a single voltage-controlled oscillator 130 can achieve a wider frequency adjustment capability. Furthermore, by eliminating the cascade effect of the varactor array, the entire voltage-controlled oscillator 130 is significantly less sensitive to external noise and interference, effectively lowering the phase noise floor and improving the stability of the voltage-controlled oscillator 130 under wide-band operation.

[0054] To introduce other functional components in the phase-locked loop 100, continue to refer to Figure 2 The phase-locked loop 100 of the embodiment of the present application further includes:

[0055] The frequency divider 140 is configured to receive a clock signal to be divided, and generate and output a divided clock signal according to the clock signal to be divided;

[0056] The phase and frequency detector 150 is configured to receive the divided clock signal and the reference clock signal output by the reference clock source 160, and generate and output a pulse signal (including an up signal and a down signal) according to the phase and frequency difference between the divided clock signal and the reference clock signal;

[0057] The charge pump 170 is configured to receive the pulse signal and generate and output a control current signal according to the pulse signal;

[0058] The filter 110 is configured to receive the control current signal, filter the control current signal, and generate a first analog voltage signal at an output end of the filter 110;

[0059] The voltage-controlled oscillator 130 is used to generate and output a frequency-adjustable clock signal based on an equivalent voltage signal generated after adjusting the control bit value of the capacitor array;

[0060] The buffer 180 is used to receive a frequency-adjustable clock signal, amplify and shape the frequency-adjustable clock signal, and generate and output a clock signal to be divided.

[0061] Continue to refer to Figure 2 The phase-locked loop 100 of the embodiment of the present application further includes:

[0062] The modulator 190 is configured to receive a frequency control signal and generate and output a frequency division ratio according to the frequency control signal;

[0063] The frequency divider 140 is further configured to receive a frequency division ratio, and perform frequency division processing on the clock signal to be divided according to the frequency division ratio, to generate and output a frequency-divided clock signal.

[0064] In order to make those skilled in the art more clearly understand the phase-locked loop control process of this application, as shown in FIG. Figure 4 As shown, the phase-locked loop control process of this application includes the following steps:

[0065] S401, the phase-locked loop is initialized and enters the frequency calibration and locking phase.

[0066] S402: The analog-to-digital conversion unit converts the first analog voltage signal into a digital signal and sends the digital signal to the digital signal processing unit.

[0067] S403: The digital signal processing unit compares the voltage value represented by the digital signal with the set voltage range. If the voltage value is greater than the upper limit of the set voltage range, step S404 is executed; if the voltage value is less than the lower limit of the set voltage range, step S405 is executed.

[0068] S404: Reduce the capacitor array control gear value according to a binary search method.

[0069] S405 , increasing the capacitor array control gear value according to a binary search method.

[0070] S406, calibration is completed, and the first analog voltage signal is tracked and detected in real time.

[0071] S407: Determine whether the voltage value falls within the set voltage range. If yes, execute step S408; if not, return to execute step S402.

[0072] S408, continue tracking and detecting.

[0073] In summary, the phase-locked loop of the embodiment of the present application includes: a filter, a processing module, and a voltage-controlled oscillator connected in sequence; wherein the filter is used to output a first analog voltage signal; the processing module is used to receive the first analog voltage signal and, based on the first analog voltage signal, adjust the control bit value of the capacitor array in the voltage-controlled oscillator to change the effective capacitance value of the capacitor array, thereby adjusting the output frequency of the voltage-controlled oscillator. Therefore, the phase-locked loop of the present application improves the linearity of the phase-locked loop by adjusting the control bit value of the capacitor array, thereby ensuring the stability of the output frequency of the voltage-controlled oscillator.

[0074] Based on the above embodiments, the present application further proposes a chip, which includes the above phase-locked loop.

[0075] In the embodiments of the present application, the chip may be an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0076] Based on the above embodiments, the present application further proposes a communication system, which includes the above phase-locked loop.

[0077] In this embodiment, the phase-locked loop may be a radio frequency phase-locked loop, a baseband phase-locked loop, or a high-speed interface phase-locked loop.

[0078] Figure 5 is a schematic diagram of a communication system according to an embodiment of the present application.

[0079] like Figure 5 As described above, the communication system 1000 of the embodiment of the present application includes: a radio frequency phase-locked loop 1100, a baseband phase-locked loop 1200 and a high-speed interface phase-locked loop 1300.

[0080] Among them, the RF phase-locked loop 110 provides local oscillation clocks to the first mixer 1411 and the second mixer 1412 respectively to realize spectrum shifting of the signal; the baseband phase-locked loop 1200 is used to provide sampling clocks to the analog-to-digital converter 1511 and the digital-to-analog converter 1512 to ensure the accuracy and synchronization of data conversion; the high-speed interface phase-locked loop 1300 is used to provide data transmission clocks to the transmitting high-speed interface 1611 and the receiving high-speed interface 1622 to support stable transmission of high-speed data.

[0081] Figure 6 This is a flow chart of a phase-locked loop control method according to an embodiment of the present application.

[0082] like Figure 6 As shown, the control method of the phase-locked loop in the embodiment of the present application includes:

[0083] S1, obtaining a first analog voltage signal output by a filter in a phase-locked loop.

[0084] S2, adjusting the control bit value of the capacitor array of the voltage controlled oscillator in the phase-locked loop according to the first analog voltage signal to adjust the output frequency of the voltage controlled oscillator.

[0085] In one embodiment of the present application, adjusting a control bit value of a capacitor array of a voltage-controlled oscillator in a phase-locked loop according to a first analog voltage signal includes:

[0086] Performing analog-to-digital conversion on the first analog voltage signal to obtain a corresponding digital signal;

[0087] According to the relationship between the voltage value represented by the digital signal and the set voltage range, the control bit value of the capacitor array is adjusted accordingly.

[0088] In one embodiment of the present application, the control bit value of the capacitor array is adjusted accordingly based on the relationship between the voltage value represented by the digital signal and the set voltage range, including:

[0089] When the response voltage value is greater than the upper limit of the set voltage range, the control bit value of the capacitor array is reduced;

[0090] When the response voltage value is less than the lower limit of the set voltage range, the control bit value of the capacitor array is increased.

[0091] In one embodiment of the present application, increasing or decreasing the control bit value of the capacitor array includes:

[0092] Increase or decrease the control bit value of the capacitor array until the adjusted voltage value falls within the set voltage range.

[0093] In one embodiment of the present application, before performing analog-to-digital conversion on the first analog voltage signal, the method includes:

[0094] In response to the phase-locked loop being in a locked state, obtaining a second analog voltage signal input to the voltage-controlled oscillator;

[0095] It is determined that the second analog voltage signal matches the first analog voltage signal.

[0096] It should be noted that for details not disclosed in the control method of the phase-locked loop in the embodiment of the present application, please refer to the details disclosed in the phase-locked loop in the embodiment of the present application, and the details will not be described in detail here.

[0097] The control method for a phase-locked loop (PLL) according to an embodiment of the present application first obtains a first analog voltage signal output by a filter in the PLL. Based on the first analog voltage signal, the control bit value of the capacitor array of a voltage-controlled oscillator in the PLL is adjusted to change the effective capacitance of the capacitor array, thereby adjusting the output frequency of the voltage-controlled oscillator. Thus, by adjusting the control bit value of the capacitor array, the method improves the linearity of the PLL circuit, thereby ensuring the stability of the output frequency of the voltage-controlled oscillator.

[0098] In order to implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps of the above method are implemented.

[0099] Figure 7This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. For example, the electronic device 700 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0100] Reference Figure 7 , electronic device 700 may include one or more of the following components: a processing component 702 , a memory 704 , a power component 706 , a multimedia component 708 , an audio component 710 , an input / output (I / O) interface 712 , a sensor component 714 , and a communication component 716 .

[0101] The processing component 702 generally controls the overall operation of the electronic device 700, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 702 may include one or more processors 720 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 702 may include one or more modules to facilitate interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate interaction between the multimedia component 708 and the processing component 702.

[0102] The memory 704 is configured to store various types of data to support operations on the electronic device 700. Examples of such data include instructions for any application or method operating on the electronic device 700, contact data, phone book data, messages, pictures, videos, etc. The memory 704 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0103] The power component 706 provides power to the various components of the electronic device 700. The power component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 700.

[0104] The multimedia component 708 includes a screen that provides an output interface between the electronic device 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 708 includes a front camera and / or a rear camera. When the electronic device 700 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0105] The audio component 710 is configured to output and / or input audio signals. For example, the audio component 710 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 700 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 704 or transmitted via the communication component 716. In some embodiments, the audio component 710 also includes a speaker for outputting audio signals.

[0106] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0107] The sensor assembly 714 includes one or more sensors for providing various aspects of status assessment for the electronic device 700. For example, the sensor assembly 714 can detect the open / closed state of the electronic device 700, the relative positioning of components, such as the display and keypad of the electronic device 700. The sensor assembly 714 can also detect changes in the position of the electronic device 700 or a component of the electronic device 700, the presence or absence of user contact with the electronic device 700, the orientation or acceleration / deceleration of the electronic device 700, and temperature changes of the electronic device 700. The sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 714 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0108] The communication component 716 is configured to facilitate wired or wireless communication between the electronic device 700 and other devices. The electronic device 700 can access a wireless network based on a communication standard, such as WiFi, 4G, or a combination thereof. In an exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0109] In an exemplary embodiment, the electronic device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0110] In order to implement the above embodiments, the present application proposes a non-transitory computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the above method is implemented.

[0111] In order to implement the above embodiments, the present application proposes a computer program product, including a computer program, which implements the steps of the above method when executed by a processor.

[0112] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0113] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0114] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0115] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0116] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement the present invention: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0117] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0118] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0119] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

[0120] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the appended claims.

[0121] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A control method for a phase-locked loop, characterized in that: include: Acquire a first analog voltage signal output by a filter in the phase-locked loop; According to the first analog voltage signal, the control bit value of the capacitor array of the voltage controlled oscillator in the phase-locked loop is adjusted to adjust the output frequency of the voltage controlled oscillator.

2. The method according to claim 1, characterized in that The adjusting the control bit value of the capacitor array of the voltage-controlled oscillator in the phase-locked loop according to the first analog voltage signal includes: Performing analog-to-digital conversion on the first analog voltage signal to obtain a corresponding digital signal; According to the relationship between the voltage value represented by the digital signal and the set voltage range, the control bit value of the capacitor array is adjusted accordingly.

3. The method according to claim 2, characterized in that The adjusting the control bit value of the capacitor array accordingly according to the relationship between the voltage value represented by the digital signal and the set voltage range includes: In response to the voltage value being greater than an upper limit of the set voltage range, reducing a control bit value of the capacitor array; In response to the voltage value being less than a lower limit of the set voltage range, the control bit value of the capacitor array is increased.

4. The method according to claim 3, characterized in that Increasing or decreasing the control bit value of the capacitor array, comprising: The control bit value of the capacitor array is increased or decreased until the adjusted voltage value falls within the set voltage range.

5. The method according to claim 2, characterized in that Before performing analog-to-digital conversion on the first analog voltage signal, the method includes: In response to the phase-locked loop being in a locked state, acquiring a second analog voltage signal input to the voltage-controlled oscillator; It is determined that the second analog voltage signal matches the first analog voltage signal.

6. A phase-locked loop, characterized in that: include: A filter, a processing module and a voltage-controlled oscillator are connected in sequence; wherein, The filter is configured to output a first analog voltage signal; The processing module is configured to receive the first analog voltage signal and adjust a control bit value of a capacitor array in the voltage-controlled oscillator according to the first analog voltage signal, so as to adjust an output frequency of the voltage-controlled oscillator.

7. The phase-locked loop according to claim 6, wherein: The processing module includes: an analog-to-digital conversion unit, configured to perform analog-to-digital conversion on the first analog voltage signal to obtain a corresponding digital signal; The digital signal processing unit is used to adjust the control bit value of the capacitor array according to the relationship between the voltage value represented by the digital signal and the set voltage range.

8. The phase-locked loop according to claim 7, wherein: The digital signal processing unit is configured to adjust the control bit value of the capacitor array accordingly according to the relationship between the voltage value represented by the digital signal and the set voltage range, including: In response to the voltage value being greater than an upper limit of the set voltage range, reducing a control bit value of the capacitor array; In response to the voltage value being less than a lower limit of the set voltage range, the control bit value of the capacitor array is increased.

9. The phase-locked loop according to claim 8, wherein: When the digital signal processing unit is used to increase or decrease the control bit value of the capacitor array, it includes: Increase or decrease the control bit value of the capacitor array until the adjusted voltage value falls within the set voltage range.

10. The phase-locked loop according to claim 7, wherein: Before the analog-to-digital conversion is performed on the first analog voltage signal, the analog-to-digital conversion unit is further configured to: In response to the phase-locked loop being in a locked state, acquiring a second analog voltage signal input to the voltage-controlled oscillator; It is determined that the second analog voltage signal matches the first analog voltage signal.

11. The phase-locked loop according to any one of claims 6 to 10, characterized in that: The capacitor array comprises: a plurality of capacitor units connected in parallel, each of the capacitor units comprising at least one switch and at least one capacitor connected in series; Wherein, when the processing module is used to adjust the control bit value of the capacitor array in the voltage-controlled oscillator, it includes: The switch state of each capacitor unit is controlled to change the effective capacitance value of the capacitor array.

12. The phase-locked loop according to claim 11, wherein: The phase-locked loop further includes: A frequency divider, configured to receive a clock signal to be divided, and generate and output a divided clock signal according to the clock signal to be divided; a phase frequency detector, configured to receive the divided clock signal and a reference clock signal output by a reference clock source, and generate and output a pulse signal according to a phase and frequency difference between the divided clock signal and the reference clock signal; a charge pump, configured to receive the pulse signal, and generate and output a control current signal according to the pulse signal; The filter is configured to receive the control current signal, filter the control current signal, and generate the first analog voltage signal at the output end of the filter; The voltage-controlled oscillator is used to generate and output a frequency-adjustable clock signal according to an equivalent voltage signal generated after adjusting the control bit value of the capacitor array; The buffer is used to receive the frequency-adjustable clock signal, amplify and shape the frequency-adjustable clock signal, and generate and output the clock signal to be divided.

13. The phase-locked loop according to claim 12, wherein: The phase-locked loop further includes: a modulator, configured to receive a frequency control signal and generate and output a frequency division ratio according to the frequency control signal; The frequency divider is further configured to receive the frequency division ratio, and perform frequency division processing on the clock signal to be divided according to the frequency division ratio, to generate and output the divided clock signal.

14. A chip, characterized in that: include: A phase-locked loop as claimed in any one of claims 6 to 13.

15. A communication system, characterized in that: include: A phase-locked loop as claimed in any one of claims 6 to 13.

16. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method according to any one of claims 1 to 5 are implemented.

17. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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