Single-slope analog-to-digital converter and correction method

Abstract

The invention provides a single-slope analog-to-digital converter and a correction method. The single-slope analog-to-digital converter comprises a first component, a second component, a third component and a fourth component. The first component is used for selecting one of the first reference voltage, the second reference voltage and the voltage to be converted as output. The second component is used for comparing the output of the first component with the current voltage of the ramp signal. And the third component is used for outputting a corresponding measurement digital value according to the comparison result of the second component. And the fourth component is used for correcting the measurement conversion digital value into an ideal conversion digital value. Wherein the fourth component performs the correction at least according to a first measurement digital value and a first ideal digital value corresponding to the first reference voltage, and a second measurement digital value and a second ideal digital value corresponding to the second reference voltage.

Description

Technical Field

[0001] The present invention relates to a single-slope analog-to-digital converter and a calibration method; in particular, to a single-slope analog-to-digital converter and a calibration method for obtaining a digital value through calibration of a reference voltage. Background Art

[0002] Single-slope analog-to-digital converters (ADCs) offer the advantage of high resolution. However, due to their circuit architecture, single-slope ADCs have a low conversion rate. Therefore, single-slope ADCs are often used in systems that require precise judgment but have a relatively low output frequency. For example, in fingerprint recognition or image recognition systems, analog-to-digital conversion of the induced voltage generated by the pixel unit is required. Because fingerprint recognition or image recognition systems require high resolution and the output frequency is relatively low, single-slope ADCs are suitable for analog-to-digital conversion.

[0003] In existing technology, the conversion principle of a single-slope ADC is to compare an input signal (the signal to be converted) with a ramp voltage, and then use a counter to synchronously count the number of times. When the input signal and the ramp voltage produce a comparison result, the counter can obtain the digital value corresponding to the signal to be converted.

[0004] However, the ramp voltage is mostly generated by the system circuit, and the slope of the ramp voltage may cause slope deviation due to circuit differences or other factors. For example, please refer to Figure 1 , Figure 1 The relationship between the input signal (VIN) and the digital value (DOUT) can be converted using an ideal ramp voltage (I). Taking the analog voltage value (VP) as an example, the ideal digital value (DI) is obtained after the analog voltage value (VP) is converted using the ideal ramp voltage (I). However, if the ideal ramp voltage (I) deviates due to various factors, as indicated by the ramp signal (M), the measured digital value (DM) converted from the analog voltage value (VP) will differ from the ideal digital value (DI). This discrepancy between the measured digital value (DM) and the ideal digital value (DI) can lead to distortion or misjudgment in subsequent system decisions.

[0005] As can be seen from the above, in the architecture of the Single-Slope ADC, there are still many problems in the existing technology that need to be overcome and solved. Summary of the Invention

[0006] Therefore, the present invention proposes a single-slope analog-to-digital converter and a calibration method to effectively solve the problems encountered in the prior art.

[0007] One of the objectives of the present invention is to provide a single-slope analog-to-digital converter and a calibration method capable of correcting a slope voltage offset.

[0008] One of the objectives of the present invention is to provide a single-slope analog-to-digital converter and a calibration method that can prevent analog-to-digital conversion from being inaccurate due to various factors.

[0009] According to a preferred embodiment of the present invention, a single-slope analog-to-digital converter is provided. The single-slope analog-to-digital converter includes a first component, a second component, a third component, and a fourth component. The first component is configured to select one of a first reference voltage, a second reference voltage, and a voltage to be converted as an output. The second component is configured to compare the output of the first component with the current voltage of the ramp signal. The third component is configured to output a corresponding measured digital value based on the comparison result of the second component. The first reference voltage corresponds to the first measured digital value, the second reference voltage corresponds to the second measured digital value, and the voltage to be converted corresponds to the measured converted digital value. The fourth component is configured to perform calibration to calibrate the measured converted digital value to an ideal converted digital value. The fourth component performs calibration based on at least a first ideal digital value corresponding to the first reference voltage, a second ideal digital value corresponding to the second reference voltage, the first measured digital value, and the second measured digital value.

[0010] In one embodiment, the first reference voltage and the second reference voltage are selected from outside the possible voltage range of the voltage to be converted.

[0011] In one embodiment, the first reference voltage and the second reference voltage are smaller or larger than the voltage to be converted.

[0012] In one embodiment, the signal variation range of the ramp signal at least includes the possible voltage ranges of the first reference voltage, the second reference voltage, and the voltage to be converted.

[0013] In one embodiment, the first component is selected from one of a multiplexer, a selector, and a switch.

[0014] According to a preferred embodiment of the present invention, a single-slope analog-to-digital converter (ADC) is provided. The single-slope ADC includes a selection unit, a comparison unit, and a counting unit. The selection unit is configured to select one of a first reference voltage, a second reference voltage, and a voltage to be converted as an output based on a control signal. The first input of the comparison unit is coupled to the output of the selection unit, and the second input of the comparison unit is coupled to a ramp signal source to receive a ramp signal. When the current voltage of the ramp signal is a transition state compared to the voltage at the first input, a comparison result signal is output from the output of the comparison unit. The counting unit is coupled to the output terminal, wherein the counting unit counts digital values based on a clock signal and outputs a current measured digital value upon receiving the comparison result signal. The first reference voltage corresponds to a first measured digital value, the second reference voltage corresponds to a second measured digital value, and the voltage to be converted corresponds to a measured converted digital value. The measured converted digital value is corrected to an ideal converted digital value based on a first ideal digital value corresponding to the first reference voltage, a second ideal digital value corresponding to the second reference voltage, the first measured digital value, and the second measured digital value.

[0015] In one embodiment, the first reference voltage and the second reference voltage are selected from outside the possible voltage range of the voltage to be converted.

[0016] In one embodiment, the first reference voltage and the second reference voltage are smaller or larger than the voltage to be converted.

[0017] In one embodiment, the signal variation range of the ramp signal at least includes the possible voltage ranges of the first reference voltage, the second reference voltage, and the voltage to be converted.

[0018] In one embodiment, the single-slope analog-to-digital converter further includes a control unit coupled to the counting unit, the control unit being configured to provide a control signal; wherein the control signal is switched according to the generation of the comparison result signal.

[0019] In one embodiment, the single-slope analog-to-digital converter further includes a calibration unit coupled to the counting unit, the calibration unit being configured to store at least the first measured digital value and the second measured digital value and calibrate the measured converted digital value to an ideal converted digital value.

[0020] According to a preferred embodiment of the present invention, a calibration method for a single-slope analog-to-digital converter is provided. The calibration method includes: selecting one of a first reference voltage, a second reference voltage, and a voltage to be converted as a voltage to be compared; comparing the voltage to be compared with a current voltage of a ramp signal to output a comparison result signal; outputting a corresponding measured digital value based on the comparison result signal; wherein the first reference voltage corresponds to a first measured digital value, the second reference voltage corresponds to a second measured digital value, and the voltage to be converted corresponds to a measured converted digital value; and performing calibration to calibrate the measured converted digital value to an ideal converted digital value; wherein the calibration is based on at least a first ideal digital value corresponding to the first reference voltage, a second ideal digital value corresponding to the second reference voltage, the first measured digital value, and the second measured digital value.

[0021] In one embodiment, the first reference voltage and the second reference voltage are selected from outside the possible voltage range of the voltage to be converted.

[0022] In one embodiment, the first reference voltage and the second reference voltage are smaller or larger than the voltage to be converted.

[0023] In one embodiment, the signal variation range of the ramp signal at least includes the possible voltage ranges of the first reference voltage, the second reference voltage, and the voltage to be converted.

[0024] According to the single-slope analog-to-digital converter and calibration method described above, the offset of a ramp signal in the single-slope analog-to-digital converter is evaluated by providing a first reference voltage and a second reference voltage. Specifically, by inputting the first and second reference voltages, a first measured digital value corresponding to the first reference voltage and a second measured digital value corresponding to the second reference voltage are obtained. The first and second measured digital values are then calibrated against the first and second ideal digital values. This determines the offset of the ramp signal, which is then used to calibrate the measured converted digital value corresponding to the voltage to be converted to the ideal converted digital value. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings presented in this application are intended to help describe various embodiments of the present invention. However, to simplify the drawings and / or highlight the intended content, existing structures and / or elements in the drawings may be depicted in a simplified schematic manner or omitted. Furthermore, the number of elements in the drawings may be singular or plural. The drawings presented in this application are intended only to illustrate these embodiments and are not intended to limit them.

[0026] Figure 1 A schematic diagram illustrating how ramp signal offset causes errors in analog-to-digital conversion.

[0027] Figure 2FIG. 1 is a block diagram of a single-slope analog-to-digital converter according to a first embodiment of the present invention.

[0028] Figure 3A Schematic diagram illustrating the analog-to-digital conversion results for an ideal ramp signal.

[0029] Figure 3B A schematic diagram illustrating the analog-to-digital conversion results for an actual ramp signal.

[0030] Figure 4 Schematic diagram illustrating other configurations of the first reference voltage and the second reference voltage.

[0031] Figure 5 FIG. 1 is a block diagram of a single-slope analog-to-digital converter according to a second embodiment of the present invention.

[0032] Figure 6 FIG. 1 is a block diagram of a single-slope analog-to-digital converter with a control unit according to a second embodiment of the present invention.

[0033] Figure 7 FIG. 4 is a block diagram of a single-slope analog-to-digital converter with a calibration unit according to a second embodiment of the present invention.

[0034] Figure 8 FIG. 4 is a flow chart of a calibration method for a single-slope analog-to-digital converter according to a third embodiment of the present invention.

[0035] Description of main component symbols:

[0036] 10 Single-slope analog-to-digital converter

[0037] 11 First Component

[0038] 12 Second component

[0039] 13 Third Component

[0040] 14 Fourth Component

[0041] 20 Single-slope analog-to-digital converters

[0042] 21 Select Unit

[0043] 22 Comparison Unit

[0044] 221 First input

[0045] 222 Second input terminal

[0046] 223 output terminal

[0047] 23 counting units

[0048] 24 calibration units

[0049] 25 control unit

[0050] CA Correction / Correction Mechanism

[0051] CLK clock signal

[0052] CS control signal

[0053] DM measurement digital value / measurement conversion digital value

[0054] DMR1 first measurement digital value

[0055] DMR2 second measurement digital value

[0056] DI Ideal digital value / ideal conversion digital value

[0057] DIR1 First ideal digital value

[0058] DIR2 Second ideal digital value

[0059] DO current measured digital value

[0060] M Actual ramp signal

[0061] I Ideal ramp signal

[0062] V11, V21 voltage

[0063] VP voltage to be converted

[0064] VR1 first reference voltage

[0065] VR2 Second reference voltage

[0066] VRAMP ramp signal

[0067] RS ramp signal source

[0068] Steps S1, S2, S3, S4 DETAILED DESCRIPTION

[0069] Any reference to elements using names such as "first" and "second" in this article does not generally limit the number or order of these elements. On the contrary, these names are used as a convenient way to distinguish two or more elements or element instances in this article. Therefore, it should be understood that the names "first", "second" and the like in the claims do not necessarily correspond to the same names in the written description. In addition, it should be understood that the reference to the first and second elements does not mean that only two elements can be used or that the first element must be before the second element. As used herein, "comprising", "including", "having", "containing" and the like are all open terms, that is, they mean including but not limited to.

[0070] The term "coupled" is used herein to refer to direct or indirect electrical coupling between two structures. For example, in an example of indirect electrical coupling, one structure may be coupled to another structure via a passive element such as a resistor, capacitor, or inductor.

[0071] In this disclosure, the words "exemplary" and "for example" are used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. The terms "approximately" and "substantially," as used herein with respect to a specified value or characteristic, are intended to mean within a certain value (e.g., 10%) of the specified value or characteristic.

[0072] According to the first embodiment of the present invention, a single slope analog-to-digital converter is provided. Figure 2 , Figure 2 A single-slope analog-to-digital converter 10 includes a first component 11 for selecting one of a first reference voltage (VR1), a second reference voltage (VR2), and a voltage to be converted (VP) as an output; a second component 12 for comparing the output of the first component 11 with the current voltage of a ramp signal (VRAMP); a third component 13 for outputting a corresponding measured digital value based on the comparison result of the second component 12; and a fourth component 14 for performing calibration (CA) to calibrate the measured converted digital value (DM) to an ideal converted digital value (DI). The first reference voltage (VR1) corresponds to a first measured digital value (DMR1), the second reference voltage (VR2) corresponds to a second measured digital value (DMR2), and the voltage to be converted (VP) corresponds to the measured converted digital value (DM). The fourth component 14 performs calibration (CA) based on at least a first ideal digital value (DIR1) corresponding to the first reference voltage (VR1), a second ideal digital value (DIR2) corresponding to the second reference voltage (VR2), the first measured digital value (DMR1), and the second measured digital value (DMR2). By inputting a first reference voltage (VR1) and a second reference voltage (VR2), a first measured digital value (DMR1) corresponding to the first reference voltage (VR1) and a second measured digital value (DMR2) corresponding to the second reference voltage (VR2) can be obtained. The first measured digital value (DMR1) and the second measured digital value (DMR2) are then calibrated against the first ideal digital value (DIR1) and the second ideal digital value (DIR2). This provides an offset for the ramp signal (VRAMP), thereby calibrating the measured converted digital value (DM) corresponding to the voltage to be converted (VP) to the ideal converted digital value (DI).

[0073] Specifically, the first component 11 may be a component with switching functionality or selection, such as a multiplexer, selector, or multi-way switch. The first component 11 can be configured to select one of various input voltages (e.g., a reference voltage or a voltage to be converted (VP)) input to the first component 11 as an output. In this embodiment, the first component 11 may be a switching component with three inputs and one output. However, it should be noted that the present invention is not limited to the number of input voltages that the first component 11 can accept.

[0074] The second component 12 can be, for example, a comparator or operational amplifier, capable of outputting a comparison result based on the magnitude of two input voltages. The comparison result output by the second component 12 can be presented as an electrical signal, such as a current or voltage. For example, a high or low potential can be used to represent the magnitude comparison between the input voltages of the second component 12. The second component 12 receives the voltage V11 output by the first component 11 and compares it with a ramp signal (VRAMP). In the present invention, the ramp signal (VRAMP) is a voltage signal that increases or decreases over time from a first potential point to a second potential point. As the potential value of the ramp signal (VRAMP) changes, when the second component 12 compares the voltage V11 with the current potential value of the ramp signal (VRAMP) and the magnitude thereof changes (transitions) (for example, from the voltage V11 being greater than the ramp signal (VRAMP) to the voltage V11 being equal to or less than the ramp signal (VRAMP), or from the voltage V11 being less than the ramp signal (VRAMP) to the voltage V11 being equal to or greater than the ramp signal (VRAMP)), the second component 12 outputs the comparison result to the third component 13.

[0075] The third component 13 may be, for example, a counter or a component that can synchronously calculate a digital value in accordance with changes in the ramp signal (VRAMP). When the ramp signal (VRAMP) begins to increase or decrease, the third component 13 can synchronously calculate the corresponding digital value (e.g., by counting). When the third component 13 receives the comparison result provided by the second component 12, it can stop counting and output the current corresponding digital value. This architecture is used to obtain the digital value corresponding to the voltage V11.

[0076] After the digital conversion of the current voltage V11 is completed, the first component 11 can reselect one of the unconverted input voltages as the new voltage V11 and output it to the second component 12. The second component 12 can then continue to compare the new voltage V11 with the ramp signal (VRAMP). It should be noted that in the present invention, the ramp signal (VRAMP) can continue to increase or decrease, or recalculate, from the previous comparison result voltage point. In a preferred embodiment, the order in which the input voltages are selected by the first component 11 can be based on magnitude, for example, from smaller voltages to larger voltages. In this case, the ramp signal (VRAMP) can be in an increasing mode. After any comparison result voltage is generated, the ramp signal (VRAMP) can continue to increase without being reset. This reduces the time required to generate a comparison result for each input voltage and reduces the risk of errors in the ramp signal (VRAMP) due to multiple resets, but is not limited to this.

[0077] Through the above process, the third component 13 can convert a first measured digital value (DMR1) corresponding to the first reference voltage (VR1), a second measured digital value (DMR2) corresponding to the second reference voltage (VR2), and a measured converted digital value (DM) corresponding to the voltage to be converted (VP). The fourth component 14 can calculate the possible error of the measured converted digital value (DM) based on the deviation between the first ideal digital value (DIR1), the second ideal digital value (DIR2), the first measured digital value (DMR1), and the second measured digital value (DMR2), thereby correcting the measured converted digital value (DM) to the ideal converted digital value (DI). Specifically, the fourth component 14 can be a component with computing functionality, such as an arithmetic unit, a processor, or a microprocessor. The first ideal digital value (DIR1) is the digital value that the first reference voltage (VR1) should have after analog-to-digital conversion, and the second ideal digital value (DIR2) is the digital value that the second reference voltage (VR2) should have after analog-to-digital conversion. However, various factors can cause the ramp signal (VRAMP) to shift or become misaligned, resulting in errors between the first measured digital value (DMR1) and the first ideal digital value (DIR1), as well as between the second measured digital value (DMR2) and the second ideal digital value (DIR2). By obtaining these errors through the fourth component 14, the possible error between the measured converted digital value (DM) and the ideal converted digital value (DI) can be estimated. Therefore, the fourth component 14 can correct the measured converted digital value (DM) to the ideal converted digital value (DI), thereby obtaining an accurate digital value corresponding to the voltage to be converted (VP).

[0078] During the above calibration process, please refer to Figure 3A and Figure 3B . Figure 3AIn an ideal situation, the first reference voltage (VR1), the second reference voltage (VR2), and the voltage to be converted (VP) are converted into a first ideal digital value (DIR1), a second ideal digital value (DIR2), and an ideal converted digital value (DI) by an ideal ramp signal I. However, in reality, the ideal ramp signal I may be offset due to various factors, for example, Figure 3B The actual ramp signal M shown in FIG. There is an error between the actual ramp signal M and the ideal ramp signal I, resulting in the first reference voltage (VR1), the second reference voltage (VR2), and the voltage to be converted (VP) being converted through single-slope analog-to-digital conversion to measure a first measured digital value (DMR1), a second measured digital value (DMR2), and a measured converted digital value (DM). The error between the actual ramp signal M and the ideal ramp signal I can be corrected by adjusting the slope and / or offset of the actual ramp signal M. For example, please refer to the following formula:

[0079]

[0080]

[0081]

[0082] DI=mVR1+m(VP-VR1)

[0083] DI = mVP, where m is the slope of the ideal ramp signal I, m' is the slope of the actual ramp signal M, and b is the offset between the actual ramp signal M and the ideal ramp signal I. The above formula can be used to calibrate the measured converted digital value (DM) to the ideal converted digital value (DI), but the calibration formula is not limited to this.

[0084] It should be noted that the selection of the first reference voltage (VR1) and the second reference voltage (VR2) is not limited to Figure 3A and Figure 3B Please refer to the embodiment shown. Figure 4 The first reference voltage (VR1) and the second reference voltage (VR2) are preferably selected outside the possible voltage range of the voltage to be converted (VP). In this way, when evaluating the error between the ideal ramp signal I and the actual ramp signal M, the first reference voltage (VR1) and the second reference voltage (VR2) will not fall into the range of the voltage to be converted (VP) and thus affect the conversion of the voltage to be converted (VP). On the other hand, if Figure 3A 、 Figure 3B and Figure 4As shown, the first reference voltage (VR1) and the second reference voltage (VR2) can be less than or greater than the possible voltage range of the voltage to be converted (VP). More specifically, when the first reference voltage (VR1) and the second reference voltage (VR2) are greater than the possible voltage range of the voltage to be converted (VP), the ramp signal can be used in a decreasing manner, from a high voltage to a low voltage. This allows the first measured digital value (DMR1) and the second measured digital value (DMR2) to be known in advance, reducing the time required to convert and / or calibrate the measured digital value (DM), but is not limited to this embodiment. Furthermore, the ramp signal's signal variation range at least includes the possible voltage ranges of the first reference voltage (VR1), the second reference voltage (VR2), and the voltage to be converted (VP). It should be noted that when the first reference voltage (VR1) or the second reference voltage (VR2) is negative, it can also be represented by shifting the digital value and used in calculations. Therefore, in this embodiment, the representation of the digital value is not limited to signed, unsigned, shifted, or two's complement digital value representations.

[0085] By combining the first to fourth components 14, a first measured digital value (DMR1) corresponding to the first reference voltage (VR1) and a second measured digital value (DMR2) corresponding to the second reference voltage (VR2) can be obtained from the known first reference voltage (VR1) and second reference voltage (VR2). The first measured digital value (DMR1) and the second measured digital value (DMR2) are then calibrated against the first ideal digital value (DIR1) and the second ideal digital value (DIR2). This allows the offset of the ramp signal to be obtained, and the measured converted digital value (DM) corresponding to the voltage to be converted (VP) to be calibrated to the ideal converted digital value (DI). This achieves a single-slope analog-to-digital converter 10 that corrects for ramp voltage offset and prevents analog-to-digital conversion inaccuracies caused by various variables.

[0086] The second embodiment of the present invention is a single slope analog to digital converter. Figure 5 , Figure 5The single-slope analog-to-digital converter 20 includes a selection unit 21, a comparison unit 22, and a counting unit 23. The selection unit 21 is configured to select one of a first reference voltage (VR1), a second reference voltage (VR2), and a voltage to be converted (VP) as an output based on a control signal. A first input terminal 221 of the comparison unit 22 is coupled to the output of the selection unit 21, and a second input terminal 222 of the comparison unit 22 is coupled to a ramp signal source RS to receive a ramp signal (VRAMP). When the current voltage of the ramp signal (VRAMP) is in a transition state compared to the voltage (V21) at the first input terminal 221, a comparison result signal (CR) is output from an output terminal 223 of the comparison unit 22. The counting unit 23 is coupled to the output terminal 223 and counts digital values based on a clock signal (CLK). When the counting unit 23 receives the comparison result signal (CR), it outputs the current measured digital value (DO). A first reference voltage (VR1) corresponds to a first measured digital value (DMR1), a second reference voltage (VR2) corresponds to a second measured digital value (DMR2), and a voltage to be converted (VP) corresponds to a measured converted digital value (DM). The measured converted digital value (DM) is calibrated to an ideal converted digital value (DI) based on a first ideal digital value (DIR1) corresponding to the first reference voltage (VR1), a second ideal digital value (DIR2) corresponding to the second reference voltage (VR2), the first measured digital value (DMR1), and the second measured digital value (DMR2).

[0087] The selection unit 21 is a switching / selection element such as a multiplexer, selector, or multiplexer. The selection unit 21 can be used to select and output one of various input voltages (such as a reference voltage or a voltage to be converted (VP)) input to the selection unit 21 .

[0088] Comparison unit 22 is a device such as a comparator or operational amplifier that can output a comparison result based on the magnitude of two input voltages. The comparison result output by comparison unit 22 is presented as an electrical signal such as a current or voltage. For example, a high or low voltage can be used to represent the magnitude comparison relationship between the input voltages of comparison unit 22. Comparison unit 22 receives voltage V21 output by selection unit 21 and compares voltage V21 with a ramp signal (VRAMP). In the present invention, ramp signal (VRAMP) is a voltage signal that increases or decreases over time from a first potential point to a second potential point. As the potential value of the ramp signal (VRAMP) changes, when the comparison unit 22 compares the voltage V21 with the current potential value of the ramp signal (VRAMP) and the magnitude thereof changes (transitions) (for example, from the voltage V21 being greater than the ramp signal (VRAMP) to the voltage V21 being equal to or less than the ramp signal (VRAMP), or from the voltage V21 being less than the ramp signal (VRAMP) to the voltage V21 being equal to or greater than the ramp signal (VRAMP)), the comparison unit 22 outputs the comparison result to the counting unit 23.

[0089] The counting unit 23 is, for example, a counter or a device that can synchronously calculate digital values according to changes in the ramp signal (VRAMP). When the ramp signal (VRAMP) begins to increase or decrease, the counting unit 23 can synchronously calculate the corresponding digital value (e.g., by counting synchronously with the clock signal (CLK)). When the counting unit 23 receives the comparison result provided by the comparison unit 22, the counting unit 23 can stop counting and output the current corresponding digital value. It should be noted that in this embodiment, the counting unit 23 can be provided with a calibration mechanism (CA) based on the first measured digital value (DMR1) and the first ideal digital value (DIR1) corresponding to the first reference voltage (VR1), and the second measured digital value (DMR2) and the second ideal digital value (DIR2) corresponding to the second reference voltage (VR2). After the calibration mechanism (CA) is generated, analog-to-digital conversion of the voltage to be converted (VP) is performed, and the calibration mechanism (CA) calibrates the measured converted digital value (DM) converted from the voltage to be converted (VP) to the ideal converted digital value (DI). The correction mechanism (CA) is similar to that described in the first embodiment and is not described in detail here.

[0090] In the extended embodiment of the second embodiment, please refer to Figure 6 . Figure 6The single-slope analog-to-digital converter 20 may further include a control unit 25 coupled to the counting unit 23, and the control unit 25 is used to provide a control signal (CS) to the selection unit 21. The selection unit 21 selects the output voltage V21 according to the control signal (CS). The control signal (CS) is generated according to the generation of the comparison result signal (CR). Specifically, the control unit 25 can provide the control signal (CS) required by the selection unit 21. For example, the generation of the comparison result signal (CR) represents that the comparison of the current voltage V21 has been completed. At this time, after receiving the comparison result signal (CR), the control unit 25 can provide the control signal (CS) required by the selection unit 21 (for example, a two-bit digital signal) so that the selection unit 21 can select the next voltage V21 to be provided to the comparison unit 22 according to the control signal (CS).

[0091] More specifically, for example, when the first reference voltage (VR1) is less than the second reference voltage (VR2) and less than the possible voltage range of the voltage to be converted (VP), the selected ramp signal (VRAMP) can be in an increasing mode. When the first reference voltage (VR1) transitions from the current voltage of the ramp signal (VRAMP) (the ramp signal (VRAMP) transitions from being less than the first reference voltage (VR1) to being equal to or greater than the first reference voltage (VR1)), the control unit can provide a control signal to the selection unit 21, causing the selection unit 21 to select the second reference voltage (VR2). The second reference voltage (VR2) can continue to be compared with the current voltage of the ramp signal (VRAMP), so the ramp signal (VRAMP) does not need to be reset and can continue to increase. Similarly, when the second reference voltage (VR2) transitions from the current voltage of the ramp signal (VRAMP), the control unit can provide a control signal to the selection unit 21, causing the selection unit 21 to select the voltage to be converted (VP). In this way, when comparing the first reference voltage (VR1), the second reference voltage (VR2) and the voltage to be converted (VP), the time required to generate the comparison result can be reduced. On the other hand, the ramp signal (VRAMP) does not need to be reset to avoid unnecessary errors.

[0092] In the extended embodiment of the second embodiment, please refer to Figure 7The single-slope analog-to-digital converter 20 further includes a calibration unit 24 coupled to the counting unit 23. The calibration unit 24 is configured to store at least the first measured digital value (DMR1) and the second measured digital value (DMR2) and calibrate the measured converted digital value (DM) to an ideal converted digital value (DI). Specifically, the calibration unit 24 may be a device with computing capabilities, such as a microprocessor, an FPGA, or an ASIC. The calibration unit 24 is configured to perform the calibration described above. A first ideal digital value (DIR1) corresponding to the first reference voltage (VR1) and a second ideal digital value (DIR2) corresponding to the second reference voltage (VR2) may be provided to the calibration unit 24. The calibration unit 24 establishes a calibration mechanism (CA) based on the first ideal digital value (DIR1), the second ideal digital value (DIR2), the first measured digital value (DMR1), and the second measured digital value (DMR2). When the measured converted digital value (DM) is provided to the calibration unit 24, it is calibrated to the ideal converted digital value (DI) through the calibration mechanism (CA). Calibration unit 24 can store the first ideal digital value (DIR1), the second ideal digital value (DIR2), the first measured digital value (DMR1), and the second measured digital value (DMR2) and establish a calibration mechanism (CA). The independent calibration unit 24 can reduce the computational burden on counting unit 23. The computational power of calibration unit 24 can also be leveraged to adjust software and firmware for the calibration mechanism (CA), providing greater flexibility and computational power for the calibration configuration of the single-slope analog-to-digital converter 20.

[0093] The third embodiment of the present invention is a calibration method for a single slope analog-to-digital converter. Figure 8 , Figure 8 The calibration method includes: (step S1) selecting one of a first reference voltage, a second reference voltage, and a voltage to be converted as a voltage to be compared; (step S2) comparing the voltage to be compared with a current voltage of a ramp signal to output a comparison result signal; (step S3) outputting a corresponding measured digital value based on the comparison result signal; wherein the first reference voltage corresponds to the first measured digital value, the second reference voltage corresponds to the second measured digital value, and (step S4) the voltage to be converted corresponds to the measured converted digital value; and performing calibration to calibrate the measured converted digital value to an ideal converted digital value; wherein the calibration is based on at least a first ideal digital value corresponding to the first reference voltage, a second ideal digital value corresponding to the second reference voltage, the first measured digital value, and the second measured digital value.

[0094] The method of this embodiment can be applied to any single-slope analog-to-digital converter. By inputting a plurality of arbitrary known reference voltage values, the offset between the ideal digital value and the measured digital value is obtained. The first and second measured digital values are then calibrated against the first and second ideal digital values. This provides the offset of the ramp signal, and thereby calibrates the measured converted digital value corresponding to the voltage to be converted to the ideal converted digital value.

[0095] The previous description of the present invention is provided to enable one skilled in the art to make or practice the present invention. Various modifications to the present invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations or the various embodiments may be combined or implemented separately without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features of the present invention.

Claims

1. A single-slope analog-to-digital converter, characterized in that: Include: a first component for selecting one of a first reference voltage, a second reference voltage, and a voltage to be converted as an output; a second component for comparing the output of the first component with a current voltage of a ramp signal; a third component for outputting a corresponding measured digital value according to the comparison result of the second component; wherein the first reference voltage corresponds to a first measured digital value, the second reference voltage corresponds to a second measured digital value, and the voltage to be converted corresponds to a measured converted digital value; and a fourth component for performing a calibration to calibrate the measured converted digital value to an ideal converted digital value; The fourth component performs the calibration at least according to a first ideal digital value corresponding to the first reference voltage, a second ideal digital value corresponding to the second reference voltage, the first measured digital value, and the second measured digital value.

2. The single-slope analog-to-digital converter according to claim 1, wherein: The first reference voltage and the second reference voltage are selected from outside a possible voltage range of the voltage to be converted.

3. The single-slope analog-to-digital converter according to claim 2, wherein: The first reference voltage and the second reference voltage are smaller than or larger than the voltage to be converted.

4. The single-slope analog-to-digital converter according to claim 1, wherein: The signal variation range of the ramp signal at least includes the possible voltage ranges of the first reference voltage, the second reference voltage, and the voltage to be converted.

5. The single-slope analog-to-digital converter according to claim 1, wherein: The first component is selected from one of a multiplexer, a selector and a switch.

6. A single-slope analog-to-digital converter, characterized in that Include: a selection unit for selecting one of a first reference voltage, a second reference voltage, and a voltage to be converted as an output according to a control signal; a comparison unit; wherein a first input terminal of the comparison unit is coupled to the output of the selection unit, and a second input terminal of the comparison unit is coupled to a ramp signal source to receive a ramp signal; when a current voltage of the ramp signal is a transition state compared to the voltage of the first input terminal, a comparison result signal is output from an output terminal of the comparison unit; as well as a counting unit coupled to the output terminal; wherein the counting unit counts digital values according to a clock signal, and outputs a current measured digital value when the counting unit receives the comparison result signal; wherein the first reference voltage corresponds to a first measured digital value, the second reference voltage corresponds to a second measured digital value, and the voltage to be converted corresponds to a measured converted digital value; The measured conversion digital value is corrected to an ideal conversion digital value according to a first ideal digital value corresponding to the first reference voltage, a second ideal digital value corresponding to the second reference voltage, the first measured digital value, and the second measured digital value.

7. The single-slope analog-to-digital converter according to claim 6, wherein: The first reference voltage and the second reference voltage are selected from outside a possible voltage range of the voltage to be converted.

8. The single-slope analog-to-digital converter according to claim 7, wherein: The first reference voltage and the second reference voltage are smaller than or larger than the voltage to be converted.

9. The single-slope analog-to-digital converter according to claim 6, wherein: The signal variation range of the ramp signal at least includes the possible voltage ranges of the first reference voltage, the second reference voltage, and the voltage to be converted.

10. The single-slope analog-to-digital converter according to claim 6, wherein: Further including: A control unit is coupled to the counting unit, and the control unit is used to provide the control signal; wherein the control signal is switched according to the generation of the comparison result signal.

11. The single-slope analog-to-digital converter according to claim 6, wherein: Further including: A calibration unit is coupled to the counting unit, and is configured to store at least the first measured digital value and the second measured digital value, and calibrate the measured converted digital value to the ideal converted digital value.

12. A calibration method for a single-slope analog-to-digital converter, characterized in that: Include: Selecting one of a first reference voltage, a second reference voltage and a voltage to be converted as a voltage to be compared; Comparing the voltage to be compared with a current voltage of a ramp signal to output a comparison result signal; Outputting a corresponding measured digital value according to the comparison result signal; wherein the first reference voltage corresponds to a first measured digital value, the second reference voltage corresponds to a second measured digital value, and the voltage to be converted corresponds to a measured conversion digital value; and A calibration is performed to calibrate the measured converted digital value to an ideal converted digital value; wherein the calibration is based on at least a first ideal digital value corresponding to the first reference voltage, a second ideal digital value corresponding to the second reference voltage, the first measured digital value, and the second measured digital value.

13. The calibration method of a single-slope analog-to-digital converter according to claim 12, wherein: The first reference voltage and the second reference voltage are selected from outside a possible voltage range of the voltage to be converted.

14. The calibration method of a single-slope analog-to-digital converter according to claim 13, wherein: The first reference voltage and the second reference voltage are smaller than or larger than the voltage to be converted.

15. The calibration method of a single-slope analog-to-digital converter according to claim 12, wherein: The signal variation range of the ramp signal at least includes the possible voltage ranges of the first reference voltage, the second reference voltage, and the voltage to be converted.

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