Semiconductor device

Abstract

A semiconductor device includes: a package substrate; and a plurality of semiconductor chips stacked on the package substrate, in which each of the plurality of semiconductor chips respectively includes a semiconductor substrate, a peripheral circuit structure and a cell array structure disposed to overlap each other in a vertical direction on the semiconductor substrate, a first contact pad in which the peripheral circuit structure includes a second contact pad in which the cell array structure includes a plurality of first conductive pads, and a plurality of second conductive pads in which the cell array structure includes a plurality of second conductive pads. And a second chip through via in the cell array structure and connected to the first contact pad, the first chip through via, penetrating through the semiconductor substrate and at least a portion of the peripheral circuit structure, and connected to the first contact pad, and the second chip through via, penetrating through at least a portion of the cell array structure and connected to the second contact pad, and the first through-chip via of the first semiconductor chip is connected to the second through-chip via of the second semiconductor chip.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0017688 filed on February 5, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device. Background Art

[0003] Recently, demand for portable devices has rapidly increased in the electronics market, and as a result, there is a continued demand for reduced size and weight of the electronic components (such as semiconductor chips) mounted on these products. To achieve this, not only are technologies for reducing the size of the mounted components, but also semiconductor devices that integrate the semiconductor chips that make up the components are needed. For example, to achieve high performance and large capacity as well as reduced size and lighter manufacturing, semiconductor devices may have a cell-on-chip (COP) structure and may have a stacked structure of semiconductor chips that include through-silicon vias (TSVs). Summary of the Invention

[0004] The present disclosure provides a semiconductor device for improving reliability and productivity.

[0005] According to an embodiment of the present disclosure, a semiconductor device includes: a packaging substrate; and a plurality of semiconductor chips stacked on the packaging substrate, wherein each semiconductor chip of the plurality of semiconductor chips respectively includes: a semiconductor substrate; a peripheral circuit structure and a unit array structure, arranged to overlap each other in a vertical direction on the semiconductor substrate; a first contact pad, in the peripheral circuit structure; a second contact pad, in the unit array structure, the second contact pad is connected to the first contact pad; a first chip through-via, penetrating at least a portion of the semiconductor substrate and the peripheral circuit structure, the first chip through-via being connected to the first contact pad; and a second chip through-via, penetrating at least a portion of the unit array structure, the second chip through-via being connected to the second contact pad, and the first chip through-via of the first semiconductor chip of the plurality of semiconductor chips is connected to the second chip through-via of the second semiconductor chip of the plurality of semiconductor chips.

[0006] According to another embodiment of the present disclosure, a semiconductor device includes: a packaging substrate; and a first group of semiconductor chips stacked on the packaging substrate, wherein each semiconductor chip in the first group of semiconductor chips respectively includes: a first semiconductor substrate; a first peripheral circuit structure on the first semiconductor substrate; a first unit array structure on the first peripheral circuit structure; a first contact pad in the first peripheral circuit structure; a second contact pad in the first unit array structure, the second contact pad contacting the first contact pad; a contact insulating layer on the boundary between the first peripheral circuit structure and the first unit array structure, the contact insulating layer surrounding the first contact pad and the second contact pad; a first chip through-via penetrating the first semiconductor substrate and the first peripheral circuit structure, the first chip through-via connected to the first contact pad; and a second chip through-via penetrating the first unit array structure, the second chip through-via connected to the second contact pad, and wherein the first chip through-via of the first semiconductor chip in the first group of semiconductor chips is connected to the second chip through-via of the second semiconductor chip in the first group of semiconductor chips.

[0007] According to another embodiment of the present disclosure, a semiconductor device includes: a package substrate including a first surface and a second surface opposite to each other; a first substrate pad and a second substrate pad, respectively disposed on the first surface and the second surface of the package substrate; an external connection terminal on the first substrate pad; a plurality of semiconductor chips, respectively including a first surface and a second surface opposite to each other, the plurality of semiconductor chips being stacked on the second surface of the package substrate; a first chip pad and a second chip pad, respectively disposed on the first surface and the second surface of each semiconductor chip of the plurality of semiconductor chips; a first chip connection terminal between the first chip pad of the first semiconductor chip and the second chip pad of the second semiconductor chip; a second chip connection terminal between the first chip pad and the second substrate pad of the third semiconductor chip; and an underfill member between adjacent semiconductor chips and between the package substrate and the plurality of semiconductor chips. between the lowermost semiconductor chip in the package; and a molding member covering the package substrate and the plurality of semiconductor chips, wherein the plurality of semiconductor chips respectively include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a cell array structure on the peripheral circuit structure; a first contact pad and a second contact pad contacting each other on a boundary between the peripheral circuit structure and the cell array structure; a contact insulating layer surrounding the first contact pad and the second contact pad; a first chip through via penetrating the semiconductor substrate and the peripheral circuit structure, the first chip through via being connected to the first contact pad and the first chip pad; and a second chip through via penetrating the cell array structure, the second chip through via being connected to the second contact pad and the second chip pad, and wherein the first chip through via of a semiconductor chip among the plurality of semiconductor chips is connected to the second chip through via of another semiconductor chip among the plurality of semiconductor chips.

[0008] According to the embodiment, a peripheral circuit structure and a cell array structure are vertically stacked, and semiconductor chips including through vias are stacked, thereby improving characteristics and area efficiency of a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment is shown.

[0010] Figure 2 Show Figure 1 A partial enlarged view of region R1.

[0011] Figure 3 A cross-sectional view illustrating a semiconductor chip included in a semiconductor device according to an embodiment.

[0012] Figure 4 and Figure 5 A partially enlarged view illustrating a cross section of a semiconductor device according to some embodiments is shown.

[0013] Figure 6 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0014] Figure 7 A cross-sectional view illustrating a semiconductor chip included in a semiconductor device according to some embodiments is shown.

[0015] Figure 8 and Figure 9 A cross section of a semiconductor device according to some embodiments is shown.

[0016] Figure 10 Show Figure 9 A partial enlarged view of region R4.

[0017] Figures 11 to 15 A cross section of a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0018] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which disclosed embodiments are shown. As those skilled in the art will realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0019] Parts irrelevant to the description will be omitted to clearly describe the present disclosure, and the same elements will be designated by the same reference numerals throughout the specification.

[0020] For better understanding and ease of description, the size and thickness of each structure shown in the drawings are arbitrarily shown, but the present invention is not limited thereto. In the drawings, the thickness of layers, films, plates, regions, etc. are exaggerated for clarity. For ease of explanation, the thickness of some layers and regions is exaggerated.

[0021] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "on" or "over" mean located above or below an object part and do not necessarily mean located on the upper side of the object part based on the direction of gravity.

[0022] Unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” and “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0023] Throughout the specification, unless the context indicates otherwise, when a component is described as "comprising" a particular element or group of elements, it will be understood that the component is formed only of that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component. On the other hand, the term "consisting of" indicates that the component is formed only of the listed elements.

[0024] It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “contacting” or “in contact with” another element (or using any form of the term “contacting”), there are no intervening elements at the point of contact.

[0025] Terms such as "same," "equal," "planar," or "coplanar" as used herein when referring to an orientation, layout, position, shape, size, composition, amount, or other metric do not necessarily mean exactly identical orientations, layouts, positions, shapes, sizes, compositions, amounts, or other metrics, but are intended to encompass nearly identical orientations, layouts, positions, shapes, sizes, compositions, amounts, or other metrics within typical variations that may occur due to conventional manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0026] The various pads of the devices described herein can be conductive terminals connected to the internal wiring of the device and can transmit signals and / or power supply voltages between the internal wiring and / or internal circuits of the device and an external source. For example, a chip pad of a semiconductor chip can be electrically connected to an integrated circuit of the semiconductor chip and a device to which the semiconductor chip is connected, and can transmit power supply voltages and / or signals between the integrated circuit of the semiconductor chip and the device to which the semiconductor chip is connected. The various pads can be disposed on or near the outer surface of the device and can have a planar surface having a dimension larger than the wiring (e.g., both the X horizontal dimension and the Y horizontal dimension of the pad are larger than the width of the internal wiring to which it is connected) to facilitate electrical connection to another terminal (such as a bump or solder ball) and / or external wiring.

[0027] The phrase “in a plan view” means that an object portion is viewed from the top, and the phrase “in a cross-sectional view” means that a cross section of the object portion is viewed from the side, which is vertically cut.

[0028] Now refer to Figure 1 and Figure 2 A semiconductor device according to an embodiment is described.

[0029] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment is shown. Figure 2 Show Figure 1 A partial enlarged view of region R1.

[0030] Reference Figure 1 and Figure 2 The semiconductor device 1 may include a package substrate 50 , first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d , a chip pad 40 , a chip connection terminal 60 , an underfill member 70 , and a molding member 80 .

[0031] The package substrate 50 may include a first surface 50 a and a second surface 50 b facing each other. A direction parallel to the first surface 50 a of the package substrate 50 may be defined as a first direction (X), a direction parallel to the first surface 50 a of the package substrate 50 and perpendicular to the first direction (X) may be defined as a second direction (Y), and a direction perpendicular to the first surface 50 a of the package substrate 50 may be defined as a third direction (Z).

[0032] The package substrate 50 may be one of a printed circuit board (PCB), a ceramic substrate, and an interposer.

[0033] In one embodiment, when the package substrate 50 is an interposer, the package substrate 50 may include a body 51, a substrate through-hole 53 for penetrating at least a portion of the body 51, and a first substrate pad 55 and a second substrate pad 57 respectively disposed on a first surface 50a and a second surface 50b of the package substrate 50.

[0034] The body 51 of the package substrate 50 may include, for example, silicon (Si). However, the material included in the body 51 is not limited thereto and may be varied in many ways. For example, the body 51 may include a semiconductor element such as germanium (Ge) and a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

[0035] The through-substrate via 53 may penetrate the body 51 in the third direction (Z) and may electrically connect the first substrate pad 55 to the second substrate pad 57 .

[0036] Despite Figure 1 Although not shown in the drawings, the package substrate 50 may further include internal conductive lines provided in the body 51 .

[0037] In some embodiments, the package substrate 50 may be a semiconductor chip including an integrated circuit. That is, the package substrate 50 may be a semiconductor chip including electronic components such as transistors. For example, the package substrate 50 may be a wafer-level bare die made of a semiconductor element such as silicon (Si). However, the type of package substrate 50 is not limited thereto and may be modified in many ways.

[0038] The external connection terminals 90 may be provided on the first surface 50a of the package substrate 50. The external connection terminals 90 may be provided on the first substrate pads 55. That is, the first substrate pads 55 may be provided between the body 51 of the package substrate 50 and the external connection terminals 90. The external connection terminals 90 may electrically connect the semiconductor device 1 to an external device, or may be mounted on an external substrate.

[0039] The external connection terminal 90 may be, for example, at least one of a solder ball, a pillar, and a conductive bump. However, the type of the external connection terminal 90 is not limited thereto and may be changed in many ways.

[0040] The external connection terminal 90 may include a conductive material. For example, the external connection terminal 90 may include one of tin (Sn), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof. However, the conductive material included in the external connection terminal 90 is not limited thereto and may be varied in many ways.

[0041] The first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be stacked along a third direction (Z), which is a vertical direction, on the second surface 50b of the package substrate 50. That is, the first semiconductor chip 10a, the second semiconductor chip 10b, the third semiconductor chip 10c, and the fourth semiconductor chip 10d may be sequentially stacked along the third direction (Z) on the second surface 50b of the package substrate 50. In other words, among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, the first semiconductor chip 10a may be disposed at the lowermost end of the stack, and the fourth semiconductor chip 10d may be disposed at the uppermost end of the stack.

[0042] The planar area of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be smaller than the planar area of the package substrate 50. The planar areas of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be substantially the same. However, the relationship between the planar areas of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d and the planar area of the package substrate 50 is not limited thereto and may be changed in many ways. The planar area of at least one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be different from the planar area of at least another of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d.

[0043] Each of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may include a first surface and a second surface facing each other. Here, the first surface may refer to the bottom surface of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, and the second surface may refer to the top surface of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. That is, the first surface may face the package substrate 50, and the second surface may face away from the package substrate 50.

[0044] The first surface of one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may face the second surface of another of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. For example, the first surface of the second semiconductor chip 10b may face the second surface of the first semiconductor chip 10a, and the second surface of the second semiconductor chip 10b may face the first surface of the third semiconductor chip 10c.

[0045] The first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be logic chips or memory chips. For example, the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be memory chips of the same type, some of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be memory chips, and the other semiconductor chips may be logic chips.

[0046] Figure 1 The semiconductor device 1 is shown to include four semiconductor chips, but the number of semiconductor chips included in the semiconductor device 1 is not limited thereto and can be changed in many ways. For example, the semiconductor device 1 may include two, three, or equal to or more than five semiconductor chips. For another example, the semiconductor device 1 may include a number of semiconductor chips that is a multiple of four.

[0047] The memory chip may be, for example, a volatile memory chip such as dynamic random access memory (DRAM) or static RAM (SRAM), or a nonvolatile memory chip such as phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), or resistive RAM (RRAM).

[0048] In some embodiments, the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d may be high bandwidth memory (HBM) DRAMs. The logic chip may be, for example, a microprocessor, an analog component, or a digital signal processor.

[0049] Hereinafter, the first to fourth semiconductor chips 10 a , 10 b , 10 c , 10 d will be assumed to be DRAMs.

[0050] Each of the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d may include a semiconductor substrate 100 , a peripheral circuit structure PS, a cell array structure CS, a contact pad BP, a contact insulating layer BPL, and chip through vias 313 and 315 , respectively.

[0051] In detail, with respect to each of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, the peripheral circuit structure PS and the cell array structure CS may be sequentially stacked on the semiconductor substrate 100. That is, the peripheral circuit structure PS may be disposed between the semiconductor substrate 100 and the cell array structure CS. However, the arrangement relationship between the peripheral circuit structure PS and the cell array structure CS is not limited thereto and may be varied in many ways. For example, in some embodiments, the cell array structure CS and the peripheral circuit structure PS may be stacked on the semiconductor substrate 100. For example, the cell array structure CS may be disposed between the semiconductor substrate 100 and the peripheral circuit structure PS.

[0052] Hereinafter, a structure in which the cell array structure CS is disposed on the peripheral circuit structure PS will be assumed.

[0053] The semiconductor substrate 100 may be a silicon substrate, or may include other materials (eg, silicon germanium, indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, and gallium antimonide), and is not limited thereto, and the materials included in the semiconductor substrate 100 may be changed in various ways.

[0054] In one embodiment, each of the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d may be a bonded semiconductor chip of a chip-to-chip structure in which the peripheral circuit structure PS is bonded to the cell array structure CS by a wafer bonding method.

[0055] The peripheral circuit structure PS may include a first surface and a second surface. The first surface of the peripheral circuit structure PS may face away from the cell array structure CS, and the second surface may face the cell array structure CS.

[0056] Here, the first surface of the peripheral circuit structure PS may refer to a back side of the peripheral circuit structure PS, and the second surface of the peripheral circuit structure PS may refer to a front side of the peripheral circuit structure PS.

[0057] The cell array structure CS may include a first surface and a second surface opposite to each other. The first surface of the cell array structure CS may face the peripheral circuit structure PS, and the second surface of the cell array structure CS may face away from the peripheral circuit structure PS.

[0058] In one embodiment, the second surface of the peripheral circuit structure PS and the first surface of the cell array structure CS may be bonding surfaces of the peripheral circuit structure PS and the cell array structure CS. That is, the second surface of the peripheral circuit structure PS and the first surface of the cell array structure CS may be bonded and combined with each other to form a bonding surface.

[0059] The contact pad BP and the contact insulating layer BPL may be disposed between the peripheral circuit structure PS and the cell array structure CS. That is, the contact pad BP may be disposed on a boundary between the peripheral circuit structure PS and the cell array structure CS.

[0060] The contact pads BP may include a first contact pad BP1 disposed in the peripheral circuit structure PS and a second contact pad BP2 disposed in the cell array structure CS.

[0061] The contact insulating layer BPL may include a first contact insulating layer BPL1 disposed in the peripheral circuit structure PS and a second contact insulating layer BPL2 disposed in the cell array structure CS.

[0062] Specifically, the first contact pad BP1 and the first contact insulating layer BPL1 may be disposed in the second surface of the peripheral circuit structure PS. The upper surface of the first contact pad BP1 and the upper surface of the first contact insulating layer BPL1 may be coplanar and may constitute the second surface of the peripheral circuit structure PS. In other words, the upper surface of the first contact pad BP1 and the upper surface of the first contact insulating layer BPL1 may be disposed at substantially the same height.

[0063] The first contact insulating layer BPL1 may surround the first contact pad BP1. For example, the first contact insulating layer BPL1 may surround the side surface of the first contact pad BP1. However, the arrangement relationship between the first contact insulating layer BPL1 and the first contact pad BP1 is not limited thereto and may be varied in many ways. For example, the first contact insulating layer BPL1 may surround the side surface and bottom surface of the first contact pad BP1, and the bottom surface of the first contact insulating layer BPL1 may be arranged at a height lower than the bottom surface of the first contact pad BP1.

[0064] The second contact pad BP2 and the second contact insulating layer BPL2 may be disposed in the first surface of the cell array structure CS. The bottom surface of the second contact pad BP2 and the bottom surface of the second contact insulating layer BPL2 may be coplanar and may constitute the first surface of the cell array structure CS. In other words, the bottom surface of the second contact pad BP2 and the bottom surface of the second contact insulating layer BPL2 may be disposed at substantially the same height.

[0065] The second contact insulating layer BPL2 may surround the second contact pad BP2. For example, the second contact insulating layer BPL2 may surround the side surface of the second contact pad BP2. However, the arrangement relationship between the second contact insulating layer BPL2 and the second contact pad BP2 is not limited thereto and may be varied in many ways. For example, the second contact insulating layer BPL2 may surround the side surface and the upper surface of the second contact pad BP2, and the upper surface of the second contact insulating layer BPL2 may be arranged at a height higher than the upper surface of the second contact pad BP2.

[0066] Each of the first contact pads BP1 and the first contact insulating layer BPL1 may be directly bonded to the second contact pad BP2 and the second contact insulating layer BPL2 at the boundary where the second surface of the peripheral circuit structure PS contacts the first surface of the cell array structure CS. For example, each of the first contact pads BP1 and the first contact insulating layer BPL1 may be bonded and combined to the second contact pad BP2 and the second contact insulating layer BPL2 by hybrid bonding or direct bonding. However, the method of bonding the first contact pad BP1 and the first contact insulating layer BPL1 to the second contact pad BP2 and the second contact insulating layer BPL2, respectively, is not limited thereto and may be modified in many ways.

[0067] A boundary between the first contact pad BP1 and the second contact pad BP2 and a boundary between the first contact insulating layer BPL1 and the second contact insulating layer BPL2 may configure a bonding surface between the peripheral circuit structure PS and the cell array structure CS.

[0068] like Figure 2 As shown in , the first contact pad BP1 and the second contact pad BP2 may respectively have first and second widths W1 and W2 in a first direction (X) as a horizontal direction, and may have first and second thicknesses D1 and D2 in a third direction (Z) as a vertical direction.

[0069] In one embodiment, the first width W1 and the second width W2 may be substantially the same, and the first thickness D1 and the second thickness D2 may be substantially the same. However, the relationship between the first width W1 and the second width W2 and the relationship between the first thickness D1 and the second thickness D2 are not limited thereto and may be varied in many ways. Figure 3 and Figure 4 Provide a detailed description of them.

[0070] In one embodiment, the first and second contact pads BP1 and BP2 may include the same material, and the first and second contact insulating layers BPL1 and BPL2 may include the same material.

[0071] In detail, the first contact pad BP1 and the second contact pad BP2 may each include a conductive material such as copper (Cu), tungsten (W), nickel (Ni), gold (Au), and silver (Ag). For example, the first contact pad BP1 and the second contact pad BP2 may each include copper (Cu). However, the materials included in the first contact pad BP1 and the second contact pad BP2 are not limited thereto and may be varied in many ways.

[0072] The first and second contact insulating layers BPL1 and BPL2 may each include an insulating material such as silicon oxide (SiO) and silicon carbon nitride (SiCN). For example, the first and second contact insulating layers BPL1 and BPL2 may each include silicon carbon nitride (SiCN). However, the materials included in the first and second contact insulating layers BPL1 and BPL2 are not limited thereto and may be modified in many ways.

[0073] As described above, when the first contact pad BP1 and the second contact pad BP2 contact each other on the boundary between the peripheral circuit structure PS and the cell array structure CS, an electrical connection path between the peripheral circuit structure PS and the cell array structure CS may be provided.

[0074] Each of the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d may include a first through-chip via 313 provided in the peripheral circuit structure PS and a second through-chip via 315 provided in the cell array structure CS.

[0075] In detail, the first chip through via 313 may penetrate at least a portion of the semiconductor substrate 100 and the peripheral circuit structure PS and may extend in the third direction (Z). The first chip through via 313 may be connected to the first contact pad BP1.

[0076] The second through-chip via 315 may penetrate at least a portion of the cell array structure CS and may extend in the third direction (Z). The second through-chip via 315 may be connected to the second contact pad BP2.

[0077] The chip pad 40 may be disposed on the first surface and the second surface of each of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, respectively. The chip pad 40 may include a first chip pad 41 disposed on the first surface of each of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, and a second chip pad 42 disposed on the second surface of each of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d.

[0078] A first die pad 41 (e.g., the first die pad 41 on the second semiconductor chip 10b) disposed on a first surface of one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may face a second die pad 42 (e.g., the second die pad 42 on the first semiconductor chip 10a) disposed on a second surface of another of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. That is, among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d adjacent to each other, the first die pad 41 and the second die pad 42 may face each other.

[0079] For example, the first die pad 41 disposed on the first surface of the second semiconductor chip 10b may face the second die pad 42 disposed on the second surface of the first semiconductor chip 10a. The second die pad 42 disposed on the second surface of the second semiconductor chip 10b may face the first die pad 41 disposed on the first surface of the third semiconductor chip 10c.

[0080] The first chip pad 41 disposed on the lowermost first semiconductor chip 10a among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d adjacent to each other may face the second substrate pad 57 disposed on the second surface 50b of the package substrate 50.

[0081] The first and second die pads 41 and 42 may include the same conductive material. For example, the first and second die pads 41 and 42 may include at least one of copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). However, the materials included in the first and second die pads 41 and 42 are not limited thereto and may be varied in many ways.

[0082] The chip connection terminals 60 may be respectively provided between adjacent semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. The chip connection terminals 60 may be provided between the first semiconductor chip 10a and the package substrate 50. The chip connection terminals 60 may electrically connect the first to fourth semiconductor chips 10a, 10b, 10c, and 10d to each other and to the package substrate 50.

[0083] In detail, the chip connection terminal 60 may be provided between the first chip pad 41 and the second chip pad 42. That is, the chip connection terminal 60 may be provided between the first chip pad 41 on one semiconductor chip of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d and the second chip pad 42 on another semiconductor chip of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d.

[0084] Therefore, the first chip through via 313 of one semiconductor chip among the first to fourth semiconductor chips 10a, 10b, 10c and 10d and the second chip through via 315 of another semiconductor chip among the first to fourth semiconductor chips 10a, 10b, 10c and 10d can be electrically connected to each other through the chip connection terminal 60.

[0085] Therefore, the first chip through-via 313 and the second chip through-via 315 respectively connected to the “first chip pad 41 on one semiconductor chip among the first to fourth semiconductor chips 10a, 10b, 10c and 10d” and the “second chip pad 42 on another semiconductor chip among the first to fourth semiconductor chips 10a, 10b, 10c and 10d” can be connected to each other through the chip connection terminal 60.

[0086] For example, the first chip through via 313 connected to the first chip pad 41 on the second semiconductor chip 10b and the second chip through via 315 connected to the second chip pad 42 on the first semiconductor chip 10a may be electrically connected to each other through the chip connection terminal 60 disposed between the first chip pad 41 and the second chip pad 42.

[0087] The chip connection terminals 60 may be disposed between the first semiconductor chip 10a and the second surface 50b of the package substrate 50. The first semiconductor chip 10a is disposed at the lowest end among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. In other words, the chip connection terminals 60 may be disposed between the first chip pad 41 on the first semiconductor chip 10a and the second substrate pad 57 on the package substrate 50, and may electrically connect the first semiconductor chip 10a to the package substrate 50.

[0088] The chip connection terminal 60 may be, for example, at least one of a solder ball, a pillar, and a conductive bump. However, the type of the chip connection terminal 60 is not limited thereto and may be changed in many ways.

[0089] The chip connection terminals 60 may include a conductive material. For example, the chip connection terminals 60 may include one of tin (Sn), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof. However, the conductive material included in the chip connection terminals 60 is not limited thereto and may be varied in many ways.

[0090] The underfill members 70 may be respectively disposed between the package substrate 50 and the first semiconductor chip 10 a , and between adjacent semiconductor chips among the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d .

[0091] The underfill member 70 may fill a gap region remaining after the second substrate pad 57 , the first chip pad 41 , and the chip connection terminal 60 are formed between the package substrate 50 and the first semiconductor chip 10 a .

[0092] The underfill member 70 may fill a gap region remaining after the chip pads 40 and the chip connection terminals 60 are formed between adjacent semiconductor chips among the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d .

[0093] The underfill member 70 may include an insulating material. For example, the underfill member 70 may include an epoxy-based polymer. However, the material included in the underfill member 70 is not limited thereto and may be changed in many ways.

[0094] Figure 1 The sides of the underfill member 70 and the sides of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d are shown to be arranged on substantially the same boundary, but the present inventive concept is not limited thereto. For example, the ends of the sides of the underfill member 70 may protrude from the sides of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d and may have a curved shape that is convex toward the first and second sides of the first direction (X).

[0095] As described, when the underfill member 70 protrudes from respective sides of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d in the first direction (X), the underfill member 70 may cover at least a portion of the respective sides of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d.

[0096] The molding member 80 may be disposed on the package substrate 50. The molding member 80 may cover a portion of the second surface 50b of the package substrate 50, side surfaces of the first to third semiconductor chips 10a, 10b, and 10c, side surfaces and an upper surface of the fourth semiconductor chip 10d, and side surfaces of the underfill member 70.

[0097] The molding member 80 may cover the second chip pad 42 disposed on the second surface of the fourth semiconductor chip 10 d .

[0098] The molding member 80 may include an insulating material. For example, the molding member 80 may include a polymer such as epoxy molding compound (EMC). As another example, the molding member 80 may include an epoxy-based material, a thermosetting material, a thermoplastic material, and an ultraviolet (UV) curable material. However, the material included in the molding member 80 is not limited thereto and may be varied in many ways.

[0099] Figure 3 A cross-sectional view illustrating a semiconductor chip included in a semiconductor device according to an embodiment.

[0100] The first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d included in the semiconductor device 1 will now be described in detail.

[0101] Figure 3 The cross section of the first semiconductor chip 10a among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d is shown, and the second to fourth semiconductor chips 10b, 10c, and 10d may have substantially the same configuration and structure as the first semiconductor chip 10a. However, embodiments are not limited thereto, and in some embodiments, at least one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may have a different configuration and structure.

[0102] The first semiconductor chip 10 a will be mainly described, and the description regarding the first semiconductor chip 10 a may be applied to the second to fourth semiconductor chips 10 b , 10 c , and 10 d in substantially the same manner.

[0103] Reference Figure 3 The first semiconductor chip 10a included in the semiconductor device 1 may be a DRAM. For example, the first semiconductor chip 10a may include a memory cell including a vertical channel transistor (VCT). However, this is an example, and the configuration, structure, and type of the first semiconductor chip 10a are not limited thereto and may be varied in many ways.

[0104] The first semiconductor chip 10 a may include a semiconductor substrate 100 , a peripheral circuit structure PS disposed on the semiconductor substrate 100 , and a cell array structure CS disposed on the peripheral circuit structure PS.

[0105] The semiconductor substrate 100 may include a cell array region CAR and a peripheral circuit region PAR defined around the cell array region CAR. For example, the peripheral circuit region PAR may be disposed near the cell array region CAR. However, the arrangement relationship between the cell array region CAR and the peripheral circuit region PAR is not limited thereto and may be varied in many ways.

[0106] The peripheral circuit structure PS may be disposed in the cell array region CAR and the peripheral circuit region PAR on the semiconductor substrate 100. That is, a portion of the peripheral circuit structure PS may be disposed in the cell array region CAR of the semiconductor substrate 100, and another portion of the peripheral circuit structure PS may be disposed in the peripheral circuit region PAR.

[0107] The peripheral circuit structure PS may include a peripheral circuit PC, a peripheral contact plug 220 , a peripheral circuit conductive line 230 , a peripheral circuit insulating layer 212 , a first contact insulating layer BPL1 , and a first contact pad BP1 .

[0108] The peripheral circuit PC may be, for example, a sensing transistor, a transfer transistor, and / or a driving transistor. However, the type of transistor of the peripheral circuit PC may be changeable according to the design and configuration of the semiconductor chip.

[0109] The peripheral circuit PC may be disposed on the semiconductor substrate 100. The peripheral circuit PC may include a peripheral circuit gate insulating layer and a peripheral circuit conductive pattern sequentially stacked on the semiconductor substrate 100.

[0110] The peripheral circuit gate insulating layer may include silicon oxide, silicon oxynitride, a high dielectric (high-k) material having a higher dielectric constant than silicon oxide, and combinations thereof. The high dielectric (high-k) material may include, for example, at least one of metal oxide, metal oxynitride, metal silicon oxide, and metal silicon oxynitride, but is not limited thereto.

[0111] The peripheral circuit conductive pattern may include a conductive material. For example, the peripheral circuit conductive pattern may include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, and a metal.

[0112] The peripheral circuit insulating layer 212 may cover the peripheral circuit PC. The peripheral circuit insulating layer 212 may include an insulating material. For example, the peripheral circuit insulating layer 212 may include silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer. However, the invention is not limited thereto.

[0113] The peripheral contact plugs 220 and the peripheral circuit conductive lines 230 may be disposed in the peripheral circuit insulating layer 212 .

[0114] The peripheral contact plugs 220 may include a first peripheral contact plug 221 , a second peripheral contact plug 223 , and a third peripheral contact plug 225 .

[0115] The peripheral circuit wire 230 may include a first peripheral circuit wire 231 and a second peripheral circuit wire 233 .

[0116] The first peripheral circuit conductive line 231 may be connected to the peripheral circuit PC through the first peripheral contact plug 221. That is, the first peripheral circuit conductive line 231 may be connected to the source / drain regions provided on at least one side of the peripheral circuit PC through the first peripheral contact plug 221. The first peripheral circuit conductive line 231 and the second peripheral circuit conductive line 233 may be connected through the second peripheral contact plug 223.

[0117] A first contact insulating layer BPL1 and a first contact pad BP1 may be disposed on the peripheral circuit insulating layer 212. The first contact pad BP1 may be connected to the second peripheral circuit conductive line 233 through a third peripheral contact plug 225.

[0118] Thus, the first contact pad BP1 may be connected to the peripheral circuit PC through the second peripheral circuit wire 233, the second peripheral contact plug 223, the first peripheral circuit wire 231, and the first peripheral contact plug 221. However, the connection relationship among the peripheral circuit PC, the peripheral contact plug 220, the peripheral circuit wire 230, and the first contact pad BP1 included in the peripheral circuit structure PS is not limited thereto and may be changed in many ways.

[0119] The first through-chip via 313 may pass through the semiconductor substrate 100 and the peripheral circuit structure PS to connect to the first contact pad BP1. That is, the first through-chip via 313 may pass through the semiconductor substrate 100 and the peripheral circuit insulation layer 212 of the peripheral circuit structure PS to connect to one of the first contact pads BP1.

[0120] A first end of the first chip through via 313 may be connected to the first contact pad BP1, and a second end of the first chip through via 313 may be connected to the first contact pad BP1. Figure 1 The first chip pad 41 on the first semiconductor chip 10a is formed on the first chip through-via 313. For example, the first chip through-via 313 may extend through the entire semiconductor substrate 100 and through the entire peripheral circuit structure PS in the vertical direction (Z). For example, the sidewall of the first chip through-via 313 may be a single, continuous, uninterrupted surface from the bottom of the semiconductor substrate 100 to the top of the peripheral circuit structure PS.

[0121] Figure 3The first chip through via 313 is shown to be directly connected to the first contact pad BP1, but the connection relationship between the first chip through via 313 and the first contact pad BP1 is not limited thereto and can be changed in many ways. For example, the first chip through via 313 can be connected to the first contact pad BP1 through the peripheral contact plug 220 and the peripheral circuit wire 230.

[0122] In some embodiments, the first through chip via 313 may be electrically connected to the first contact pad BP1 and the peripheral circuit PC simultaneously through the peripheral contact plug 220 and the peripheral circuit conductive line 230 .

[0123] Depending on the aspect ratio of the cross section, the width of the first through-chip via 313 in the first direction (X) may decrease as the distance from the first contact pad BP1 increases. For example, the width of the first through-chip via 313 may narrow as it approaches the first contact pad BP1. However, the cross-sectional shape of the first through-chip via 313 is not limited thereto and may vary in many ways. For example, depending on the aspect ratio of the cross section, the width of the first through-chip via 313 in the first direction (X) may increase as the distance from the first contact pad BP1 increases.

[0124] The first through-chip via 313 may include a conductive material. For example, the conductive material may include at least one of metals such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and copper (Cu), or a combination thereof. However, the conductive material is not limited thereto and may be varied in many ways.

[0125] The cell array structure CS may be disposed on the peripheral circuit structure PS. That is, the cell array structure CS may overlap the peripheral circuit structure PS in the third direction (Z) that is the vertical direction.

[0126] The cell array structure CS arranged in the cell array region CAR may include a second contact insulating layer BPL2, a second contact pad BP2, a bit line BL (160), a shielding pattern SP, a first active pattern AP1 and a second active pattern AP2, a first word line WL1 and a second word line WL2, a back gate electrode BG, a buried contact BC, a landing pad (also called a pad, a bonding pad) LP and a capacitor DSP, and the cell array structure CS arranged in the peripheral circuit region PAR may include a second chip through via 315.

[0127] As described above, the cell array structure CS and the peripheral circuit structure PS can be combined and connected to each other through the contact pads BP and the contact insulating layer BPL. That is, the first contact pads BP1 and the first contact insulating layer BPL1 provided in the peripheral circuit structure PS can be bonded and connected to the respective second contact pads BP2 and the second contact insulating layer BPL2 provided in the cell array structure CS. The detailed description thereof is substantially the same as that described above and will therefore be omitted.

[0128] The semiconductor chip 10a may further include a cell array insulating layer 214 disposed on the second contact pad BP2 and the second contact insulating layer BPL2, a lower contact plug 241 disposed in the cell array insulating layer 214, and a lower conductive line 242. The cell array insulating layer 214 may include an insulating material. For example, the cell array insulating layer 214 may include one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0129] The lower conductive line 242 may be connected to a component provided in the cell array structure CS, and the lower contact plug 241 may connect the second contact pad BP2 to the lower conductive line 242 .

[0130] Thus, the first contact pad BP1 provided in the peripheral circuit structure PS and the second contact pad BP2 provided in the cell array structure CS are bonded to each other to provide an electrical connection path between the peripheral circuit structure PS and the cell array structure CS. For example, the lower conductive line 242 connected to the component included in the cell array structure CS can be electrically connected to at least one of the peripheral circuit PC included in the peripheral circuit structure PS, the peripheral contact plug 220, and the peripheral circuit conductive line 230 through the contact pad BP.

[0131] The peripheral contact plugs 220 and the peripheral circuit conductive lines 230 provided in the peripheral circuit structure PS, and the lower contact plugs 241 and the lower conductive lines 242 provided in the cell array structure CS, may each include a conductive material. For example, the conductive material may include aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), and tantalum (Ta). However, the conductive material is not limited thereto and may be modified in many ways.

[0132] The bit lines BL may extend parallel to each other in a first direction (X) crossing the second direction (Y). The bit lines BL may be spaced apart from each other in the second direction (Y) on the semiconductor substrate 100 .

[0133] Each bit line BL ( 160 ) may include a polysilicon layer 161 , a first metal layer 163 , a second metal layer 165 , and a bit line hard mask layer 167 , which are sequentially stacked.

[0134] Polysilicon layer 161 may include polysilicon doped with impurities, and first metal layer 163 and second metal layer 165 may include conductive materials. For example, first metal layer 163 may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and second metal layer 165 may include a metal (e.g., tungsten, titanium, tantalum, etc.). At least one of first metal layer 163 and second metal layer 165 may include a metal silicide (e.g., titanium silicide, cobalt silicide, or nickel silicide). However, the materials included in first metal layer 163 and second metal layer 165 are not limited thereto and may be varied in many ways.

[0135] The bit line hard mask layer 167 may include an insulating material such as silicon nitride or silicon oxynitride.

[0136] The bit line BL may be disposed near the peripheral circuit structure PS. Therefore, the electrical connection path between the bit line BL and the peripheral circuit PC may be reduced.

[0137] The shielding pattern SP may be disposed between the peripheral circuit structure PS and the bit line BL.

[0138] The shielding pattern SP may be made of a conductive material and may include, for example, a metal material such as tungsten (W), titanium (Ti), nickel (Ni), and cobalt (Co). For another example, the shielding pattern SP may include a conductive 2D material such as graphene.

[0139] The first semiconductor chip 10a may further include a spacer insulating layer 175 disposed between the shielding pattern SP and the bit line BL. The spacer insulating layer 175 may have a substantially uniform thickness and may be conformally disposed between the bit line BL and the shielding pattern SP.

[0140] The spacer insulating layer 175 may include, for example, silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer.

[0141] The first semiconductor chip 10a may also include a shielding cover pattern 179 arranged on the shielding pattern SP, a first lower insulating layer 177 arranged between the spacer insulating layer 175 and the cell array insulating layer 214, a second lower insulating layer 173 arranged on the spacer insulating layer 175, a bit line etch stopper 171 arranged between the bit line BL and the spacer insulating layer 175, and a cell area shallow trench isolation STI arranged on the second lower insulating layer 173.

[0142] A shielding capping pattern 179 may be disposed on the shielding pattern SP, and the shielding capping pattern 179 may contact the cell array insulating layer 214 .

[0143] A first lower insulating layer 177 may be disposed on the cell array insulating layer 214 . An upper surface of the first lower insulating layer 177 may contact the spacer insulating layer 175 , and side surfaces of the first lower insulating layer 177 may contact side surfaces of the shielding pattern SP and the shield cap pattern 179 .

[0144] The second lower insulating layer 173 may be disposed on the spacer insulating layer 175. Side surfaces of the second lower insulating layer 173 may face side surfaces of the bit lines BL.

[0145] The bit line etch stopper 171 may be disposed between the bit line BL and the spacer insulating layer 175. The bit line etch stopper 171 may extend along the lower surface and side surfaces of the bit line BL. The bit line etch stopper 171 may be disposed on the second lower insulating layer 173 and may extend along the upper surface and side surfaces of the second lower insulating layer 173.

[0146] The cell region shallow trench isolation (STI) may be disposed on the second lower insulating layer 173 . A portion of the bit line etch stopper 171 may be disposed between the cell region shallow trench isolation (STI) and the second lower insulating layer 173 .

[0147] The shield cap pattern 179 , the first lower insulating layer 177 , the second lower insulating layer 173 , the bit line etch stopper 171 , and the cell region shallow trench isolation STI may include silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric layer.

[0148] The first semiconductor chip 10 a may further include a bit line contact plug 247 .

[0149] The bit line contact plug 247 may be connected to a peripheral portion of an end portion of the bit line BL that does not overlap the shielding pattern SP in the third direction (Z).

[0150] The bit line BL may be connected to the second contact pad BP2 through a bit line contact plug 247 penetrating the cell array insulating layer 214 , the first lower insulating layer 177 , the spacer insulating layer 175 , the bit line etch stopper 171 , and the bit line hard mask layer 167 .

[0151] The bit line BL connected to the second contact pad BP2 can be connected to the peripheral circuit conductive line 230 and / or the peripheral circuit PC provided in the peripheral circuit structure PS through the first contact pad BP1. However, the connection relationship between the bit line BL and the peripheral circuit structure PS is not limited thereto and can be changed in many ways.

[0152] Despite Figure 3 Although not shown, the first semiconductor chip 10 a according to some embodiments may further include a shielding contact plug for connecting the shielding pattern SP and the peripheral circuit structure PS.

[0153] The first active pattern AP1 and the second active pattern AP2 may be disposed on the bit line BL. The first active pattern AP1 and the second active pattern AP2 may be alternately disposed and may extend in the second direction (Y).

[0154] The first active pattern AP1 and the second active pattern AP2 may be made of a single crystalline semiconductor material. For example, the first active pattern AP1 and the second active pattern AP2 may be made of single crystalline silicon.

[0155] When operating the semiconductor chip, the first and second active patterns AP1 and AP2 may be controlled by the first and second word lines WL1 and WL2 and the back gate electrode BG. The first and second active patterns AP1 and AP2 are made of a single crystalline semiconductor material, thereby improving leakage current characteristics of the semiconductor memory device.

[0156] The back gate electrode BG may be disposed on the bit line BL and the shield pattern SP. The first active pattern AP1 may be disposed on a first side of the back gate electrode BG, and the second active pattern AP2 may be disposed on a second side of the back gate electrode BG. The height of the back gate electrode BG in the third direction (Z) may be smaller than the heights of the first active pattern AP1 and the second active pattern AP2 in the third direction (Z).

[0157] The first active pattern AP1 may be disposed between the first word line WL1 and the back gate electrode BG. The second active pattern AP2 may be disposed between the second word line WL2 and the back gate electrode BG.

[0158] The back gate electrode BG may include a conductive material, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, and metal.

[0159] When operating the semiconductor chip, the back gate electrode BG may receive a negative voltage and increase the threshold voltage of the vertical channel transistor. In other words, as the vertical channel transistor becomes smaller, the threshold voltage may decrease. A negative voltage is applied to the back gate electrode BG to prevent the threshold voltage from decreasing, thereby preventing the leakage current characteristics from deteriorating.

[0160] The first semiconductor chip 10 a may further include a first back gate separation pattern 111 , a second back gate separation pattern 113 , a back gate insulating pattern 115 , and a back gate capping pattern 117 .

[0161] The first back gate separation pattern 111 and the second back gate separation pattern 113 may be disposed between the first active pattern AP1 and the second active pattern AP2 disposed adjacent to each other.

[0162] The first back gate separation pattern 111 may contact the first and second active patterns AP1 and AP2 , and the second back gate separation pattern 113 may be spaced apart from the first and second active patterns AP1 and AP2 , with the first back gate separation pattern 111 therebetween.

[0163] The back gate electrode BG may include a first surface and a second surface that are opposite to each other in a third direction (Z), which is a vertical direction. The first surface of the back gate electrode BG may face the bit line BL and the shielding pattern SP, and the second surface of the back gate electrode BG may face the first back gate separation pattern 111 and the second back gate separation pattern 113. In other words, the first back gate separation pattern 111 and the second back gate separation pattern 113 may be provided on the second surface of the back gate electrode BG.

[0164] The first back gate separation pattern 111 and the second back gate separation pattern 113 may include an insulating material. The first back gate separation pattern 111 and the second back gate separation pattern 113 may each include at least one of silicon oxide, a silicon oxynitride layer, and a silicon nitride layer. For example, the first back gate separation pattern 111 may include silicon oxide, and the second back gate separation pattern 113 may include at least one of a silicon oxynitride layer and a silicon nitride layer. However, the materials included in the first back gate separation pattern 111 and the second back gate separation pattern 113 are not limited thereto and may be varied in many ways.

[0165] The back gate insulating pattern 115 may be disposed between the back gate electrode BG and the first active pattern AP1 and between the back gate electrode BG and the second active pattern AP2 . The back gate insulating pattern 115 may also be disposed between the back gate electrode BG and a gate insulating pattern GOX to be described.

[0166] The back gate insulating pattern 115 may include, for example, silicon oxide, a silicon oxynitride layer, a high dielectric insulating layer having a higher dielectric constant than silicon oxide, and combinations thereof.

[0167] The back gate capping pattern 117 may cover the back gate electrode BG between the bit line BL and the back gate electrode BG. That is, the back gate capping pattern 117 may cover the first surface of the back gate electrode BG.

[0168] The back gate capping pattern 117 may include an insulating material. For example, the back gate capping pattern 117 may include one of silicon oxide, silicon nitride, silicon oxynitride, and a combination thereof. However, the material included in the back gate capping pattern 117 is not limited thereto and may be varied in many ways.

[0169] The first and second word lines WL1 and WL2 may be disposed on the bit lines BL and the shielding pattern SP.

[0170] The first and second word lines WL1 and WL2 may include first and second surfaces, respectively, facing each other in the third direction (Z). A first surface of each of the first and second word lines WL1 and WL2 may face the bit line BL and the shield pattern SP, and a second surface of each of the first and second word lines WL1 and WL2 may face a buried contact BC and a second gate capping pattern 155 to be described.

[0171] The first word line WL1 and the second word line WL2 may be disposed between the bit line BL and the buried contact BC and may extend in a third direction (Z).

[0172] The first and second word lines WL1 and WL2 may include a conductive material (eg, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, and metal).

[0173] Despite Figure 3 Although not shown, the first semiconductor chip 10 a according to some embodiments may further include word line contact plugs for connecting the first and second word lines WL1 and WL2 and the peripheral circuit structure PS to each other.

[0174] The first semiconductor chip 10a may further include a gate insulating pattern GOX disposed on side surfaces of the first word line WL1 and the second word line WL2, a gate separation pattern 151 disposed between the first word line WL1 and the second word line WL2, and a first gate capping pattern 153 and a second gate capping pattern 155 disposed on the first surface and the second surface of the first word line WL1 and the second word line WL2, respectively.

[0175] The gate insulating pattern GOX may extend along the third direction (Z) between the first and second active patterns AP1 and AP2 and the first and second word lines WL1 and WL2 and may be disposed between the first active pattern AP1 and the first and second gate capping patterns 153 and 155 and between the second active pattern AP2 and the first and second gate capping patterns 153 and 155.

[0176] A portion of the gate insulation pattern GOX may be disposed on a side surface of the cell region shallow trench isolation STI. That is, a portion of the gate insulation pattern GOX may be disposed between the cell region shallow trench isolation STI and the first gate capping pattern 153. During the process for patterning the gate insulation pattern GOX, the gate insulation pattern GOX disposed on the cell region shallow trench isolation STI may remain.

[0177] The gate insulating pattern GOX may be made of silicon oxide, a silicon oxynitride layer, a high dielectric layer having a higher dielectric constant than silicon oxide, or a combination thereof. The high dielectric layer may be made of a metal oxide or a metal oxide nitride. For example, the high dielectric layer that may be used as the gate insulating pattern GOX may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0178] The gate separation pattern 151 may be disposed between the first word line WL1 and the second word line WL2. The gate separation pattern 151 may be disposed between the first gate capping pattern 153 and the second gate capping pattern 155. The gate separation pattern 151 may contact the first word line WL1 and the second word line WL2. The first word line WL1 and the second word line WL2 may be separated by the gate separation pattern 151. The gate separation pattern 151 may extend along a third direction (Z) between the first word line WL1 and the second word line WL2.

[0179] The first gate capping pattern 153 may be disposed between the spacer insulating layer 175 and the first and second word lines WL1 and WL2 and between the spacer insulating layer 175 and the gate separation pattern 151 .

[0180] In detail, the first gate capping pattern 153 may be disposed on the first surfaces of the first and second word lines WL1 and WL2 and the first surface of the gate separation pattern 151. The first gate capping pattern 153 may surround the first surface of the gate separation pattern 151 and a portion of each side thereof.

[0181] like Figure 3 As shown in FIG, the first gate capping pattern 153 may cover the first surface of the second word line WL2 and the end of the second word line WL2. The first gate capping pattern 153 covering the end of the second word line WL2 may be opposite to the cell region shallow trench isolation STI, with the gate insulation pattern GOX between the first gate capping pattern 153 and the cell region shallow trench isolation STI. The arrangement relationship between the second word line WL2 and the first gate capping pattern 153 may be substantially identically applied to the arrangement relationship between the first word line WL1 and the first gate capping pattern 153.

[0182] The second gate capping pattern 155 may be disposed between the first and second word lines WL1 and WL2 and the contact interlayer insulating layer 271 .

[0183] In detail, the second gate capping pattern 155 may be disposed on the second surfaces of the first and second word lines WL1 and WL2 and the second surface of the gate separation pattern 151 .

[0184] The second gate capping pattern 155 may surround the second surface of the gate separating pattern 151 and a portion of each side of the gate separating pattern 151. That is, the second gate capping pattern 155 may extend in the second direction (Y), which is a horizontal direction, on the second surface of the gate separating pattern 151, and may extend in the third direction (Z), which is a vertical direction, on each side of the gate separating pattern 151.

[0185] The gate separation pattern 151, the first gate capping pattern 153, and the second gate capping pattern 155 may include an insulating material (eg, silicon oxide, silicon nitride, and combinations thereof). For example, the gate separation pattern 151 may include silicon oxide, and the first gate capping pattern 153 and the second gate capping pattern 155 may include silicon nitride.

[0186] The first semiconductor chip 10 a may further include a contact interlayer insulating layer 271 , a pad separation insulating layer 273 , and a contact etch stopper 275 .

[0187] The contact interlayer insulating layer 271, the pad separation insulating layer 273, and the contact etch stopper 275 may include insulating materials (e.g., silicon oxide, silicon nitride, and combinations thereof). The contact interlayer insulating layer 271 may be disposed on the first active pattern AP1 and the second active pattern AP2. The contact interlayer insulating layer 271 may cover the first and second back gate separation patterns 111 and 113, the second gate capping pattern 155, and the cell region shallow trench isolation (STI).

[0188] In the cell array structure CS provided in the cell array region CAR, buried contacts BC, landing pads LP, and capacitors DSP may be sequentially stacked.

[0189] The buried contacts BC may penetrate the contact interlayer insulating layer 271. The buried contacts BC may be connected to the first active pattern AP1 and the second active pattern AP2, respectively. The buried contacts BC adjacent to each other may be separated from each other by the contact interlayer insulating layer 271.

[0190] The buried contact BC may include a conductive material. For example, the buried contact BC may include at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, and metal.

[0191] The landing pad LP may be disposed on the buried contact BC. The pad separation insulating layer 273 may be disposed on the contact interlayer insulating layer 271. The pad separation insulating layer 273 may be disposed between the landing pads LP. The upper surface of the landing pad LP may be substantially coplanar with the upper surface of the pad separation insulating layer 273.

[0192] The landing pad LP may include a conductive material, such as at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, 2D material, and metal.

[0193] Capacitors DSP may be provided on the landing pads LP. Capacitors DSP may be connected to the first active pattern AP1 and the second active pattern AP2, respectively. Capacitors DSP may completely or partially overlap the landing pads LP in the third direction (Z). Capacitors DSP may contact all or part of the upper surface of each landing pad LP.

[0194] Each capacitor DSP may include a cell lower electrode 251, a cell upper electrode 255, and a cell dielectric layer 253 disposed between the cell lower electrode 251 and the cell upper electrode 255. The cell lower electrode 251 may penetrate the contact etch stopper 275 to contact the landing pad LP. The cell lower electrode 251 may extend in a third direction (Z) as a vertical direction on the landing pad LP.

[0195] The cell lower electrode 251 may include a metal, a conductive metal nitride, or a combination thereof. For example, the cell lower electrode 251 may be made of TiN, Ru, TaN, WN, Pt, Ir, or a combination thereof. However, the material included in the cell lower electrode 251 is not limited thereto and may be varied in many ways.

[0196] The cell dielectric layer 253 may be conformally disposed along the contours of the upper and side surfaces of the cell lower electrode 251. That is, the cell dielectric layer 253 may cover the side and upper surfaces of the cell lower electrode 251. A portion of the cell dielectric layer 253 may be disposed on the upper surface of the contact etch stopper 275. That is, a portion of the cell dielectric layer 253 may be disposed between the contact etch stopper 275 and the cell upper electrode 255.

[0197] The cell dielectric layer 253 may include tantalum oxide (Ta2O5), aluminum oxide (Al2O3), titanium oxide (TiO2), and combinations thereof. However, not limited thereto, the material included in the cell dielectric layer 253 may be varied in many ways.

[0198] The cell upper electrode 255 may be disposed on the cell dielectric layer 253. The cell upper electrode 255 may cover the cell dielectric layer 253. That is, the cell upper electrode 255 may cover the upper surface and the side surface of the cell dielectric layer 253.

[0199] The cell upper electrode 255 may include a protrusion extending from a portion extending along the side surface of the cell dielectric layer 253 in a first direction (X) as a horizontal direction and disposed on the contact etch stopper 275. That is, the protrusion of the cell upper electrode 255 may correspond to a terminal of the cell upper electrode 255, and the terminal of the cell upper electrode 255 may be disposed on the contact etch stopper 275.

[0200] The protrusion of the cell upper electrode 255 may extend in a horizontal direction from the cell upper electrode 255 contacting a portion of the cell dielectric layer 253 contacting the contact etch stopper 275. The protrusion of the cell upper electrode 255 may be disposed in the cell array region CAR and the peripheral circuit region PAR.

[0201] The first semiconductor chip 10 a may further include a capacitor contact plug 243 for connecting the cell upper electrode 255 to the second contact pad BP2 .

[0202] The capacitor contact plug 243 may penetrate the cell dielectric layer 253 , the contact etch stopper 275 , and an insulating layer disposed between the second contact insulating layer BPL2 and the pad separation insulating layer 273 , and may electrically connect the cell upper electrode 255 to the second contact pad BP2 .

[0203] For example, the cell upper electrode 255 may be connected to the second contact pad BP2 through a lower conductive line 242 connected to the capacitor contact plug 243 and the lower contact plug 241 .

[0204] When the first contact pad BP1 contacts the second contact pad BP2, the cell upper electrode 255 connected to the second contact pad BP2 may be connected to the peripheral circuit conductive line 230 and / or the peripheral circuit PC provided in the peripheral circuit structure PS. However, the connection relationship between the cell upper electrode 255 and the peripheral circuit structure PS is not limited thereto and may be changed in many ways.

[0205] The cell upper electrode 255 may include a metal material such as W, Ti, Ru, or SiGe. For example, the cell upper electrode 255 may include tungsten (W). However, the material included in the cell upper electrode 255 is not limited thereto and may be varied in many ways. For example, the cell upper electrode 255 may include a conductive metal nitride, a metal silicide, or a combination thereof.

[0206] The first semiconductor chip 10 a may include first and second upper insulating layers 277 and 279 sequentially stacked on the contact etch stopper 275 , first upper contact plugs 261 and first upper conductive lines 262 disposed in the first upper insulating layer 277 , and second upper contact plugs 263 and second upper conductive lines 264 disposed in the second upper insulating layer 279 .

[0207] The first upper insulating layer 277 may cover the capacitor DSP. That is, the first upper insulating layer 277 may cover the upper surface and the side surface of the capacitor DSP.

[0208] In the cell array region CAR, the capacitor DSP may be connected to the first upper conductive line 262 through the first upper contact plug 261 , and the first upper conductive line 262 may be connected to the second upper conductive line 264 through the second upper contact plug 263 .

[0209] The first upper contact plug 261 , the first upper conductive line 262 , the second upper contact plug 263 , and the second upper conductive line 264 may include at least one of metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta), or a combination thereof.

[0210] The second chip through via 315 may be provided in the peripheral circuit region PAR of the cell array structure CS. The second chip through via 315 may penetrate at least a portion of the cell array structure CS.

[0211] In detail, the second chip through via 315 can penetrate the first upper insulating layer 277 and the second upper insulating layer 279, the contact etch stopper 275, the pad separation insulating layer 273, the contact interlayer insulating layer 271, the cell area shallow trench isolation STI, the bit line etch stopper 171, the first lower insulating layer 177 and the second lower insulating layer 173, the spacer insulating layer 175 and the cell array insulating layer 214, and can be connected to one of the second contact pads BP2 in the cell array structure CS set in the peripheral circuit area PAR.

[0212] A first end of the second chip through via 315 may be connected to the second contact pad BP2, and a second end of the second chip through via 315 may be connected to the second contact pad BP2. Figure 1 The second chip pad 42 is provided on the first semiconductor chip 10 a.

[0213] Therefore, the first through-chip via 313 provided in the peripheral circuit structure PS and the second through-chip via 315 provided in the cell array structure CS may be electrically connected to each other through the contact pad BP.

[0214] Figure 3 The second chip through via 315 is shown to be directly connected to the second contact pad BP2, but the connection relationship between the second chip through via 315 and the second contact pad BP2 is not limited thereto and can be changed in many ways. For example, the second chip through via 315 can be electrically connected to the second contact pad BP2 through the lower conductive line 242 and the lower contact plug 241.

[0215] In one embodiment, when viewed in cross-section, the width of the second chip through via 315 in the first direction (X) may decrease according to the distance from the semiconductor substrate 100 according to the aspect ratio. For example, the width of the second chip through via 315 may become narrower as it approaches the semiconductor substrate 100, but is not limited thereto.

[0216] The length of the first through-chip via 313 in the third direction (Z) may be different from the length of the second through-chip via 315 in the third direction (Z). For example, the length of the first through-chip via 313 in the third direction (Z) may be smaller than the length of the second through-chip via 315 in the third direction (Z). However, the relationship between the length of the first through-chip via 313 in the third direction (Z) and the length of the second through-chip via 315 in the third direction (Z) is not limited thereto and may vary in many ways.

[0217] The second through-chip via 315 may include a conductive material. For example, the conductive material may include at least one of metals such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and copper (Cu), or a combination thereof. However, the conductive material is not limited thereto and may be varied in many ways.

[0218] Therefore, the first through-chip via 313 provided in the peripheral circuit structure PS may be electrically connected to the second through-chip via 315 provided in the cell array structure CS through the contact pad BP.

[0219] According to the semiconductor device 1 according to the embodiment, when the first to fourth semiconductor chips 10a, 10b, 10c and 10d of the peripheral circuit structure PS and the cell array structure CS stacked in the vertical direction are stacked sequentially by bonding and connecting the contact pads BP, and the first to fourth semiconductor chips 10a, 10b, 10c and 10d are electrically connected to each other through the first chip through vias 313 and the second chip through vias 315, the area efficiency and characteristics of the semiconductor device 1 can be improved.

[0220] That is, compared with the case where the peripheral circuit structure PS and the cell array structure CS are arranged on the same plane, when the peripheral circuit structure PS and the cell array structure CS of the respective first to fourth semiconductor chips 10a, 10b, 10c and 10d are stacked in the vertical direction, the size (for example, the horizontal size) of the respective first to fourth semiconductor chips 10a, 10b, 10c and 10d can be reduced, and the characteristics of the respective first to fourth semiconductor chips 10a, 10b, 10c and 10d can be improved.

[0221] Therefore, the semiconductor device 1 according to the embodiment can reduce the height of stacking the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d , and can improve the reliability of the semiconductor device 1 .

[0222] Now refer to Figures 4 to 15 Semiconductor devices according to embodiments are described. In the following embodiments, the same reference numerals will be used for the same configurations as those in the above-described embodiments, repeated descriptions will be omitted or simplified, and differences will be mainly described.

[0223] Figure 4 and Figure 5 A partially enlarged view of a cross section of a semiconductor device according to some embodiments is shown. Figure 4 and Figure 5 Shown with Figure 1 Partially enlarged view of region R2 and region R3 corresponding to region R1.

[0224] according to Figure 4 The embodiment shown in Figure 2 In the embodiment shown in FIG. 5 , the width of the first contact pad BP1 and the width of the second contact pad BP2 are substantially the same, there is a difference in that the width of the first contact pad BP1 is different from the width of the second contact pad BP2 .

[0225] Reference Figure 4 , the first width W1 may be different from the second width W2. For example, the first width W1 may be greater than the second width W2. The ratio of the first width W1 to the second width W2 may be about 3:1 to about 7:1. However, the relationship and ratio of the first width W1 to the second width W2 are not limited thereto and may vary in many ways. For example, the first width W1 may be smaller than the second width W2.

[0226] Figure 4 The first contact pad BP1 and the second contact pad BP2 are shown stacked such that the center of the first contact pad BP1 matches the center of the second contact pad BP2. However, the arrangement of the first contact pad BP1 and the second contact pad BP2 is not limited to this and can be varied in many ways. For example, the center of the first contact pad BP1 can be offset from the center of the second contact pad BP2. In other words, the center of the second contact pad BP2 can be spaced apart from the center of the first contact pad BP1 toward the first side or the second side of the first direction (X) and / or the second direction (Y).

[0227] For another example, the second contact pad BP2 may overlap a portion of the first contact pad BP1 in the third direction (Z). That is, a portion of the second contact pad BP2 may be disposed on the first contact pad BP1, and another portion of the second contact pad BP2 may be disposed on the first contact insulating layer BPL1.

[0228] according to Figure 5 In the embodiment shown in FIG, there is a difference in thickness between the first contact pad BP1 and the second contact pad BP2.

[0229] Reference Figure 5 , the first thickness D1 may be different from the second thickness D2. For example, the first thickness D1 may be greater than the second thickness D2. The ratio of the first thickness D1 to the second thickness D2 may be from about 3:1 to about 7:1. However, the relationship and ratio of the first thickness D1 to the second thickness D2 are not limited thereto and may vary in many ways. For example, the first thickness D1 may be less than the second thickness D2.

[0230] In this embodiment, the thickness of the first contact insulating layer BPL1 in the third direction (Z) may be different from the thickness of the second contact insulating layer BPL2 in the third direction (Z). In other words, the thickness relationship between the first contact insulating layer BPL1 and the second contact insulating layer BPL2 may be substantially the same as the thickness relationship between the first contact pad BP1 and the second contact pad BP2. For example, the thickness of the first contact insulating layer BPL1 may be greater than the thickness of the second contact insulating layer BPL2. However, this is not limiting, and the thickness relationship between the first contact insulating layer BPL1 and the second contact insulating layer BPL2 may be varied in many ways.

[0231] Although not shown, in some embodiments, the width and thickness of the first contact pad BP1 may be different from the width and thickness of the second contact pad BP2. For example, the first width W1 and the first thickness D1 of the first contact pad BP1 may be greater than the second width W2 and the second thickness D2 of the second contact pad BP2, respectively.

[0232] According to Figure 4 and Figure 5 In the semiconductor device of the embodiment shown in , at least one of the width and thickness of the first contact pad BP1 and the second contact pad BP2 is different from each other, so that the bonding margin of the first contact pad BP1 and the second contact pad BP2 can be obtained, and the first contact pad BP1 and the second contact pad BP2 can be stably bonded.

[0233] At least one of the width and thickness of the first contact pad BP1 and the second contact pad BP2 is different, so when the first to fourth semiconductor chips 10a, 10b, 10c and 10d are stacked, the first contact pad BP1 and the second contact pad BP2 can stably maintain their bonding, and the respective first chip through vias 313 and the second chip through vias 315 can be stably connected to the first contact pad BP1 and the second contact pad BP2.

[0234] Figure 6 A cross-sectional view of a semiconductor device according to some embodiments is shown. Figure 7 A cross-sectional view illustrating a semiconductor chip included in a semiconductor device according to some embodiments is shown.

[0235] About the basis Figure 6 and Figure 7 In the semiconductor device 1_1 of one embodiment shown in FIG, there is a difference in that the connection between the peripheral circuit structure PS and the cell array structure CS is different in each of the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d included in the semiconductor device 1_1 .

[0236] The first chip through-vias 313 provided in the peripheral circuit structure PS of the respective first to fourth semiconductor chips 10a, 10b, 10c and 10d included in the semiconductor device 1_1 and the second chip through-vias 315 provided in the cell array structure CS can be connected to each other through the upper contact pad UMP, the conductive contact electrode MC and the lower contact pad LMP.

[0237] The first semiconductor chip 10 a will now be generally described.

[0238] In detail, in this embodiment, referring to Figure 6 and Figure 7 , the first semiconductor chip 10a may include a lower contact pad LMP disposed in the peripheral circuit structure PS and an upper contact pad UMP disposed in the cell array structure CS.

[0239] The lower contact pad LMP and the upper contact pad UMP may be disposed in the peripheral circuit region PAR of the semiconductor substrate 100. However, the positions of the lower contact pad LMP and the upper contact pad UMP are not limited thereto and may be varied in many ways. For example, the lower contact pad LMP and the upper contact pad UMP may be disposed in the cell array region CAR of the semiconductor substrate 100.

[0240] The lower contact pad LMP may include the same material as the peripheral circuit wire 230 in the peripheral circuit structure PS and may be disposed at substantially the same height as the peripheral circuit wire 230. For example, the lower contact pad LMP may include the same material as the second peripheral circuit wire 233 among the peripheral circuit wires 230 and may be disposed at substantially the same height as the second peripheral circuit wire 233. For another example, the lower contact pad LMP may include the same material as the first peripheral circuit wire 231 among the peripheral circuit wires 230 and may be disposed at substantially the same height as the first peripheral circuit wire 231. For another example, the lower contact pad LMP may include a different material than the peripheral circuit wire 230 and may be disposed at a different height than the peripheral circuit wire 230.

[0241] In this embodiment, the first chip through-via 313 provided in the peripheral circuit structure PS may be connected to the lower contact pad LMP. The first chip through-via 313 may penetrate at least a portion of the semiconductor substrate 100 and the peripheral circuit insulation layer 212 and may be connected to the bottom surface of the lower contact pad LMP.

[0242] The upper contact pad UMP may include the same material as the capacitor DSP and may be provided at substantially the same height as the capacitor DSP in the cell array structure CS. For example, the upper contact pad UMP may include the same material as the cell upper electrode 255 of the capacitor DSP and may be provided at substantially the same height as the protrusion of the cell upper electrode 255. That is, the upper contact pad UMP may be provided on the contact etch stopper 275.

[0243] For another example, the upper contact pad UMP may include the same material as the unit lower electrode 251 of the capacitor DSP and may be disposed at substantially the same height as the unit lower electrode 251. That is, the upper contact pad UMP may be disposed in the contact etch stopper 275 and on the pad separation insulating layer 273.

[0244] For another example, the upper contact pad UMP may include the same material as the landing pad LP and may be disposed at substantially the same height as the landing pad LP. That is, the upper contact pad UMP may be disposed in the pad separation insulating layer 273 .

[0245] The upper contact pads UMP may include a first upper contact pad UMP1 connected to the bit line contact plug 247 and a second upper contact pad UMP2 connected to the second through-chip via 315 provided in the cell array structure CS.

[0246] In this embodiment, the bit line contact plugs 247 may include a first bit line contact plug 247 a for connecting the first upper contact pad UMP1 to the peripheral circuit conductive line 230 and a second bit line contact plug 247 b for connecting the first upper contact pad UMP1 to the bit line BL.

[0247] The first bit line contact plug 247a can penetrate the contact interlayer insulating layer 271, the pad separation insulating layer 273, the contact etch stopper 275, the cell area shallow trench isolation STI, the bit line etch stopper 171, the first lower insulating layer 177, the spacer insulating layer 175, the second lower insulating layer 173 and the cell array insulating layer 214, and can be connected to the second peripheral circuit wire 233 among the peripheral circuit wires 230.

[0248] The second bit line contact plug 247 b may penetrate the contact interlayer insulating layer 271, the pad separation insulating layer 273, the contact etch stopper 275, and the cell region shallow trench isolation STI and may be connected to the polysilicon layer 161 of the bit line BL. However, the present invention is not limited thereto, and the second bit line contact plug 247 b may be connected to one of the first metal layer 163 and the second metal layer 165 of the bit line BL.

[0249] The peripheral circuit conductive line 230 of the peripheral circuit structure PS and / or the peripheral circuit PC and the bit line BL of the cell array structure CS may be electrically connected to each other through the first bit line contact plug 247 a and the second bit line contact plug 247 b connected to the first upper contact pad UMP1. However, the connection relationship between the bit line BL and the peripheral circuit structure PS is not limited thereto and may be changed in many ways.

[0250] In the present embodiment, the widths of the first and second bit line contact plugs 247 a and 247 b in the first direction (X) may decrease according to the distance from the semiconductor substrate 100, depending on the aspect ratio in cross section. For example, the first and second bit line contact plugs 247 a and 247 b may become narrower as they approach the semiconductor substrate 100.

[0251] In the present embodiment, the second through-chip via 315 provided in the cell array structure CS may be connected to the second upper contact pad UMP2 .

[0252] The second chip through-via 315 may penetrate at least a portion of the cell array structure CS and may be connected to the upper surface of the second upper contact pad UMP2. That is, the second chip through-via 315 may penetrate the first upper insulating layer 277 and the second upper insulating layer 279 and may be connected to the second upper contact pad UMP2.

[0253] In the present embodiment, the first semiconductor chip 10 a may include a conductive contact electrode MC for connecting the lower contact pad LMP to an upper contact pad UMP (eg, the second upper contact pad UMP2 ).

[0254] The conductive contact electrode MC may penetrate a portion of the peripheral circuit structure PS and a portion of the cell array structure CS. That is, the conductive contact electrode MC may extend in the third direction (Z) from the peripheral circuit structure PS to the cell array structure CS. In other words, a portion of the conductive contact electrode MC may be disposed in the peripheral circuit structure PS, and another portion of the conductive contact electrode MC may be disposed in the cell array structure CS.

[0255] The conductive contact electrode MC may penetrate some or all of the contact interlayer insulating layer 271, the pad separation insulating layer 273, the contact etch stopper 275, the cell area shallow trench isolation STI, the bit line etch stopper 171, the first lower insulating layer 177, the spacer insulating layer 175, the second lower insulating layer 173 and the cell array insulating layer 214, and may be connected to the lower contact pad LMP.

[0256] In this embodiment, the width of the conductive contact electrode MC in the first direction (X) may decrease according to the distance from the semiconductor substrate 100 according to the aspect ratio in cross section. For example, the conductive contact electrode MC may become narrower as it approaches the semiconductor substrate 100.

[0257] In this embodiment, a first through-chip via 313 connected to a lower contact pad LMP provided in the peripheral circuit structure PS and a second through-chip via 315 connected to a second upper contact pad UMP2 provided in the cell array structure CS can be electrically connected to each other through a conductive contact electrode MC. However, the connection relationship between the first through-chip via 313 and the second through-chip via 315 is not limited to this and can be changed in many ways. For example, the first through-chip via 313 can be electrically connected to the conductive contact electrode MC when connected to the peripheral circuit wire 230 provided in the peripheral circuit structure PS.

[0258] Despite Figure 7 Although not shown, the first semiconductor chip 10a according to some embodiments may further include word line contact plugs for connecting the first and second word lines WL1 and WL2 to the peripheral circuit structure PS and contact pads other than the first and second upper contact pads UMP1 and UMP2.

[0259] Despite Figure 7 Although not shown, in some embodiments, the first semiconductor chip 10a may further include capacitor contact plugs for connecting the capacitor DSP to the peripheral circuit structure PS. For example, the capacitor contact plugs may further include a first capacitor contact plug for connecting the second upper conductive line 264 to the capacitor DSP, and a second capacitor contact plug for connecting the second upper conductive line 264 to a component of the peripheral circuit structure PS.

[0260] For another example, a capacitor contact plug (not shown) for connecting the capacitor DSP to the peripheral circuit structure PS and a contact pad (not shown) other than the first upper contact pad UMP1 and the second upper contact pad UMP2 may be further included.

[0261] The first semiconductor chip 10 a has been generally described in the present embodiment, and the description of the first semiconductor chip 10 a can be applied to the second to fourth semiconductor chips 10 b , 10 c , 10 d .

[0262] The first to fourth semiconductor chips 10a, 10b, 10c, and 10d are shown to be the same in this embodiment, and in some embodiments, some of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may have Figure 3 , and the other semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may have Figure 7 The structure of the semiconductor chip shown in FIG.

[0263] Figure 6 and Figure 7 The semiconductor device 1_1 shown in FIG. 1 can have substantially the same effects as the semiconductor device 1 according to the embodiment.

[0264] Figure 8 A cross section of a semiconductor device according to some embodiments is shown.

[0265] Figure 8 The semiconductor device 1_2 shown in FIG. 1 is different from the semiconductor device 1 according to the embodiment in that a method for connecting the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d is different.

[0266] For details, refer to Figure 8 , the chip bonding pad CP and the chip bonding insulation layer CPL may be provided between adjacent semiconductor chips among the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d .

[0267] That is, the chip bonding pad CP and the chip bonding insulation layer CPL may be provided between the first and second semiconductor chips 10a and 10b, between the second and third semiconductor chips 10b and 10c, and between the third and fourth semiconductor chips 10c and 10d.

[0268] The chip bonding pads CP may include first chip bonding pads CP1 disposed on second surfaces of the first, second, and third semiconductor chips 10a, 10b, and 10c, and second chip bonding pads CP2 disposed on first surfaces of the second, third, and fourth semiconductor chips 10d.

[0269] The chip bonding insulation layer CPL may include a first chip bonding insulation layer CPL1 surrounding a side surface of the first chip bonding pad CP1 and a second chip bonding insulation layer CPL2 surrounding a side surface of the second chip bonding pad CP2 .

[0270] In this embodiment, the first chip bonding pad CP1 and the first chip bonding insulating layer CPL1 may be bonded and connected to the second chip bonding pad CP2 and the second chip bonding insulating layer CPL2, respectively, to form a bonding surface. That is, the first chip bonding pad CP1 may contact the second chip bonding pad CP2 to form a bonding surface, and the first chip bonding insulating layer CPL1 may contact the second chip bonding insulating layer CPL2 to form a bonding surface.

[0271] In the present embodiment, the first chip bonding pad CP1 and the first chip bonding insulating layer CPL1 may be combined and bonded to the second chip bonding pad CP2 and the second chip bonding insulating layer CPL2, respectively, by chip hybrid bonding or direct bonding. However, the method for bonding the first chip bonding pad CP1 and the first chip bonding insulating layer CPL1 to the second chip bonding pad CP2 and the second chip bonding insulating layer CPL2, respectively, is not limited thereto and may be varied in many ways.

[0272] The upper surface of the first chip bonding pad CP1 and the upper surface of the first chip bonding insulating layer CPL1 may be coplanar and may be disposed at substantially the same height as each other. The bottom surface of the second chip bonding pad CP2 and the bottom surface of the second chip bonding insulating layer CPL2 may be coplanar and may be disposed at substantially the same height as each other.

[0273] When the chip bonding pad CP and the chip bonding insulation layer CPL are arranged between adjacent semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c and 10d, the first chip through via 313 of one of the first to fourth semiconductor chips 10a, 10b, 10c and 10d can be connected to the second chip bonding pad CP2, and the second chip through via 315 can be connected to the first chip bonding pad CP1.

[0274] When the chip bonding pad CP and the chip bonding insulation layer CPL are arranged between adjacent semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c and 10d, the first chip through via 313 of one of the first to fourth semiconductor chips 10a, 10b, 10c and 10d can be electrically connected to the second chip through via 315 of another one of the first to fourth semiconductor chips through the chip bonding pad CP.

[0275] For example, the first chip through via 313 of the second semiconductor chip 10b can be electrically connected to the second chip through via 315 of the first semiconductor chip 10a through the chip bonding pad CP, and the second chip through via 315 of the second semiconductor chip 10b can be electrically connected to the first chip through via 313 of the third semiconductor chip 10c through the chip bonding pad CP.

[0276] In this embodiment, the first chip bonding pad CP1 and the second chip bonding pad CP2 may each include a conductive material such as copper (Cu), tungsten (W), nickel (Ni), gold (Au), or silver (Ag). For example, the first chip bonding pad CP1 and the second chip bonding pad CP2 may each include copper (Cu). However, the materials included in the first chip bonding pad CP1 and the second chip bonding pad CP2 are not limited thereto and may be varied in many ways.

[0277] The first and second chip-bonding insulating layers CPL1 and CPL2 may each include an insulating material such as silicon oxide (SiO) and silicon carbon nitride (SiCN). For example, the first and second chip-bonding insulating layers CPL1 and CPL2 may each include silicon carbon nitride (SiCN). However, the materials included in the first and second chip-bonding insulating layers CPL1 and CPL2 are not limited thereto and may be modified in many ways.

[0278] In the present embodiment, the first semiconductor chip 10a, which is located at the bottom among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, can be electrically connected to the package substrate 50 through the chip connection terminal 60. That is, the first semiconductor chip 10a can be electrically connected to the package substrate 50 through the chip connection terminal 60 provided between the chip pad 40 and the second substrate pad 57, the chip pad 40 being provided on the first surface of the first semiconductor chip 10a, and the second substrate pad 57 being provided on the second surface 50b of the package substrate 50. However, the method for connecting the first semiconductor chip 10a to the package substrate 50 is not limited thereto and can be changed in many ways. For example, a chip bonding pad CP and a chip bonding insulation layer CPL can also be provided between the first semiconductor chip 10a and the package substrate 50, and the first semiconductor chip 10a and the package substrate 50 can be connected and bonded to each other through the chip bonding pad CP.

[0279] according to Figure 8 The semiconductor device 1_2 of the embodiment shown in FIG can have substantially the same effects as the semiconductor device 1 according to the embodiment. In addition, when the chip connection terminals 60 provided between adjacent semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d are omitted, the total stacking height of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d can be reduced, and the area efficiency can be improved.

[0280] The first to fourth semiconductor chips 10a, 10b, 10c and 10d can be flexibly bent when performing hybrid bonding, thereby preventing bonding defects from being generated between adjacent semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c and 10d, and no stress can be provided to the bonded first to fourth semiconductor chips 10a, 10b, 10c and 10d during a subsequent process for performing heat treatment.

[0281] Figure 9 A cross section of a semiconductor device according to some embodiments is shown. Figure 10 Show Figure 9 A partially enlarged view of region R4.

[0282] Figure 9 and Figure 10 The semiconductor device 1_3 shown in FIG. 1 is different from the semiconductor device 1 according to the embodiment in that a method for connecting the respective first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d is different.

[0283] Reference Figure 9 and Figure 10 In this embodiment, the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d may be electrically connected to the first chip through vias 313 through the second chip through vias 315 .

[0284] In detail, the first chip through-via 313 of one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be directly connected to the second chip through-via 315 of another one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. For example, the bottom surface of the first chip through-via 313 of the second semiconductor chip 10b may contact the upper surface of the second chip through-via 315 of the first semiconductor chip 10a, and the upper surface of the second chip through-via 315 of the second semiconductor chip 10b may contact the bottom surface of the first chip through-via 313 of the third semiconductor chip 10c.

[0285] Figure 9The terminals of the first through-chip vias 313 and the second through-chip vias 315 provided on the first to fourth semiconductor chips 10a, 10b, 10c, and 10d are shown to be coplanar with the first and second surfaces of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, but the inventive concept is not limited thereto. For example, the first through-chip vias 313 may protrude from the first and second surfaces of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, or the second through-chip vias 315 may protrude from the second surfaces of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. For another example, the terminals of both the first through-chip vias 313 and the second through-chip vias 315 may protrude from the first and second surfaces of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d.

[0286] In this embodiment, the first surface of one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may contact the second surface of another of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. For example, the first surface of the second semiconductor chip 10b may contact the second surface of the first semiconductor chip 10a, and the second surface of the second semiconductor chip 10b may contact the first surface of the third semiconductor chip 10c. However, the arrangement relationship of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d is not limited to this and can be varied in many ways. For example, the first surface of one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be spaced apart from the second surface of another of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d in the third direction (Z).

[0287] That is, as described above, when the first chip through vias 313 protrude from the respective first surfaces of the first to fourth semiconductor chips 10a, 10b, 10c and 10d, or the second chip through vias 315 protrude from the respective second surfaces of the first to fourth semiconductor chips 10a, 10b, 10c and 10d, the respective first to fourth semiconductor chips 10a, 10b, 10c and 10d (for example, adjacent semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c and 10d) can be spaced apart from each other.

[0288] Reference Figure 10In this embodiment, the first through-chip vias 313 and the second through-chip vias 315 provided on each of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may have different widths in the first direction (X). That is, the first through-chip via 313 may have a first width W3 in the first direction (X), and the second through-chip via 315 may have a second width W4 in the first direction (X). The first width W3 may be different from the second width W4. For example, the first width W3 may be smaller than the second width W4. However, the relationship between the first width W3 and the second width W4 is not limited to this and may vary in many ways. For example, the first width W3 may be larger than the second width W4.

[0289] As described above, when the first chip through via 313 and the second chip through via 315 have different widths, a margin for connecting the first chip through via 313 to the second chip through via 315 can be obtained, and the first chip through via 313 and the second chip through via 315 can be stably connected to each other.

[0290] according to Figure 9 and Figure 10 The semiconductor device 1_3 of the embodiment shown in FIG. 1 can have substantially the same effects as the semiconductor device 1 according to the embodiment.

[0291] In addition, the chip connection terminals 60 arranged in the first to fourth semiconductor chips 10a, 10b, 10c and 10d can be omitted, and the first chip through-vias 313 and the second chip through-vias 315 can be directly connected, thereby reducing the total stacking height of the first to fourth semiconductor chips 10a, 10b, 10c and 10d and improving area efficiency.

[0292] Figure 11 and Figure 12 A cross section of a semiconductor device according to some embodiments is shown.

[0293] Figure 11 and Figure 12 The semiconductor devices 1_4 and 1_5 shown in FIG. 1 are different from the semiconductor device 1 according to the embodiment in that methods for connecting the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d , respectively, are different.

[0294] Reference Figure 11 and Figure 12 The first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d may be electrically connected to the first and second chip through-vias 313 and 315 of adjacent semiconductor chips through the chip pads 40 .

[0295] In the present embodiment, the die pad 40 may be disposed on one or both of the first and second surfaces of the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d .

[0296] according to Figure 11 In the embodiment shown in FIG, the chip pad 40 may be disposed not on the first surfaces of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, but on the second surfaces of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d.

[0297] according to Figure 12 In the embodiment shown in FIG, the die pad 40 may be disposed on the first surfaces of the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d , but not on the second surfaces of the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d .

[0298] Therefore, the chip pad 40 may be provided between adjacent semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d. The underfill member 70 may be provided between adjacent semiconductor chips among the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, and may surround the chip pad 40.

[0299] according to Figure 11 and Figure 12 In the embodiment shown in , the first chip through via 313 of one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d and the second chip through via 315 of another one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be electrically connected to each other through the chip pad 40. That is, the upper surface of the chip pad 40 may be connected to the first chip through via 313 of one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d, and the second chip through via 315 of another one of the first to fourth semiconductor chips 10a, 10b, 10c, and 10d may be connected to the bottom surface of the chip pad 40.

[0300] Therefore, the first to fourth semiconductor chips 10 a , 10 b , 10 c , and 10 d may be electrically connected through the chip pads 40 .

[0301] according to Figure 11In the semiconductor device 1_4 of the embodiment shown in FIG, when the chip pad 40 is not provided on the first surface of the first semiconductor chip 10a provided at the lowermost end among the first to fourth semiconductor chips 10a, 10b, 10c and 10d, the first semiconductor chip 10a and the package substrate 50 can be electrically connected to each other through the second substrate pad 57.

[0302] That is, the first chip through-via 313 of the first semiconductor chip 10a can be directly connected to the second substrate pad 57 on the package substrate 50. The underfill member 70 can be provided between the first semiconductor chip 10a and the package substrate 50 and can surround the second substrate pad 57. However, the method for connecting the first semiconductor chip 10a to the package substrate 50 is not limited thereto and can be changed in many ways. For example, Figure 12 As shown in , when the chip pads 40 and the chip connection terminals 60 are further provided between the first surface of the first semiconductor chip 10 a and the second substrate pads 57 on the package substrate 50 , the first semiconductor chip 10 a and the package substrate 50 may be electrically connected to each other through the chip connection terminals 60 .

[0303] according to Figure 11 and Figure 12 The semiconductor devices 1_4 and 1_5 of the embodiment shown in FIG. 1 may have substantially the same effects as the semiconductor device 1 according to the embodiment.

[0304] In addition, the chip connection terminals 60 provided among the first to fourth semiconductor chips 10a, 10b, 10c and 10d may be omitted, and the first chip through-vias 313 and the second chip through-vias 315 may be connected to the chip pads 40, thereby reducing the total stacking height of the first to fourth semiconductor chips 10a, 10b, 10c and 10d and improving area efficiency.

[0305] Figures 13 to 15 A cross section of a semiconductor device according to some embodiments is shown.

[0306] Figures 13 to 15The semiconductor devices 1_6, 1_7, and 1_8 shown in FIG. 1 differ from the semiconductor device 1 according to the embodiment in that they include a first type of semiconductor chip (or a first group of semiconductor chips) 11 (e.g., cell-on-peripheral semiconductor chips) and a second type of semiconductor chip (or a second group of semiconductor chips) 22 (e.g., cell-adjacent-to-peripheral semiconductor chips) having different structures. In the cell-on-peripheral semiconductor chips, the cell array structure CS is above the peripheral circuit structure PS, while in the cell-adjacent-to-peripheral semiconductor chips, the cell array structure CS is horizontally adjacent to the peripheral circuit structure PS.

[0307] about Figures 13 to 15 In the semiconductor devices 1_6, 1_7, and 1_8 shown in FIG, the first type semiconductor chip 11 may include first to fourth semiconductor chips 11a, 11b, 11c, and 11d.

[0308] The respective first to fourth semiconductor chips 11a, 11b, 11c, and 11d of the first type semiconductor chips 11 may be connected to the reference Figures 1 to 3 The first to fourth semiconductor chips 10a, 10b, 10c, and 10d described are substantially the same. However, not limited thereto, in some embodiments, the first type semiconductor chip 11 may be the same as the first type semiconductor chip 10a, 10b, 10c, and 10d described above. Figure 6 The first to fourth semiconductor chips 10a, 10b, 10c, and 10d described are substantially the same, and the description provided previously can be applied here and thus will be omitted.

[0309] The second type semiconductor chips 22 may include first to third semiconductor chips 22 a , 22 b , and 22 c .

[0310] Unlike the first-type semiconductor chip 11, each of the first to third semiconductor chips 22a, 22b, and 22c of the second-type semiconductor chip 22 may include a semiconductor substrate 100, a peripheral circuit structure PS, and a cell array structure CS, and the peripheral circuit structure PS and the cell array structure CS may be disposed on the same plane on the semiconductor substrate 100. That is, the peripheral circuit structure PS and the cell array structure CS of the second-type semiconductor chip 22 may be disposed parallel to each other on the semiconductor substrate 100. For example, the peripheral circuit structure PS and the cell array structure CS of the second-type semiconductor chip 22 may be disposed horizontally adjacent to each other, or disposed side by side.

[0311] Figures 13 to 15While the peripheral circuit structure PS and the cell array structure CS are shown as being arranged in parallel, the arrangement relationship between the peripheral circuit structure PS and the cell array structure CS is not limited thereto and may be varied in various ways. For example, the peripheral circuit structure PS may be arranged in a plan view near at least one of the first side and the second side of the cell array structure CS in the first direction (X), and near at least one of the first side and the second side of the cell array structure CS in the second direction (Y). As another example, the peripheral circuit structure PS may surround the cell array structure CS in a plan view.

[0312] The second-type semiconductor chip 22 may include a third chip through-via 317 that penetrates at least a portion of each of the first semiconductor chip to the third semiconductor chip 22a, 22b, and 22c. The third chip through-via 317 may be provided in the peripheral circuit structure PS and the cell array structure CS, respectively. However, the location of the third chip through-via 317 is not limited thereto and may be changed in many ways. For example, the third chip through-via 317 may be provided in one of the peripheral circuit structure PS and the cell array structure CS but not in the other.

[0313] Reference Figure 13 and Figure 14 The chip pads 40 may be disposed on the first and second surfaces of the first type semiconductor chip 11 and the first and second surfaces of the second type semiconductor chip 22 , respectively.

[0314] The chip pad 40 may include a first chip pad 41 disposed on first surfaces of the first and second type semiconductor chips 11 and 22 , and a second chip pad 42 disposed on second surfaces of the first and second type semiconductor chips 11 and 22 .

[0315] In detail, about Figure 13 In the semiconductor device 1_6 shown in FIG, first-type semiconductor chips 11 and second-type semiconductor chips 22 may be alternately stacked along a third direction (Z) on a second surface 50 b of a package substrate 50 .

[0316] That is, the first semiconductor chip 11a of the first type semiconductor chip 11, the first semiconductor chip 22a of the second type semiconductor chip 22, the second semiconductor chip 11b of the first type semiconductor chip 11, the second semiconductor chip 22b of the second type semiconductor chip 22, the third semiconductor chip 11c of the first type semiconductor chip 11 and the third semiconductor chip 22c of the second type semiconductor chip 22 can be stacked sequentially in this order.

[0317] according to Figure 13In the embodiment shown in FIG, chip connection terminals 60 may be provided between the respective first type semiconductor chips 11 and second type semiconductor chips 22. The first type semiconductor chips 11 and the second type semiconductor chips 22 may be electrically connected via the chip connection terminals 60.

[0318] The chip connection terminal 60 may be disposed between the first chip pad 41 and the second chip pad 42. That is, the chip connection terminal 60 may be disposed between the first chip pad 41 on one of the first type semiconductor chips 11 and the second chip pad 42 on one of the second type semiconductor chips 22.

[0319] The corresponding first chip through-vias 313 and second chip through-vias 315 of the first type semiconductor chip 11 can be electrically connected to the third chip through-via 317 of one of the second type semiconductor chips 22 and the third chip through-via 317 of another of the second type semiconductor chips 22 through the chip connection terminals 60.

[0320] That is, the corresponding first chip through vias 313 and the second chip through vias 315 of the first type semiconductor chip 11 can be electrically connected to the third chip through via 317 of one of the second type semiconductor chips 22 and the third chip through via 317 of another of the second type semiconductor chips 22 through the chip pad 40 and the chip connection terminal 60.

[0321] For example, the first chip through-via 313 disposed in the second semiconductor chip 11 b of the first type semiconductor chip 11 may be electrically connected to the third chip through-via 317 disposed in the first semiconductor chip 22 a of the second type semiconductor chip 22 through the chip pad 40 and the chip connection terminal 60 .

[0322] The second through-chip via 315 disposed in the second semiconductor chip 11 b of the first type semiconductor chip 11 may be electrically connected to the third through-chip via 317 disposed in the second semiconductor chip 22 b of the second type semiconductor chip 22 through the chip pad 40 and the chip connection terminal 60 .

[0323] Figure 13The first-type semiconductor chip 11 and the second-type semiconductor chip 22 are shown as each including three semiconductor chips. However, the number of semiconductor chips included in the first-type semiconductor chip 11 and the second-type semiconductor chip 22 is not limited thereto and can be varied in many ways. For example, the first-type semiconductor chip 11 and the second-type semiconductor chip 22 may each include two, four, or five or more semiconductor chips. For another example, the first-type semiconductor chip 11 and the second-type semiconductor chip 22 may each include a number of semiconductor chips that is a multiple of four.

[0324] Figure 14 The semiconductor device 1_7 shown in FIG Figure 13 The semiconductor device 1_6 shown in FIG. 1 is different in that the number of first-type semiconductor chips 11 and the number of second-type semiconductor chips 22 and their stacking order are different.

[0325] Reference Figure 14 Regarding the semiconductor device 1_7 according to the present embodiment, the number of the first-type semiconductor chips 11 may be different from the number of the second-type semiconductor chips 22. In the present embodiment, the number of the first-type semiconductor chips 11 may be greater than the number of the second-type semiconductor chips 22. For example, the first-type semiconductor chips 11 may include first to fourth semiconductor chips 11a, 11b, 11c, and 11d, and the second-type semiconductor chips 22 may include first and second semiconductor chips 22a and 22b. However, this is an example, and in some embodiments, the number of the second-type semiconductor chips 22 may be greater than the number of the first-type semiconductor chips 11.

[0326] In this embodiment, the semiconductor device 1_7 may have a stacked structure in which the first-type semiconductor chips 11 are repeatedly stacked in the third direction (Z), and the second-type semiconductor chips 22 are alternately stacked in the third direction. That is, a stacking unit including the first-type semiconductor chips 11 stacked in series and the second-type semiconductor chips 22 stacked on the first-type semiconductor chips 11 stacked in series may be repeatedly stacked on the second surface 50 b of the package substrate 50.

[0327] For example, the first semiconductor chip 11a of the first type semiconductor chip 11, the second semiconductor chip 11b of the first type semiconductor chip 11, the first semiconductor chip 22a of the second type semiconductor chip 22, the third semiconductor chip 11c of the first type semiconductor chip 11, the fourth semiconductor chip 11d of the first type semiconductor chip 11, and the second semiconductor chip 22b of the second type semiconductor chip 22 can be sequentially stacked on the package substrate 50 in this order. However, the number and stacking order of the semiconductor chips included in the first type semiconductor chip 11 and the second type semiconductor chip 22 are not limited to this and can be changed in many ways. For example, a stacking unit including at least three repeatedly stacked first type semiconductor chips 11 and at least two repeatedly stacked second type semiconductor chips 22 can be repeatedly stacked on the package substrate 50. For another example, the first type semiconductor chips 11 can be stacked continuously, and the second type semiconductor chips 22 can be stacked continuously on the first type semiconductor chip 11. For another example, the second type semiconductor chips 22 can be stacked continuously, and the first type semiconductor chips 11 can be stacked continuously on the second type semiconductor chips 22.

[0328] like Figure 14 As shown in , when the first type semiconductor chips 11 are repeatedly stacked, the first chip through-via 313 of one of the first type semiconductor chips 11 can be electrically connected to the second chip through-via 315 of another of the first type semiconductor chips 11 through the chip pad 40 and the chip connection terminal 60.

[0329] according to Figure 13 and Figure 14 The semiconductor devices 1_6 and 1_7 of the embodiment shown in FIG. 1 may have substantially the same effects as the semiconductor device 1 according to the embodiment.

[0330] Besides, when the semiconductor device includes the first type semiconductor chips 11 and the second type semiconductor chips 22 having different configurations, the stack structure and stack height of the semiconductor device may vary according to the characteristics and purposes of the semiconductor devices 1_6 and 1_7 .

[0331] Figure 15 The semiconductor device 1_8 shown in FIG Figure 13 The semiconductor device 1_6 shown in FIG. 1 is different in that the method for connecting the first type semiconductor chip 11 to the second type semiconductor chip 22 is different.

[0332] For details, refer to Figure 15 , the chip bonding pad CP and the chip bonding insulation layer CPL may be disposed between the corresponding first type semiconductor chip 11 and the second type semiconductor chip 22 .

[0333] Chip bonding pad CP, chip bonding insulation layer CPL and their bonding method and reference Figure 8 Given the descriptions being substantially the same, their detailed descriptions will be omitted.

[0334] When the chip bonding pad CP and the chip bonding insulation layer CPL are arranged between the corresponding first type semiconductor chip 11 and the second type semiconductor chip 22, the first chip through via 313 of the first type semiconductor chip 11 can be connected to the second chip bonding pad CP2, and the second chip through via 315 of the first type semiconductor chip 11 can be connected to the first chip bonding pad CP1.

[0335] A first end of the third through-chip via 317 of the second type semiconductor chip 22 may be connected to the first chip bonding pad CP1 , and a second end of the third through-chip via 317 of the second type semiconductor chip 22 may be connected to the second chip bonding pad CP2 .

[0336] Therefore, the first and second chip through vias 313 and 315 of the first type semiconductor chip 11 may be electrically connected to the third chip through via 317 of the second type semiconductor chip 22 through the chip bonding pad CP.

[0337] according to Figure 15 The semiconductor device 1_8 of the embodiment shown in FIG. 1 may have Figure 13 The semiconductor device 1_6 shown in FIG. 1 has basically the same effect.

[0338] In addition, the chip connection terminals 60 between the first type semiconductor chip 11 and the second type semiconductor chip 22 are omitted, thereby reducing the stacking height of the semiconductor device 1_8 and improving area efficiency.

[0339] In addition, flexible bending can be generated when hybrid bonding is performed, thereby preventing bonding defects from being generated between the first type semiconductor chip 11 and the second type semiconductor chip 22, and preventing stress from being applied to the bonded first type semiconductor chip 11 and second type semiconductor chip 22 during the process for performing subsequent heat treatment.

[0340] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments and / or examples, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the inventive concepts.

Claims

1. A semiconductor device comprising: packaging substrate; as well as Multiple semiconductor chips are stacked on a packaging substrate. Each of the plurality of semiconductor chips comprises: semiconductor substrates, The peripheral circuit structure and the cell array structure are arranged to overlap each other in a vertical direction on the semiconductor substrate. The first contact pad, in the peripheral circuit structure, a second contact pad, wherein in the cell array structure, the second contact pad is connected to the first contact pad, a first through-chip via penetrating the semiconductor substrate and at least a portion of the peripheral circuit structure, the first through-chip via being connected to the first contact pad, and The second chip through-via penetrates at least a portion of the cell array structure, the second chip through-via is connected to the second contact pad, and The first through-chip via of a first semiconductor chip among the plurality of semiconductor chips is connected to the second through-chip via of a second semiconductor chip among the plurality of semiconductor chips.

2. The semiconductor device according to claim 1, wherein For each semiconductor chip, a peripheral circuit structure is between the semiconductor substrate and the cell array structure.

3. The semiconductor device according to claim 2, wherein For each semiconductor chip, the first contact pad contacts the second contact pad, and wherein each semiconductor chip further comprises: a first contact insulating layer surrounding the first contact pad; and The second contact insulating layer surrounds the second contact pad and contacts the first contact insulating layer.

4. The semiconductor device according to claim 3, wherein For each semiconductor chip, a first contact pad is directly connected to a first through-chip via, and a second contact pad is directly connected to a second through-chip via.

5. The semiconductor device according to claim 4, wherein For each semiconductor chip, the first contact pad and the second contact pad include copper, and the first contact insulating layer and the second contact insulating layer include at least one of silicon oxide and silicon carbonitride. The semiconductor device according to claim 3 , wherein: The width of the first contact pad is different from the width of the second contact pad, or the thickness of the first contact pad is different from the thickness of the second contact pad.

7. The semiconductor device according to claim 3, wherein The first through-chip via of the first semiconductor chip and the second through-chip via of the second semiconductor chip have different widths, and The first through-chip via of the first semiconductor chip is directly connected to the second through-chip via of the second semiconductor chip.

8. The semiconductor device according to claim 3, further comprising: Chip pads, between the plurality of semiconductor chips, The first through-chip via of the first semiconductor chip and the second through-chip via of the second semiconductor chip are connected to the chip pad.

9. The semiconductor device according to claim 8, wherein The plurality of semiconductor chips respectively include: The first surface and the second surface are opposite to each other, and A chip pad is on at least one of the first surface and the second surface of at least one semiconductor chip among the plurality of semiconductor chips.

10. The semiconductor device according to claim 9, wherein Chip pad includes: a first chip pad on the first surface; and A second chip pad, on the second surface, Wherein, a chip connection terminal is provided between a first chip pad on the first surface of the first semiconductor chip and a second chip pad on the second surface of the second semiconductor chip.

11. The semiconductor device according to claim 3, further comprising: a first chip bonding pad and a second chip bonding pad contacting each other between the first semiconductor chip and the second semiconductor chip; a first chip bonding insulation layer surrounding the first chip bonding pad; as well as a second chip bonding insulating layer surrounding the second chip bonding pad, the second chip bonding insulating layer contacting the first chip bonding insulating layer; wherein the first chip bonding pad is directly connected to the first chip through via of the first semiconductor chip, and The second chip bonding pad is directly connected to the second through-chip via of the second semiconductor chip.

12. The semiconductor device according to claim 2, wherein The plurality of semiconductor chips further include: Conductive contact electrodes extend from the peripheral circuit structure to the cell array structure, The conductive contact electrode is connected to the first contact pad and the second contact pad.

13. A semiconductor device comprising: packaging substrate; as well as The first group of semiconductor chips is stacked on a package substrate. Each semiconductor chip in the first group of semiconductor chips comprises: a first semiconductor substrate, A first peripheral circuit structure is formed on a first semiconductor substrate. A first cell array structure, on a first peripheral circuit structure, a first contact pad, in a first peripheral circuit structure, a second contact pad, wherein in the first cell array structure, the second contact pad contacts the first contact pad; a contact insulating layer, on a boundary between the first peripheral circuit structure and the first cell array structure, the contact insulating layer surrounding the first contact pad and the second contact pad, a first through-chip via penetrating the first semiconductor substrate and the first peripheral circuit structure, the first through-chip via being connected to the first contact pad, and The second chip has a through-hole penetrating the first unit array structure, and the second chip has a through-hole connected to the second contact pad, and The first through-chip via of a first semiconductor chip in the first group of semiconductor chips is connected to the second through-chip via of a second semiconductor chip in the first group of semiconductor chips.

14. The semiconductor device according to claim 13, further comprising: The second group of semiconductor chips is stacked on the package substrate. Each semiconductor chip in the second group of semiconductor chips comprises: a second semiconductor substrate, The second peripheral circuit structure and the second cell array structure are on the same plane on the second semiconductor substrate, and The third chip has a through-hole penetrating the second semiconductor substrate, and The third through-chip via of the third semiconductor chip in the second group of semiconductor chips is connected to the first through-chip via of the first semiconductor chip and to the second through-chip via of the second semiconductor chip.

15. The semiconductor device according to claim 14, wherein The first group of semiconductor chips and the second group of semiconductor chips are alternately stacked on the package substrate.

16. The semiconductor device according to claim 15, further comprising: a first chip pad connected to a first chip through via of the first semiconductor chip; a second chip pad facing the first chip pad and connected to a third chip through via of the third semiconductor chip; a third chip pad connected to the second chip through via of the second semiconductor chip; a fourth chip pad facing the third chip pad and connected to the third chip through via of the third semiconductor chip; as well as The chip connection terminal is between the first chip pad and the second chip pad, and between the third chip pad and the fourth chip pad.

17. The semiconductor device according to claim 15, further comprising: a first chip bonding pad and a second chip bonding pad contacting each other between one semiconductor chip of the first group of semiconductor chips and one semiconductor chip of the second group of semiconductor chips; a first chip bonding insulation layer surrounding the first chip bonding pad; as well as a second chip bonding insulating layer surrounding the second chip bonding pad, the second chip bonding insulating layer contacting the first chip bonding insulating layer; wherein the second chip through via of one semiconductor chip in the first group of semiconductor chips is directly connected to the first chip bonding pad, and The third through-chip via of one semiconductor chip in the second group of semiconductor chips is directly connected to the second chip bonding pad.

18. The semiconductor device according to claim 14, wherein The number of semiconductor chips included in the first group of semiconductor chips is different from the number of semiconductor chips included in the second group of semiconductor chips.

19. The semiconductor device according to claim 18, wherein The number of semiconductor chips included in the first group of semiconductor chips is greater than the number of semiconductor chips included in the second group of semiconductor chips.

20. A semiconductor device comprising: a packaging substrate comprising a first surface and a second surface opposite to each other; A first base pad and a second base pad are respectively arranged on a first surface and a second surface of the packaging substrate; external connection terminals on the first substrate pad; a plurality of semiconductor chips, each comprising a first surface and a second surface opposite to each other, wherein the plurality of semiconductor chips are stacked on the second surface of the package substrate; A first chip pad and a second chip pad are respectively disposed on a first surface and a second surface of each semiconductor chip of the plurality of semiconductor chips; a first chip connection terminal between a first chip pad on a first semiconductor chip among the plurality of semiconductor chips and a second chip pad on a second semiconductor chip among the plurality of semiconductor chips; a second chip connection terminal between the first chip pad and the second substrate pad on the lowermost semiconductor chip of the plurality of semiconductor chips; an underfill member between adjacent semiconductor chips and between the package substrate and a lowermost semiconductor chip among the plurality of semiconductor chips; as well as a molding member covering the package substrate and the plurality of semiconductor chips, Wherein, the plurality of semiconductor chips respectively include: semiconductor substrates, Peripheral circuit structure, on the semiconductor substrate, Cell array structure, in the peripheral circuit structure, The first contact pad and the second contact pad are in contact with each other at a boundary between the peripheral circuit structure and the cell array structure. a contact insulating layer surrounding the first contact pad and the second contact pad, a first chip through-via penetrating the semiconductor substrate and the peripheral circuit structure, the first chip through-via being connected to the first contact pad and the first chip pad, and The second chip has a through-via penetrating the cell array structure, and the second chip has a through-via connected to the second contact pad and the second chip pad, and The first through-chip via of one semiconductor chip among the plurality of semiconductor chips is connected to the second through-chip via of another semiconductor chip among the plurality of semiconductor chips.

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