Ferroelectric capacitor interface layer trap density and energy distribution test method and system

Abstract

The invention provides a ferroelectric capacitor interface layer trap density and energy distribution test method and system, and the method comprises the steps: constructing a test circuit which comprises a characteristic analyzer and a to-be-tested ferroelectric capacitor, and enabling a top electrode and a bottom electrode of the ferroelectric capacitor to be connected with a source measurement unit channel of the characteristic analyzer, a series of pulse voltages are applied to the top electrode of the ferroelectric capacitor through a characteristic analyzer, the series of pulse voltages comprise a recovery pulse sequence and a reading pulse sequence, the recovery pulse sequence comprises a first stress pulse and a recovery positive pulse sequence, and the reading pulse sequence is applied after the recovery positive pulse. The read pulse sequence comprises an initial negative pulse and a read positive pulse sequence of which the amplitudes are sequentially increased; the final pulse amplitude and pulse width of the read positive pulse sequence applied after each recovery positive pulse are not greater than the amplitude and pulse width of the previous recovery positive pulse; and the change condition of the electric domain along with time and the defect concentration distribution condition under each energy level are determined based on the electric signals collected by the high-bandwidth oscilloscope.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor solid-state dielectric material testing, and in particular to a method and system for testing trap density and energy distribution in a ferroelectric capacitor interface layer. Background Art

[0002] In recent years, ferroelectric memory has attracted widespread attention from the industry due to its fast read and write speeds and low power consumption, and its great potential in applications such as in-memory computing and neural synapses, integration on nanowires, and combination with two-dimensional material technology.

[0003] For hafnium-based ferroelectric devices, obtaining high-quality interfaces is one of the most important aspects of fabrication. Previous studies have shown that traps tend to accumulate at interfaces, where domain pinning sites tend to aggregate. This can lead to a loss of ferroelectric polarization, potentially impairing the performance of ferroelectric memory devices (and thus affecting ferroelectric domain inversion and memory performance). Therefore, a deep understanding and characterization of these traps near the finite element / electrode interface is crucial. However, conventional characterization methods, such as Figure 1-2 As shown, Figure 1 The conductivity and capacitance response curves of ferroelectric capacitors (FeCAP) at different frequencies are shown in Figure 2. Figure 2 The conductivity method uses peak values to calculate the concentration distribution of defects at the interface, such as capacitance-voltage (CV) analysis, leakage current measurement, and trap-related noise in the device, including random telegraph noise (RTN) and 1 / f noise. It cannot have a wide range of defect energy levels (localized electronic states) and cannot detect defect sources. For positive-up-negative-down (PUND), it cannot distinguish between trap signals and leakage current at the limited frequency (low frequency), which limits its ability to detect defects near the interface.

[0004] In view of this, there is an urgent need to provide a method for testing the trap density and energy distribution of the ferroelectric capacitor interface layer that is suitable for the defect concentration distribution under a larger range of energy levels. Summary of the Invention

[0005] In order to overcome the problems existing in the related art, the present disclosure provides a method and system for testing the trap density and energy distribution of the interface layer of a ferroelectric capacitor to solve the technical problems in the related art.

[0006] One or more embodiments of this specification provide a method for testing the trap density and energy distribution of a ferroelectric capacitor interface layer, including the following steps:

[0007] Constructing a test circuit; constructing a test circuit including a characteristic analyzer and a ferroelectric capacitor to be tested, wherein the top electrode and the bottom electrode of the ferroelectric capacitor are connected to a source measurement unit channel of the characteristic analyzer;

[0008] Testing phase: applying a series of pulse voltages to the top electrode of the ferroelectric capacitor through a characteristic analyzer, the series of pulse voltages including a recovery pulse sequence and a read pulse sequence, the recovery pulse sequence including a first stress pulse and a recovery positive pulse sequence, a read pulse sequence applied after each recovery positive pulse, the read pulse sequence including an initial negative pulse and a read positive pulse sequence with successively increasing amplitudes; the final pulse amplitude and pulse width of the read positive pulse sequence applied after each recovery positive pulse are not greater than the amplitude and pulse width of the previous recovery positive pulse;

[0009] Analysis process: Based on the electrical signals collected by the characteristic analyzer, the change of the polarization charge density of the ferroelectric capacitor under each recovery positive pulse and read pulse sequence with time is determined to determine the change of the electric domain with time and the defect concentration distribution at each energy level.

[0010] Furthermore, the steps include:

[0011] Before applying the first stress pulse, an initial stress pulse and an initial read pulse sequence are applied to the top electrode of the ferroelectric capacitor through a characteristic analyzer. The final pulse amplitude and pulse width of the initial read pulse sequence are not greater than the amplitude and pulse width of the initial stress pulse.

[0012] Furthermore, the recovery positive pulse sequence is a rectangular pulse sequence with an amplitude increasing by 0.2V in sequence, the duration of each recovery positive pulse is 8-10s, the rise and fall time is 10us, and the time interval between the recovery positive pulses is 10-20us.

[0013] Furthermore, the read pulse sequence is a rectangular positive pulse sequence with an amplitude increasing by 0.1 V, each read positive pulse has a duration of 200 ns, a rise and fall time of 100 ns, and a time interval between the read positive pulses is 150-200 ns.

[0014] Furthermore, the amplitude of the initial negative pulse is -2V, and the pulse duration is 0.5-1us.

[0015] Furthermore, the amplitude of the initial negative pulse is -2V, and the pulse duration is 0.5-1us.

[0016] Furthermore, the first stress pulse and the initial stress pulse are rectangular pulses with the same amplitude and pulse width, and the time interval between the initial stress pulse and the first stress pulse is 8-10s, the amplitude is -2V, the pulse duration is 0.8-1s, and the final pulse amplitude and pulse width of the initial read pulse sequence are smaller than the amplitude and pulse width of the initial stress pulse.

[0017] One or more embodiments of the present specification provide a system for testing the trap density and energy distribution of the interface layer of a ferroelectric capacitor, including a test circuit, the test circuit including a characteristics analyzer and a ferroelectric capacitor to be tested, wherein the top electrode and the bottom electrode of the ferroelectric capacitor are connected to a source measurement unit channel of the characteristics analyzer;

[0018] The characteristic analyzer applies a series of pulse voltages to the top electrode of the ferroelectric capacitor, the series of pulse voltages including a recovery pulse sequence and a read pulse sequence, the recovery pulse sequence including a first stress pulse and a recovery positive pulse sequence, and a read pulse sequence applied after each recovery positive pulse, the read pulse sequence including an initial negative pulse and a read positive pulse sequence with successively increasing amplitudes; the final pulse amplitude and pulse width of the read positive pulse sequence applied after each recovery positive pulse are no greater than the amplitude and pulse width of the previous recovery positive pulse;

[0019] The characteristic analyzer determines the change of the polarization charge density of the ferroelectric capacitor with time under each recovery positive pulse and read pulse sequence through the collected electrical signals, so as to determine the change of the electric domain with time and the defect concentration distribution at each energy level.

[0020] Furthermore, before applying the first stress pulse to the top electrode of the ferroelectric capacitor, the characteristic analyzer also applies an initial stress pulse and an initial read pulse sequence, and the final pulse amplitude and pulse width of the initial read pulse sequence are not greater than the amplitude and pulse width of the initial stress pulse.

[0021] Furthermore, the recovery positive pulse sequence is a rectangular pulse sequence with an amplitude increasing by 0.2V in sequence, the duration of each recovery positive pulse is 8-10s, the rise and fall time is 10us, and the time interval between the recovery positive pulses is 10-20us.

[0022] Furthermore, the first stress pulse and the initial stress pulse are rectangular pulses with the same amplitude and pulse width, and the time interval between the initial stress pulse and the first stress pulse is 8-10s, the amplitude is 2V, the pulse duration is 1s, and the final pulse amplitude and pulse width of the initial read pulse sequence are smaller than the amplitude and pulse width of the initial stress pulse.

[0023] The present disclosure provides a method and system for testing trap density and energy distribution in the interface layer of a ferroelectric capacitor. Advantageously, to study the relationship between domain wall expansion and polarization reversal, a recovery pulse and a read pulse sequence are applied to the top electrode of the ferroelectric capacitor via a characteristic analyzer. The first stress pulse is used to positively charge all vacancies at the bottom electrode to pin the domains. The recovery positive pulse sequence is used to gradually capture electrons from the vacancies under each positive pulse, causing all vacancies at the bottom electrode interface to lose electrons and become positively charged, thereby gradually restoring the pinned domains to free domains. The initial negative pulse is used to achieve domain reversal, and the read pulse sequence is used to test changes in ferroelectric polarization charge. Thus, by testing the incremental changes in the ferroelectric polarization charge caused by the incremental changes in the read pulse sequence under each recovery pulse, the polarization reversal time at each energy level voltage is determined, thereby accumulating more polarization values and determining the defect concentration distribution at each energy level. To ensure that the test process does not change the charged state of the traps, the amplitude and pulse width of the read pulse sequence after each recovery positive pulse do not exceed the amplitude and pulse width of the current recovery positive pulse. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 The conductance and capacitance response curves of the ferroelectric capacitor at different frequencies provided in the prior art of this specification;

[0026] Figure 2 The prior art conductivity method provided in this specification calculates the defect concentration distribution at the interface from the peak value;

[0027] Figure 3 A flow chart of a method for testing the trap density and energy distribution of the ferroelectric capacitor interface layer provided for one or more embodiments of this specification;

[0028] Figure 4 A schematic diagram of a step recovery pulse sequence provided for one or more embodiments of this specification;

[0029] Figure 5 A schematic diagram of a read pulse sequence provided for one or more embodiments of this specification;

[0030] Figure 6 A schematic diagram of another step recovery pulse sequence provided for one or more embodiments of this specification;

[0031] Figure 7 A series of pulse voltage diagrams provided for one or more embodiments of this specification;

[0032] Figure 8 One or more embodiments of this specification provide Figure 7 Transient current density response obtained under pulse voltage

[0033] Figure 9 One or more embodiments of this specification provide Figure 8 The charge density variation diagram under Vtest is provided;

[0034] Figure 10 A graph showing the step recovery pulse test results of a TiN-HZO-TiN FeCAP capacitor under the conditions of one or more embodiments of this specification;

[0035] Figure 11 Response diagrams of different depth energy levels of a TiN-HZO-TiN FeCAP capacitor under different external voltages provided by TCAD simulation for one or more embodiments of this specification;

[0036] Figure 12 The defect density distribution diagram of TiN-HZO-TiN FeCAP capacitor at different defect energy levels provided by one or more embodiments of this specification. DETAILED DESCRIPTION

[0037] In order to help those skilled in the art better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0038] The present invention will be described in detail below with reference to specific implementation methods and the accompanying drawings.

[0039] Method Example

[0040] According to an embodiment of the present invention, a method for testing the trap density and energy distribution of a ferroelectric capacitor interface layer is provided. Figure 3 FIG. 1 is a flow chart of a method for testing the trap density and energy distribution of a ferroelectric capacitor interface layer provided in this embodiment. The method for testing the trap density and energy distribution of a ferroelectric capacitor interface layer according to an embodiment of the present invention includes the following steps:

[0041] Step S1, constructing a test circuit; constructing a test circuit including a characteristics analyzer and a ferroelectric capacitor to be tested, wherein the top electrode and the bottom electrode of the ferroelectric capacitor are connected to a source measurement unit channel of the characteristics analyzer;

[0042] In this embodiment, the ferroelectric capacitor is first fixed on a probe station, and the characteristic analyzer can use a B1500a semiconductor parameter analyzer. The top electrode and bottom electrode of the ferroelectric capacitor are connected to the SMU (source measurement unit) channel of the semiconductor parameter analyzer. One SMU applies a scanning voltage (such as SMU1), and the other SMU is grounded or set to a high impedance state (Hi-Z) to detect current.

[0043] When testing the waveform on the B1500a semiconductor analyzer, the corresponding ferroelectric capacitor will have a corresponding pulse input at one end and receive the output of the recorded current at the other end.

[0044] Step S2, testing phase; applying a series of pulse voltages to the top electrode of the ferroelectric capacitor through a characteristic analyzer, the series of pulse voltages including a recovery pulse sequence and a read pulse sequence, the recovery pulse sequence including a first stress pulse and a recovery positive pulse sequence, a read pulse sequence applied after each recovery positive pulse, the read pulse sequence including an initial negative pulse and a read positive pulse sequence with successively increasing amplitudes; the final pulse amplitude and pulse width of the read positive pulse sequence applied after each recovery positive pulse are not greater than the amplitude and pulse width of the previous recovery positive pulse;

[0045] Step S3, analysis process; based on the electrical signal collected by the characteristic analyzer, determine the change of the ferroelectric capacitor polarization charge density over time under each recovery positive pulse and read pulse sequence to determine the change of the electric domain over time and the defect concentration distribution at each energy level.

[0046] The present embodiment provides a method for testing the trap density and energy distribution in the interface layer of a ferroelectric capacitor. Due to the presence of some charged oxygen vacancies at the interface of the ferroelectric capacitor during its manufacturing process, these charged vacancies will attract one end of the ferroelectric domain, thereby pinning the domain and preventing it from undergoing polarization reversal with an external electric field. To study the relationship between domain wall expansion and polarization reversal, a recovery pulse and a read pulse sequence are applied to the top electrode of the ferroelectric capacitor using a characteristic analyzer. The first stress pulse is used to positively charge all vacancies at the bottom electrode to pin the domain. The recovery positive pulse sequence is used to enable the vacancies to gradually capture electrons under each positive pulse, so that all vacancies at the bottom electrode interface lose electrons and become positively charged. So that the pinned domains are gradually restored to free domains, the initial negative pulse is used to achieve domain reversal, and the read pulse sequence is used to test the change in ferroelectric polarization charge; in this way, the recovery pulses and read pulse sequences at each stage are used to test the incremental change in ferroelectric polarization charge caused by the incremental change in the read pulse sequence under each recovery pulse, thereby determining the polarization reversal time under each energy level voltage, achieving the accumulation of more polarization values, and determining the defect concentration distribution at each energy level. In order to ensure that the test process does not change the charged state of the trap, the amplitude and pulse width of the read pulse sequence after each recovery positive pulse in this embodiment do not exceed the amplitude and pulse width of the current recovery positive pulse.

[0047] like Figure 4 and 5 As shown in the figure, the step recovery pulse sequence diagram and the read pulse sequence diagram provided in this embodiment are respectively Figure 4 , a first stress pulse Vstr is applied to the ferroelectric capacitor (FeCAP) for a certain time to release electrons from the boundary traps of the ferroelectric capacitor. Then, a recovery positive pulse is used to fill the boundary traps and restore the device state. After the stress and recovery operations, a multi-pulse read pulse sequence test is applied to characterize the state of the trapped electrons, such as Figure 5 As shown, an initial negative pulse is used to flip all the domains to the negative direction, and a read positive pulse sequence (Vtest) is used to measure the ferroelectric polarization charge increment as a function of voltage (because our test voltage is a read operation, it is only used to achieve the reversal of the domain and the reversal time confirmation process. Vstr and Vrec are operating voltages to achieve electron capture and decapture.

[0048] In one embodiment, the amplitude of the first stress pulse Vstr is -2V, the pulse width is 1s, the recovery positive pulse sequence is a rectangular pulse sequence Vrec: Vr1~Vrn with an amplitude increasing by 0.2V, the duration of each recovery positive pulse is 8-10s, the rise and fall time is 10us, and the time interval between the recovery positive pulses is 10-20us.

[0049] Preferably, the recovery positive pulse sequence is preferably set to 10 pulses, the starting recovery positive pulse Vr1 is 0.2V, the ending recovery positive pulse Vrn is 2V, the recovery positive pulse duration is 8-10s, the rise and fall time of each recovery positive pulse is 10us, and the time interval between pulses is 10us; the pulse height and pulse width designed in this way can realize the release and capture of electrons during the test without generating new leakage current.

[0050] In one embodiment, the read pulse sequence is a rectangular positive pulse sequence Vtest: V1~Vt with an amplitude increasing by 0.1V. The value of Vt in each test stage depends on the value of Vrn, that is, Vt=Vrn. For example, when the current Vrec=0.6V, the read pulse sequence Vtest=0.1, 0.2...0.6V; when Vrec=2, the read pulse sequence Vtest=0.1, 0.2...2V; the duration of each read positive pulse is 200ns, and the time interval between the read positive pulses is 150-200ns; the amplitude of the initial negative pulse is -2V, and the pulse duration is 0.5-1us. The initial negative pulse is set to reverse all ferroelectric domains in the dielectric to a negative direction, and then all ferroelectric domains are flipped to the positive direction little by little through the read pulse sequence. However, some ferroelectric domains at the bottom electrode interface cannot be reversed to the positive direction because they are pinned by positively charged vacancies.

[0051] Preferably, the initial read positive pulse V1 is 0.1V, the recovery positive pulse duration is 200ns, and the time interval between pulses is 150-200ns. In this way, the Vt pulse width of the read positive pulse sequence Vtest applied after each step of the recovery positive pulse is much smaller than the pulse width of the first stress pulse and the recovery pulse, avoiding the read voltage from affecting the operation of vacancy capturing electrons, and ensuring that the test process does not change the charged state of the trap.

[0052] In this embodiment, the following steps are also included:

[0053] refer to Figure 6As shown, before applying the first stress pulse, an initial stress pulse and an initial read pulse sequence are applied to the top electrode of the ferroelectric capacitor through a characteristic analyzer, wherein the initial stress pulse is a rectangular pulse with the same amplitude and pulse width as the first stress pulse, and the time interval between the initial stress pulse and the first stress pulse is 8-10s, the amplitude is -2V, the pulse duration is 0.8-1s, and the final pulse amplitude and pulse width of the initial read pulse sequence are not greater than the amplitude and pulse width of the initial stress pulse. In this embodiment, the initial stress pulse and initial read pulse sequence are configured by initially obtaining a semiconductor sample whose internal polarization state is unknown. The initial stress pulse Vstress causes all electric domains to reverse to a single state, and all defects at the interface lose electrons. A series of test waveforms (initial read pulse sequence) are then applied to measure the change in Qrem in this state. Logically, Vr1 should be directly applied afterwards and Qrem measured in the Vr1 state. However, a similar first stress pulse is added before applying Vr1. This is because the initial read pulse sequence Vtest following the initial stress pulse Vstress is a pulse sequence of 0.1V to 2V. This series of positive voltages can cause errors in the subsequent Vrec operation. To avoid this, the first stress pulse is only applied before the first Vrec operation.

[0054] The following describes the testing process of the method of this embodiment through a specific example.

[0055] In this example, the series of pulse voltages are specifically set as follows: the amplitude of the initial stress pulse and the first stress pulse is -2V, the width is 1s, the recovery pulse sequence Vrec: Vr1, Vr2, ..., Vrn = 0.2V, 0.4V, ..., 1V, the amplitude of the initial negative pulse of the read pulse sequence is -2V, the pulse duration is 1us, the read pulse sequence V1 is 0.1V, and the amplitudes of other pulses increase by 0.1V successively to ensure that the final pulse amplitude is no greater than the amplitude of the previous recovery positive pulse or initial stress pulse. In this example, the read pulse sequence Vt input after the initial stress pulse is 2V, and Vrn = 0.2V, 0.4V, ..., 1V, corresponding to Vt of 0.2V, 0.4V, ..., 1V respectively.

[0056] refer to Figure 7 and 8 , Figure 7 To restore the positive pulse 1V, read the pulse sequence Vtest=0.1V~1V series pulse voltage diagram, Figure 8 for Figure 7 The transient current density response diagram obtained under the pulse voltage is obtained by Figure 8 The charge density obtained by integrating the current at each Vtest is as follows: Figure 9As shown in FIG, when the voltage is stabilized at 0 V, the residual charge density is marked as Qrem, which represents the residual value of the ferroelectric domain polarization corresponding to each Vtest, which is the change in polarization charge caused by the increase of Vtest.

[0057] Based on the above Figure 7-9 The experimental process is to realize the recovery of positive pulse Vrec: 0.2~2V, and read the pulse sequence to adapt to the recovery of positive pulse conditions and obtain the change of polarization charge caused by the increase of Vtest. Figure 10 , is a graph based on the step recovery pulse test results of TiN-HZO-TiN FeCAP capacitors, which can determine the change of the residual charge density Qrem under Vrec: 0.2V~2V and Vtest. Each line represents the evolution of Qrem, that is, the test process of applying Vtest after different recovery positive pulses. As Vrec gradually increases, more boundary defects near the bottom electrode are filled, and the charged traps capture electrons and become neutral, resulting in the release of the originally pinned ferroelectric domains and an increase in the residual polarization value, which can be observed as an increase in Qrem.

[0058] Figure 11 In order to simulate the response diagram of TiN-HZO-TiN FeCAP capacitor under different external voltages, we first use TCAD to make our capacitor model and use the actual tested PV curve (such as Figure 7 and Figure 8 ) is input into the capacitor model in TCAD to simulate the defect distribution in the capacitor model, and then it can be simulated which defect energy level participates in the response under each external voltage.

[0059] Figure 12 The defect density distribution diagram under different defect energy levels is obtained by combining Figure 11 TCAD simulation results and Figure 10 The density and energy level distribution of boundary traps near the bottom electrode of TiN-HZO-TiN FeCAP capacitor were extracted based on the step recovery pulse experimental results. Figure 10 Each test voltage Vtest corresponds to Figure 11 The simulated external voltage (v) is Figure 10 The difference in the number of defects filled at each test voltage under each recovery positive pulse is ΔQ, and Figure 11 The energy level response corresponding to each external voltage in the Figure 12 The x and y axes represent the defect density distribution in each defect energy level at different defect energy levels.

[0060] System Example

[0061] According to an embodiment of the present invention, a system for testing the trap density and energy distribution of a ferroelectric capacitor interface layer is provided. The system for testing the trap density and energy distribution of a ferroelectric capacitor interface layer according to an embodiment of the present invention includes:

[0062] A test circuit includes a characteristic analyzer and a ferroelectric capacitor to be tested, wherein a top electrode and a bottom electrode of the ferroelectric capacitor are connected to a source measurement unit channel of the characteristic analyzer;

[0063] The characteristic analyzer applies a series of pulse voltages to the top electrode of the ferroelectric capacitor, the series of pulse voltages including a recovery pulse sequence and a read pulse sequence, the recovery pulse sequence including a first stress pulse and a recovery positive pulse sequence, and a read pulse sequence applied after each recovery positive pulse, the read pulse sequence including an initial negative pulse and a read positive pulse sequence with successively increasing amplitudes; the final pulse amplitude and pulse width of the read positive pulse sequence applied after each recovery positive pulse are no greater than the amplitude and pulse width of the previous recovery positive pulse;

[0064] The characteristic analyzer determines the change of the polarization charge density of the ferroelectric capacitor with time under each recovery positive pulse and read pulse sequence through the collected electrical signals, so as to determine the change of the electric domain with time and the defect concentration distribution at each energy level.

[0065] The present embodiment provides a system for testing the trap density and energy distribution in the interface layer of a ferroelectric capacitor. To study the relationship between domain wall expansion and polarization reversal, a characteristic analyzer applies a recovery pulse and a read pulse sequence to the top electrode of the ferroelectric capacitor. The first stress pulse is used to positively charge all vacancies at the bottom electrode to pin the domains. The recovery positive pulse sequence is used to gradually capture electrons from the vacancies under each positive pulse, causing all vacancies at the bottom electrode interface to lose electrons and become positively charged, thereby gradually restoring the pinned domains to free domains. The initial negative pulse is used to achieve domain reversal, and the read pulse sequence is used to test the change in ferroelectric polarization charge. In this way, the incremental change in ferroelectric polarization charge caused by the incremental change in the read pulse sequence under each recovery pulse is tested by the recovery pulse and read pulse sequence at each stage, thereby determining the polarization reversal time at each energy level voltage, achieving the accumulation of more polarization values, and determining the defect concentration distribution at each energy level. To ensure that the test process does not change the charged state of the traps, the amplitude and pulse width of the read pulse sequence after each recovery positive pulse do not exceed the amplitude and pulse width of the current recovery positive pulse.

[0066] In this embodiment, before applying the first stress pulse to the top electrode of the ferroelectric capacitor, the characteristic analyzer also applies an initial stress pulse and an initial read pulse sequence, and the final pulse amplitude and pulse width of the initial read pulse sequence are no greater than the amplitude and pulse width of the initial stress pulse.

[0067] In this embodiment, the recovery positive pulse sequence is a rectangular pulse sequence with an amplitude increasing by 0.2V. The duration of each recovery positive pulse is 8-10s, the rise and fall time is 10us, and the time interval between the recovery positive pulses is 10-20us.

[0068] In this embodiment, the first stress pulse and the initial stress pulse are rectangular pulses with the same amplitude and pulse width, and the time interval between the initial stress pulse and the first stress pulse is 8-10s, the amplitude is 2V, the pulse duration is 1s, and the final pulse amplitude and pulse width of the initial read pulse sequence are smaller than the amplitude and pulse width of the initial stress pulse.

[0069] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device or system embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, refer to the partial description of the method embodiments. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. A person of ordinary skill in the art can understand and implement it without making any creative efforts.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and the contents not described in detail in the specification of the present invention are common knowledge to those skilled in the art.

Claims

1. A method for testing the trap density and energy distribution of a ferroelectric capacitor interface layer, characterized in that: Including steps: Constructing a test circuit; constructing a test circuit including a characteristic analyzer and a ferroelectric capacitor to be tested, wherein the top electrode and the bottom electrode of the ferroelectric capacitor are connected to a source measurement unit channel of the characteristic analyzer; Testing phase: applying a series of pulse voltages to the top electrode of the ferroelectric capacitor through a characteristic analyzer, the series of pulse voltages including a recovery pulse sequence and a read pulse sequence, the recovery pulse sequence including a first stress pulse and a recovery positive pulse sequence, a read pulse sequence applied after each recovery positive pulse, the read pulse sequence including an initial negative pulse and a read positive pulse sequence with successively increasing amplitudes; the final pulse amplitude and pulse width of the read positive pulse sequence applied after each recovery positive pulse are not greater than the amplitude and pulse width of the previous recovery positive pulse; Analysis process: Based on the electrical signals collected by the characteristic analyzer, the change of the polarization charge density of the ferroelectric capacitor under each recovery positive pulse and read pulse sequence with time is determined to determine the change of the electric domain with time and the defect concentration distribution at each energy level.

2. The method for testing the trap density and energy distribution of the ferroelectric capacitor interface layer according to claim 1, wherein: Also includes the steps: Before applying the first stress pulse, an initial stress pulse and an initial read pulse sequence are applied to the top electrode of the ferroelectric capacitor through a characteristic analyzer, and the final pulse amplitude and pulse width of the initial read pulse sequence are not greater than the amplitude and pulse width of the initial stress pulse.

3. The method for testing the trap density and energy distribution of the ferroelectric capacitor interface layer according to claim 1, wherein: The recovery positive pulse sequence is a rectangular pulse sequence with an amplitude increasing by 0.2V in sequence. The duration of each recovery positive pulse is 8-10s, the rise and fall time is 10us, and the time interval between the recovery positive pulses is 10-20us.

4. The method for testing the trap density and energy distribution of the ferroelectric capacitor interface layer according to claim 1, wherein: The read pulse sequence is a rectangular positive pulse sequence with an amplitude increasing by 0.1 V. The duration of each read positive pulse is 200 ns, the rise and fall time is 100 ns, and the time interval between the read positive pulses is 150-200 ns.

5. The method for testing the trap density and energy distribution of the ferroelectric capacitor interface layer according to claim 1, wherein: The amplitude of the initial negative pulse is -2V, and the pulse duration is 0.5-1us.

6. The method for testing the trap density and energy distribution of the ferroelectric capacitor interface layer according to claim 2, wherein: The first stress pulse and the initial stress pulse are rectangular pulses with the same amplitude and pulse width, and the time interval between the initial stress pulse and the first stress pulse is 8-10s, the amplitude is -2V, the pulse duration is 0.8-1s, and the final pulse amplitude and pulse width of the initial read pulse sequence are smaller than the amplitude and pulse width of the initial stress pulse.

7. A ferroelectric capacitor interface layer trap density and energy distribution testing system, characterized in that: include: A test circuit includes a characteristic analyzer and a ferroelectric capacitor to be tested, wherein a top electrode and a bottom electrode of the ferroelectric capacitor are connected to a source measurement unit channel of the characteristic analyzer; The characteristic analyzer applies a series of pulse voltages to the top electrode of the ferroelectric capacitor, the series of pulse voltages including a recovery pulse sequence and a read pulse sequence, the recovery pulse sequence including a first stress pulse and a recovery positive pulse sequence, and a read pulse sequence applied after each recovery positive pulse, the read pulse sequence including an initial negative pulse and a read positive pulse sequence with successively increasing amplitudes; the final pulse amplitude and pulse width of the read positive pulse sequence applied after each recovery positive pulse are no greater than the amplitude and pulse width of the previous recovery positive pulse; The characteristic analyzer determines the change of the polarization charge density of the ferroelectric capacitor with time under each recovery positive pulse and read pulse sequence through the collected electrical signals, so as to determine the change of the electric domain with time and the defect concentration distribution at each energy level.

8. The ferroelectric capacitor interface layer trap density and energy distribution testing system according to claim 7, characterized in that: Before applying the first stress pulse to the top electrode of the ferroelectric capacitor, the characteristic analyzer also applies an initial stress pulse and an initial read pulse sequence, and the final pulse amplitude and pulse width of the initial read pulse sequence are not greater than the amplitude and pulse width of the initial stress pulse.

9. The ferroelectric capacitor interface layer trap density and energy distribution testing system according to claim 7, wherein: The recovery positive pulse sequence is a rectangular pulse sequence with an amplitude increasing by 0.2V in sequence. The duration of each recovery positive pulse is 8-10s, the rise and fall time is 10us, and the time interval between the recovery positive pulses is 10-20us.

10. The ferroelectric capacitor interface layer trap density and energy distribution testing system according to claim 8, wherein: The first stress pulse and the initial stress pulse are rectangular pulses with the same amplitude and pulse width, and the time interval between the initial stress pulse and the first stress pulse is 8-10s, the amplitude is 2V, the pulse duration is 1s, and the final pulse amplitude and pulse width of the initial read pulse sequence are smaller than the amplitude and pulse width of the initial stress pulse.

Images