Semiconductor test structure and preparation method thereof

Abstract

The invention provides a semiconductor test structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to solve the problem of low yield of the semiconductor test structure caused by incomplete removal of a sacrificial material in the process of preparing the semiconductor test structure. The semiconductor test structure provided by the invention comprises a packaging substrate, an adapter shell structure, an adapter plate and at least one test chip. Wherein the adapter shell structure is located on one side of the packaging substrate, and an accommodating cavity is defined by the adapter shell structure and the packaging substrate. The adapter plate and the at least one test chip are both located in the accommodating chamber; the at least one test chip is arranged between the packaging substrate and the adapter plate; the adapter plate comprises a third test contact, and the third test contact is connected with the second test contact. When the semiconductor test structure is manufactured, the test contact does not need to be covered with a sacrificial material, and the problem that the yield of the semiconductor test structure is low due to the fact that the sacrificial material is not thoroughly removed is solved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor test structure and a preparation method thereof. Background Art

[0002] Semiconductor testing is an important step in the semiconductor design, production, packaging, and testing process. It is the process of using specific equipment to detect DUT (Device Under Test) to identify device defects and verify whether the device meets the design goals. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor test structure and a method for manufacturing the same.

[0004] The embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a semiconductor test structure is provided, comprising: a packaging substrate, an adapter shell structure, an adapter board, and at least one test chip. The adapter shell structure is located on one side of the packaging substrate, and the adapter shell structure and the packaging substrate enclose a accommodating chamber; the adapter shell structure includes a first test contact and a second test contact, the first test contact is located on the side of the adapter shell structure facing away from the packaging substrate, and the second test contact is located on the side of the adapter shell structure facing the packaging substrate, and the first test contact is connected to the second test contact. In addition, the adapter board and at least one test chip are both located in the accommodating chamber; the at least one test chip is arranged between the packaging substrate and the adapter board; the adapter board includes a third test contact, and the third test contact is connected to the second test contact.

[0006] In some embodiments, the third test contact is located on a side of the interposer facing away from the package substrate.

[0007] In some embodiments, at least one chipset is included, and each chipset includes a plurality of the test chips; in the chipset: the plurality of test chips are stacked along a direction perpendicular to the packaging substrate, and the plurality of test chips are connected by connecting wires; the chipset is located between the packaging substrate and the adapter board, and the chipset is connected to the packaging substrate and the adapter board respectively; when there are multiple chipsets, the plurality of chipsets are spaced apart along a direction parallel to the packaging substrate.

[0008] In some embodiments, the transfer shell structure includes a top plate and a side plate; the top plate is opposite to the packaging substrate, and the side plate connects the top plate and the packaging substrate.

[0009] In some embodiments, an adhesive is further included, wherein the adhesive is located between the side plate and the packaging substrate, and the adhesive is used to connect the side plate and the packaging substrate.

[0010] In some embodiments, the top plate includes a first groove, the opening of the first groove faces the packaging substrate, and at least part of the connection wires connecting the test chip and the adapter board are located in the first groove.

[0011] In some embodiments, the adapter board also includes a connecting contact, a first board portion and a second board portion, the first board portion and the second board portion are connected, the connecting contact is located in the first board portion, and the third test contact is located in the second board portion; wherein, in a direction perpendicular to the packaging substrate, the thickness of the first board portion is less than the thickness of the second board portion; the test chip is connected to the connecting contact through a connecting wire.

[0012] In some embodiments, in a direction parallel to the package substrate, a size of the first plate portion is smaller than a size of the second plate portion.

[0013] In some embodiments, the top plate includes a protruding structure, the protruding structure is located on the side of the top plate facing the packaging substrate, and the second test contact is located on the protruding structure; the second plate portion includes a second groove, the third test contact is located at the bottom of the second groove, and the protruding structure is located in the second groove.

[0014] In some embodiments, the top plate includes a protruding structure, the protruding structure being located on a side of the top plate facing the package substrate, the protruding structure being connected to the first plate portion and surrounding the second plate portion.

[0015] In some embodiments, in a direction perpendicular to the package substrate, a distance from the first plate portion to the transfer shell structure ranges from 150 μm to 300 μm.

[0016] On the other hand, a method for preparing a semiconductor test structure is provided, comprising: forming at least one test chip on one side of a packaging substrate; forming an adapter board on a side of the at least one test chip facing away from the packaging substrate, the adapter board comprising a third test contact; connecting an adapter shell structure on one side of the packaging substrate, the adapter shell structure comprising a first test contact and a second test contact, the first test contact being located on a side of the adapter shell structure facing away from the packaging substrate, and the second test contact being located on a side of the adapter shell structure facing the packaging substrate; the adapter shell structure and the packaging substrate enclosing a accommodating chamber, the adapter board and the test chip being both located in the accommodating chamber; and connecting the third test contact to the second test contact.

[0017] In some embodiments, connecting the transfer shell structure on one side of the packaging substrate includes: forming an adhesive on the packaging substrate and / or the transfer shell structure; fastening the transfer shell structure on the packaging substrate through the adhesive; and curing the adhesive.

[0018] In some embodiments, before connecting the transfer shell structure on one side of the packaging substrate, the method further includes: forming a transfer shell structure, the transfer shell structure including a top plate and a side plate; and forming a first groove on the side of the top plate facing the packaging substrate.

[0019] In some embodiments, the transfer board is formed on the side of the at least one test chip facing away from the packaging substrate, including: forming a first board portion and a second board portion on the side of the at least one test chip facing away from the packaging substrate, the first board portion including a connecting contact, the second board portion including a third test contact, and the first board portion and the second board portion are connected; wherein, in a direction perpendicular to the packaging substrate, the thickness of the first board portion is less than the thickness of the second board portion.

[0020] In some embodiments, before connecting the transfer shell structure on one side of the packaging substrate, it also includes: forming a transfer shell structure, the transfer shell structure including a top plate and a side plate; forming a protruding structure on the side of the top plate facing the packaging substrate, and the second test contact is located on the protruding structure; forming a second groove on the side of the second plate portion facing away from the packaging substrate; and positioning the protruding structure in the second groove.

[0021] In some embodiments, before connecting the transfer shell structure on one side of the packaging substrate, it also includes: forming a transfer shell structure, the transfer shell structure including a top plate and a side plate; forming a protruding structure on the side of the top plate facing the packaging substrate; and connecting the protruding structure to the first plate portion and surrounding the second plate portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0023] Figure 1 is a side view of a semiconductor test structure according to some embodiments;

[0024] Figure 2is a top view of a semiconductor test structure according to some embodiments;

[0025] Figure 3 for Figure 2 A cross-sectional view of the semiconductor test structure along the AA section line;

[0026] Figure 4 is a schematic structural diagram of a semiconductor test structure according to some other embodiments;

[0027] Figure 5 is a structural schematic diagram of a semiconductor test structure during preparation according to some embodiments;

[0028] Figure 6 is a cross-sectional view of a semiconductor test structure according to some embodiments;

[0029] Figure 7 is a cross-sectional view of another semiconductor test structure according to some embodiments;

[0030] Figure 8 is a cross-sectional view of another semiconductor test structure according to some embodiments;

[0031] Figure 9 is a cross-sectional view of another semiconductor test structure according to some embodiments;

[0032] Figure 10 is a flow chart of a method for preparing a semiconductor test structure according to some embodiments;

[0033] Figure 11 A schematic diagram of a structure after providing a packaging substrate according to some embodiments;

[0034] Figure 12 is a schematic structural diagram after at least one test chip is formed on one side of a packaging substrate according to some embodiments;

[0035] Figure 13 is a structural schematic diagram of forming an adapter board on a side of at least one test chip facing away from the package substrate according to some embodiments;

[0036] Figure 14 is a schematic diagram of a structure after forming connecting lines according to some embodiments;

[0037] Figure 15 is a schematic diagram of the structure after forming the adhesive according to some embodiments;

[0038] Figure 16 is a structural schematic diagram of a transfer shell structure connected to one side of a package substrate according to some embodiments;

[0039] Figure 17is a flow chart of a method for preparing a semiconductor test structure according to some embodiments;

[0040] Figure 18 is a flow chart of a method for preparing a semiconductor test structure according to some embodiments.

[0041] Figure numerals: 1. semiconductor test structure; 10. packaging substrate; 20. adapter shell structure; 21. first test contact; 22. second test contact; 23. top plate; 231. first groove; 232. protruding structure; 24. side plate; 30. adapter plate; 31. third test contact; 32. connection contact; 33. first plate portion; 34. second plate portion; 341. second groove; 40. test chip; 41. chipset; 50. accommodating chamber; 60. adhesive; 70. connecting wire; 80. solder ball; 90. sacrificial material. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0043] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the embodiments disclosed herein.

[0046] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0047] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0048] Before a chip can be finally made into a terminal product, it generally needs to go through the following links: chip design, wafer manufacturing, packaging, semiconductor testing, board-level packaging, etc. Semiconductor testing, as an important step, is a process of using specific instruments to test the DUT (Device Under Test) to verify whether the device under test meets the design goals and separate good products from bad products. For example, the device under test may include a packaged chip product. According to the "ten-fold rule" in electronic system fault detection: if semiconductor testing fails to find fault problems related to chip design and manufacturing, then the cost of finding the fault at the circuit board level will rise to ten times that of the chip level. By analogy, the cost of finding a fault increases exponentially. Therefore, semiconductor testing plays an important role in reducing cost waste. Semiconductor testing provides engineers with real and effective test results. Engineers can improve the design and manufacturing plans of the chip based on these test results, thereby reducing cost waste.

[0049] The basic working mechanism of semiconductor testing is: program the tester so that it generates any type of signal. Multiple signals together form a test vector. The tester applies a test vector to the DUT, transmits the output signal generated by the DUT to the instrument of the tester to measure its parameters, and compares the test result with the test vector stored in the tester. If the difference between the measurement result and the test vector is within the acceptable tolerance range, then the DUT will be considered to be good, otherwise it is a bad product.

[0050] According to some embodiments, the present disclosure provides a semiconductor test structure as a device under test for performing semiconductor testing. Figure 1 FIG. 1 is a side view of a semiconductor test structure according to some embodiments. Figure 2 FIG. 4 is a top view of a semiconductor test structure according to some embodiments. Figure 3 for Figure 2 Some embodiments of the present disclosure provide a semiconductor test structure, such as Figure 1 、 Figure 2 and Figure 3 As shown, the semiconductor test structure 1 includes a package substrate 10, at least one test chip 40, an adapter plate 30, and an adapter shell structure 20. The adapter shell structure 20 is located on one side of the package substrate 10, and the adapter shell structure 20 and the package substrate 10 enclose a receiving chamber 50. Exemplarily, the adapter shell structure 20 may include an adapter plate structure. Exemplarily, the adapter shell structure 20 may be a box-shaped adapter plate structure; alternatively, the adapter shell structure 20 may be a bowl-shaped adapter plate; alternatively, the adapter shell structure 20 may be a box-shaped structure with at least the top portion being the adapter plate structure; alternatively, the adapter shell structure 20 may be a bowl-shaped structure with at least the top portion being the adapter plate structure. By attaching the adapter shell structure 20 to one side of the package substrate 10, the adapter shell structure 20 and the package substrate 10 enclose a receiving chamber 50. Exemplarily, the adapter shell structure 20 may be bonded to the package substrate 10. The adapter plate 30 and the at least one test chip 40 are both located within the receiving chamber 50. At least one test chip 40 is disposed between the package substrate 10 and the interposer 30. The test chip 40 is connected to the package substrate 10 and the interposer 30, respectively.

[0051] The transfer shell structure 20 includes a first test contact 21 and a second test contact 22. The first test contact 21 is located on the side of the transfer shell structure 20 facing away from the package substrate 10, and the second test contact 22 is located on the side of the transfer shell structure 20 facing the package substrate 10, and the first test contact 21 is connected to the second test contact 22. Exemplarily, the first test contact 21 and the second test contact 22 can be connected through a through-silicon via. The transfer board 30 includes a third test contact 31, and the third test contact 31 is connected to the second test contact 22. Exemplarily, the third test contact 31 can be connected to the second test contact 22 through a solder ball, or the third test contact 31 can be connected to the second test contact 22 through a wire, thereby achieving electrical connection between the third test contact 31 and the second test contact 22. Since the second test contact 22 is connected to the first test contact 21, the third test contact 31 can be electrically connected to the first test contact 21. Among them, the first test contact 21 can be electrically connected to the test machine, and the first test contact 21 is used to transmit the test signal from the test machine to the third test contact 31 and the second test contact 22, or the first test contact 21 is used to transmit the test signal from the third test contact 31 and the second test contact 22 to the test machine.

[0052] The semiconductor test structure 1 provided in some embodiments of the present disclosure adopts a method of setting a transfer shell structure 20 on one side of the package substrate 10, so that a accommodating chamber 50 is formed between the transfer shell structure 20 and the package substrate 10, so that the test chip 40 and the transfer board 30 are both located in the accommodating chamber 50, thereby protecting the transfer board 30 and the test chip 40 from the influence of the external environment (water vapor, temperature, pollution, etc.). In addition, the third test contact 31 on the transfer board 30 is connected to the second test contact 22 of the transfer shell structure 20, and the second test contact 22 is connected to the first test contact 21, so that the electrical signal can be transmitted from the third test contact 31 to the first test contact 21 through the second test contact 22. The first test contact 21 is located on the surface of the transfer shell structure 20 away from the package substrate 10, which facilitates the connection between the probe of the test machine and the first test contact 21, which is beneficial to prevent problems such as false touch or short circuit during the test process and achieve the purpose of the test. Furthermore, during testing, the semiconductor test structure 1 needs to be placed on a test machine, which clamps the semiconductor test structure 1. The transfer shell structure 20 can provide composite functions such as moisture resistance, pressure resistance, and support for the semiconductor test structure 1. Furthermore, the package substrate 10 and transfer shell structure 20 in the semiconductor test structure 1 provided in the embodiments of the present disclosure can be bonded together to complete the package, which helps simplify the manufacturing process of the semiconductor test structure 1.

[0053] Figure 4 FIG. 1 is a schematic structural diagram of a semiconductor test structure according to some other embodiments. Figure 4As shown, in some embodiments, a semiconductor test structure 1 includes a package substrate 10, a test chip 40, an adapter plate 30, and an EMC (Epoxy Molding Compound). The EMC, test chip 40, and adapter plate 30 are all located on the same side of the package substrate 10. The EMC encapsulates the test chip 40 and adapter plate 30, while exposing third test contacts 31 on the adapter plate 30. EMC is a thermosetting chemical material used in semiconductor packaging. It is made from epoxy resin as a base resin, high-performance phenolic resin as a curing agent, fillers such as silica powder, and various additives.

[0054] Figure 5 FIG. 1 is a schematic diagram of a structure during the preparation of a semiconductor test structure according to some embodiments. Figure 5 As shown, in some embodiments, when preparing a semiconductor test structure 1, a plurality of test chips 40 and an adapter plate 30 are stacked and sequentially formed on one side of a package substrate 10 in a direction perpendicular to the package substrate 10. Wire bonding is achieved between the package substrate 10 and the test chip 40 closest to the package substrate 10, between the test chips 40 and 40, and between the adapter plate 30 and the test chip 40 closest to the adapter plate 30 via a plurality of connecting wires 70. Before filling the mold cavity of the semiconductor test structure 1 with EMC, a sacrificial material 90 is required to be applied over the third test contact 31 of the adapter plate 30. Exemplarily, the sacrificial material 90 can include high-temperature adhesive tape or a hydrosol. After forming the sacrificial material 90 over the test contact, the EMC is extruded into the mold cavity of the semiconductor test structure 11 and encapsulates the test chip 40 and the adapter plate 30. After curing and forming within the mold cavity, the EMC forms a structure having a certain hardness. After the EMC is solidified and formed, special equipment is required to grind the EMC and reduce the thickness of the mold to expose the sacrificial material 90. The sacrificial material 90 is then removed to expose the third test contact 31, and finally the following is formed: Figure 1 The semiconductor test structure 1 shown in FIG. During the preparation process of the semiconductor test structure 1 , there is a problem that the sacrificial material 90 is not completely removed.

[0055] According to some embodiments of the present disclosure, a semiconductor test structure 1 is provided, such as Figure 2 and Figure 3As shown, by providing an adapter shell structure 20 on one side of the package substrate 10, the test chip 40 and the adapter plate 30 are protected from the influence of the external environment (water vapor, temperature, pollution, etc.), and the composite functions of moisture resistance, pressure resistance and support are achieved. When making the semiconductor test structure 1 in this embodiment, there is no need to cover the sacrificial material 90 above the test contact, which solves the problem of incomplete removal of the sacrificial material 90, which is beneficial to improving the yield of the semiconductor test structure 1. In addition, when making the semiconductor test structure 1 provided in some embodiments of the present disclosure, there is no need to fill the mold cavity with EMC injection molding and there is no need to use special equipment to grind the EMC, which is beneficial to simplifying the production process and improving production efficiency; it is beneficial to reduce equipment utilization, reduce packaging materials, and reduce production costs.

[0056] In the following, we continue to combine Figure 2 and Figure 3 , the positional relationship between the third test contact 31 and the transfer in the semiconductor test structure 1 is introduced.

[0057] In some embodiments, as Figure 3 As shown, the third test contact 31 is located on the side of the interposer 30 facing away from the package substrate 10, facilitating connection between the third test contact 31 and the second test contact 22 via a solder ball 80. It is understood that the third test contact 31 and the second test contact 22 can be connected via tiny solder balls 80, which helps reduce the space between the interposer 30 and the interposer housing structure 20. Furthermore, achieving electrical connection via solder balls 80 offers the advantages of low resistance and good signal transmission.

[0058] In the following, we continue to combine Figure 2 and Figure 3 , when the semiconductor test structure 1 includes a plurality of test chips 40 , the positional relationship and connection relationship of the test chips 40 are introduced.

[0059] In some embodiments, as Figure 3 As shown, the semiconductor test structure 1 includes at least one chipset 41, and each chipset 41 includes a plurality of test chips 40. Exemplarily, the semiconductor test structure 1 may include one chipset 41, or the semiconductor test structure 1 may include two or more chipsets 41. Exemplarily, each chipset 41 may include 4, 8 or 16 test chips 40, etc. The above is only an example, and the present disclosure does not limit the number of chipsets 41 and the number of test chips 40 in the chipset 41. In the chipset 41, the plurality of test chips 40 may be stacked in a direction perpendicular to the package substrate 10, and the plurality of test chips 40 are connected by connecting wires 70. Exemplarily, the plurality of test chips 40 may be staggered in sequence by a distance in a direction parallel to the package substrate 10 (for example Figure 3In the figure, the multiple test chips 40 are horizontally staggered to the right by a distance, but not completely staggered. The multiple test chips 40 still overlap partially in the direction perpendicular to the package substrate 10, exposing the connection portion of each test chip 40. The connection portions of the multiple test chips 40 are connected by a connection wire 70. For example, the connection portions of the multiple test chips 40 can be connected in sequence by a single connection wire 70; alternatively, the connection portions of the multiple test chips 40 can be connected by multiple connection wires 70, for example, two adjacent test chips 40 are connected by a single connection wire 70, and the two adjacent connection wires 70 are connected at the connection portions of the test chips 40.

[0060] The chipset 41 is located between the package substrate 10 and the adapter board 30, and the chipset 41 is connected to the package substrate 10 and the adapter board 30 respectively. For example, the test chip 40 closest to the package substrate 10 in the chipset 41 is connected to the package substrate 10 via a connection line 70; the test chip 40 closest to the adapter board 30 in the chipset 41 is connected to the adapter board 30 via a connection line 70. Figure 3 In the embodiment, the bottom test chip 40 in the chipset 41 is connected to the package substrate 10 via a connection line 70 , and the top test chip 40 in the chipset 41 is connected to the adapter board 30 via a connection line 70 .

[0061] like Figure 3 As shown, when there are multiple chipsets 41, the multiple chipsets 41 are spaced apart in a direction parallel to the package substrate 10. When there are multiple chipsets 41, the adapter board 30 can be correspondingly longer in a direction parallel to the package substrate 10 to facilitate connection between the adapter board 30 and the multiple chipsets 41.

[0062] In this embodiment, the semiconductor test structure 1 encapsulates a plurality of test chips 40 , which can simulate the actual use scenario of the chips in products, and is conducive to making the test results obtained by the semiconductor test more referenceable.

[0063] In the following, combined Figure 3 , the positional relationship between the transfer shell structure 20 and the package substrate 10 in the semiconductor test structure 1 is introduced.

[0064] In some embodiments, the transfer shell structure 20 includes a top plate 23 and a side plate 24. The top plate 23 is arranged opposite to the package substrate 10, and the side plate 24 connects the top plate 23 and the package substrate 10. Exemplarily, the top plate 23 and the side plate 24 can be fixedly connected by bonding, welding, etc., or formed as one piece. The top plate 23 may include a transfer plate 30 structure; the side plate 24 may include a transfer plate 30 structure or an ordinary flat plate. In some examples, the top plate 23 and the side plate 24 are both flat plates, and the transfer shell structure 20 composed of the top plate 23 and the side plate 24 is a box structure. In other examples, the top plate 23 and the side plate 24 are both curved plates, and the transfer shell structure 20 composed of the top plate 23 and the side plate 24 is a round cover structure. The material of the package shell in the above examples may include metal, alloy or other materials with a certain hardness. The first test contact 21 and the second test contact 22 can be correspondingly arranged on both sides of the top plate 23, for example Figure 3 In the embodiment, the first test contact 21 and the second test contact 22 are arranged on the upper and lower sides of the top plate 23 relative to each other. For example, the first test contact 21 and the second test contact 22 can be connected by a silicon through hole. The first test contact 21 is arranged on the upper surface of the top plate (the side away from the adapter plate 30), and the second test contact 22 is arranged on the lower surface of the top plate (the side facing the adapter plate 30). Through the above arrangement, it is convenient for the second test contact 22 to be connected to the third test contact 31 on the adapter plate 30, and it is also convenient for the probe of the test machine to be connected to the first test contact 21, which is conducive to preventing problems such as false touch or short circuit from occurring during the test process, thereby achieving the purpose of the test. In addition, the top plate 23, the side plate 24 and the packaging substrate 10 can enclose a accommodating chamber 50, so that the test chip 40 and the adapter plate 30 are both located in the accommodating chamber 50, thereby protecting the adapter plate 30 and the test chip 40 from the influence of the external environment (water vapor, temperature, pollution, etc.). In addition, the semiconductor test structure 1 needs to be placed on a test machine during testing. The test machine clamps the semiconductor test structure 1 , and the top plate 23 and the side plates 24 can provide the semiconductor test structure 1 with composite functions such as moisture resistance, pressure resistance and support.

[0065] In some embodiments, the semiconductor test structure 1 further includes an adhesive 60. The adhesive 60 is located between the side plate 24 and the package substrate 10 and is used to connect the side plate 24 to the package substrate 10. Exemplarily, the adhesive 60 may include a thermosetting adhesive 60, a hot melt adhesive 60, a room temperature curing adhesive 60, a pressure-sensitive adhesive 60, and the like. In this embodiment, the adhesive 60 may be applied to the package substrate 10 or to the bottom of the side plate 24 of the transfer shell structure 20, and then the transfer shell structure 20 may be attached to the package substrate 10. Finally, the adhesive 60 may be cured to complete the package. This is simple to operate, helps to simplify the manufacturing process of the semiconductor test structure 1, and improves production efficiency.

[0066] In the following, combined Figure 3 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9 , the connection relationship between the top plate 23 and the adapter plate 30 of the semiconductor test structure 1 is introduced in detail.

[0067] like Figure 3 As shown, the test chip 40 closest to the adapter board 30 is connected to the adapter board 30 via a connecting wire 70. The connecting wire 70 is bent at a certain angle, and some connecting wires 70 are higher than the adapter board 30. Therefore, a gap is provided between the top plate 23 and the adapter board 30 to avoid the connecting wires 70 connecting the test chip 40 and the adapter board 30.

[0068] In some embodiments, as Figure 6 As shown, the top plate 23 may include a first groove 231, the opening of which faces the package substrate 10. Furthermore, at least a portion of the connection wires 70 connecting the test chip 40 to the adapter plate 30 are located within the first groove 231. For example, the first groove 231 may be provided above the test chip 40 closest to the adapter plate 30 and the adapter plate 30, and the orthographic projections of the first groove 231, the adapter plate 30, and the test chip 40 closest to the adapter plate 30 on the package substrate 10 may partially overlap. Providing the first groove 231 on the side of the top plate 23 facing the package substrate 10 facilitates avoiding portions of the connection wires 70 that are higher than the adapter plate 30.

[0069] In some embodiments, as Figure 7 As shown, the adapter board 30 further includes a connection contact 32, a first board portion 33, and a second board portion 34. The first board portion 33 is connected to the second board portion 34, and the thickness of the first board portion 33 is less than the thickness of the second board portion 34 in the direction perpendicular to the package substrate 10. For example, the first board portion 33 and the second board portion 34 can be bonded or integrally formed. Since the thickness of the first board portion 33 is less than the thickness of the second board portion 34 in the direction perpendicular to the package substrate 10, as shown in FIG. Figure 7 As shown, the connected first plate portion 33 and second plate portion 34 are stepped, and the second plate portion 34 is higher than the first plate portion 33 .

[0070] The connection contacts 32 are located on the first plate portion 33, and the third test contacts 31 are located on the second plate portion 34. The test chip 40 is connected to the connection contacts 32 via connection wires 70. The third test contacts 31 on the second plate portion 34 can be connected to the second test contacts 22 on the adapter shell structure 20 via solder balls 80. Because the thickness of the first plate portion 33 is less than that of the second plate portion 34 in a direction perpendicular to the package substrate 10, a gap is created between the first plate portion 33 and the top plate 23 when the second plate portion 34 is connected to the top plate 23 of the adapter shell structure 20. This helps avoid the connection wires 70 connecting the test chip 40 closest to the adapter plate 30 and the adapter plate 30.

[0071] In some embodiments, as Figure 7 As shown in FIG, in the direction parallel to the package substrate 10, the size of the first plate portion 33 is smaller than the size of the second plate portion 34. It should be noted that the "size" here refers to the size of the first plate portion 33. Figure 7 In the cross-section shown, the length of the first plate portion 33 is shorter than the length of the second plate portion 34 in a direction parallel to the package substrate 10. Furthermore, the surface area of the second plate portion 34 is larger than the surface area of the first plate portion 33. The larger upper surface area of the second plate portion 34 facilitates the placement of the third test contact 31 on the second plate portion 34 and also facilitates the connection of the third test contact 31 to the second test contact 22 on the adapter housing structure 20.

[0072] In some embodiments, as Figure 8 As shown, the top plate 23 includes a protruding structure 232. The protruding structure 232 is located on the side of the top plate 23 facing the package substrate 10, and the second test contact 22 is located on the protruding structure 232. Exemplarily, the second test contact 22 is located on the surface of the protruding structure 232 facing the adapter board 30, so that the second test contact 22 is connected to the third test contact 31 on the adapter board 30. The second plate portion 34 includes a second groove 341, and the third test contact 31 is located at the bottom of the second groove 341, that is, the third test contact 31 is located on the surface of the bottom of the second groove 341. The protruding structure 232 is located in the second groove 341, so that the second test contact 22 is connected to the third test contact 31. At the same time, the second plate portion 34 is located around the protruding structure 232, and the second plate portion 34 is connected to the top plate 23. Exemplarily, the second plate portion 34 can surround the protruding structure 232 and be connected to the top plate 23. For example, the second plate portion 34 can be bonded to the top plate 23 to improve the sealing performance at the connection between the second test contact 22 and the third test contact 31, thereby reducing interference from the external environment (such as water vapor, pollution, etc.) and improving the accuracy of the test results.

[0073] In some embodiments, as Figure 9As shown, the adapter plate 30 includes multiple first plate portions 33. For example, in this embodiment, the adapter plate 30 includes two first plate portions 33, and the second plate portion 34 is located between the two first plate portions 33. Since the thickness of the first plate portion 33 is less than the thickness of the second plate portion 34 in the direction perpendicular to the package substrate 10, the shape of the adapter plate 30 in this embodiment is similar to a "convex" shape, with a high middle and low sides. Figure 3 When the semiconductor test structure 1 includes multiple chip groups 41, multiple first board portions 33 may be provided accordingly to facilitate connection between the transfer board 30 and the chip groups 41. Figure 3 The semiconductor test structure 1 includes two chip sets 41 , and the adapter board 30 includes two first board portions 33 and one second board portion 34 . The two first board portions 33 are respectively located on both sides of the second board portion 34 and are respectively connected to the two chip sets 41 .

[0074] The top plate 23 may include a raised structure 232, which is located on the side of the top plate 23 facing the package substrate 10. The raised structure 232 is connected to the first plate portion 33 and surrounds the second plate portion 34. Exemplarily, the raised structure 232 may be an annular raised protrusion, so that the raised structure 232 surrounds the second plate portion 34. Moreover, the raised structure 232 surrounds the second test contact 22 so as to facilitate the connection between the second test contact 22 and the third test contact 31 on the second plate portion 34. Exemplarily, the raised structure 232 contacts the first plate portion 33, or the raised structure 232 can be bonded to the first plate portion 33. The coordinated arrangement of the raised structure 232 with the second plate portion 34 and the third plate portion is conducive to improving the sealing of the connection between the second test contact 22 and the third test contact 31, helping to reduce interference from the external environment (such as water vapor, pollution, etc.), and helping to improve the accuracy of the test results.

[0075] As can be seen from the embodiments described above, a gap is required between the adapter plate 30 and the top plate 23 to allow for the connection wires 70 connecting the test chip 40 and the adapter plate 30. If the distance d between the adapter plate 30 and the top plate 23 is too small, the gap will not be sufficient to allow for the connection wires 70 connecting the test chip 40 and the adapter plate 30. If the distance d between the adapter plate 30 and the top plate 23 is too large, space in the housing chamber 50 and material will be wasted.

[0076] Therefore, in some embodiments, Figure 3As shown, in the direction perpendicular to the package substrate 10, the distance d from the first plate portion 33 to the top plate 23 ranges from 150μm to 300μm. Exemplarily, the distance from the first plate portion 33 to the top plate 23 can be 150μm, 200μm or 300μm. When the distance from the first plate portion 33 to the top plate 23 approaches 150μm, it is more conducive to saving materials and controlling costs. When the distance from the first plate portion 33 to the top plate 23 approaches 300μm, it is more conducive to avoiding the connection line 70 between the test chip 40 and the adapter board 30. When the distance from the first plate portion 33 to the top plate 23 ranges from 150μm to 300μm, the top plate 23 can avoid the connection line 70 between the test chip 40 and the adapter board 30, and at the same time, it is conducive to saving materials and reducing production costs.

[0077] In the following, combined Figure 6 、 Figure 7 、 Figure 8 and Figure 9 , the solder ball 80 in the semiconductor test structure 1 is introduced.

[0078] In some embodiments, reference Figure 6 、 Figure 7 、 Figure 8 and Figure 9 The semiconductor test structure 1 further includes solder balls 80, which are located on the side of the package substrate 10 facing away from the test chip 40. During semiconductor testing, the solder balls 80 are electrically connected to the tester to obtain test vectors output by the tester and transmit the obtained test vectors to the test chip 40 via the package substrate 10. This arrangement facilitates the semiconductor test structure 1 to obtain test vectors output by the tester.

[0079] In addition, the solder ball 80 may be further located between the second test contact 22 and the third test contact 31 to connect the second test contact 22 and the third test contact 31 .

[0080] In the following, combined Figures 10 to 18 , a preparation method of the semiconductor test structure 1 is introduced in detail.

[0081] Figure 10 FIG. 4 is a flow chart of a method for preparing a semiconductor test structure according to some embodiments.

[0082] In some embodiments, as Figure 10 As shown, a method for preparing a semiconductor test structure 1 is also provided, including: S1 to S4.

[0083] S1. Form at least one test chip on one side of a packaging substrate.

[0084] Figure 11is a schematic structural diagram after providing a packaging substrate according to some embodiments, Figure 12 FIG. 1 is a schematic diagram of a structure after at least one test chip is formed on one side of a package substrate according to some embodiments. Figure 11 and Figure 12 As shown, a test chip 40 or a plurality of test chips 40 are formed on one side of the provided package substrate 10. The plurality of test chips 40 are stacked in a direction perpendicular to the package substrate 10, and the plurality of test chips 40 are connected by connecting wires 70 to form a chipset 41. The plurality of test chips 40 in the chipset 41 can be staggered in sequence along a direction parallel to the package substrate 10 by a certain distance (e.g., Figure 12 In the embodiment, multiple test chips 40 are horizontally staggered to the right from bottom to top (but not completely staggered), exposing the connection portion of each test chip 40 to facilitate interconnection of the multiple test chips 40 in subsequent steps. In this embodiment, two chip groups 41 are formed on one side of the package substrate 10.

[0085] S2. Form a transfer board on a side of the at least one test chip facing away from the package substrate, wherein the transfer board includes a third test contact.

[0086] Figure 13 FIG. 1 is a schematic structural diagram of forming an adapter plate on a side of at least one test chip facing away from a package substrate according to some embodiments. Figure 14 FIG. 1 is a schematic diagram of a structure after forming a connecting line according to some embodiments. Figure 13 and Figure 14 As shown, the adapter board 30 includes two first board portions 33 and a second board portion 34, with the second board portion 34 being located between the two first board portions 33. The adapter board 30 also includes connection pads 32 and third test pads 31. The connection pads 32 are located on the upper surface of the first board portion 33 to facilitate connection of the connection pads 32 with the test chip 40 in subsequent steps. The third test pads 31 are located on the upper surface of the second board portion 34 to facilitate connection of the third test pads 31 with the second test pads 22 in subsequent steps to transmit data. The adapter board 30 is formed on the test chip 40 farthest from the package substrate 10 among the multiple test chips 40, with one first board portion 33 correspondingly located above one chip group 41, and another first board portion 33 correspondingly located above another chip group 41. The first board portion 33 and the chipset 41 are stacked in a direction perpendicular to the package substrate 10 and offset from the chipset 41 by a distance in a direction parallel to the package substrate 10, exposing the connection portion of the test chip 40 closest to the adapter board 30 to facilitate connection between the test chip 40 and the connection pad 32 on the first board portion 33.

[0087] For example, Figure 14As shown, after forming the adapter board 30 on the side of at least one test chip 40 facing away from the packaging substrate 10, a connecting wire 70 can be formed, so that the connecting wire 70 connects the test chip 40 with the packaging substrate 10, the test chip 40 with the adapter board 30, and the test chip 40 with the test chip 40. For example, in this step, one connecting wire 70 can be formed, and the connecting wire 70 sequentially connects the packaging substrate 10 with the test chip 40, the test chip 40 with the test chip 40, and the test chip 40 with the adapter board 30. Alternatively, multiple connecting wires 70 can be formed, and the multiple connecting wires 70 respectively connect the packaging substrate 10 with the test chip 40, the test chip 40 with the test chip 40, and the test chip 40 with the adapter board 30, and two adjacent connecting wires 70 are short-circuited at the connection portion of the test chip 40.

[0088] S3. Connect an adapter shell structure on one side of the packaging substrate. The adapter shell structure includes a first test contact and a second test contact. The first test contact is located on the side of the adapter shell structure facing away from the packaging substrate, and the second test contact is located on the side of the adapter shell structure facing the packaging substrate. The adapter shell structure and the packaging substrate enclose a accommodating chamber, and the adapter board and the test chip are both located in the accommodating chamber.

[0089] Figure 15 is a schematic diagram of the structure after the adhesive is formed according to some embodiments, Figure 16 FIG. 1 is a schematic diagram of a structure after connecting a transfer shell structure to one side of a package substrate according to some embodiments. Figure 15 and Figure 16As shown, the adapter shell structure 20 may include a top plate 23 and a side plate 24, and the side plate 24 is connected to the top plate 23. The first test contact 21 is located on the top plate 23 and on the same side as the side plate 24, and the second test contact 22 can be arranged on the other side of the top plate 23 corresponding to the first test contact 21 (for example, the first test contact 21 and the second test contact 22 can be symmetrically arranged on both sides of the top plate 23), and the first test contact 21 and the second test contact 22 can be electrically connected through a silicon via. The first test contact 21 is used to connect to the test machine to transmit data signals. The second test contact 22 is used to connect to the third test contact 31 on the adapter board 30 to transmit data signals. By connecting the side plate 24 of the adapter shell structure 20 to one side of the package substrate 10, a accommodating chamber 50 can be naturally formed between the adapter shell structure 20 and the package substrate 10. For example, adhesive 60 can be formed on the package substrate 10, or on the bottom of the side panel 24. The transfer shell structure 20 is then buckled onto the package substrate 10, with the adhesive 60 located between the transfer shell structure 20 and the package substrate 10. The adhesive 60 is then cured by high temperature or other methods, thereby securing the transfer shell structure 20 to the package substrate 10. In this step, the transfer shell structure 20 is buckled onto the exterior of the test chip 40 and the transfer board 30, so that the transfer board 30 and the test chip 40 are located within the accommodating chamber 50 enclosed by the transfer shell structure 20 and the package substrate 10.

[0090] S4. Connect the third test contact to the second test contact.

[0091] In this step, if Figure 15 and Figure 16 As shown, solder balls 80 may be formed on the third test contacts 31 before the interposer housing structure 20 is connected to one side of the package substrate 10. Subsequently, when the interposer housing structure 20 is connected to one side of the package substrate 10, the second test contacts 22 are aligned with the solder balls 80 on the third test contacts 31 to connect the third test contacts 31 to the second test contacts 22.

[0092] Continue to refer Figure 16 After connecting the third test contact 31 to the second test contact 22, a solder ball 80 may be formed on the side of the package substrate 10 facing away from the test chip 40. The solder ball 80 may be connected to a test machine so that the test machine can input a test vector to the semiconductor test structure 1.

[0093] The semiconductor test structure 1 prepared by the above-mentioned preparation method can be used for semiconductor testing. Among them, the transfer shell structure 20 can protect the test chip 40 and the transfer board 30 from the influence of the external environment (water vapor, temperature, pollution, etc.), and realize the composite functions of moisture resistance, pressure resistance and support. In addition, the first test contact 21 and the second test contact 22 on the transfer shell structure 20 can be connected through a silicon through hole, and the second test contact 22 and the third test contact 31 can be connected through a solder ball 80, wherein the first test contact 21 is located on the surface of the transfer shell structure 20 away from the packaging substrate 10, which is convenient for the probe of the test machine to be connected to the first test contact 21, which is beneficial to prevent problems such as accidental touch or short circuit during the test process, thereby achieving the purpose of the test. In addition, the packaging substrate 10 and the transfer shell structure 20 in the semiconductor test structure 1 are packaged by bonding, which is beneficial to simplify the preparation process of the semiconductor test structure 1.

[0094] Furthermore, when manufacturing semiconductor test structures 1 according to the methods for manufacturing semiconductor test structures 1 provided in some embodiments of the present disclosure, there is no need to cover the third test contacts 31 with sacrificial material 90, thus resolving the issue of incomplete removal of sacrificial material 90 and improving the yield of semiconductor test structures 1. In this embodiment, there is no need to perform EMC injection molding within the mold cavity or to use special equipment to grind the EMC, simplifying the production process and improving production efficiency. This also reduces equipment utilization, packaging materials, and production costs.

[0095] In some embodiments, as Figure 6 As shown, before connecting the transfer shell structure 20 to one side of the package substrate 10, the process further includes: forming the transfer shell structure 20, which includes a top plate 23 and a side plate 24. A first groove 231 is formed on the side of the top plate 23 facing the package substrate 10. In this step, the formation position of the first groove 231 on the top plate 23 can be set according to the positional relationship between the transfer shell structure 20 and the transfer plate 30 after the transfer shell structure 20 is connected to the package substrate 10. The first groove 231 is formed on the top plate 23 above the connection contact 32 of the transfer plate 30 to avoid the connection wire 70 connecting the test chip 40 and the connection contact 32.

[0096] In some embodiments, as Figure 7As shown, step S2, forming an adapter board 30 on the side of at least one test chip 40 away from the packaging substrate 10, the adapter board 30 includes a third test contact 31, and can include: forming a first board portion 33 and a second board portion 34 on the side of at least one test chip 40 away from the packaging substrate 10, the first board portion 33 including a connecting contact 32, the second board portion 34 including the third test contact 31, and the first board portion 33 and the second board portion 34 are connected; wherein, in a direction perpendicular to the packaging substrate 10, the thickness of the first board portion 33 is less than the thickness of the second board portion 34.

[0097] In this step, the first plate portion 33 and the second plate portion 34 can be integrally formed to form a step-like shape, and the second plate portion 34 is higher than the first plate portion 33 in a direction perpendicular to the package substrate 10. In subsequent steps, the test chip 40 is connected to the connection contact 32 on the first plate portion 33 via a connecting wire 70, and the third test contact 31 is connected to the second test contact 22. With the above arrangement, since the thickness of the first plate portion 33 is less than the thickness of the second plate portion 34 in a direction perpendicular to the package substrate 10, a gap will exist between the first plate portion 33 and the top plate 23 when the second plate portion 34 is connected to the top plate 23 of the adapter shell structure 20, which helps to avoid the connecting wire 70 connecting the test chip 40 closest to the adapter board 30 and the adapter board 30.

[0098] In some embodiments, as Figure 17 As shown, before one side of the package substrate 10 is connected to the transfer shell structure 20 , the following steps are further included: S21 to S24 .

[0099] S21. Forming a transfer shell structure, where the transfer shell structure includes a top plate and side plates.

[0100] In this step, if Figure 8 As shown, the top plate 23 and the side plate 24 are connected, and the top plate 23 and the side plate 24 can be integrally formed. The formed transfer shell structure 20 can be a box-shaped structure. In subsequent steps, the transfer shell structure 20 is connected to the packaging substrate 10 to form a receiving chamber 50.

[0101] S22 . Form a protruding structure on a side of the top plate facing the package substrate, with the second test contact being located on the protruding structure.

[0102] In this step, if Figure 8 As shown, a protruding structure 232 is formed on the top plate 23, and the protruding structure 232 and the side plate 24 are located on the same side of the top plate 23. The second test contact 22 can be disposed on the surface of the protruding structure 232 parallel to the top plate 23, so as to facilitate subsequent connection between the second test contact 22 and the third test contact 31.

[0103] S23 , forming a second groove on a side of the second plate portion facing away from the packaging substrate.

[0104] In this step, if Figure 8 As shown, a second groove 341 can be formed on the side of the second plate portion 34 facing away from the package substrate 10 to cooperate with the transfer shell structure 20 formed in this embodiment. The third test contact 31 can be disposed at the bottom of the second groove 341 to facilitate connection between the third test contact 31 and the second test contact 22.

[0105] S24, positioning the protruding structure in the second groove.

[0106] In this step, if Figure 8 As shown, before connecting the transfer housing structure 20 to one side of the package substrate 10, the connection point between the transfer housing structure 20 and the package substrate 10 can be determined. The protrusion 232 on the transfer housing structure 20 is inserted into the second groove 341 on the transfer board 30 to determine the connection point between the transfer housing structure 20 and the package substrate 10, and the connection point is marked to facilitate connecting the transfer housing structure 20 to one side of the package substrate 10 in subsequent steps.

[0107] In the semiconductor test structure 1 prepared through the above steps, the second connection contact 32 on the protruding structure 232 is connected to the third test contact 31 in the second recess 341. The second plate portion 34 is located around the protruding structure 232, and the second plate portion 34 is connected to the top plate 23. For example, the second plate portion 34 can surround the protruding structure 232 and be connected to the top plate 23. For example, the second plate portion 34 can be bonded to the top plate 23 to improve the sealing at the connection between the second test contact 22 and the third test contact 31, thereby reducing interference from the external environment (e.g., moisture, pollution, etc.), and improving the accuracy of the test results.

[0108] In some embodiments, as Figure 18 As shown, before one side of the package substrate 10 is connected to the transfer shell structure 20 , the following steps are further included: S25 to S27 .

[0109] S25. Forming a transfer shell structure, where the transfer shell structure includes a top plate and side plates.

[0110] In this step, if Figure 9 As shown, the top plate 23 and the side plate 24 are connected, and the top plate 23 and the side plate 24 can be integrally formed. The formed transfer shell structure 20 can be a box-shaped structure. In subsequent steps, the transfer shell structure 20 is connected to the packaging substrate 10 to form a receiving chamber 50.

[0111] S26 , forming a protruding structure on a side of the top plate facing the packaging substrate.

[0112] In this step, if Figure 9As shown, a protrusion structure 232 is formed on the top plate 23 , and the protrusion structure 232 and the side plate 24 are located on the same side of the top plate 23 . For example, the protrusion structure 232 may be an annular protrusion, and the protrusion structure 232 may be disposed around the second test contact 22 .

[0113] S27, connecting the protruding structure to the first plate portion and surrounding the second plate portion.

[0114] In this step, if Figure 9 As shown, an adapter plate 30 compatible with the adapter shell structure 20 in this embodiment can be selected, for example, an adapter plate 30 including two first plate portions 33 and one second plate portion 34, and the second plate portion 34 is located between the two first plate portions 33. The raised structure 232 on the top plate 23 can be bonded to the first plate portion 33 and surround the second plate portion 34. Through the above arrangement, the second test contact 22 is easily connected to the third test contact 31. In addition, it is beneficial to improve the sealing performance of the connection between the second test contact 22 and the third test contact 31, to reduce interference from the external environment (such as water vapor, pollution, etc.), and to improve the accuracy of the test results.

[0115] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor test structure, characterized in that: include: Package substrate; An adapter shell structure is located on one side of the package substrate, and the adapter shell structure and the package substrate enclose a receiving chamber; The transfer shell structure includes a first test contact and a second test contact, wherein the first test contact is located on a side of the transfer shell structure facing away from the package substrate, and the second test contact is located on a side of the transfer shell structure facing the package substrate, and the first test contact is connected to the second test contact; as well as, The adapter board and at least one test chip are both located in the accommodating chamber; the at least one test chip is arranged between the packaging substrate and the adapter board; the adapter board includes a third test contact, and the third test contact is connected to the second test contact.

2. The semiconductor test structure according to claim 1, wherein: The third test contact is located on a side of the transfer board facing away from the packaging substrate.

3. The semiconductor test structure according to claim 1 or 2, characterized in that: comprising at least one chipset, each chipset comprising a plurality of the test chips; In the chipset: a plurality of the test chips are stacked in a direction perpendicular to the package substrate, and the plurality of the test chips are connected by connecting wires; the chipset is located between the package substrate and the adapter board, and the chipset is connected to the package substrate and the adapter board respectively; When there are multiple chipsets, the chipsets are spaced apart from each other along a direction parallel to the package substrate.

4. The semiconductor test structure according to claim 1, wherein: The transfer shell structure includes a top plate and side plates; the top plate is opposite to the packaging substrate, and the side plates connect the top plate and the packaging substrate.

5. The semiconductor test structure according to claim 4, wherein: The invention also includes an adhesive, wherein the adhesive is located between the side plate and the packaging substrate, and the adhesive is used to connect the side plate and the packaging substrate.

6. The semiconductor test structure according to claim 4, wherein: The top plate includes a first groove, the opening of the first groove faces the packaging substrate, and at least part of the connection wires connecting the test chip and the adapter board are located in the first groove.

7. The semiconductor test structure according to claim 4, wherein: The transfer board further includes a connection contact, a first plate portion, and a second plate portion, wherein the first plate portion and the second plate portion are connected, the connection contact is located on the first plate portion, and the third test contact is located on the second plate portion; wherein, in a direction perpendicular to the package substrate, a thickness of the first plate portion is less than a thickness of the second plate portion; The test chip is connected to the connection pad via a connection wire.

8. The semiconductor test structure according to claim 7, wherein: In a direction parallel to the packaging substrate, a size of the first plate portion is smaller than a size of the second plate portion.

9. The semiconductor test structure according to claim 7, wherein: The top plate includes a protruding structure, the protruding structure is located on a side of the top plate facing the package substrate, and the second test contact is located on the protruding structure; The second plate portion includes a second groove, the third test contact is located at the bottom of the second groove, and the protruding structure is located in the second groove.

10. The semiconductor test structure according to claim 7, wherein: The top plate includes a protruding structure, and the protruding structure is located on a side of the top plate facing the packaging substrate; The protruding structure is connected to the first plate portion and surrounds the second plate portion.

11. The semiconductor test structure according to any one of claims 7 to 10, characterized in that: In a direction perpendicular to the packaging substrate, a distance from the first plate portion to the transfer shell structure ranges from 150 μm to 300 μm.

12. A method for preparing a semiconductor test structure, characterized in that: include: forming at least one test chip on one side of the package substrate; forming an adapter plate on a side of the at least one test chip facing away from the package substrate, the adapter plate comprising a third test contact; A transfer shell structure is connected to one side of the package substrate, the transfer shell structure including a first test contact and a second test contact, the first test contact being located on a side of the transfer shell structure facing away from the package substrate, and the second test contact being located on a side of the transfer shell structure facing the package substrate; the transfer shell structure and the package substrate enclose a receiving chamber, the transfer board and the test chip being located in the receiving chamber; The third test contact is connected to the second test contact.

13. The method for preparing a semiconductor test structure according to claim 12, wherein: The transfer shell structure is connected to one side of the package substrate, including: forming an adhesive on the packaging substrate and / or the transfer shell structure; The transfer shell structure is fastened on the packaging substrate by the adhesive; The adhesive is allowed to cure.

14. The method for preparing a semiconductor test structure according to claim 12, wherein: Before connecting the transfer shell structure on one side of the package substrate, the method further includes: forming an adapter shell structure, the adapter shell structure including a top plate and side plates; A first groove is formed on a side of the top plate facing the packaging substrate.

15. The method for preparing a semiconductor test structure according to claim 12, wherein: The step of forming a transfer board on a side of the at least one test chip facing away from the packaging substrate comprises: A first board portion and a second board portion are formed on a side of the at least one test chip facing away from the packaging substrate, wherein the first board portion includes a connection contact, the second board portion includes a third test contact, and the first board portion and the second board portion are connected; wherein, in a direction perpendicular to the packaging substrate, the thickness of the first board portion is less than the thickness of the second board portion.

16. The method for preparing a semiconductor test structure according to claim 15, wherein: Before connecting the transfer shell structure on one side of the package substrate, the method further includes: forming an adapter shell structure, the adapter shell structure including a top plate and side plates; forming a protruding structure on a side of the top plate facing the package substrate, wherein the second test contact is located on the protruding structure; forming a second groove on a side of the second plate portion facing away from the packaging substrate; The protruding structure is located in the second groove.

17. The method for preparing a semiconductor test structure according to claim 15, wherein: Before connecting the transfer shell structure on one side of the package substrate, the method further includes: forming an adapter shell structure, the adapter shell structure including a top plate and side plates; forming a protruding structure on a side of the top plate facing the packaging substrate; The protruding structure is connected to the first plate portion and surrounds the second plate portion.

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