Chip testing method, testing device and storage medium

Abstract

The invention provides a chip testing method, a testing device and a storage medium. The test method comprises the following steps: providing a chip to be tested; applying different stresses to the to-be-tested chip, and detecting electrical performance parameters of the to-be-tested chip under different stresses; and determining an electrical failure critical point of the to-be-tested chip based on the electrical performance parameters. Therefore, the electrical property evolution process of the chip to be tested under the action of the force field is accurately recorded by the electrical property parameters, and then the tested electrical property failure critical point can accurately reflect whether the chip to be tested has electrical property failure or not, so that the accuracy of the test result of the electrical property failure critical point can be further improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a chip testing method, a chip testing device, and a storage medium. Background Art

[0002] In the performance evaluation of packaged chips, the traditional three-point bend test can only obtain deformation data when the packaged chip is physically broken, and cannot record the evolution process of the chip's electrical performance under the action of the force field in real time, making it difficult to accurately determine the critical point of electrical failure.

[0003] Currently, the industry generally regards the physical fracture point as the critical point of electrical failure, which leads to deviations in the judgment of the critical state of electrical failure and cannot meet the needs of accurate testing of packaged chip performance in the fall and drop resistance evaluation of mobile electronic devices. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a chip testing method, a testing device, and a storage medium to further improve the accuracy of test results.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] An embodiment of the present disclosure provides a chip testing method, comprising: providing a chip to be tested; applying different stresses to the chip to be tested, and detecting electrical performance parameters of the chip to be tested under different stresses; and determining an electrical failure critical point of the chip to be tested based on the electrical performance parameters.

[0007] In the above solution, before applying different stresses to the chip to be tested, the testing method further includes: electrically connecting the chip to be tested to a host computer via a wire.

[0008] In the above solution, the testing method further includes: in the process of detecting the electrical performance parameters of the chip to be tested, detecting the deformation parameters of the chip to be tested under different stresses; and determining the strain performance of the chip to be tested based on the deformation parameters.

[0009] In the above scheme, the chip to be tested includes: a solder ball; the wire includes: a test probe and a connecting wire; connecting the chip to be tested to the host computer through the wire includes: melting the solder ball; inserting the test probe into the melted solder ball and curing it; connecting the test probe inserted into the solder ball to the host computer through the connecting wire.

[0010] In the above scheme, the electrical performance parameters include at least one of voltage, current, power consumption, timing parameters, operating frequency, resistance, capacitance and inductance; the deformation parameters include at least one of bending displacement, surface strain distribution, deflection and elastic modulus.

[0011] An embodiment of the present disclosure also provides a testing device, which includes: a first testing unit, a first detection unit and a data processing unit; wherein the first testing unit is configured to apply different stresses to the chip to be tested; the first detection unit is connected to the chip to be tested and is configured to detect the electrical performance parameters of the chip to be tested under different stresses; the data processing unit is connected to the first detection unit and is configured to determine the critical point of electrical failure of the chip to be tested based on the electrical performance parameters.

[0012] The above scheme also includes: a second detection unit; the second detection unit is configured to detect the deformation parameters of the chip to be tested under different stresses; the data processing unit is connected to the second detection unit and is also configured to determine the strain performance of the chip to be tested based on the deformation parameters.

[0013] In the above solution, the first detection unit includes: a wire and a host computer; wherein the wire includes a connecting wire and a test probe; the test probe is inserted into the solder ball of the chip to be tested and connected to the host computer through the connecting wire.

[0014] In the above scheme, the first test unit includes: the first test unit includes: a first support column, a second support column, a pressure head assembly and a first sensor; wherein, the first support column and the second support column are configured to support the chip to be tested; the pressure head assembly is configured to apply stress to the chip to be tested; the first sensor is integrated in the pressure head assembly, and is configured to detect the stress applied to the chip to be tested.

[0015] An embodiment of the present disclosure further provides a computer-readable storage medium having a computer program or instruction stored thereon, which, when executed, enables a computer to execute the test method according to any one of the above-mentioned solutions.

[0016] The embodiment of the present disclosure provides a chip testing method, comprising: providing a chip to be tested; applying different stresses to the chip to be tested, and detecting the electrical performance parameters of the chip to be tested under different stresses; and determining the electrical failure critical point of the chip to be tested based on the electrical performance parameters. In other words, the electrical failure critical point tested by the embodiment of the present disclosure is highly correlated with the electrical performance parameters of the chip to be tested. In this way, the electrical performance parameters accurately record the electrical performance evolution process of the chip to be tested under the action of the force field, and furthermore, the electrical failure critical point tested can accurately reflect whether there is electrical failure in the chip to be tested. Therefore, compared with the test method in the prior art that uses the fracture point as the electrical failure critical point, the embodiment of the present disclosure can further improve the accuracy of the test results of the electrical failure critical point. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the test method provided in the embodiment of the present disclosure Figure 1 ;

[0018] Figure 2 A schematic diagram of the structure of the test device provided in the embodiment of the present disclosure Figure 1 ;

[0019] Figure 3 A schematic structural diagram of the stress conditions of a chip under test provided by an embodiment of the present disclosure;

[0020] Figure 4 Schematic diagram of the test method provided in the embodiment of the present disclosure Figure 2 ;

[0021] Figure 5 A schematic diagram of the structure of the test device provided in the embodiment of the present disclosure Figure 2 ;

[0022] Figure 6 A schematic diagram of the structure of the test device provided in the embodiment of the present disclosure Figure 3 ;

[0023] Figure 7 A schematic diagram of the structure of the test device provided in the embodiment of the present disclosure Figure 4 . DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0025] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0028] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, test method, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, test method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, test method, article, or device comprising the element.

[0029] It should be noted that in the prior art, the breaking point of the chip is usually used as the critical point of electrical failure. If the breaking point directly causes the conductive path to be disconnected or the adjacent circuit to be short-circuited, the breaking point is directly correlated with the electrical failure, and the breaking point of the chip can be used as the critical point of electrical failure. However, whether the chip is broken is judged by whether the external packaging structure (for example, the potting compound or the PCB) is broken. In the case where the die inside the packaging structure is microscopically broken due to stress concentration or mechanical impact before the tough packaging structure, that is, the external packaging structure has not broken, the internal die has abnormal resistance or short circuit. The electrical failure of the chip is earlier than the break. Therefore, using the breaking point as the critical point of electrical failure will reduce the accuracy of the test.

[0030] Figure 1 is a flow chart of an optional testing method provided by an embodiment of the present disclosure, Figure 2 This is a schematic diagram of the structure of an optional testing device 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 2 The test apparatus 100 shown can be used to implement Figure 1 The test method shown in Figure 1 The steps shown are explained.

[0031] S101. Provide a chip to be tested.

[0032] S102 , applying different stresses to the chip to be tested, and detecting electrical performance parameters of the chip to be tested under the different stresses.

[0033] Figure 3 This is a schematic diagram of an optional chip under test 200 provided in an embodiment of the present disclosure. It should be noted that, Figure 3The packaging method of the chip to be tested 200 shown in the example is a ball grid array package (BGA). The packaging method of the chip to be tested 200 can also be any one of the packaging methods such as a land grid array package (LGA) and a pin grid array package (PGA), which is not limited here.

[0034] It should also be noted that Figure 3 The stress application method of the chip under test 200 is a three-point bending test, namely: Figure 2 The testing device 100 can apply vertical upward supporting forces F1 and F2 and vertical downward pressure F3 to the chip under test 200 , so that the chip under test 200 generates three-point bending deformation. Figure 2 The testing device 100 in the embodiment may also apply stress to the chip under test 200 in other ways, which are not limited here.

[0035] In the embodiments of the present disclosure, reference Figure 2 , the testing device 100 can apply different stresses to the chip under test. For example, Figure 3 As shown, the testing apparatus 100 can adjust the stress applied to the chip under test 200 by gradually increasing the pressure F3 .

[0036] In the embodiments of the present disclosure, reference Figure 2 Testing device 100 can detect the electrical performance parameters of the chip under test under different stresses. For example, solder balls 201 of chip under test 200 can be electrically connected to testing device 100 via wires. Testing device 100 can perform electrical performance testing on the chip under test and collect electrical performance parameters of chip under test 200. Electrical performance parameters may include at least one of voltage, current, power consumption, timing parameters, operating frequency, resistance, capacitance, and inductance.

[0037] S103 : Determine the electrical failure critical point of the chip to be tested based on the electrical performance parameters.

[0038] In the embodiments of the present disclosure, reference Figure 2 The electrical failure threshold is the critical state where a chip transitions from normal operation to functional failure under specific conditions (e.g., voltage, temperature, and frequency). For example, the testing apparatus 100 can monitor the point at which electrical performance parameters such as leakage current suddenly increase or decrease by varying the stress on the chip under test 200. If the point at which this occurs exceeds the design tolerance for the chip under test, the chip deformation at the point at which this occurs is considered the electrical failure threshold for the chip under test.

[0039] It can be understood that the embodiment of the present disclosure detects the electrical performance parameters of the chip to be tested under different stresses, and determines the electrical failure critical point of the chip to be tested based on the electrical performance parameters. In other words, the electrical failure critical point tested by the embodiment of the present disclosure is highly correlated with the electrical performance parameters of the chip to be tested. In this way, the electrical performance parameters accurately record the electrical performance evolution process of the chip to be tested under the action of the force field, and furthermore, the electrical failure critical point tested can accurately reflect whether the chip to be tested has electrical failure. Therefore, compared with the test method of using the fracture point as the electrical failure critical point in the prior art, the embodiment of the present disclosure can further improve the accuracy of the test results of the electrical failure critical point.

[0040] Figure 4 This is a flow chart of another optional testing method provided by the embodiment of the present disclosure, which is combined with Figure 4 The steps shown are explained.

[0041] S201 . In the process of detecting electrical performance parameters of the chip to be tested, simultaneously detecting deformation parameters of the chip to be tested under different stresses.

[0042] Figure 5 and Figure 6 is a schematic structural diagram of an optional testing device 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 5 and Figure 6 The first support column 111 and the second support column 112 provided by the test device 100 are used to apply the following force to the chip under test 200: Figure 3 The pressure head assembly 113 is used to apply the support forces F1 and F2 to the chip under test 200. Figure 3 The pressure F3 is shown. A force sensor may be integrated on the press head assembly 113 to detect and monitor the change in the stress value applied by the press head assembly 113 in real time.

[0043] In the embodiments of the present disclosure, reference Figure 5 , the testing device 100 can detect the deformation parameters of the chip under test 200 under different stresses. For example, the testing device 100 can apply stress to the chip under test 200 by controlling the pressure head assembly 113 to move vertically. At least one stress sensor 114 is provided on the chip under test 200. The stress sensor 114 can be a laser displacement meter or a strain gauge. When the pressure head assembly 113 applies stress to the chip under test 200, the stress sensor 114 can collect the deformation parameters of the chip under test 200. The deformation parameters may include at least one of bending displacement (the distance the pressure head assembly presses down), surface strain distribution (strain distribution on the surface of the chip under test), deflection (displacement of the midpoint of the chip under test) and elastic modulus.

[0044] S202 : Determine the strain performance of the chip to be tested based on the deformation parameters.

[0045] In the embodiments of the present disclosure, reference Figure 2 The testing device 100 can determine the strain performance of the chip under test based on the deformation parameters. For example, the testing device 100 can establish a stress-strain curve of the chip under test and then determine the fracture strength and other indicators of the chip under test based on the stress-strain curve of the chip under test.

[0046] It is understood that, while testing the electrical performance parameters of the chip under test, the disclosed embodiments simultaneously test the deformation parameters of the chip under test under different stresses. In other words, the disclosed embodiments can simultaneously test the strain performance and electrical failure threshold of the chip under test. Thus, during the stress application process, the disclosed embodiments can simultaneously test the performance of multiple chips under test, thereby further improving testing efficiency.

[0047] In some embodiments of the present disclosure, before applying different stresses to the chip to be tested, a testing method may be implemented through S301 .

[0048] S301, electrically connecting the chip to be tested to a host computer through wires.

[0049] In the embodiments of the present disclosure, reference Figure 4 The testing device 100 can electrically connect the chip under test 200 to the host computer through the wire 120.

[0050] It is understandable that the disclosed embodiment connects the chip under test and the host computer via wires. Thus, when stress is applied to the chip under test, the wires do not interfere with the stress changes in the chip under test. The electrical performance parameters and deformation parameters can accurately record the evolution of the electrical and strain properties of the chip under test under the force field, thereby improving the reliability and accuracy of the test results.

[0051] It should also be noted that the above-mentioned method of electrically connecting the chip under test to the host computer via wires is for illustrative purposes only. Alternatively, the chip under test may be connected using a flexible printed circuit board or other method. In other words, any implementation method that can connect the chip under test without interfering with the stress of the chip under test is applicable and is not limited here.

[0052] In some embodiments of the present disclosure, S201 may also be implemented through S401 to S403 , which will be described in conjunction with each step.

[0053] S401, melting the solder balls.

[0054] S402: inserting a test probe into the melted solder ball and performing solidification.

[0055] In the embodiments of the present disclosure, reference Figure 5The test device 100 can be equipped with a reflow oven (or laser) and an automatic pin insertion device. The test device 100 can use the reflow oven (or laser) to melt the solder balls 201 of the chip under test 200. When the solder balls 201 are in a melted state, the test probe 121 is accurately inserted into the solder balls 201 using a tool such as an automatic pin insertion device. The test device 100 then solidifies the solder balls 201 by lowering the temperature, causing them to resolidify and firmly fix the test probe 121 to the chip under test 200.

[0056] S403 , electrically connecting the test probe inserted into the solder ball to the host computer via a connecting wire.

[0057] In the embodiments of the present disclosure, reference Figure 5 , the testing device 100 can electrically connect the test probe 121 inserted into the solder ball 201 to the host computer 130 through the connecting wire 122. The connecting wire 122 can be connected to the test probe 121 by welding, crimping, etc. The connecting wire 122 can be connected to the pin 131 of the host computer 130 through the wire handle 123. The test probe 121 can be a copper pillar. Thus, the embodiment of the present disclosure can connect the chip to be tested 200 to the host computer 130 through the test probe 121, the connecting wire 122 and the wire handle 123, and then, the chip to be tested 200 can be tested through the host computer 130.

[0058] It should be noted that Figure 6 Both ends of the connecting wire 122 are provided with a wire handle 123. Thus, the embodiment of the present disclosure can connect the connecting wire 122 to the test probe 121 via the wire handle 123 after the test probe 121 is inserted into the solder ball 201. Thus, the present disclosure can prevent the connecting wire 122 from interfering with the insertion of the test probe 121 into the solder ball 201.

[0059] In some embodiments of the present disclosure, reference Figure 2 The testing device 100 includes a first testing unit 10, a first detection unit 20, and a data processing unit 30. The first testing unit 10 is configured to apply different stresses to the chip under test. When testing the critical point of electrical failure of the chip under test, the first testing unit 10 can simulate the stress conditions experienced by the chip under test in scenarios such as a drop, applying stress with controllable magnitude and direction to the chip under test, thereby simulating performance changes of the chip under test in scenarios such as a drop.

[0060] In the embodiments of the present disclosure, reference Figure 2The first detection unit 20 is connected to the chip under test and is configured to detect the electrical performance parameters of the chip under test 200 under different stresses. For example, the first detection unit 20 can be connected to the chip under test via a wire. When the first test unit 10 applies different levels of stress to the chip under test, the chip under test will undergo corresponding deformations, such as stretching, compression, bending, etc. The first detection unit 20 can then use various detection methods to accurately measure the changes in the electrical performance of the chip under test under different stresses and obtain specific parameters of the electrical performance, such as current and power.

[0061] Specifically, the first detection unit 20 uses consistent testing methods under different stresses. For example, the first detection unit 20 can evaluate the power consumption characteristics of the chip under test by measuring the current drawn by the chip under test in different operating states, thereby determining whether the chip under test is operating normally and whether there are abnormal conditions such as leakage. For another example, the first detection unit 20 can detect the voltage of the chip's input pins (solder balls) at different input signal levels, as well as the output voltage of the output pins (solder balls) under various operating conditions, thereby determining whether the logical function of the chip under test is normal.

[0062] In the embodiments of the present disclosure, reference Figure 2 , the data processing unit 30 is connected to the first detection unit 20, and is configured to determine the electrical failure critical point of the chip to be tested based on the electrical performance parameters. The data processing unit 30 can be the host computer 130 shown in the above embodiment. The data processing unit 30 can receive the electrical performance parameters detected by the first detection unit 20. For example, the data processing unit 30 can receive the electrical performance parameters detected by the first detection unit 20. Then, the data processing unit 30 uses specific algorithms and models to analyze and process the electrical performance parameters, combines the stress data (from the above-mentioned first sensor), establishes a correlation curve between the electrical performance parameters and stress changes, and calculates the electrical mutation point of the chip to be tested under the action of the force field.

[0063] It will be appreciated that in the disclosed embodiment, the first detection unit 20 detects the electrical performance parameters of the chip under test under different stresses, and the data processing unit 30 determines the critical electrical failure point of the chip under test based on the electrical performance parameters. Thus, the electrical performance parameters accurately record the evolution of the electrical performance of the chip under test under the influence of the force field. Furthermore, the detected critical electrical failure point can accurately reflect whether the chip under test has experienced electrical failure, thereby further improving the accuracy of the test results for the critical electrical failure point.

[0064] In some embodiments of the present disclosure, reference Figure 5The first test unit includes a press head assembly 113, a first sensor 115, a first support column 111, and a second support column 112. The first sensor 115 is integrated with the press head assembly 113 and is configured to detect stress applied to the chip under test 200. The first sensor 115 can be a high-precision force sensor. The tips of the press head assembly 113, the first support column 111, and the second support column 112 are typically arc-shaped to prevent stress concentration from damaging the chip under test.

[0065] During testing, chip 200 is placed on first and second support posts 111, 112. These support posts 111, 112 serve as support points, providing stable support for chip 200 and ensuring it remains relatively fixed when subjected to stress. The indenter assembly 113 acts as a force application point, applying varying stresses to chip 200.

[0066] In some embodiments of the present disclosure, reference Figure 5 The first detection unit includes a wire 120 and a host computer 130. The wire 120 includes a connecting wire 122 and a test probe 121. The test probe 121 is inserted into the solder ball 201 of the chip under test 200 and connected to the host computer 130 via the connecting wire 122. Thus, in the embodiment of the present disclosure, when stress is applied to the chip under test 200, the wire 120 does not interfere with the stress changes in the chip under test 200, thereby improving the reliability and accuracy of the test results.

[0067] Figure 7 This is a schematic structural diagram of another optional testing device 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 7 The first test unit 10 and the first detection unit 20 can refer to Figure 2 The structure shown in FIG2 is understood for convenience and will not be described in detail here.

[0068] In some embodiments of the present disclosure, reference Figure 7 The testing device 100 further includes a second detection unit 40. The second detection unit 40 is configured to detect deformation parameters of the chip under test 200 under different stresses. When the first testing unit 10 applies different levels of stress to the chip under test, the chip under test will undergo corresponding deformations, such as stretching, compression, and bending. The second detection unit 40 can accurately measure the deformation of the chip under test under different stresses through various detection methods, such as optical measurement and stress sensors, and obtain deformation parameters such as displacement and strain rate.

[0069] In the embodiments of the present disclosure, reference Figure 7, the data processing unit 30 is connected to the second detection unit 40, and is also configured to determine the strain performance of the chip to be tested based on the deformation parameters. The data processing unit 30 can receive the deformation parameters detected by the second detection unit 40. For example, the data processing unit 30 can use specific algorithms and models to analyze and process the deformation parameters, and combine the stress data (from the above-mentioned first sensor) to calculate the strain performance indicators such as the strain coefficient and elastic modulus of the chip, and evaluate the mechanical properties and reliability of the chip to be tested under different stress conditions. In this way, in the process of applying stress, the embodiment of the present disclosure can simultaneously test the performance of multiple chips to be tested, thereby further improving the test efficiency.

[0070] Based on the above embodiments, the present disclosure further provides a computer-readable storage medium, which stores one or more programs that can be executed by one or more processors to implement the following. Figure 1 The corresponding embodiments provide steps of the testing method.

[0071] It should be noted that the above-mentioned computer-readable storage medium can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface storage, an optical disc, or a compact disc read-only memory (CD-ROM); it can also be various electronic devices that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0072] An embodiment of the present disclosure provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps in the method corresponding to the above-mentioned testing device are implemented.

[0073] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, test method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, test method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, test method, article, or apparatus comprising the element.

[0074] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The test methods disclosed in the several test method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new test method embodiments. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several test method or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new test method embodiments or device embodiments.

[0075] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A chip testing method, characterized in that: include: Provide the chip to be tested; Applying different stresses to the chip to be tested, and detecting electrical performance parameters of the chip to be tested under the different stresses; Based on the electrical performance parameters, the electrical failure critical point of the chip to be tested is determined.

2. The testing method according to claim 1, wherein: Before applying different stresses to the chip to be tested, the testing method further includes: The chip to be tested is electrically connected to a host computer via wires.

3. The testing method according to claim 1, wherein: The test method further comprises: In the process of detecting the electrical performance parameters of the chip to be tested, detecting the deformation parameters of the chip to be tested under different stresses; Based on the deformation parameters, the strain performance of the chip to be tested is determined.

4. The testing method according to claim 2, wherein: The chip to be tested includes: solder balls; the wires include: test probes and connecting wires; Connecting the chip to be tested to the host computer through the wire includes: melting the solder balls; inserting a test probe into the melted solder ball and performing solidification; The test probe inserted into the solder ball is connected to the host computer through the connecting line.

5. The testing method according to claim 3, wherein: The electrical performance parameters include at least one of voltage, current, power consumption, timing parameters, operating frequency, resistance, capacitance and inductance; The deformation parameter includes at least one of bending displacement, surface strain distribution, deflection and elastic modulus.

6. A chip testing device, characterized in that: include: A first testing unit, a first detection unit and a data processing unit; wherein, The first testing unit is configured to apply different stresses to the chip under test; The first detection unit is connected to the chip to be tested and is configured to detect electrical performance parameters of the chip to be tested under different stresses; The data processing unit is connected to the first detection unit and is configured to determine the electrical failure critical point of the chip to be tested based on the electrical performance parameters.

7. The testing device according to claim 6, characterized in that Also includes: a second detection unit; The second detection unit is configured to detect deformation parameters of the chip under test under different stresses; The data processing unit is connected to the second detection unit and is further configured to determine the strain performance of the chip to be tested based on the deformation parameters.

8. The testing device according to claim 6, characterized in that The first detection unit includes: a wire and a host computer; wherein the wire includes a connecting wire and a test probe; The test probe is inserted into the solder ball of the chip to be tested and is connected to the host computer through the connecting line.

9. The testing device according to claim 7, characterized in that: The first test unit includes: a first support column, a second support column, a pressure head assembly and a first sensor; wherein, The first supporting column and the second supporting column are configured to support the chip to be tested; The pressure head assembly is configured to apply stress to the chip to be tested; The first sensor is integrated in the pressure head assembly and is configured to detect stress applied to the chip to be tested.

10. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instructions are executed, the computer is caused to perform the testing method according to any one of claims 1 to 5.

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