Chip testing method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a chip testing method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and can ensure the shipment quality and yield of chips during chip testing. The chip testing method comprises the following steps: detecting the current temperature of a to-be-tested chip; according to the current temperature of the to-be-tested chip and a pre-established corresponding relation between the chip temperature and the performance test point for the to-be-tested function of the to-be-tested chip, determining an actual test point for testing the to-be-tested function of the to-be-tested chip at the current temperature; and testing the to-be-tested function of the to-be-tested chip at the current temperature based on the test voltage and the working frequency corresponding to the actual test point. The method and the device are suitable for chip functional test scenes.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a chip testing method, device, electronic equipment and storage medium. Background Art

[0002] Testing logic chips requires running various functions at different voltages and frequencies to ensure the chip operates properly under all conditions. Each voltage / frequency is called a test point. Furthermore, as the chip's operating current changes in different operating modes, its temperature also changes accordingly.

[0003] Current chip testing solutions can only account for extreme temperature conditions, setting relatively loose test points to ensure product yield. However, loose test points can lead to reduced chip quality. Therefore, a testing method that can simultaneously ensure chip quality and yield is urgently needed. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a chip testing method, device, electronic device, and storage medium, which can simultaneously ensure chip shipment quality and yield during chip testing.

[0005] In a first aspect, an embodiment of the present invention provides a chip testing method, comprising: detecting the current temperature of the chip to be tested; determining an actual test point for performing a test of the function to be tested on the chip to be tested at the current temperature based on the current temperature of the chip to be tested and a correspondence between chip temperature and performance test points pre-established for the function to be tested of the chip to be tested; and performing a test of the function to be tested on the chip to be tested at the current temperature based on a test voltage and an operating frequency corresponding to the actual test point.

[0006] Optionally, before detecting the current temperature of the chip to be tested, the method also includes: determining performance test points of the chipset to be tested at at least three discrete temperature points; wherein, the chipset to be tested includes multiple chips with different process parameters and / or different process angles; the chip to be tested is a single chip in the chipset to be tested or a combination of more than two single chips; the test parameters corresponding to the performance test points include test voltage and test operating frequency; and fitting the performance test points corresponding to the at least three discrete temperature points to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the performance test points.

[0007] Optionally, determining performance test points of the chipset to be tested at at least three discrete temperature points includes: Determine the distribution of the working critical points of the function to be tested of the chip to be tested in the chip group to be tested at at least three discrete temperature points; the electrical parameters of the working critical points include the working critical voltage and the working critical frequency; based on the distribution of the working critical points of the function to be tested, determine the performance test points for testing the function to be tested of the chip to be tested.

[0008] Optionally, determining the performance test points for testing the function to be tested of the chip to be tested based on the distribution of working critical points of the function to be tested includes: determining the performance test points for testing the function to be tested of the chip to be tested according to the 3σ principle based on the distribution of working critical points of the function to be tested.

[0009] Optionally, the performance test points corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the performance test points, including: for a given test operating frequency, the test voltages corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the test voltage under the given test operating frequency.

[0010] Optionally, the performance test points corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the performance test points, including: for a given test voltage, the test operating frequency corresponding to the at least three discrete temperature points is fitted to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the test operating frequency under the given test voltage.

[0011] Optionally, the actual test point for performing the function to be tested test on the chip to be tested at the current temperature is determined based on the current temperature of the chip to be tested and the correspondence between the chip temperature and the performance test point pre-established for the function to be tested of the chip to be tested, including: for a given test operating frequency, the actual test point for performing the function to be tested test on the chip to be tested at the current temperature is determined based on the current temperature of the chip to be tested and a performance test point fitting curve reflecting the correspondence between the chip temperature and the test voltage; wherein, the test of the function to be tested on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point includes: testing the function to be tested on the chip to be tested at the current temperature based on the test voltage corresponding to the actual test point and the given test operating frequency.

[0012] Optionally, the method of determining the actual test point for performing the function to be tested test on the chip to be tested at the current temperature based on the current temperature of the chip to be tested and the correspondence between the chip temperature and the performance test point pre-established for the function to be tested of the chip to be tested includes: for a given test voltage, determining the actual test point for performing the function to be tested test on the chip to be tested at the current temperature based on the current temperature of the chip to be tested and a performance test point fitting curve reflecting the correspondence between the chip temperature and the test operating frequency; wherein, the method of performing the function to be tested on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point includes: performing the function to be tested on the chip to be tested at the current temperature based on the test operating frequency corresponding to the actual test point and the given test voltage.

[0013] In a second aspect, the present invention also provides an embodiment of a chip testing device, comprising: a temperature detection module for detecting the current temperature of the chip to be tested; a first determination module for determining the actual test point for performing the function to be tested test on the chip to be tested at the current temperature based on the current temperature of the chip to be tested and the correspondence between the chip temperature and the performance test point pre-established for the function to be tested of the chip to be tested; and a function test module for performing the function to be tested test on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point.

[0014] Optionally, the chip testing device also includes: a second determination module, used to determine the performance test points of the chipset to be tested at at least three discrete temperature points before detecting the current temperature of the chip to be tested; wherein, the chipset to be tested includes multiple chips with different process parameters and / or different process angles; the chip to be tested is a single chip in the chipset to be tested or a combination of more than two single chips; the test parameters corresponding to the performance test points include test voltage and test operating frequency; a data fitting module, used to fit the performance test points corresponding to the at least three discrete temperature points to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the performance test points.

[0015] Optionally, the second determination module includes: a first determination sub-module, used to determine the distribution of the working critical points of the function to be tested of the chip to be tested in the chip group to be tested at at least three discrete temperature points; the electrical parameters of the working critical points include the working critical voltage and the working critical frequency; a second determination sub-module, used to determine the performance test points for testing the function to be tested of the chip to be tested based on the distribution of the working critical points of the function to be tested.

[0016] Optionally, the second determining submodule is specifically configured to determine a performance test point for testing the function to be tested of the chip to be tested based on the distribution of working critical points of the function to be tested and according to the 3σ principle.

[0017] Optionally, the data fitting module is specifically used to fit the test voltages corresponding to the at least three discrete temperature points for a given test operating frequency, and obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test voltage at the given test operating frequency.

[0018] Optionally, the data fitting module is also used to fit the test operating frequencies corresponding to the at least three discrete temperature points for a given test voltage, so as to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test operating frequency under the given test voltage.

[0019] Optionally, the first determination module is specifically used to determine, for a given test operating frequency, the actual test point for performing the function test on the chip to be tested at the current temperature according to the current temperature of the chip to be tested and a performance test point fitting curve reflecting the correspondence between the chip temperature and the test voltage; wherein the functional test module is specifically used to perform the function test on the chip to be tested at the current temperature based on the test voltage corresponding to the actual test point and the given test operating frequency.

[0020] Optionally, the first determination module is also used to determine, for a given test voltage, the actual test point for performing the function test on the chip to be tested at the current temperature according to the current temperature of the chip to be tested and a performance test point fitting curve reflecting the correspondence between the chip temperature and the test operating frequency; wherein the functional test module is specifically used to perform the function test on the chip to be tested at the current temperature based on the test operating frequency corresponding to the actual test point and the given test voltage.

[0021] In a third aspect, an embodiment of the present invention also provides an electronic device, comprising: a processor and a memory, wherein the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute any chip testing method described in the first aspect.

[0022] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement any chip testing method described in the first aspect.

[0023] The present invention provides a chip testing method, device, electronic device, and storage medium. When performing each functional test on a chip under test, the current temperature of the chip under test is detected. Based on a pre-established correspondence between temperature and performance test points, the actual test point at which the chip under test performs the functional test at the current temperature is obtained. Based on the test voltage and operating frequency corresponding to the actual test point, the functional test of the chip under test is performed at the current temperature. This allows the test point for the functional test to be dynamically adjusted based on the current temperature of the chip under test, making the test conditions for the chip test more stringent and thereby ensuring both the quality and yield of the chip shipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic flow chart of a chip testing method according to one or more embodiments of the present invention; Figure 2 A schematic flow chart of a chip testing method according to one or more embodiments of the present invention; Figure 3 A Shmoo image obtained in the chip testing method provided by one or more embodiments of the present invention; Figure 4 This is an image of the distribution of critical working points of a chip at a temperature of -5°C during a chip testing process provided by one embodiment of the present invention; Figure 5 An image showing the corresponding relationship between chip temperature and performance test points during chip testing provided by one or more embodiments of the present invention; Figure 6 An image showing the corresponding relationship between chip temperature and performance test points during chip testing provided by one or more embodiments of the present invention; Figure 7 An image showing the corresponding relationship between chip temperature and performance test points during chip testing provided by one or more embodiments of the present invention; Figure 8 An image showing the corresponding relationship between chip temperature and performance test points during chip testing provided by one or more embodiments of the present invention; Figure 9 A performance test point fitting curve showing the corresponding relationship between chip temperature and test voltage during chip testing provided by one embodiment of the present invention; Figure 10A schematic structural diagram of a chip testing device provided by one or more embodiments of the present invention; Figure 11 A schematic block diagram of an electronic device architecture provided for one or more embodiments of the present invention. DETAILED DESCRIPTION

[0026] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0028] Test point: refers to the chip running various functions under different test operating voltages / test operating frequencies. Each set of test operating voltages / test operating frequencies is called a test point.

[0029] Tester: Used to test logic chips, it is composed of electronic systems that generate signals, establish appropriate test patterns, set them up correctly in sequence, and then use them to drive the chip itself and capture the chip's output feedback, either recording it or comparing it with the expected feedback in the tester to determine whether it is good or bad.

[0030] Testing logic chips requires running various functions at different voltages and frequencies to ensure proper function under all conditions. As the operating current changes in different operating modes, the chip's temperature also changes, known as the chip's real-time temperature. The chip's real-time temperature changes when testing different functions as the chip heats up or dissipates heat. Current chip testing solutions can only account for extreme temperatures, ensuring product yield by setting relatively relaxed test points. However, these relaxed test points can lead to reduced chip quality before shipment.

[0031] In order to solve the above technical problems, the embodiment of the present invention provides a chip testing method. Figure 1 As shown, Figure 1 This is a flow chart of a chip testing method provided in one or more embodiments of the present invention. The method can be applied to electronic devices such as test platforms and test terminals, and includes the following steps: S110, detecting the current temperature of the chip to be tested; In this step, before performing a functional test on the chip under test, a chip temperature detection module is set up. For example, a temperature sensor is used to collect the chip's real-time temperature. This module is used to detect the current temperature of the chip under test before each functional test. Therefore, during the functional test of the chip under test, the tester receives the chip temperature collected in real time by the temperature sensor and reads the current temperature of the chip under test.

[0032] S120, determining an actual test point for performing the function under test on the chip under test at the current temperature based on the current temperature of the chip under test and a pre-established correspondence between chip temperature and performance test points for the function under test of the chip under test; In this step, after the tester reads the current temperature of the chip to be tested, it uses the pre-established correspondence between the chip temperature and the performance test point according to the functional test item to be performed to obtain the actual test point for performing the functional test at the current temperature, where the actual test point includes the test voltage and operating frequency.

[0033] S130: Based on the test voltage and operating frequency corresponding to the actual test point, test the function to be tested on the chip to be tested at the current temperature.

[0034] In this step, the function to be tested of the chip to be tested is tested based on the test voltage and operating frequency corresponding to the actual test point at the current temperature; when performing the next functional test, the current temperature of the chip to be tested is detected again, and the actual test point of the next functional test is determined until all functional tests are completed and chips that do not meet the performance requirements are screened out.

[0035] The chip testing method provided in this embodiment detects the current temperature of the chip under test when performing each functional test on the chip under test. Based on the pre-established correspondence between temperature and performance test points, the actual test point at which the chip under test performs the functional test at the current temperature is obtained. Based on the test voltage and operating frequency corresponding to the actual test point, the chip under test is tested at the current temperature. In this way, when performing a functional test on the chip under test, compared with the prior art method that can only perform chip testing at fixed test points, the present invention dynamically adjusts the test points of the functional test according to the current temperature of the chip under test, making the test conditions of the chip test more stringent and able to simultaneously ensure the quality and yield of the chip shipment.

[0036] Existing chip testing methods can only test chips at fixed test points. This only allows for testing chips at extreme temperatures, resulting in relatively loose test points and a reduction in the quality of shipped chips. The chip testing method provided in this embodiment redefines how test points are generated for chip testing, enabling dynamic adjustment of test points at different temperatures to meet the more stringent test point requirements under current conditions. This avoids missed tests due to overly loose test conditions and allows for the early screening of chips that do not meet performance standards.

[0037] Optionally, in some embodiments, before detecting the current temperature of the chip to be tested, the method further includes: Determine performance test points of the chipset to be tested at at least three discrete temperature points; wherein, the chipset to be tested includes multiple chips with different process parameters and / or different process angles; the chip to be tested is a single chip in the chipset to be tested or a combination of two or more single chips; the test parameters corresponding to the performance test points include test voltage and test operating frequency.

[0038] The performance test points corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the performance test points. The process parameters refer to process deviations existing in the chip manufacturing process, including doping concentration, diffusion depth, etching degree, precision, etc. The process corner refers to the fluctuation range of device speed defined by deviations in the manufacturing process, that is, the speed fluctuation range of NMOSFET (N-Metal-Oxide-Semiconductor Field-Effect Transistor) and PMOSFET (P-Metal-Oxide-Semiconductor Field-Effect Transistor) transistors is limited to a rectangle defined by four process corners, including fast NFET and fast PFET (FF), slow NFET and slow PFET (SS), fast NFET and slow PFET (FS), and slow NFET and fast PFET (SF). In addition, there is a normal fluctuation range TT, where F stands for fast (high current), S stands for slow (low current), and T stands for typical (average value).

[0039] The present invention adopts the form of data collection and fitting. Since the temperature of the chip will change in real time when it is working, when determining the correspondence between the temperature and the performance test point, it is necessary to determine the performance test points of the chip to be tested at at least three discrete temperature points, and fit the performance test points corresponding to at least three discrete temperature points to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the performance test point, thereby obtaining the correspondence between the temperature and the performance test point. The at least three discrete temperature points may include high temperature, medium temperature and low temperature. It should be noted that the discrete temperature points can be set according to the actual test. In this embodiment, the high temperature range is 90℃~100℃; the medium temperature range is 75℃~85℃; and the low temperature range is -10℃~0℃ for testing.

[0040] Specifically, this embodiment uses three discrete temperature points, namely, a high temperature of 95° C., a medium temperature of 80° C., and a low temperature of −5° C., as examples for description.

[0041] Optionally, in some embodiments, see Figure 2 As shown, the method of determining the performance test points of the chipset to be tested at at least three discrete temperature points includes the steps of: S210: Determine the distribution of the working critical points of the tested function of the chips in the tested chipset at at least three discrete temperature points; the electrical parameters of the working critical points include a working critical voltage and a working critical frequency; For each function of the chip, there is a critical working voltage and critical working frequency. When the chip working voltage is lower than the critical working voltage, or the working frequency is higher than the critical working frequency, the chip will not work properly. Figure 3 As shown, Figure 3 The horizontal axis of the Shmoo image (parameter scan distribution image or performance boundary test image) represents the chip operating voltage. The light-colored area is the pass area, and the combination of the critical operating voltage and critical operating frequency is the critical operating point.

[0042] In this step, Shmoo testing is used to perform functional testing on the chip under test in the chip set to obtain a Shmoo image. Shmoo testing is a visualization tool for verifying the performance of integrated circuit devices. Shmoo images are parameter scan distribution images or performance boundary test diagrams, which are used to reflect the performance boundaries of the chip under different parameter (such as voltage, frequency, and temperature) combinations or to intuitively display the working limits of the chip (such as pass / fail critical conditions); for example Figure 3 It shows the critical voltage point at a certain operating frequency. The horizontal axis represents the chip operating voltage. The dark area is the failure area, and the light area is the pass area. 0.76V is the critical point under the current conditions.

[0043] In chip mass production, since it is impossible for chips to always operate at the critical working point, it is necessary to integrate multiple chips with different process parameters and / or different process angles and find a suitable test point to ensure that all chips in the chipset to be tested can operate normally at this suitable test point.

[0044] S220 : Determine a performance test point for testing the function to be tested of the chip to be tested based on the distribution of the working critical points of the function to be tested.

[0045] In this embodiment, the chips in the chip set to be tested are functionally tested at three temperatures: high temperature, medium temperature, and low temperature. The test results are obtained to determine the distribution of the working critical points, thereby determining the performance test points for testing the tested functions of the chips to be tested. Specifically, by integrating the distribution of the working critical points of multiple chips to be tested with different process parameters and / or different process angles at the three discrete temperature points of high temperature, medium temperature, and low temperature of the tested functions, the relationship between the working critical points and the performance test points is fitted. For example, see Figure 4 As shown, Figure 4 The performance test point curves of the operating voltage and operating frequency of the chips under test with different process angles (for example, the chip with the chip unique code AZDGU19111005 and the process angle SF, the chip with the chip unique code AZDGU14090505 and the process angle SF, the chip with the chip unique code AZDH216041305 and the process angle TT, the chip with the chip unique code AZDGU20041105 and the process angle FS, the chip with the chip unique code AZDGU18030505 and the process angle SS, the chip unique code AZDGU20021305 and the process angle TT, and the chip unique code AZDH217031005 and the process angle FF) at a temperature of -5°C are shown. The horizontal axis represents the operating frequency, the vertical axis represents the operating voltage, and the vertical axis represents the operating frequency. Figure 4 It can be seen that when the temperature is -5°C, the critical operating points of all chips under test are distributed between 0.8V and 0.66V / @2G, that is, the critical operating voltage is distributed between 0.8V and 0.66V, and the critical operating frequency is 2000MHz.

[0046] Optionally, in some embodiments, the determining of the performance test points for testing the function to be tested of the chip to be tested based on the distribution of the working critical points of the function to be tested includes: determining the performance test points for testing the function to be tested of the chip to be tested according to the 3σ principle based on the distribution of the working critical points of the function to be tested. The 3σ principle is a statistical law based on the normal distribution, which describes that the probability of data falling within the range of mean (μ) ± 3 times standard deviation (σ) is approximately 99.73%; in the embodiment of the present invention, the reasonable fluctuation range of chip test parameters is defined by the 3σ principle. Based on this, a correspondence between the temperature of the chip test and the performance test points is established to achieve dynamic adjustment of the test points at different temperatures when performing chip testing, so as to meet the most stringent test requirements under the current test conditions and ensure the quality and yield of the chip.

[0047] Optionally, in some embodiments, fitting the performance test points corresponding to the at least three discrete temperature points to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the performance test points includes: For a given test operating frequency, the test voltages corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test voltage at the given test operating frequency.

[0048] In this embodiment, when establishing the correspondence between chip test temperature and performance test points, based on Shmoo test, data collection and fitting are adopted to obtain a performance test point fitting curve reflecting the correspondence between chip temperature and performance test points.

[0049] For details, see Figure 5-Figure 8 As shown in FIG, using Shmoo test, for given test operating frequencies, for example, frequencies of 1500MHz, 2000MHz, 2500MHz and 3000MHz, tests are performed at temperatures of -5°C, 80°C and 95°C, respectively, to obtain test data of chips with different process parameters or different process angles, that is, to obtain distribution curves of test voltages at different temperatures. Specifically, the test chips may include: chips with a chip unique code of AZDGU19111005, a process angle of SF, chips with a chip unique code of 19111005, a process angle of SF, chips with a chip unique code of 19111006, a process angle of SF, chips with a chip unique code of 19111007, a process angle of SF ... test data of chips with different process parameters or different process angles, that is, to obtain test data of chips with different process parameters or different process angles, that is, to obtain distribution curves of test voltages at different temperatures. The chip with the unique code of AZDGU14090505 and the process corner of SF is AZDH216041305; the chip with the process corner of TT is AZDGU20041105; the chip with the process corner of FS is AZDGU18061505; the chip with the process corner of SS is AZDGU20021305; the chip with the process corner of TT and the chip with the unique code of AZDH217031005 and the process corner of FF; Figure 5-Figure 8The horizontal axis is the test temperature, and the vertical axis is the test voltage. For example, Figure 5 Performance test point curve showing the corresponding relationship between chip temperature and test voltage at different process corners at an operating frequency of 1500MHz; Figure 6 Performance test point curve showing the corresponding relationship between chip temperature and test voltage at different process corners at an operating frequency of 2000MHz; Figure 7 Performance test point curve showing the corresponding relationship between chip temperature and test voltage at different process corners at an operating frequency of 2500MHz; Figure 8 Performance test point curve showing the relationship between chip temperature and test voltage at different process corners at an operating frequency of 3000 MHz.

[0050] Afterwards, based on the distribution of the working critical points of the function to be tested and according to the 3σ principle, the performance test points for testing the function to be tested of the chip to be tested are determined, for example, see Figure 4 As shown in the figure, at a temperature of -5°C, the critical operating points of all chips under test are distributed between 0.8V and 0.66V / @2G. According to the 3σ principle, the test point at the current temperature is determined to be 0.82V / @2G, that is, the chip will be tested at 0.82V / @2G at -5°C, that is, the operating voltage is 0.82V and the operating frequency is 2GHz.

[0051] Optionally, in some embodiments, the performance test points corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the performance test points, including: for a given test voltage, the test operating frequencies corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the test operating frequency under the given test voltage. Similarly, for a given test voltage, the test operating frequency under the current test conditions (current temperature) is obtained based on the Shmoo test. It should be noted that the method for obtaining the performance test point curve of the correspondence between the chip temperature and the test operating frequency is the same as the method for obtaining the performance test point curve of the correspondence between the chip temperature and the test voltage, which will not be repeated here.

[0052] Furthermore, after obtaining the performance test point data corresponding to the three discrete temperature points, a quadratic fitting is performed to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the performance test point. Figure 9 As shown, Figure 9 The performance test point fitting curve of the corresponding relationship between chip temperature and test voltage is obtained. Based on the fitting curve, the test voltage of the chip at different temperatures can be obtained. Figure 9The performance test point fitting curve of the corresponding relationship between chip temperature and test voltage at an operating frequency of 2000MHz is shown in Figure 1. The horizontal axis represents chip temperature, the vertical axis represents test voltage, and the fitting function is y=2E-0.6x 2 -0.0004x+0.6779; where the coefficient of determination R 2 =1; x is temperature, y is test voltage.

[0053] Optionally, in some embodiments, in step S120, determining, based on the current temperature of the chip to be tested and a pre-established correspondence between chip temperature and performance test points for the function to be tested of the chip to be tested, an actual test point for performing the function to be tested on the chip to be tested at the current temperature includes: For a given test operating frequency, determining the actual test point for performing the function test on the chip under test at the current temperature based on the current temperature of the chip under test and a performance test point fitting curve reflecting the corresponding relationship between chip temperature and test voltage; The method of testing the function to be tested on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point includes: testing the function to be tested on the chip to be tested at the current temperature based on the test voltage corresponding to the actual test point and the given test operating frequency. For example, when the given test operating frequency is 2000MHz, the function to be tested is tested on the chip to be tested based on the current test temperature of the chip to be tested obtained by detection, and the test voltage at the current temperature obtained by the performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test voltage. The chip must pass the current test voltage to pass the test. When the next functional test is performed after passing the functional test, the tester obtains the current temperature of the chip again, and calculates the actual test point of the next functional test based on the pre-established corresponding relationship between the chip temperature and the performance test point, until the functional test is completed.

[0054] Optionally, in some embodiments, in step S120, determining, based on the current temperature of the chip to be tested and a pre-established correspondence between chip temperature and performance test points for the function to be tested of the chip to be tested, an actual test point for performing the function to be tested on the chip to be tested at the current temperature includes: For a given test voltage, determining the actual test point for performing the function test on the chip under test at the current temperature based on the current temperature of the chip under test and a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test operating frequency; Among them, the testing of the function to be tested on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point includes: testing the function to be tested on the chip to be tested at the current temperature based on the test operating frequency corresponding to the actual test point and the given test voltage.

[0055] Figure 10 A schematic diagram of a chip testing device according to one or more embodiments of the present invention is provided. Figure 10 As shown, the chip testing device 10 includes: The temperature detection module 11 is used to detect the current temperature of the chip to be tested; A first determining module 12 is configured to determine an actual test point for performing the function under test test on the chip under test at the current temperature based on the current temperature of the chip under test and a pre-established correspondence between chip temperature and performance test points for the function under test of the chip under test; The function test module 13 is configured to test the function to be tested on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point.

[0056] Optionally, in one or more embodiments of the present invention, Figure 10 The chip testing device shown may further include: A second determination module is configured to determine performance test points of the chipset under test at at least three discrete temperature points before detecting the current temperature of the chipset under test; wherein the chipset under test includes a plurality of chips having different process parameters and / or different process angles; the chipset under test is a single chip or a combination of two or more single chips in the chipset under test; and the test parameters corresponding to the performance test points include a test voltage and a test operating frequency; The data fitting module is used to fit the performance test points corresponding to the at least three discrete temperature points to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the performance test points.

[0057] Optionally, in one or more embodiments of the present invention, Figure 10 The second determination module in the chip testing device shown includes: A first determining submodule is configured to determine the distribution of the working critical points of the function to be tested of the chip to be tested in the chipset to be tested at at least three discrete temperature points; the electrical parameters of the working critical points include a working critical voltage and a working critical frequency; The second determining submodule is configured to determine a performance test point for testing the function to be tested of the chip to be tested based on the distribution of working critical points of the function to be tested.

[0058] Optionally, in one or more embodiments of the present invention, the second determination submodule is specifically used to determine the performance test points for testing the function to be tested of the chip to be tested based on the distribution of working critical points of the function to be tested and according to the 3σ principle.

[0059] Optionally, in one or more embodiments of the present invention, the data fitting module is specifically used to fit the test voltages corresponding to the at least three discrete temperature points for a given test operating frequency, and obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the test voltage at the given test operating frequency.

[0060] Optionally, in one or more embodiments of the present invention, the data fitting module is also used to fit the test operating frequencies corresponding to the at least three discrete temperature points for a given test voltage, so as to obtain a performance test point fitting curve reflecting the correspondence between the chip temperature and the test operating frequency under the given test voltage.

[0061] Optionally, in one or more embodiments of the present invention, the first determining module is specifically configured to determine, for a given test operating frequency, an actual test point for performing the function test on the chip under test at the current temperature based on the current temperature of the chip under test and a performance test point fitting curve reflecting a corresponding relationship between chip temperature and test voltage; The functional test module is specifically configured to test the function to be tested on the chip to be tested at the current temperature based on the test voltage corresponding to the actual test point and the given test operating frequency.

[0062] Optionally, in one or more embodiments of the present invention, the first determining module is further configured to determine, for a given test voltage, an actual test point for performing the function test on the chip under test at the current temperature based on the current temperature of the chip under test and a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test operating frequency; The functional test module is further configured to test the function to be tested on the chip to be tested at the current temperature based on the test operating frequency corresponding to the actual test point and the given test voltage.

[0063] Figure 11 FIG. 1 is a schematic block diagram of an electronic device according to an embodiment of the present invention; based on the same technical concept as the above embodiment, the electronic device provided by the embodiment of the present invention is as follows: Figure 11 As shown, the step flow of the chip testing method described in any one of the embodiments of the present invention can be implemented.

[0064] The above-mentioned electronic device may include: a processor 111 and a memory 112; wherein the memory 112 is used to store executable program code; the processor 111 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 112, so as to execute the chip testing method described in any of the above-mentioned embodiments.

[0065] The specific execution process of the above steps by the processor 111 and the steps further executed by the processor 111 by running the executable program code can be found in the description of the first embodiment of the present invention, and will not be repeated here.

[0066] The electronic devices exist in various forms, including but not limited to: (1) Computer equipment: This type of equipment belongs to the category of personal computers, has computing and processing functions, and generally also has mobile Internet access features.

[0067] (2) Server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to a general computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0068] (3) Other electronic devices with data interaction functions.

[0069] An embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the chip testing method described in any of the aforementioned embodiments.

[0070] It should be noted that in this article, relational terms such as first and second are only used to One entity or operation is distinguished from another entity or operation without necessarily requiring or implying that these There is no such actual relationship or order between entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0071] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0072] For the convenience of description, when referring to a system, server, etc., it may be described separately by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0073] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0074] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A chip testing method, characterized in that: include: Detect the current temperature of the chip under test; Determining an actual test point for performing the function under test test on the chip under test at the current temperature based on the current temperature of the chip under test and a pre-established correspondence between chip temperature and performance test points for the function under test of the chip under test; Based on the test voltage and operating frequency corresponding to the actual test point, the function to be tested is tested on the chip to be tested at the current temperature.

2. The chip testing method according to claim 1, characterized in that: Before detecting the current temperature of the chip to be tested, the method further includes: Determining performance test points of a chipset under test at at least three discrete temperature points; wherein the chipset under test includes multiple chips having different process parameters and / or different process angles; the chip under test is a single chip in the chipset under test or a combination of two or more single chips; and the test parameters corresponding to the performance test points include a test voltage and a test operating frequency; The performance test points corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the performance test points.

3. The chip testing method according to claim 2, characterized in that: Determining the performance test points of the chipset to be tested at at least three discrete temperature points includes: Determining the distribution of the working critical points of the tested function of the chip under test in the tested chipset at at least three discrete temperature points; the electrical parameters of the working critical points include a working critical voltage and a working critical frequency; Based on the distribution of the working critical points of the function to be tested, a performance test point for testing the function to be tested of the chip to be tested is determined.

4. The chip testing method according to claim 3, characterized in that: The determining, based on the distribution of the working critical points of the function to be tested, the performance test points for testing the function to be tested of the chip to be tested includes: Based on the distribution of the working critical points of the function to be tested and according to the 3σ principle, a performance test point for testing the function to be tested of the chip to be tested is determined.

5. The chip testing method according to claim 2, characterized in that: The fitting of the performance test points corresponding to the at least three discrete temperature points to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the performance test points includes: For a given test operating frequency, the test voltages corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test voltage at the given test operating frequency.

6. The chip testing method according to claim 2, characterized in that: The fitting of the performance test points corresponding to the at least three discrete temperature points to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the performance test points includes: For a given test voltage, the test operating frequencies corresponding to the at least three discrete temperature points are fitted to obtain a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test operating frequency under the given test voltage.

7. The chip testing method according to claim 5, characterized in that: The determining, based on the current temperature of the chip to be tested and a pre-established correspondence between chip temperature and performance test points for the function to be tested of the chip to be tested, an actual test point for performing the function to be tested on the chip to be tested at the current temperature includes: For a given test operating frequency, determining the actual test point for performing the function test on the chip under test at the current temperature based on the current temperature of the chip under test and a performance test point fitting curve reflecting the corresponding relationship between chip temperature and test voltage; The step of testing the function to be tested on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point includes: Based on the test voltage corresponding to the actual test point and the given test operating frequency, the function to be tested is tested on the chip to be tested at the current temperature.

8. The chip testing method according to claim 6, characterized in that: The determining, based on the current temperature of the chip to be tested and a pre-established correspondence between chip temperature and performance test points for the function to be tested of the chip to be tested, an actual test point for performing the function to be tested on the chip to be tested at the current temperature includes: For a given test voltage, determining the actual test point for performing the function test on the chip under test at the current temperature based on the current temperature of the chip under test and a performance test point fitting curve reflecting the corresponding relationship between the chip temperature and the test operating frequency; The step of testing the function to be tested on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point includes: Based on the test operating frequency corresponding to the actual test point and the given test voltage, the function to be tested is tested on the chip to be tested at the current temperature.

9. A chip testing device, characterized in that: include: Temperature detection module, used to detect the current temperature of the chip to be tested; A first determining module is configured to determine, based on the current temperature of the chip to be tested and a pre-established correspondence between chip temperature and performance test points for the function to be tested of the chip to be tested, an actual test point for performing the function to be tested on the chip to be tested at the current temperature; The functional testing module is used to test the function to be tested on the chip to be tested at the current temperature based on the test voltage and operating frequency corresponding to the actual test point.

10. An electronic device, characterized in that: include: A processor and a memory, wherein the memory is used to store executable program code; The processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the chip testing method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip testing method according to any one of claims 1 to 8.

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