A chip internal circuit aging detection circuit

Abstract

The application discloses a kind of chip internal circuit aging detection circuit, it is related to chip detection technical field, including power module, power regulation is carried out, by input detection module cooperation second judging module to the signal of input chip module is carried out voltage drop detection, when input exception, detection control module cooperation prevents detection module and first judging module detection chip module total resistance value condition, then judge whether chip module occurs aging and aging degree, when reaching maximum aging degree, power-off protection is carried out and the signal path of input to chip module is disconnected, micro-control module can be according to the type of pulse signal output by chip module, control output detection module carries out pulse conversion, phase shift, phase shift superposition and superposition potential detection, and whether the signal appears fluctuation according to the potential after superposition judges, the working state of chip module is judged.The application chip internal circuit aging detection circuit can improve the aging detection precision of chip module and the safety of circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip detection, and in particular to a chip internal circuit aging detection circuit. BACKGROUND

[0002] Chip internal circuit aging is a test for evaluating the performance stability and reliability of a chip during long-term use. In general, the chip internal circuit is placed in a corresponding temperature and humidity environment, powered on with a load, and run for a corresponding time in this environment. Then, it is observed whether the chip can work normally, and then it is judged whether the chip has aged. However, since the chip has multiple IO interfaces, each IO interface has different functions, which makes it impossible to accurately determine the power state of the corresponding IO interface of the chip, and thus it is impossible to accurately determine the aging of the chip internal circuit. Therefore, there is room for improvement. SUMMARY

[0003] The present application provides a chip internal circuit aging detection circuit to solve the problems in the background art.

[0004] According to the present application, a chip internal circuit aging detection circuit is provided, which comprises:

[0005] A power module is configured to adjust the power of the input power and output a first power.

[0006] A detection control module is connected to the power module and the chip module, configured to transmit the first power to the chip module, switch the transmission path, and divide the first power to detect the resistance value of the chip module and output a first detection signal.

[0007] A chip module is configured to receive power and start, input a signal and output a pulse signal.

[0008] A resistance detection module is connected to the detection control module, configured to perform voltage following and differential amplification on the first detection signal and output a second detection signal.

[0009] A first judgment module is connected to the resistance detection module, configured to output a first electrical signal, a second electrical signal, and a third electrical signal when the first resistance threshold value, the second resistance threshold value, or the third resistance threshold value is greater than the second detection signal.

[0010] An input detection module is connected to the chip module, configured to perform voltage drop state detection and signal differential amplification on the input signal and output a third detection signal.

[0011] The second judging module is connected with the input detecting module and the detecting control module, and is used for outputting a fourth electric signal, a fifth electric signal and a sixth electric signal respectively and triggering the path switching work of the detecting control module when the set first pressure drop threshold, the second pressure drop threshold or the third pressure drop threshold is greater than the third detecting signal.

[0012] The output detecting module is connected with the chip module, and is used for converting the pulse signal into a sine wave signal, performing phase shift processing and phase shift superposition processing on the sine wave signal or the pulse signal, detecting whether the potential of the superimposed signal is zero, and outputting a seventh electric signal when the potential is not zero.

[0013] The micro control module is connected with the output detecting module, the power module, the detecting control module, the first judging module and the second judging module, and is used for controlling the power module to perform power adjustment, receiving the first electric signal, the second electric signal, the third electric signal, the fourth electric signal, the fifth electric signal, the sixth electric signal and the seventh electric signal and performing aging degree judgment, controlling the signal transmission path of the output detecting module and controlling the output detecting module to perform pulse conversion when the pulse signal is a square wave signal.

[0014] The protection module is connected with the power module, the chip module, the first judging module and the second judging module, and is used for controlling the power module to be powered off and controlling the chip module to stop accessing signals when the third electric signal or the sixth electric signal is received.

[0015] As a further scheme of the present application, the power module comprises a power interface, a first power tube, a first diode, a first inductor and a first capacitor; and the micro control module comprises a first controller.

[0016] Preferably, the first end of the power interface is connected with the drain of the first power tube, the source of the first power tube is connected with the cathode of the first diode and the first end of the first capacitor and the detecting control module through the first inductor, the anode of the first diode is connected with the second end of the first capacitor, the second end of the power interface and the ground end, and the gate of the first power tube is connected with the IO1 end of the first controller.

[0017] As a further scheme of the present application, the detecting control module comprises a first relay, a first resistor, a second resistor and a first analog switch; and the first relay comprises a first relay switch.

[0018] Preferably, the first moving end and the second moving end of the first relay switch are both connected with the first end of the first capacitor, the first stationary end of the first relay switch is connected with the chip module and the first end of the first resistor and the IN end of the first analog switch through the second resistor, the second end of the first resistor is connected with the second stationary end of the first relay switch, the control end of the first relay is connected with the CTRL end of the first analog switch, the first judging module and the second judging module, and the OUT end of the first analog switch is connected with the resistance detecting module.

[0019] As a further scheme of the present application: the chip module comprises the chip to be detected and a third resistor;

[0020] Preferably, the VCC end of the chip to be detected is connected to the first static end of the first relay switch, the IO1 end of the chip to be detected is connected to the input detection module, the IO2 end of the chip to be detected is connected to the output detection module and the GND end of the chip to be detected and the ground end are connected through the third resistor.

[0021] As a further scheme of the present application: the input detection module comprises a second capacitor, a fourth resistor, a fifth resistor, a third capacitor, a third diode, a second diode, a fifth diode, a fourth diode, a seventh resistor, a first power supply, a first operational amplifier, a sixth resistor, a sixth diode, a second power supply, a third power supply, a seventh diode and an eighth diode;

[0022] Preferably, the cathode of the fourth diode is connected to the IO1 end of the chip to be detected and one end of the second capacitor and connected to the other end of the second capacitor, one end of the fifth resistor, one end of the third capacitor, the anode of the third diode and the cathode of the fifth diode through the fourth resistor, the cathode of the third diode is connected to the cathode of the second diode, the anode of the second diode is connected to the cathode of the sixth diode, the other end of the third capacitor, the other end of the fifth resistor, the anode of the eighth diode and the ground end, the anode of the fifth diode is connected to the anode of the fourth diode and the non-inverting end of the first operational amplifier and connected to the first power supply through the seventh resistor, the inverting end of the first operational amplifier is connected to the anode of the sixth diode and connected to the third power supply through the sixth resistor, the output end of the first operational amplifier is connected to the anode of the seventh diode, the cathode of the eighth diode and the second judgment module, and the cathode of the seventh diode is connected to the second power supply.

[0023] As a further scheme of the present application: the resistance detection module comprises an eighth resistor, a third operational amplifier, a second operational amplifier, a tenth resistor, a ninth resistor and a fourth operational amplifier;

[0024] Preferably, the non-inverting end of the third operational amplifier is connected to the second end of the first resistor, the inverting end of the third operational amplifier is connected to the output end of the third operational amplifier and connected to the inverting end of the fourth operational amplifier, the output end of the fourth operational amplifier and the first judgment module through the tenth resistor, the non-inverting end of the fourth operational amplifier is connected to the output end and the inverting end of the second operational amplifier through the ninth resistor, and the non-inverting end of the second operational amplifier is connected to the OUT end of the first analog switch through the eighth resistor.

[0025] As a further scheme of the present application: the first judgment module comprises a first reference power supply, a ninth diode, a twelfth diode, a first comparator, a second comparator and a third comparator;

[0026] Preferably, the first reference power source is connected to the inverting terminal of the first comparator and the anode of the ninth diode, the cathode of the ninth diode is connected to the inverting terminal of the second comparator, the non-inverting terminal of the first comparator, the non-inverting terminal of the second comparator and the non-inverting terminal of the third comparator are all connected to the output terminal of the fourth operational amplifier, the output terminal of the first comparator, the output terminal of the second comparator and the output terminal of the third comparator are respectively connected to the IO2 terminal, the IO3 terminal and the IO4 terminal of the first controller.

[0027] As a further scheme of the present application, the second judging module comprises a second reference power source, an electric energy comparison device, an eleventh diode, a tenth diode and a thirteenth diode.

[0028] Preferably, the reference terminal of the electric energy comparison device is connected to the second reference power source, the input terminal of the electric energy comparison device is connected to the output terminal of the first operational amplifier, the first output terminal of the electric energy comparison device is connected to the anode of the eleventh diode and the IO5 terminal of the first controller, the second output terminal of the electric energy comparison device is connected to the anode of the tenth diode and the IO6 terminal of the first controller, the third output terminal of the electric energy comparison device is connected to the anode of the thirteenth diode and the IO7 terminal of the first controller, the cathode of the eleventh diode is connected to the cathode of the tenth diode, the cathode of the thirteenth diode and the CTRL terminal of the first analog switch.

[0029] As a further scheme of the present application, the output detecting module comprises a second analog switch, a waveform conversion device, an eleventh resistor, a twelfth resistor, a phase shifting device, a fourth comparator, a fifth comparator and a first logic chip.

[0030] Preferably, the IN1 terminal and the IN2 terminal of the second analog switch are both connected to the IO8 terminal of the first controller, the OUT1 terminal of the second analog switch is connected to the input terminal of the phase shifting device and the output terminal of the waveform conversion device and is connected to one end of the twelfth resistor, the inverting terminal of the fifth comparator and the non-inverting terminal of the fourth comparator through the eleventh resistor, the OUT2 terminal of the second analog switch is connected to the input terminal of the waveform conversion device, the output terminal of the phase shifting device is connected to the other end of the twelfth resistor, the inverting terminal of the fourth comparator is connected to the non-inverting terminal of the fifth comparator and the ground terminal, the output terminal of the fourth comparator and the output terminal of the fifth comparator are respectively connected to the A terminal and the B terminal of the first logic chip, the Y terminal of the first logic chip is connected to the IO11 terminal of the first controller, the CTRL1 terminal and the CTRL2 terminal of the second analog switch are respectively connected to the IO9 terminal and the IO10 terminal of the first controller.

[0031] As a further scheme of the present application, the protection module comprises a fourteenth diode, a fifteenth diode, a first switch tube and a second switch tube.

[0032] Preferably, the anode of the fourteenth diode and the anode of the fifteenth diode are connected to the third output end of the power comparison device and the output end of the first comparator respectively, the cathode of the fourteenth diode is connected to the cathode of the fifteenth diode, the base of the first switch tube and the base of the second switch tube, the collector of the first switch tube is connected to the gate of the first power tube, the collector of the second switch tube is connected to the IO1 end of the chip to be detected, and the emitter of the first switch tube and the emitter of the second switch tube are both grounded.

[0033] Compared with the prior art, the chip internal circuit aging detection circuit of the present application has the following advantages: the chip internal circuit aging detection circuit of the present application can be power-regulated by a power module to meet different voltage supplies, and the detected signals are transmitted to the chip module by the detection control module, and the input detection module cooperates with the second judgment module to detect the voltage drop of the signals input to the chip module, to determine whether the signals on the input side of the chip module are abnormal, and when the input is abnormal, the detection control module cooperates with the blocking detection module and the first judgment module to detect the total resistance value of the chip module, and the micro control module receives the detection result to determine whether the chip module is aging and the aging degree of the chip module according to the second judgment module and the first judgment module, and when the maximum aging degree is reached, the protection module is controlled to be powered off and the signal path input to the chip module is disconnected, thereby improving the aging detection precision and the safety of the circuit, and the micro control module can control the output detection module to perform pulse conversion, pulse phase shift, phase shift superposition and superposition potential detection according to the type of the pulse signal output by the chip module, and determine whether the output signal fluctuates according to the superimposed potential, and then determine the working state of the chip module, thereby further improving the aging detection precision of the chip module. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0035] Figure 1 A principle block diagram of a chip internal circuit aging detection circuit is provided for the embodiments of the present application.

[0036] Figure 2 A circuit diagram of a chip internal circuit aging detection circuit is provided for the embodiments of the present application.

[0037] Figure 3 A circuit diagram of a resistance detection module is provided for the embodiments of the present application.

[0038] Figure 4 A circuit diagram of a first judgment module is provided for the embodiments of the present application.

[0039] Figure 5 The circuit diagram of the second judging module provided for the embodiment of the present application.

[0040] Figure 6 The circuit diagram of the output detecting module provided for the embodiment of the present application.

[0041] Figure 7 The circuit diagram of the protection module provided for the embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0043] In one embodiment, referring to Figure 1 , a chip internal circuit aging detection circuit comprises:

[0044] A power module 1 is configured to perform power adjustment on the accessed electric energy and output first electric energy.

[0045] A detection control module 2 is connected with the power module 1 and a chip module 3, configured to transmit the first electric energy to the chip module 3, switch the transmission path and perform voltage division processing on the first electric energy, detect the resistance value of the chip module 3 and output a first detection signal.

[0046] The chip module 3 is configured to receive electric energy and start, access an input signal and output a pulse signal.

[0047] A resistance value detection module 4 is connected with the detection control module 2, configured to perform voltage following and differential amplification processing on the first detection signal and output a second detection signal.

[0048] A first judging module 5 is connected with the resistance value detection module 4, configured to output a first electric signal, a second electric signal and a third electric signal respectively when the set first resistance threshold value, second resistance threshold value or third resistance threshold value is greater than the second detection signal.

[0049] An input detection module 6 is connected with the chip module 3, configured to perform voltage drop state detection and signal differential amplification processing on the input signal and output a third detection signal.

[0050] The second judging module 7 is connected with the input detecting module 6 and the detecting control module 2, and is used for outputting the fourth electric signal, the fifth electric signal and the sixth electric signal respectively and triggering the path switching work of the detecting control module 2 when the set first pressure drop threshold, the second pressure drop threshold or the third pressure drop threshold is greater than the third detecting signal.

[0051] The output detecting module 8 is connected with the chip module 3, and is used for converting the pulse signal into the sine wave signal, performing the phase shift processing and the phase shift superposition processing on the sine wave signal or the pulse signal, detecting whether the potential of the superposed signal is zero, and outputting the seventh electric signal when the potential is not zero.

[0052] The micro control module 9 is connected with the output detecting module 8, the power supply module 1, the detecting control module 2, the first judging module 5 and the second judging module 7, and is used for controlling the power supply module 1 to perform the power adjustment, receiving the first electric signal, the second electric signal, the third electric signal, the fourth electric signal, the fifth electric signal, the sixth electric signal and the seventh electric signal and performing the aging degree judgment, controlling the signal transmission path of the output detecting module 8 and controlling the output detecting module 8 to perform the pulse conversion when the pulse signal is the square wave signal.

[0053] The protection module 10 is connected with the power supply module 1, the chip module 3, the first judging module 5 and the second judging module 7, and is used for controlling the power supply module 1 to be powered off and controlling the chip module 3 to stop accessing the signal when the third electric signal or the sixth electric signal is received.

[0054] In specific embodiments, the power module 1 described above can adopt a power supply circuit composed of a power interface, a field effect tube, a capacitor, an inductor, etc., which can perform power regulation processing on the input power to achieve voltage fluctuation control; the detection control module 2 described above can adopt a detection control circuit composed of a relay, a resistor, an analog switch, etc., which can control the transmission path of the power and the transmission path of the signal, and sample the voltage division of the input power; the chip module 3 described above can adopt a chip circuit composed of a chip to be detected IC1 and a resistor, which is powered by the detection control module 2, and can realize signal input and signal output, and the output pulse signal can be a sine signal or a square wave signal; the resistance detection module 4 described above can adopt a resistance detection circuit composed of an operational amplifier and a resistor, which can perform voltage following processing and differential amplification processing on the signal divided by the detection control module 2, and then calculate the total resistance value of the chip module 3; the first judgment module 5 described above can adopt a first judgment circuit composed of a comparator, a diode and a reference power supply, which can provide a first resistance threshold, a second resistance threshold and a third resistance threshold by the reference power supply in cooperation with the diode and compare the voltage with the input signal, wherein the first resistance threshold is less than the second resistance threshold, which is less than the third resistance threshold, and the first resistance threshold is the total resistance value of the chip to be detected IC1 in the chip module 3 when it is not aged; the input detection module 6 described above can adopt an input detection circuit composed of a resistor, a capacitor, an operational amplifier, etc., which can detect the signal voltage drop state and perform signal differential amplification processing; the second judgment module 7 described above can adopt a second judgment circuit composed of a power comparison device, a reference power supply and a diode, which can set a first voltage drop threshold, a second voltage drop threshold and a third voltage drop threshold and compare the voltage with the input signal, wherein the first voltage drop threshold is less than the second voltage drop threshold, which is less than the third voltage drop threshold; the output detection module 8 described above can adopt an output detection circuit composed of an analog switch, a waveform conversion device, a phase shift device, a comparator, etc., which can switch the transmission path of the signal according to the type of the signal output by the chip module 3, and can also perform waveform conversion, phase shift processing, phase shift superposition processing and superposition potential detection processing, and then detect whether the signal output by the chip module 3 fluctuates; the micro control module 9 described above can adopt a micro control circuit composed of a single chip microcomputer, which integrates many components such as an arithmetic unit, a controller, a memory and an input and output unit, and realizes functions such as signal processing, data storage, module control and timing control; the protection module 10 described above can adopt a protection circuit composed of a diode and a triode, which can control the working state of the power module 1 and the chip module 3, and perform power-off protection and interface protection.

[0055] In another embodiment, please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 , the power module 1 includes a power interface, a first power tube Q1, a first diode D1, a first inductor L1 and a first capacitor C1; the micro control module 9 includes a first controller U1;

[0056] Specifically, the first end of the power interface is connected to the drain of the first power tube Q1, the source of the first power tube Q1 is connected to the cathode of the first diode D1 and the first end of the first capacitor C1 and the detection control module 2 through the first inductor L1, the anode of the first diode D1 is connected to the second end of the first capacitor C1, the second end of the power interface and the ground, and the gate of the first power tube Q1 is connected to the IO1 end of the first controller U1.

[0057] In specific embodiments, the first power tube Q1 can be an N-channel field effect tube, and the first controller U1 can be an STM32 single-chip microcomputer.

[0058] Further, the detection control module 2 comprises a first relay K1, a first resistor R1, a second resistor R2 and a first analog switch U2; the first relay K1 comprises a first relay switch K1-1;

[0059] Specifically, the first moving end and the second moving end of the first relay switch K1-1 are both connected to the first end of the first capacitor C1, the first stationary end of the first relay switch K1-1 is connected to the chip module 3 and the first end of the first resistor R1 and the IN end of the first analog switch U2 through the second resistor R2, the second end of the first resistor R1 is connected to the second stationary end of the first relay switch K1-1, the control end of the first relay K1 is connected to the CTRL end of the first analog switch U2, the first judgment module 5 and the second judgment module 7, and the OUT end of the first analog switch U2 is connected to the resistance detection module 4.

[0060] In specific embodiments, the first relay switch K1-1 can be a double-pole single-throw switch, the first stationary end and the first moving end of the first relay switch K1-1 are normally closed switches, the second stationary end and the second moving end are normally open switches, and the first relay K1 controls them by magnetic attraction; the resistance value of the first resistor R1 is equal to that of the second resistor R2; and the first analog switch U2 can be a CD4066 chip.

[0061] Further, the chip module 3 comprises a chip to be detected IC1 and a third resistor R3;

[0062] Specifically, the VCC end of the chip to be detected IC1 is connected to the first stationary end of the first relay switch K1-1, the IO1 end of the chip to be detected IC1 is connected to the input detection module 6, the IO2 end of the chip to be detected IC1 is connected to the output detection module 8 and the GND end of the chip to be detected IC1 and the ground through the third resistor R3.

[0063] In specific embodiments, the IO1 end of the chip to be detected IC1 is a signal input end, the IO2 end is a signal output end, and the model of the chip to be detected IC1 is not limited;

[0064] Further, the input detection module 6 comprises a second capacitor C2, a fourth resistor R4, a fifth resistor R5, a third capacitor C3, a third diode D3, a second diode D2, a fifth diode D5, a fourth diode D4, a seventh resistor R7, a first power supply VCC1, a first operational amplifier OP1, a sixth resistor R6, a sixth diode D6, a second power supply VCC2, a third power supply VCC3, a seventh diode D7 and an eighth diode D8;

[0065] Specifically, the cathode of the fourth diode D4 is connected to the I01 terminal of the chip IC1 to be detected and one end of the second capacitor C2, and the other end of the second capacitor C2, one end of the fifth resistor R5, one end of the third capacitor C3, the anode of the third diode D3 and the cathode of the fifth diode D5 are connected through the fourth resistor R4, the cathode of the third diode D3 is connected to the cathode of the second diode D2, the anode of the second diode D2 is connected to the cathode of the sixth diode D6, the other end of the third capacitor C3, the other end of the fifth resistor R5, the anode of the eighth diode D8 and the ground terminal, the anode of the fifth diode D5 is connected to the anode of the fourth diode D4 and the non-inverting terminal of the first operational amplifier OP1 and is connected to the first power supply VCC1 through the seventh resistor R7, the inverting terminal of the first operational amplifier OP1 is connected to the anode of the sixth diode D6 and is connected to the third power supply VCC3 through the sixth resistor R6, the output terminal of the first operational amplifier OP1 is connected to the anode of the seventh diode D7, the cathode of the eighth diode D8 and the second judgment module 7, and the cathode of the seventh diode D7 is connected to the second power supply VCC2.

[0066] In specific embodiments, the first operational amplifier OP1 described above can be selected as an OP07 operational amplifier for differential amplification processing.

[0067] Further, the resistance detection module 4 comprises an eighth resistor R8, a third operational amplifier OP3, a second operational amplifier OP2, a tenth resistor R10, a ninth resistor R9 and a fourth operational amplifier OP4.

[0068] Specifically, the non-inverting terminal of the third operational amplifier OP3 is connected to the second terminal of the first resistor R1, the inverting terminal of the third operational amplifier OP3 is connected to the output terminal of the third operational amplifier OP3 and is connected to the inverting terminal of the fourth operational amplifier OP4, the output terminal of the fourth operational amplifier OP4 and the first judgment module 5 through the tenth resistor R10, the non-inverting terminal of the fourth operational amplifier OP4 is connected to the output terminal and the inverting terminal of the second operational amplifier OP2 through the ninth resistor R9, and the non-inverting terminal of the second operational amplifier OP2 is connected to the OUT terminal of the first analog switch U2 through the eighth resistor R8.

[0069] In specific embodiments, the third operational amplifier OP3, the second operational amplifier OP2 and the fourth operational amplifier OP4 described above can be selected as OP07 operational amplifiers, wherein the third operational amplifier OP3 and the second operational amplifier OP2 perform voltage follower processing, and the fourth operational amplifier OP4 performs differential amplification processing.

[0070] Further, the first judging module 5 comprises a first reference power supply VREF1, a ninth diode D9, a twelfth diode D10, a first comparator A1, a second comparator A2 and a third comparator A3;

[0071] Specifically, the first reference power supply VREF1 is connected to the inverting terminal of the first comparator A1 and the anode of the ninth diode D9, the cathode of the ninth diode D9 is connected to the inverting terminal of the second comparator A2, the non-inverting terminal of the first comparator A1, the non-inverting terminal of the second comparator A2 and the non-inverting terminal of the third comparator A3 are all connected to the output terminal of the fourth operational amplifier OP4, the output terminal of the first comparator A1, the output terminal of the second comparator A2 and the output terminal of the third comparator A3 are respectively connected to the IO2 terminal, the IO3 terminal and the IO4 terminal of the first controller U1.

[0072] In a specific embodiment, the first reference power supply VREF1 provides a third resistance threshold, the ninth diode D9 provides a second resistance threshold, and the twelfth diode D10 provides a first resistance threshold.

[0073] Further, the second judging module 7 comprises a second reference power supply VREF2, an electric energy comparison device, an eleventh diode D11, a tenth diode D12 and a thirteenth diode D13;

[0074] Specifically, the reference terminal of the electric energy comparison device is connected to the second reference power supply VREF2, the input terminal of the electric energy comparison device is connected to the output terminal of the first operational amplifier OP1, the first output terminal of the electric energy comparison device is connected to the anode of the eleventh diode D11 and the IO5 terminal of the first controller U1, the second output terminal of the electric energy comparison device is connected to the anode of the tenth diode D12 and the IO6 terminal of the first controller U1, the third output terminal of the electric energy comparison device is connected to the anode of the thirteenth diode D13 and the IO7 terminal of the first controller U1, the cathode of the eleventh diode D11 is connected to the cathode of the tenth diode D12, the cathode of the thirteenth diode D13 and the CTRL terminal of the first analog switch U2.

[0075] In a specific embodiment, the circuit composition structure of the electric energy comparison device is the same as that of the ninth diode D9, the twelfth diode D10, the first comparator A1, the second comparator A2 and the third comparator A3.

[0076] In another embodiment, please refer to Figure 1 , Figure 6 and Figure 7 , the output detection module 8 comprises a second analog switch U3, a waveform conversion device, an eleventh resistor R11, a twelfth resistor R12, a phase shift device, a fourth comparator A4, a fifth comparator A5 and a first logic chip J1;

[0077] Specifically, the IN1 end and the IN2 end of the second analog switch U3 are connected to the IO8 end of the first controller U1, the OUT1 end of the second analog switch U3 is connected to the input end of the phase shifting device and the output end of the waveform conversion device, and is connected to one end of the twelfth resistor R12, the inverting end of the fifth comparator A5 and the non-inverting end of the fourth comparator A4 through the eleventh resistor R11, the OUT2 end of the second analog switch U3 is connected to the input end of the waveform conversion device, the output end of the phase shifting device is connected to the other end of the twelfth resistor R12, the inverting end of the fourth comparator A4 is connected to the non-inverting end of the fifth comparator A5 and the ground, the output end of the fourth comparator A4 and the output end of the fifth comparator A5 are connected to the A end and the B end of the first logic chip J1 respectively, the Y end of the first logic chip J1 is connected to the IO11 end of the first controller U1, and the CTRL1 end and the CTRL2 end of the second analog switch U3 are connected to the IO9 end and the IO10 end of the first controller U1 respectively.

[0078] In specific embodiments, the second analog switch U3 can be selected as a CD4066 chip, the waveform conversion device can be composed of resistors, capacitors, operational amplifiers, and can convert the input square wave signal into a sine wave signal, the phase shifting device can be composed of resistors, capacitors, potentiometers and operational amplifiers, and can perform 0-180 degree phase shifting processing on the input signal, the fourth comparator A4 and the fifth comparator A5 can be selected as LM358 comparators, and the first logic chip J1 can be selected as an XOR gate chip.

[0079] Further, the protection module 10 includes a fourteenth diode D14, a fifteenth diode D15, a first switch tube V1 and a second switch tube V2.

[0080] Specifically, the anode of the fourteenth diode D14 and the anode of the fifteenth diode D15 are connected to the third output end of the electric energy comparison device and the output end of the first comparator A1 respectively, the cathode of the fourteenth diode D14 is connected to the cathode of the fifteenth diode D15, the base of the first switch tube V1 and the base of the second switch tube V2, the collector of the first switch tube V1 is connected to the gate of the first power tube Q1, the collector of the second switch tube V2 is connected to the IO1 end of the chip IC1 to be detected, and the emitter of the first switch tube V1 and the emitter of the second switch tube V2 are both grounded.

[0081] In specific embodiments, the first switch tube V1 and the second switch tube V2 can be selected as NPN type triodes.

[0082] In the chip internal circuit aging detection circuit, the first power tube Q1 is driven to be turned on by the IO1 terminal of the first controller U1, the power of the power supply interface is adjusted by the first diode D1, the first inductor L1 and the first capacitor C1, and then transmitted to the VCC terminal of the chip IC1 to be detected through the first relay switch K1-1, so as to control the chip IC1 to be detected to start. The signal is input from the IO1 terminal of the chip IC1 to be detected, and the signal is processed by the first operational amplifier OP1, the second capacitor C2, the fifth resistor R5, the fourth resistor R4, the third capacitor C3, the fourth diode D4, the third diode D3, the second diode D2, the fifth diode D5, the sixth diode D6, the seventh resistor R7, the sixth resistor R6, the first power supply VCC1 and the second power supply VCC2 for voltage drop detection and differential amplification, the output signal is clamped by the second power supply VCC2, the seventh diode D7 and the eighth diode D8, and the third detection signal is output. The third detection signal is compared with the first voltage drop threshold, the second voltage drop threshold and the third voltage drop threshold of the power comparison device respectively. When the third detection signal is greater than the first voltage drop threshold, the first output terminal of the power comparison device controls the first analog switch U2 to be turned on, the first relay K1 is powered on, the first relay switch K1-1 is switched, the third operational amplifier, the second operational amplifier OP2, the eighth resistor R8, the tenth resistor R10, the ninth resistor R9 and the fourth operational amplifier OP4 cooperate with the first resistor R1 and the second resistor R2 to output the second detection signal, the voltage of the chip IC1 to be detected under the specific power supply is calculated, and then the total resistance of the chip IC1 to be detected is judged. When the second detection signal is greater than the first reference voltage VREF1, the ninth diode D9 and the twelfth diode D10 set the first resistance threshold, it is proved that the chip IC1 to be detected is aging. According to the voltage size of the second detection signal and the second resistance threshold or the third resistance threshold, and the voltage size of the third detection signal and the second voltage drop threshold and the third voltage drop threshold, the aging degree of the chip IC1 to be detected is judged. When it is greater than the third voltage drop threshold or the third resistance threshold, it is proved that the aging degree reaches the maximum, the first switch tube V1 and the second switch tube V2 are controlled to be turned on, the first power tube Q1 is controlled to be cut off, the IO1 terminal potential of the chip IC1 to be detected is pulled down, and when the pulse signal output from the IO2 terminal of the chip IC1 to be detected is a square wave signal, the IO10 terminal of the first controller U1 controls the second analog switch U3 to transmit the pulse signal to the waveform conversion device and convert it into a sine wave signal. After 180 phase shift processing by the phase shift device, the signal potential of the superimposed output is zero when the waveform is stable, and the fourth comparator A4 or the fifth comparator A5 outputs high level when the waveform is unstable. The first logic chip J1 outputs the seventh electric signal, which is received by the IO11 terminal of the first controller U1. Similarly, when the pulse signal is a sine wave signal,The IO9 end of the first controller U1 directly transmits the pulse signal to the phase-shifting device for phase-shifting processing, and then judges the waveform stability.

[0083] It is apparent to those skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and that the present application can be carried out in other specific forms without departing from the spirit or essential characteristics of the present application. Accordingly, no matter from which point of view, the embodiments should be considered as exemplary and not restrictive, the scope of the present application being defined by the appended claims rather than by the foregoing description, and it is intended to embrace all changes and modifications that fall within the meaning and scope of equivalency of the claims. Any reference signs in the claims should not be construed as limiting the claims to the figures in which the reference signs are used.

[0084] Furthermore, it should be understood that although the present specification is described in terms of embodiments, not every embodiment according to the present specification needs to exhibit each and every characteristic specified in the embodiments disclosed herein. The specification can also be regarded as a whole in one aspect, and the technical solutions in each embodiment can be properly combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A chip internal circuit aging detection circuit characterized by comprising: The circuit comprises: a power module for power regulation of the accessed power and output of first power; a detection control module connected with the power module and the chip module, for transmission of the first power to the chip module, switching of the transmission path and voltage division of the first power, detection of the resistance of the chip module and output of a first detection signal; a chip module for receiving power and starting, access of an input signal and output of a pulse signal; a resistance detection module connected with the detection control module, for voltage following and differential amplification of the first detection signal and output of a second detection signal; a first judgment module connected with the resistance detection module, for output of a first electric signal, a second electric signal and a third electric signal respectively when the first resistance threshold value, the second resistance threshold value or the third resistance threshold value is greater than the second detection signal; an input detection module connected with the chip module, for voltage drop state detection and signal differential amplification of the input signal and output of a third detection signal; a second judgment module connected with the input detection module and the detection control module, for output of a fourth electric signal, a fifth electric signal and a sixth electric signal respectively when the first voltage drop threshold value, the second voltage drop threshold value or the third voltage drop threshold value is greater than the third detection signal and triggering of the path switching work of the detection control module; an output detection module connected with the chip module, for conversion of the pulse signal into a sine wave signal, phase shift processing and phase shift superposition processing of the sine wave signal or the pulse signal, detection of whether the potential of the superimposed signal is zero and output of a seventh electric signal when the potential is not zero; a micro control module connected with the output detection module, the power module, the detection control module, the first judgment module and the second judgment module, for power regulation of the power module, reception of the first electric signal, the second electric signal, the third electric signal, the fourth electric signal, the fifth electric signal, the sixth electric signal and the seventh electric signal and aging degree judgment, control of the signal transmission path of the output detection module and control of the output detection module for pulse conversion when the pulse signal is a square wave signal; a protection module connected with the power module, the chip module, the first judgment module and the second judgment module, for control of the power module for power-off and control of the chip module for stopping access of the signal when the third electric signal or the sixth electric signal is received.

2. The chip internal circuit aging detection circuit according to claim 1, characterized in that, The power module comprises a power interface, a first power tube, a first diode, a first inductor and a first capacitor; the micro control module comprises a first controller; the first end of the power interface is connected with the drain of the first power tube, the source of the first power tube is connected with the cathode of the first diode and the first end of the first capacitor and the detection control module through the first inductor, the anode of the first diode is connected with the second end of the first capacitor, the second end of the power interface and the ground end, and the gate of the first power tube is connected with the IO1 end of the first controller.

3. The chip internal circuit aging detection circuit according to claim 2, characterized in that, The detection control module comprises a first relay, a first resistor, a second resistor and a first analog switch; the first relay comprises a first relay switch. The first moving terminal and the second moving terminal of the first relay switch are connected with the first terminal of the first capacitor, the first stationary terminal of the first relay switch is connected with the chip module and the first terminal of the first resistor and the IN terminal of the first analog switch through the second resistor, the second terminal of the first resistor is connected with the second stationary terminal of the first relay switch, the control terminal of the first relay switch is connected with the CTRL terminal of the first analog switch, the first judging module and the second judging module, and the OUT terminal of the first analog switch is connected with the resistance value detecting module.

4. The chip internal circuit aging detection circuit according to claim 3, characterized in that, The chip module comprises a chip to be detected and a third resistor; The VCC terminal of the chip to be detected is connected with the first stationary terminal of the first relay switch, the IO1 terminal of the chip to be detected is connected with the input detecting module, and the IO2 terminal of the chip to be detected is connected with the output detecting module and the GND terminal and the ground terminal of the chip to be detected through the third resistor.

5. The chip internal circuit aging detection circuit according to claim 4, characterized in that, The input detecting module comprises a second capacitor, a fourth resistor, a fifth resistor, a third capacitor, a third diode, a second diode, a fifth diode, a fourth diode, a seventh resistor, a first power supply, a first operational amplifier, a sixth resistor, a sixth diode, a second power supply, a third power supply, a seventh diode and an eighth diode; The cathode of the fourth diode is connected with the IO1 terminal of the chip to be detected and one end of the second capacitor and connected with the other end of the second capacitor, one end of the fifth resistor, one end of the third capacitor, the anode of the third diode and the cathode of the fifth diode through the fourth resistor, the cathode of the third diode is connected with the cathode of the second diode, the anode of the second diode is connected with the cathode of the sixth diode, the other end of the third capacitor, the other end of the fifth resistor, the anode of the eighth diode and the ground terminal, the anode of the fifth diode is connected with the anode of the fourth diode and the non-inverting terminal of the first operational amplifier and connected with the first power supply through the seventh resistor, the inverting terminal of the first operational amplifier is connected with the anode of the sixth diode and connected with the third power supply through the sixth resistor, the output terminal of the first operational amplifier is connected with the anode of the seventh diode, the cathode of the eighth diode and the second judging module, and the cathode of the seventh diode is connected with the second power supply.

6. The chip internal circuit aging detection circuit according to claim 5, characterized by, The resistance value detecting module comprises an eighth resistor, a third operational amplifier, a second operational amplifier, a tenth resistor, a ninth resistor and a fourth operational amplifier; The non-inverting terminal of the third operational amplifier is connected with the second terminal of the first resistor, the inverting terminal of the third operational amplifier is connected with the output terminal of the third operational amplifier and connected with the inverting terminal of the fourth operational amplifier, the output terminal of the fourth operational amplifier and the first judging module through the tenth resistor, the non-inverting terminal of the fourth operational amplifier is connected with the output terminal and the inverting terminal of the second operational amplifier through the ninth resistor, and the non-inverting terminal of the second operational amplifier is connected with the OUT terminal of the first analog switch through the eighth resistor.

7. The chip internal circuit aging detection circuit according to claim 6, characterized by, The first judging module comprises a first reference power supply, a ninth diode, a twelfth diode, a first comparator, a second comparator and a third comparator; The first reference power supply is connected with the inverting terminal of the first comparator and the anode of the ninth diode, the cathode of the ninth diode is connected with the inverting terminal of the second comparator, the non-inverting terminal of the first comparator, the non-inverting terminal of the second comparator and the non-inverting terminal of the third comparator are all connected with the output terminal of the fourth operational amplifier, and the output terminal of the first comparator, the output terminal of the second comparator and the output terminal of the third comparator are respectively connected with the IO2 terminal, the IO3 terminal and the IO4 terminal of the first controller.

8. The chip internal circuit aging detection circuit according to claim 7, characterized by, The second judging module comprises a second reference power supply, an electric energy comparison device, an eleventh diode, a tenth diode and a thirteenth diode; The reference end of the electric energy comparison device is connected with the second reference power supply, the input end of the electric energy comparison device is connected with the output end of the first operational amplifier, the first output end of the electric energy comparison device is connected with the anode of the eleventh diode and the IO5 end of the first controller, the second output end of the electric energy comparison device is connected with the anode of the tenth diode and the IO6 end of the first controller, the third output end of the electric energy comparison device is connected with the anode of the thirteenth diode and the IO7 end of the first controller, the cathode of the eleventh diode is connected with the cathode of the tenth diode, the cathode of the thirteenth diode and the CTRL end of the first analog switch.

9. The chip internal circuit aging detection circuit according to claim 8, characterized by, The output detecting module comprises a second analog switch, a waveform conversion device, an eleventh resistor, a twelfth resistor, a phase shifting device, a fourth comparator, a fifth comparator and a first logic chip; The IN1 end and the IN2 end of the second analog switch are both connected with the IO8 end of the first controller, the OUT1 end of the second analog switch is connected with the input end of the phase shifting device and the output end of the waveform conversion device and is connected with one end of the twelfth resistor through the eleventh resistor, the inverting end of the fifth comparator and the non-inverting end of the fourth comparator, the OUT2 end of the second analog switch is connected with the input end of the waveform conversion device, the output end of the phase shifting device is connected with the other end of the twelfth resistor, the inverting end of the fourth comparator is connected with the non-inverting end of the fifth comparator and the ground end, the output end of the fourth comparator and the output end of the fifth comparator are respectively connected with the A end and the B end of the first logic chip, the Y end of the first logic chip is connected with the IO11 end of the first controller, the CTRL1 end and the CTRL2 end of the second analog switch are respectively connected with the IO9 end and the IO10 end of the first controller.

10. The chip internal circuit aging detection circuit according to claim 8, characterized in that, The protection module comprises a fourteenth diode, a fifteenth diode, a first switching tube and a second switching tube; The anode of the fourteenth diode and the anode of the fifteenth diode are respectively connected with the third output end of the electric energy comparison device and the output end of the first comparator, the cathode of the fourteenth diode is connected with the cathode of the fifteenth diode, the base of the first switching tube and the base of the second switching tube, the collector of the first switching tube is connected with the gate of the first power tube, the collector of the second switching tube is connected with the IO1 end of the chip to be detected, and the emitter of the first switching tube and the emitter of the second switching tube are both grounded.

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