Chip debugging device and method based on SPI (Serial Peripheral Interface) and multi-chip interconnection debugging structure

Abstract

The invention provides a chip debugging device and method based on an SPI and a multi-chip interconnection debugging structure, and relates to the technical field of chip debugging, and the chip debugging device comprises a plurality of SPI to AMBA interface modules; the plurality of SPI to AMBA interface modules communicate with the same SPI main equipment and are respectively connected to different devices to be debugged so as to debug the devices to be debugged by sharing SPI signals of the SPI main equipment; each SPI to AMBA interface module is provided with a unique input identifier; the SPI to AMBA interface module is used for: receiving an SPI command from an SPI master device; comparing the input identifier with an identifier domain segment in the SPI command; if the comparison result is consistent, the SPI command is analyzed, and a corresponding AMBA bus access command is generated, so that the device to be debugged executes corresponding operation based on the AMBA bus access command, and a command execution result fed back by the device to be debugged is sent to the SPI master device. According to the invention, on the premise that hardware pin resources are not increased, rapid identification and accurate debugging control of a plurality of chip modules are realized.

Description

Technical Field

[0001] The present application relates to the field of chip debugging technology, and in particular to a chip debugging device and method based on SPI and a multi-chip interconnected debugging structure. Background Art

[0002] After chip tape-out, during the debugging phase, engineers often need external access to key internal chip registers and memory to quickly identify issues. This access is crucial for functional verification, fault analysis, and performance optimization. To meet this requirement, debug interfaces are widely used in the industry for chip debugging. The Joint Test Action Group (JTAG) interface is the most widely used standard debug interface.

[0003] JTAG was originally used primarily for boundary-scan testing at the printed circuit board (PCB) level. With the advancement of semiconductor technology, its functionality has gradually expanded to include chip-level debugging, and it has become widely used in chip design and verification processes. The JTAG interface offers advantages such as a flexible structure and support for both one-to-one and daisy-chain cascade access, making it particularly suitable for unified debugging of multiple modules in complex systems. However, the JTAG interface has a relatively low transmission rate, with a clock frequency generally not exceeding 25MHz. When multiple debug targets are daisy-chained, debug commands must sequentially traverse each node in the link, increasing debug link latency and reducing access efficiency. Furthermore, once a chip enters mass production, the JTAG interface is typically closed, making it difficult to use for on-site debugging.

[0004] To increase the access speed of debug interfaces and expand debugging applications, existing technologies have proposed chip debugging using the SPI (Serial Peripheral Interface). The SPI interface is a common serial peripheral communication interface with high transmission speeds, minimal hardware resource usage, and a simple protocol structure. Therefore, it is used in some designs as a replacement for the JTAG interface for debugging. Existing SPI debugging solutions often convert the SPI protocol into an internal chip system bus protocol, such as AXI or APB, and inject debug commands into the system bus for resource access.

[0005] However, existing SPI debugging solutions still have several technical limitations. First, they rely on the availability of the chip's internal system bus. If a bus anomaly (such as a hang) occurs during debugging, the debug path is interrupted, the debugging system fails, and they lack independence and robustness. Second, these solutions are primarily designed for single-chip or single-die (bare chip) structures and do not support multi-die packaging or cascaded debugging of multiple chips. To support multiple dies, multiple SPI interfaces must be configured, which not only increases hardware complexity but also consumes a large amount of I / O resources.

[0006] In summary, the existing debug interface solutions are difficult to simultaneously meet the requirements of efficient access, bus decoupling and multi-chip adaptability, and an urgent solution is needed. Summary of the Invention

[0007] In response to the problems in the prior art, the embodiments of the present application provide a chip debugging device, method and multi-chip interconnection debugging structure based on SPI, which can solve the problems of the existing debugging method in complex chip systems, such as low speed, long access link, dependence on the system bus structure and difficulty in expansion, and difficulty in meeting the requirements of flexibility and efficiency in the wafer debugging and batch debugging stages.

[0008] In a first aspect, the present application provides an SPI-based chip debugging device, comprising: a plurality of SPI to AMBA interface modules;

[0009] The multiple SPI to AMBA interface modules communicate with the same SPI master device and are respectively connected to different devices to be debugged, so as to debug the devices to be debugged by sharing the SPI signal of the SPI master device; each SPI to AMBA interface module has a unique input identifier; the SPI signal includes an SPI command;

[0010] The SPI to AMBA interface module is used for:

[0011] Receiving the SPI command from the SPI master device;

[0012] Comparing the input identifier with the identifier field in the SPI command;

[0013] If the comparison results are consistent, the SPI command is parsed and a corresponding AMBA bus access command is generated, so that the device to be debugged performs a corresponding operation based on the AMBA bus access command, and the command execution result fed back by the device to be debugged is sent to the SPI master device.

[0014] Furthermore, the SPI to AMBA interface module is an SPI to APB interface module; the SPI to APB interface module includes a first SPI slave interface module and a first SPI slave control module; the AMBA bus access command includes an APB access command;

[0015] The first SPI slave interface module is used to receive SPI commands from the SPI master device;

[0016] The first SPI slave control module is used to convert the SPI command into the APB access command.

[0017] Furthermore, the SPI to AMBA interface module is an SPI to AXI interface module; the SPI to AXI interface module includes a second SPI slave interface module and a second SPI slave control module; the AMBA bus access command includes an AXI access command;

[0018] The second SPI slave interface module is used to receive SPI commands from the SPI master device;

[0019] The second SPI slave control module is used to convert the SPI command into the AXI access command.

[0020] Furthermore, the SPI to AMBA interface module is provided with multiple clock domains; the clock domains include the SPI interface clock, the on-chip high-frequency sampling clock and the AMBA bus interface clock;

[0021] The SPI interface clock is used to drive the serial communication between the SPI master device and the SPI to AMBA interface module;

[0022] The on-chip high-frequency sampling clock is used to drive the SPI to AMBA interface module to perform data input and output;

[0023] The AMBA bus interface clock is used to drive the bus access operation between the SPI to AMBA interface module and the device to be debugged.

[0024] Furthermore, the bit width of the identification field segment is 8 bits.

[0025] Furthermore, the SPI master device identifies and addresses 256 different SPI-to-AMBA interface modules based on the identification field.

[0026] Furthermore, the SPI commands include write commands, read commands, status query commands and data read commands;

[0027] The write command is used to write data to a specified address of the device to be debugged;

[0028] The read command is used to read data from a specified address of the device to be debugged;

[0029] The status query command is used to obtain the execution status information of the previous command;

[0030] The data read command is used to read the return result of the previous read command.

[0031] Furthermore, the SPI signal also includes: an SPI interface clock signal and a chip select signal;

[0032] The SPI interface clock signal is used to synchronize the data transmission timing between the SPI master device and the SPI to AMBA interface module;

[0033] The chip select signal is used to enable the communication function of the SPI to AMBA interface module and control it to receive or send data during a valid chip select period.

[0034] In a second aspect, the present application provides an SPI-based chip debugging method, which is applied to the SPI-to-AMBA interface module in the SPI-based chip debugging device described in any of the above embodiments, comprising:

[0035] Receiving the SPI command from the SPI master device;

[0036] Comparing the input identifier with the identifier field in the SPI command;

[0037] If the comparison results are consistent, the SPI command is parsed and a corresponding AMBA bus access command is generated to enable the device to be debugged to perform a corresponding operation, and the command execution result fed back by the device to be debugged is sent to the SPI master device.

[0038] In a third aspect, the present application provides a chip, comprising the SPI-based chip debugging device described in any of the above embodiments.

[0039] In a fourth aspect, the present application provides a multi-chip interconnect debugging structure, comprising a plurality of the chips described above.

[0040] In a fifth aspect, the present application provides an electronic device comprising the chip described above.

[0041] The present application provides an SPI-based chip debugging device, method, and multi-chip interconnect debugging structure. The SPI-based chip debugging device includes: multiple SPI-to-AMBA interface modules; the multiple SPI-to-AMBA interface modules communicate with the same SPI master device and are respectively connected to different devices to be debugged, so as to debug the devices to be debugged by sharing the SPI signal of the SPI master device; each SPI-to-AMBA interface module has a unique input identifier; the SPI signal includes an SPI command; the SPI-to-AMBA interface module is used to: receive the SPI command from the SPI master device; compare the input identifier with the identifier field in the SPI command; if the comparison result is consistent, parse the SPI command and generate a corresponding AMBA bus access command, so that the device to be debugged performs the corresponding operation based on the AMBA bus access command, and sends the command execution result fed back by the device to be debugged to the SPI master device. The SPI-based chip debugging device, method, and multi-chip interconnect debugging structure provided by the present application realize rapid identification and precise debugging control of multiple chip modules without increasing hardware pin resources.

[0042] Among them, the debugging operation capability of multiple devices to be debugged is realized through multiple SPI-to-AMBA interface modules, meeting the demand for parallel debugging of multiple modules in complex chip systems; the input ends of the multiple SPI-to-AMBA interface modules are respectively connected to the SPI signal lines of the same SPI master device to share the SPI signals of the SPI master device, thereby realizing unified access of multiple modules without increasing pin resources, improving signal utilization and simplifying the hardware wiring structure; each SPI-to-AMBA interface module has a unique input identifier, thereby realizing unique identification and positioning of multiple modules, ensuring that debugging commands can accurately act on the devices to be debugged, and avoiding conflicts or misoperations.

[0043] By receiving the SPI command from the SPI master device, a communication path can be established between the main control and each module, ensuring that external debugging instructions can be correctly transmitted into the system; by comparing the input identifier and the identifier field in the SPI command, it can be ensured that the debugging command only acts on the selected device to be debugged, thereby improving the reliability and security of system debugging; by parsing the SPI command and generating a corresponding AMBA bus access command when the comparison results are consistent, so as to execute the corresponding operation, thereby achieving effective triggering of the function of the device to be debugged under command drive and supporting flexible debugging access control; by not responding to the SPI command when the comparison results are inconsistent, it can avoid that the non-device to be debugged responds to irrelevant commands, thereby improving the specificity of debugging behavior and system stability; by returning the command execution result to the SPI master device after the operation is completed, closed-loop feedback of the debugging result is achieved, which facilitates the host computer to judge the operation status and perform subsequent control. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 This is a schematic diagram of the structure of an SPI-based chip debugging device provided in one embodiment of the present application;

[0046] Figure 2 This is a structural diagram of an SPI to APB interface module provided in one embodiment of the present application;

[0047] Figure 3 This is a schematic diagram of the structure of the SPI to AXI interface module provided in one embodiment of the present application;

[0048] Figure 4 This is a schematic diagram of the structure of an SPI-based chip debugging device provided in one embodiment of the present application;

[0049] Figure 5 This is a flow chart of a chip debugging method based on SPI provided in one embodiment of the present application;

[0050] Figure 6 This is a structural diagram of a multi-chip interconnect debugging structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0051] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clearly understood, the embodiments of the present application are further described in detail below with reference to the accompanying drawings. The illustrative embodiments of the present application and their descriptions are used to explain the present application but are not intended to limit the present application. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present application may be combined with each other in any manner.

[0052] SPI (Serial Peripheral Interface) is a serial peripheral interface that allows microcontrollers to communicate with various peripheral devices in a serial manner to exchange information. AMBA (Advanced Microcontroller Bus Architecture) is a bus architecture used in the ARM architecture, developed by Arm International Technology in 1996. It plays an important role in very large-scale integrated circuit design. APB (Advanced Peripheral Bus) is a bus protocol developed by ARM and is one of the AMBA bus architectures. It is mainly used to connect low-bandwidth peripherals. AXI (Advanced eXtensible Interface) is a bus protocol and the most important part of ARM's AMBA (Advanced Microcontroller Bus Architecture). It is an intra-chip bus designed for high performance, high bandwidth, and low latency. JTAG, short for Joint Test Action Group, is the common name for IEEE Standard 1149.1, Standard Test Access Port and Boundary Scan Architecture. This standard is used to verify the functionality of designs and tests of manufactured printed circuit boards.

[0053] Figure 1 FIG. 1 is a schematic diagram of the structure of a chip debugging device based on SPI provided in an embodiment of the present application. Figure 1 As shown, the SPI-based chip debugging device provided by this application includes: multiple SPI to AMBA interface modules (SPI2AMBA modules);

[0054] The multiple SPI-to-AMBA interface modules communicate with the same SPI master device (SPI master) and are respectively connected to different devices to be debugged (device 0 to device n) to debug the devices to be debugged by sharing the SPI signal of the SPI master device; each SPI-to-AMBA interface module has a unique input identifier; the SPI signal includes an SPI command;

[0055] The SPI to AMBA interface module is used for:

[0056] Receiving the SPI command from the SPI master device;

[0057] Comparing the input identifier with the identifier field in the SPI command;

[0058] If the comparison results are consistent, the SPI command is parsed and a corresponding AMBA bus access command is generated, so that the device to be debugged performs a corresponding operation based on the AMBA bus access command, and the command execution result fed back by the device to be debugged is sent to the SPI master device.

[0059] Specifically, the SPI-based chip debugging device can access and control multiple devices to be debugged through a standard SPI interface during the chip debugging phase, thereby improving the integration and resource reuse capabilities of the debugging system.

[0060] This chip debugging device includes multiple SPI-to-AMBA interface modules, each deployed within the chip and connected to its corresponding device to be debugged. These modules are used to control access to and debug the device. These modules communicate with the same external SPI master device, sharing the master's SPI signals. This means the entire debugging architecture only requires one set of SPI interfaces to connect to multiple interface modules, simplifying system wiring, reducing pin usage, and improving overall scalability.

[0061] Each SPI-to-AMBA interface module has a unique input identifier (id[7:0]), which can be used to distinguish the identity information of different modules during communication, allowing multiple modules to share the same SPI channel. When the SPI master device sends an SPI command to the chip, it includes an identifier field in the command to indicate the identifier of the target SPI-to-AMBA interface module.

[0062] After receiving an SPI command from the SPI master, each SPI-to-AMBA interface module compares its input identifier with the identifier field in the SPI command. If the comparison results match, the command is intended for that module. The module then parses the SPI command and generates the corresponding AMBA bus access command, enabling the device to perform debug operations based on the AMBA bus access command, such as register reads and writes. If the comparison results are inconsistent, the module does not respond to the SPI command, thus avoiding communication interference and erroneous access.

[0063] In addition, after the command operation is completed, the SPI to AMBA interface module will convert the command execution result into an SPI signal and feed it back to the SPI master device through the OR gate, realizing closed-loop transmission of the operation result, making it easier for the upper debugging system to obtain the execution status, data content or error information, etc., thereby enhancing the controllability and observability of the debugging operation.

[0064] In one embodiment, the device to be debugged includes a CPU main system, an Ethernet port, a direct memory access (DMA), a bus, and a PCIe high-speed interface.

[0065] Through the above structure and mechanism, the SPI-based chip debugging device provided in this application can achieve precise debugging access to multiple modules while minimizing hardware interface overhead, effectively improving the operability and engineering efficiency of multi-module chips during the development and debugging stage.

[0066] Figure 2 This is a schematic diagram of the structure of the SPI to APB interface module provided in one embodiment of the present application. Figure 2 As shown, the SPI to AMBA interface module is a SPI to APB interface module (SPI2APB module); the SPI to APB interface module includes a first SPI slave interface module spi slave and a first SPI slave control module spi slave ctrl0;

[0067] The first SPI slave interface module is used to receive SPI commands from the SPI master device;

[0068] The first SPI slave control module is used to convert the SPI command into an APB access command.

[0069] Specifically, the SPI-to-AMBA interface module is an SPI-to-APB interface module or an SPI-to-AXI interface module. The SPI-to-APB interface module is used to convert received SPI commands into APB bus access commands that can be executed within the device to be debugged, thereby enabling debug access to APB slave devices within the chip. The SPI-to-APB interface module includes: a first SPI slave interface module and a first SPI slave control module.

[0070] The first SPI slave interface module is used to communicate with the SPI master device and receive SPI commands sent by the SPI master device. This interface module follows the standard SPI communication protocol and extracts information such as command words, address fields, and control fields from the serialized data stream by receiving the clock signal, chip select signal, and data signal sent by the SPI master device.

[0071] The first SPI slave control module is connected to the first SPI slave interface module and is configured to parse and process received SPI commands. The first SPI slave control module extracts valid control information from received SPI commands and, based on the type and content of the SPI command, generates corresponding APB access commands, including read or write operations on the APB bus.

[0072] With this structure, the SPI master device can issue debug commands to the device being debugged via the standard SPI interface. The SPI to APB interface module receives the commands and completes protocol conversion, enabling access control to APB bus devices within the chip and ensuring the timing and protocol consistency of debug operations. This architecture also effectively improves the versatility and flexibility of chip debugging, making it applicable to multiple chip architectures that include APB bus subsystems.

[0073] Figure 3 This is a schematic diagram of the structure of the SPI to AXI interface module provided in one embodiment of the present application. Figure 3 As shown, the SPI to AMBA interface module is a SPI to AXI interface module (SPI2AXI module); the SPI to AXI interface module includes a second SPI slave interface module spi slave and a second SPI slave control module spi slave ctrl1;

[0074] The second SPI slave interface module is used to receive SPI commands from the SPI master device;

[0075] The second SPI slave control module is used to convert the SPI command into an AXI access command.

[0076] Specifically, the SPI-to-AMBA interface module is an SPI-to-APB interface module or an SPI-to-AXI interface module. The SPI-to-AXI interface module is used to convert debug commands sent by the SPI master device into access commands that comply with the AXI protocol, thereby enabling access and control of the chip's internal AXI bus resources. The SPI-to-AXI interface module includes: a second SPI slave interface module and a second SPI slave control module.

[0077] The second SPI slave interface module is used to receive SPI commands from the SPI master device. This module operates in SPI slave mode, receiving the clock signal, chip select signal, and serial data stream from the SPI master device according to the SPI communication protocol. It synchronizes and caches the received serialized command data, providing input data for subsequent parsing and processing.

[0078] The second SPI slave control module is connected to the second SPI slave interface module and is responsible for parsing the control information, address field, and any data field contained in the SPI command and generating the corresponding AXI access command according to the AXI protocol specification. Depending on the command type, this module can execute AXI write or read transactions to access devices to be debugged mounted on the AXI bus within the chip, such as high-performance control units or on-chip storage resources.

[0079] Through this structure, an SPI master device can use a unified SPI interface to communicate with multiple SPI-to-AXI interface modules, issuing standardized SPI commands to complete the AXI read and write operations required to debug the device being debugged, thereby achieving a protocol bridge between debug access and the AXI bus. This structure is suitable for system scenarios where an AXI interconnect structure exists within the chip, and offers excellent scalability and debugging efficiency.

[0080] In one embodiment, if Figure 4 As shown, the SPI-based chip debugging device includes one or more SPI to APB interface modules and / or one or more SPI to AXI interface modules. This application is not limited to the number of SPI to APB interface modules and SPI to AXI interface modules.

[0081] In one embodiment, if Figure 1 As shown, the SPI signal lines include a clock signal line (sclk signal line), a chip select signal line (cs signal line) and a data signal line (din / dout signal line).

[0082] Specifically, the SPI signal lines include clock signal lines, chip select signal lines and data signal lines, which are used to complete the communication between the SPI master device and each SPI to AMBA interface module.

[0083] The clock signal line is used to transmit the serial clock signal generated by the SPI master device. This signal serves as a synchronization reference to ensure the timing consistency of data transmission between the master and slave devices in SPI communication. The chip select signal line is used to indicate the validity of SPI communication. When the chip select signal is valid, the slave device starts to receive or send data. The data signal line is used to carry the actual SPI command data.

[0084] The three SPI signal lines described above enable a universal communication mechanism between a master device and multiple SPI-to-AMBA interface modules. All SPI-to-AMBA interface modules share the same set of SPI signal lines, and each module determines whether to respond to the current communication based on the identification field carried in the command. This avoids the need to configure a separate chip select line for each slave device in the traditional one-to-many SPI architecture, significantly reducing I / O resource usage and improving the integration and scalability of the system debugging architecture.

[0085] In one embodiment, if Figure 2 and Figure 3 As shown, the SPI to AMBA interface module sets multiple clock domains; the clock domains include the SPI interface clock, the on-chip high-frequency sampling clock and the AMBA bus interface clock;

[0086] The SPI interface clock is used to drive the serial communication between the SPI master device and the SPI to AMBA interface module;

[0087] The on-chip high-frequency sampling clock is used to drive the SPI to AMBA interface module to perform data input and output;

[0088] The AMBA bus interface clock is used to drive the bus access operation between the SPI to AMBA interface module and the device to be debugged.

[0089] Specifically, the clock domain of the SPI to AMBA interface module includes the SPI interface clock sclk, the on-chip high-frequency sampling clock ssi_clk, and the AMBA bus interface clock pclk, which are used to drive the workflow of different functional modules respectively.

[0090] The SPI interface clock is used to synchronize communications with the SPI master device and serves as the basic timing reference for SPI protocol communications. The on-chip high-frequency sampling clock drives the SPI-to-AMBA interface module for data input and output, ensuring reliable data reception and command parsing. The AMBA bus interface clock drives the AMBA protocol interface, ensuring that access requests after command conversion are correctly and stably applied to the device or resource being debugged within the chip. Decoupling the on-chip high-frequency sampling clock and the AMBA bus interface clock improves module flexibility.

[0091] The division and coordination of these three clock domains effectively decouples the communication domain from the bus access domain, improving the module's clock adaptability and system compatibility. This multi-clock domain design is not only suitable for debugging communication scenarios between master devices and chip systems with large clock frequency differences, but also facilitates data isolation and timing stability control between different modules, improving the reliability and flexibility of the entire system.

[0092] In one embodiment, the bit width of the identification field is 8 bits.

[0093] Specifically, the bit width of the identification field in the SPI command is 8 bits, which is used to distinguish and address different SPI to AMBA interface modules in a multi-module debugging system.

[0094] When the SPI master generates and sends a debug command, it includes an 8-bit identification field in the command structure. This field identifies the target receiving module for the command. In the chip debug device, each SPI-to-AMBA interface module is preconfigured with a unique 8-bit input identifier for comparison with the identification field in the command.

[0095] The above design scheme significantly improves the module expansion capability and logic access clarity of the chip debugging system, and provides effective addressing means and scheduling control capabilities for large-scale integrated debugging architecture.

[0096] In one embodiment, the SPI master device identifies and addresses 256 different SPI-to-AMBA interface modules based on the identification field.

[0097] Specifically, the identification field is 8 bits wide and can represent up to 256 different identifiers, allowing the deployment of up to 256 SPI-to-AMBA interface modules in the chip. The SPI master device uses the identification field to identify and address each of these 256 different SPI-to-AMBA interface modules. This identification mechanism enables unique addressing and independent access to each module, even when all modules share the same set of SPI signal lines. This ensures that debug commands are accurately delivered to the device being debugged, while avoiding command conflicts or incorrect responses.

[0098] In one embodiment, the SPI command includes a write command, a read command, a status query command, and a data read command;

[0099] The write command is used to write data to a specified address of the device to be debugged;

[0100] The read command is used to read data from a specified address of the device to be debugged;

[0101] The status query command is used to obtain the execution status information of the previous command;

[0102] The data read command is used to read the return result of the previous read command.

[0103] Specifically, SPI commands include write commands, read commands, status query commands, and data read commands, which correspond to different types of debugging operation requirements.

[0104] Among them, the write command is used to write data to the specified address of the device to be debugged, which is used to configure or modify the control registers or operating parameters of the device to be debugged; the read command is used to read data from the specified address of the device to be debugged, so as to obtain the current status of the register or internal operating information; the status query command is used to obtain the execution status of the last debug command (such as a write or read operation), such as whether it was completed successfully, whether a timeout or access error occurred, etc.; and the data read command is used to read the return result from the device to be debugged after issuing the read command, completing the debug data return process.

[0105] Through the above command design, a complete and logically clear debugging control system can be built based on the SPI communication protocol. It supports classified command processing and asynchronous result return, improving the flexibility and fault tolerance of system debugging operations. At the same time, this command system is adaptable to different types of SPI-to-AMBA interface modules, facilitating the design of unified control structures and cross-module protocol reuse.

[0106] In one embodiment, if Figure 1 As shown, the SPI signal also includes: an SPI interface clock signal and a chip select signal;

[0107] The SPI interface clock signal is used to synchronize the data transmission timing between the SPI master device and the SPI to AMBA interface module;

[0108] The chip select signal is used to enable the communication function of the SPI to AMBA interface module and control it to receive or send data during a valid chip select period.

[0109] In one embodiment, the SPI to AMBA interface module uses the standard SPI protocol for communication. Since the SPI protocol itself does not specify the data format, this application customizes the SPI command format based on the access requirements of the APB and AXI buses, adding necessary fields such as address, data, and transaction ID to adapt to access operations of the corresponding bus protocols.

[0110] To address the issue of traditional SPI one-to-many connections requiring multiple chip select signals, this application introduces the spi_id field in SPI commands. This field is used to identify the device to be debugged. Multiple SPI-to-AMBA interface modules can share a set of SPI signals, enabling selective response by comparing spi_ids. This simplifies hardware wiring and improves system scalability and debugging efficiency.

[0111] In one embodiment, the write command write_cmd is fixed at 128 bits and is sent by the SPI master device to write data to a certain address on the chip. It consists of three parts: the first 16 bits are cmd, with a value of 0xA0+spi_id. spi_id is an 8-bit value used to indicate which SPI-to-AMBA interface module the SPI master device wants to communicate with. Therefore, the entire bus supports a maximum of 256 SPI-to-AMBA interface modules. Then comes the 32-bit addr and the 32-bit data. Its format is shown in Table 1:

[0112] Table 1

[0113]

[0114] In one embodiment, the read command read_cmd is fixed to 96 bits and is sent by the SPI master device to read a certain address in the chip. It consists of two parts. The first 16 bits are cmd, with a value of 0xA1+spi_id, followed by a 32-bit addr. Its format is shown in Table 2:

[0115] Table 2

[0116]

[0117] In one embodiment, the status query command get_status is fixed at 48 bits and is used by the SPI master device to obtain the status of the previous pen transmission. It consists of three parts: the first 16 bits are cmd, with a value of 0xA2+spi_id, followed by a 16-bit idle beat to allow the SPI to AMBA interface module time to parse the cmd and prepare the status value, and finally the 16-bit status value. Its format is shown in Table 3:

[0118] Table 3

[0119]

[0120] In one embodiment, the format of the status information (status) is 0xAAxx, where only bits [4:0] are valid bits, and the meanings of each bit are as follows:

[0121] Bit 0 indicates that a timeout error occurred in the previous write_cmd or read_cmd command (timeouterror);

[0122] bit1: indicates that a slave error (slaveerror) occurred in the previous write_cmd or read_cmd command;

[0123] bit2: indicates that the cmd field in the previous command is undefined;

[0124] bit3: indicates that the previous operation has not been completed and is still being processed. You can continue to wait by polling;

[0125] bit4: Indicates that the SPI master device sends a new command before the previous write_cmd or read_cmd is completed.

[0126] When bits [4:0] are all 0, it indicates that the previous write_cmd or read_cmd command was successfully completed without any errors. If the previous command was a write_cmd, you can continue to send new commands; if it was a read_cmd, you can then send a read_data command to obtain the read result.

[0127] In one embodiment, the data read command read_data is fixed at 64 bits and is sent by the SPI master device to obtain the result of the previous read command read_cmd. It consists of three parts: the first 16 bits are cmd, with a value of 0xA3+spi_id, followed by a 16-bit idle beat to allow the SPI to AMBA interface module time to parse cmd and prepare the value of data, and finally the value of data. Its format is shown in Table 4:

[0128] Table 4

[0129]

[0130] This application can be applied to all chips that contain SPI interfaces. It is only necessary to instantiate the SPI to AMBA interface module as needed during the chip design phase, assign a unique ID value, and interconnect the SPI to AMBA interface modules at the top level according to the solution. This application can also be applied to normal business data transmission between dies or chips. Existing low-speed peripheral interfaces between dies or chips usually require both parties to have a CPU to control the SPI interface, read and parse the data content, and then write the data content to the destination address. This application does not rely on the CPU on the slave side, so some business data between dies or chips that require delay stability can be unloaded from the CPU to the hardware, such as timestamps, heartbeat packets, some error or status reports, etc., to avoid delays introduced by the CPU software program.

[0131] The present application provides an SPI-based chip debugging device, comprising: multiple SPI-to-AMBA interface modules; the multiple SPI-to-AMBA interface modules communicate with the same SPI master device and are respectively connected to different devices to be debugged, so as to debug the devices to be debugged by sharing the SPI signal of the SPI master device; each SPI-to-AMBA interface module has a unique input identifier; the SPI signal includes an SPI command; the SPI-to-AMBA interface module is used to: receive the SPI command from the SPI master device; compare the input identifier with the identifier field in the SPI command; if the comparison result is consistent, parse the SPI command and generate a corresponding AMBA bus access command, so that the device to be debugged performs the corresponding operation based on the AMBA bus access command, and sends the command execution result fed back by the device to be debugged to the SPI master device. The SPI-based chip debugging device provided by the present application realizes rapid identification and precise debugging control of multiple chip modules without increasing hardware pin resources.

[0132] Among them, the debugging operation capability of multiple devices to be debugged is realized through multiple SPI-to-AMBA interface modules, meeting the demand for parallel debugging of multiple modules in complex chip systems; the input ends of the multiple SPI-to-AMBA interface modules are respectively connected to the SPI signal lines of the same SPI master device to share the SPI signals of the SPI master device, thereby realizing unified access of multiple modules without increasing pin resources, improving signal utilization and simplifying the hardware wiring structure; each SPI-to-AMBA interface module has a unique input identifier, thereby realizing unique identification and positioning of multiple modules, ensuring that debugging commands can accurately act on the devices to be debugged, and avoiding conflicts or misoperations.

[0133] By receiving the SPI command from the SPI master device, a communication path can be established between the main control and each module, ensuring that external debugging instructions can be correctly transmitted into the system; by comparing the input identifier and the identifier field in the SPI command, it can be ensured that the debugging command only acts on the selected device to be debugged, thereby improving the reliability and security of system debugging; by parsing the SPI command and generating a corresponding AMBA bus access command when the comparison results are consistent, so as to execute the corresponding operation, thereby achieving effective triggering of the function of the device to be debugged under command drive and supporting flexible debugging access control; by not responding to the SPI command when the comparison results are inconsistent, it can avoid that the non-device to be debugged responds to irrelevant commands, thereby improving the specificity of debugging behavior and system stability; by returning the command execution result to the SPI master device after the operation is completed, closed-loop feedback of the debugging result is achieved, which facilitates the host computer to judge the operation status and perform subsequent control.

[0134] This application also provides a chip debugging method based on SPI. Figure 5 FIG. 1 is a flow chart of a chip debugging method based on SPI provided in an embodiment of the present application, such as Figure 5 As shown, the SPI-based chip debugging method includes:

[0135] S501: Receive the SPI command from the SPI master device;

[0136] S502: Compare the input identifier with the identifier field in the SPI command;

[0137] S503: If the comparison results are consistent, the SPI command is parsed and a corresponding AMBA bus access command is generated to enable the device to be debugged to perform a corresponding operation, and the command execution result fed back by the device to be debugged is sent to the SPI master device.

[0138] The present application provides an SPI-based chip debugging method, which receives the SPI command from the SPI master device; compares the input identifier with the identifier field in the SPI command; if the comparison results are consistent, parses the SPI command and generates a corresponding AMBA bus access command to enable the device to be debugged to perform the corresponding operation, and sends the command execution result fed back by the device to be debugged to the SPI master device, thereby achieving rapid identification and precise debugging control of multiple chip modules without increasing hardware pin resources.

[0139] Among them, by receiving the SPI command from the SPI master device, a communication path can be established between the main control and each module, ensuring that external debugging instructions can be correctly transmitted into the system; by comparing the input identifier and the identifier field in the SPI command, it can be ensured that the debugging command only acts on the selected device to be debugged, thereby improving the reliability and security of system debugging; by parsing the SPI command and generating a corresponding AMBA bus access command when the comparison results are consistent, so as to execute the corresponding operation, thereby achieving effective triggering of the function of the device to be debugged under command drive and supporting flexible debugging access control; by not responding to the SPI command when the comparison results are inconsistent, it can avoid that the non-device to be debugged responds to irrelevant commands, thereby improving the specificity of debugging behavior and system stability; by returning the command execution result to the SPI master device after the operation is completed, closed-loop feedback of the debugging result is achieved, which facilitates the host computer to judge the operation status and perform subsequent control.

[0140] The present application also provides a chip, comprising the SPI-based chip debugging device described in any of the above embodiments.

[0141] This application also provides a multi-chip interconnect debugging structure, Figure 6This is a schematic diagram of a multi-chip interconnect debugging structure provided by an embodiment of the present application. Figure 6 As shown, the multi-chip interconnect debugging structure includes multiple chips mentioned above.

[0142] In one embodiment, a multi-chip interconnect debugging structure consists of four chip dies, each of which integrates 30 subsystems. An SPI-to-AMBA interface module (SPI2AMBA module) is instantiated at the entry point of each subsystem, and each module is assigned a unique ID. Specifically, the lower seven bits (bits [6:0]) of the ID, ranging from 0 to 29, correspond to each subsystem within the die; the upper two bits (bits [7:6]) serve as the die identifier (die ID).

[0143] Within the same die, the SPI signals are interconnected as follows: the chip select signal (cs), data signal (din), and clock signal (sclk) are input from the pad and connected to the input terminals of all SPI2AMBA modules in the die. The dout signal is output by each module, combined through "OR" logic at the top level of the die, and then output to the pad.

[0144] The SPI signal interconnection between multiple dies is as follows: the cs, din, and sclk signals are input from chip pins and fed into each die's input pads; each die's dout signal is connected to a chip pin via its output pad. Ultimately, the chip only needs to provide a set of cs, din, and sclk signal lines, as well as four dout signal lines (dout0, dout1, dout2, and dout3) from each die. These dout signals are logically combined on the printed circuit board (PCB) to interface with an external SPI master device, enabling unified debugging access.

[0145] The present application provides an SPI-based chip debugging device, method, and multi-chip interconnect debugging structure. The SPI-based chip debugging device includes: multiple SPI-to-AMBA interface modules; the multiple SPI-to-AMBA interface modules communicate with the same SPI master device and are respectively connected to different devices to be debugged, so as to debug the devices to be debugged by sharing the SPI signal of the SPI master device; each SPI-to-AMBA interface module has a unique input identifier; the SPI signal includes an SPI command; the SPI-to-AMBA interface module is used to: receive the SPI command from the SPI master device; compare the input identifier with the identifier field in the SPI command; if the comparison result is consistent, parse the SPI command and generate a corresponding AMBA bus access command, so that the device to be debugged performs the corresponding operation based on the AMBA bus access command, and sends the command execution result fed back by the device to be debugged to the SPI master device. The SPI-based chip debugging device, method, and multi-chip interconnect debugging structure provided by the present application realize rapid identification and precise debugging control of multiple chip modules without increasing hardware pin resources.

[0146] Among them, the multi-chip interconnected debugging structure realizes the unified identification and distributed debugging control of the devices to be debugged in each chip under the premise of sharing the same set of debugging channels between multiple chips, thereby improving the debugging consistency and scalability of the multi-chip system. The debugging operation capability of multiple devices to be debugged is realized through multiple SPI to AMBA interface modules, meeting the demand for parallel debugging of multiple modules in complex chip systems; the input ends of the multiple SPI to AMBA interface modules are respectively connected to the SPI signal lines of the same SPI master device to share the SPI signals of the SPI master device, which can realize unified access of multiple modules without increasing pin resources, improve signal utilization and simplify hardware wiring structure; each SPI to AMBA interface module has a unique input identifier, which realizes unique identification and positioning of multiple modules, ensuring that the debugging command can accurately act on the device to be debugged to avoid conflicts or misoperation.

[0147] By receiving the SPI command from the SPI master device, a communication path can be established between the main control and each module, ensuring that external debugging instructions can be correctly transmitted into the system; by comparing the input identifier and the identifier field in the SPI command, it can be ensured that the debugging command only acts on the selected device to be debugged, thereby improving the reliability and security of system debugging; by parsing the SPI command and generating a corresponding AMBA bus access command when the comparison results are consistent, so as to execute the corresponding operation, thereby achieving effective triggering of the function of the device to be debugged under command drive and supporting flexible debugging access control; by not responding to the SPI command when the comparison results are inconsistent, it can avoid that the non-device to be debugged responds to irrelevant commands, thereby improving the specificity of debugging behavior and system stability; by returning the command execution result to the SPI master device after the operation is completed, closed-loop feedback of the debugging result is achieved, which facilitates the host computer to judge the operation status and perform subsequent control.

[0148] The present application also provides an electronic device, including the chip described above. The electronic device may be a terminal device or a server, and the present application does not limit the specific type of the electronic device.

[0149] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "multiple" means two or more.

[0150] The descriptions with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. The order of steps involved in each embodiment is used to schematically illustrate the implementation of the present application, and the order of steps therein is not limited and can be appropriately adjusted as needed.

[0151] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0152] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A chip debugging device based on SPI, characterized in that: include: Multiple SPI to AMBA interface modules; The multiple SPI to AMBA interface modules communicate with the same SPI master device and are respectively connected to different devices to be debugged, so as to debug the devices to be debugged by sharing the SPI signal of the SPI master device; each SPI to AMBA interface module has a unique input identifier; the SPI signal includes an SPI command; The SPI to AMBA interface module is used for: Receiving the SPI command from the SPI master device; Comparing the input identifier with the identifier field in the SPI command; If the comparison results are consistent, the SPI command is parsed and a corresponding AMBA bus access command is generated, so that the device to be debugged performs a corresponding operation based on the AMBA bus access command, and the command execution result fed back by the device to be debugged is sent to the SPI master device.

2. The SPI-based chip debugging device according to claim 1, characterized in that: The SPI to AMBA interface module includes an SPI to APB interface module or an SPI to AXI interface module; the AMBA bus access command includes an APB access command or an AXI access command; The SPI to APB interface module includes a first SPI slave interface module and a first SPI slave control module; The first SPI slave interface module is used to receive SPI commands from the SPI master device; The first SPI slave control module is used to convert the SPI command into the APB access command; The SPI to AXI interface module includes a second SPI slave interface module and a second SPI slave control module; The second SPI slave interface module is used to receive SPI commands from the SPI master device; The second SPI slave control module is used to convert the SPI command into the AXI access command.

3. The SPI-based chip debugging device according to claim 1, characterized in that: The SPI to AMBA interface module is configured with multiple clock domains; the clock domains include the SPI interface clock, the on-chip high-frequency sampling clock, and the AMBA bus interface clock; The SPI interface clock is used to drive the serial communication between the SPI master device and the SPI to AMBA interface module; The on-chip high-frequency sampling clock is used to drive the SPI to AMBA interface module to perform data input and output; The AMBA bus interface clock is used to drive the bus access operation between the SPI to AMBA interface module and the device to be debugged.

4. The SPI-based chip debugging device according to claim 1, characterized in that: The bit width of the identification field is 8 bits.

5. The SPI-based chip debugging device according to claim 4, characterized in that: The SPI master device identifies and addresses 256 different SPI-to-AMBA interface modules based on the identification field.

6. The SPI-based chip debugging device according to claim 1, characterized in that: The SPI signal also includes: an SPI interface clock signal and a chip select signal; The SPI interface clock signal is used to synchronize the data transmission timing between the SPI master device and the SPI to AMBA interface module; The chip select signal is used to enable the communication function of the SPI to AMBA interface module and control it to receive or send data during a valid chip select period.

7. A chip debugging method based on SPI, applied to the SPI to AMBA interface module in the chip debugging device based on SPI according to any one of claims 1 to 6, characterized in that: include: Receiving the SPI command from the SPI master device; Comparing the input identifier with the identifier field in the SPI command; If the comparison results are consistent, the SPI command is parsed and a corresponding AMBA bus access command is generated to enable the device to be debugged to perform a corresponding operation, and the command execution result fed back by the device to be debugged is sent to the SPI master device.

8. A chip, characterized in that: The invention comprises an SPI-based chip debugging device as described in any one of claims 1 to 6.

9. A multi-chip interconnect debugging structure, characterized in that: The method comprises a plurality of chips according to claim 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 8.

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