Floating-point exponential comparison circuit and chip based on SRAM

Abstract

The present application relates to an SRAM-based floating-point exponent comparison circuit and its chip, wherein the floating-point exponent comparison circuit includes a plurality of exponential operation units distributed in an array, each of which includes a carry-propagation full adder and a 15T-SRAM storage unit. Compared with related technologies, by adding auxiliary transistors to the traditional storage array to integrate comparison and addition functions, the circuit implements in-memory exponent comparison to find the maximum value and subtraction to calculate the shift amount, thereby reducing data migration power consumption compared with traditional exponential calculation methods. At the same time, the circuit realizes the perception of abnormal exponent values ​​in the exponent readout stage and dynamically skips the redundant shift amount calculation process based on the perception result, thereby optimizing energy consumption. Compared with some existing exponential comparison circuits that use single-bit serial comparison, the proposed exponential comparison circuit realizes high-speed parallel maximum value comparison and subtraction to calculate the shift amount, providing a low-power and efficient parallel solution for floating-point exponent processing, thus solving the problem of low computational efficiency of current floating-point exponent comparison circuits.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an SRAM-based floating-point exponent comparison circuit and a chip thereof. Background Art

[0002] The core breakthrough of the memory-computing fusion architecture lies in directly performing matrix operations by leveraging the physical properties of the memory array. This in-situ computing mode significantly reduces data transfer energy consumption and demonstrates a tens-fold energy efficiency advantage in typical scenarios such as image classification. However, existing memory-computing chips are primarily optimized for fixed-point arithmetic, making it difficult to meet the dynamic numerical range required for neural network training. Floating-point arithmetic requires exponent comparison and mantissa alignment, so floating-point arithmetic circuits include floating-point exponent comparison circuits. However, current floating-point exponent comparison circuits often use a binary search comparison tree structure, where exponents are compared pairwise until the maximum value is determined. This increases circuit complexity rapidly as the number of exponents increases. Other floating-point exponent comparison circuits use single-bit serial comparison, performing single-bit exponent comparisons within a single computation cycle, with the computation cycle increasing linearly with the exponent bit width. Consequently, current floating-point exponent comparison circuits suffer from low computational efficiency, resulting in long computation cycles for the entire floating-point arithmetic circuit. Summary of the Invention

[0003] The present invention provides an SRAM-based floating-point exponent comparison circuit and a chip thereof to solve the problem of low computational efficiency of current floating-point exponent comparison circuits.

[0004] In a first aspect, the present invention provides an SRAM-based floating-point exponential comparison circuit, comprising a plurality of exponential operation units distributed in an array, each exponential operation unit comprising a carry-propagation full adder and a 15T-SRAM storage unit;

[0005] The 15T-SRAM memory cells in the same row have the same set of signal lines ALL_0, ALL_1 and ENB_SPARE, and ALL_0 and ALL_1 in the same group are connected to the two input terminals of the same NOR gate. The 15T-SRAM memory cells in the same column have the same set of signal lines MAXB and ENB_COMPARE, and MAXB is connected to the signal line MAX through an inverter.

[0006] The 15T-SRAM memory cell includes a 6T-SRAM memory cell and NMOS transistors N5 to N11 and PMOS transistors P3 and P4. The 6T-SRAM memory cell has storage nodes Q and QB; the gate, source and drain of N5 are connected to Q, ENB_SPARE and ALL_0 of the corresponding row respectively; the gate, source and drain of N6 are connected to QB, ENB_SPARE and ALL_1 of the corresponding row respectively; the gate, source and drain of N7 are connected to Q, ground and The drain of N8, the gate and source of N8 are connected to the drain of P3 and the MAXB of the corresponding column respectively; the gate, source and drain of N9 are connected to the MAX, QB and drain of the corresponding column respectively; the gate and source of N10 are connected to the MAXB and Q of the corresponding column respectively; the gate, source and drain of N11 are connected to the drain of N10, the ground line and the drain of P4 respectively; the gate and source of P3 are connected to the ENB_COMPARE of the corresponding column and the source of P4 respectively, and the gate of P4 is connected to the gate of N11;

[0007] The input ports A and B of the carry propagation full adder and the power supply terminal VDD are connected to the corresponding QB, the MAX of the corresponding column and the output of the NOR gate of the corresponding row respectively;

[0008] In the same line, the drain of P4 in the previous level 15T-SRAM storage unit is connected to the gate of N8 in the next level 15T-SRAM storage unit, and the carry output Cout of the previous level carry propagation full adder is connected to the carry input Cin of the next level carry propagation full adder.

[0009] In a second aspect, the present invention provides a floating-point in-memory calculation circuit, comprising an exponent array, an input mantissa array, a weight mantissa array, and a peripheral circuit;

[0010] The exponent array is the SRAM-based floating-point exponent comparison circuit described in the first aspect.

[0011] In a third aspect, the present invention provides a chip integrating the SRAM-based floating-point exponent comparison circuit described in the first aspect.

[0012] In a fourth aspect, the present invention provides an electronic device that implements floating-point operations using the chip described in the third aspect.

[0013] Compared with related technologies, low-power and efficient parallel floating-point exponent processing is achieved by skipping redundant calculations through abnormal exponent value perception, parallel exponent maximum value comparison, and subtraction to calculate the shift amount. It can more quickly calculate the shift amount of different exponents relative to the maximum exponent, solving the problem of low computational efficiency of current floating-point exponent comparison circuits.

[0014] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is an architectural diagram of an SRAM-based floating-point exponent comparison circuit provided in this embodiment;

[0016] Figure 2 15T-SRAM memory cell circuit diagram provided in this embodiment;

[0017] Figure 3 is a circuit diagram of an SRAM-based floating-point exponent comparison circuit provided in this embodiment;

[0018] Figure 4 2 is an architectural diagram of the floating-point in-memory computing circuit provided in this embodiment. DETAILED DESCRIPTION

[0019] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0020] Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meanings as understood by persons of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these," and similar expressions in this application do not denote limitations on quantity and may be singular or plural. The terms "comprise," "include," "have," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include unlisted steps or modules (units) or other steps or modules (units) inherent to the process, method, product, or device. The terms "connected," "connected," "coupled," and similar expressions used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. As used in this application, "plurality" means two or more. "And / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone; A and B exist simultaneously; or B exists alone. Generally, the character " / " indicates that the objects in the preceding and following relationship are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0021] In this embodiment, a floating-point exponent comparison circuit based on SRAM is provided.

[0022] Reference Figure 1 The SRAM-based floating-point exponent comparison circuit provided in this embodiment includes a plurality of exponential operation units (UEBs) arranged in an array. Each exponential operation unit (UEB) includes a carry-propagate full adder (FA) and a 15T-SRAM storage unit. In this embodiment, the plurality of exponential operation units (UEBs) are arranged in an array of 64 rows by 8 columns.

[0023] Reference Figure 3 15T-SRAM memory cells in the same row share the same set of signal lines ALL_0, ALL_1, and ENB_SPARE. All_0 and ALL_1 are connected to the two inputs of the same NOR gate. 15T-SRAM memory cells in the same column share the same set of signal lines MAXB and ENB_COMPARE. Signal line MAXB is connected to signal line MAX via an inverter. Signal line MAXB is also connected to the power supply via a switch, and precharge is achieved through the power supply. The switch can also be an NMOS transistor, with its gate connected to signal line PRE_COMPARE. That is, the switch is turned on or off by the PRE_COMPARE signal.

[0024] It should be noted that, in this embodiment, for the convenience of description, the signal line and its signal are named the same, for example, the signal of the signal line MAXB is also defined as MAXB.

[0025] Reference Figure 2 The 15T-SRAM storage unit includes a 6T-SRAM storage unit and NMOS transistors N5 to N11 and PMOS transistors P3 and P4. The 6T-SRAM storage unit has storage nodes Q and QB; the gate, source and drain of the NMOS transistor N5 are respectively connected to the storage node Q and the signal lines ENB_SPARE and ALL_0 of the corresponding row; the gate, source and drain of the NMOS transistor N6 are respectively connected to the storage node QB and the signal lines ENB_SPARE and ALL_1 of the corresponding row; the gate, source and drain of the NMOS transistor N7 are respectively connected to the storage node Q, the ground line and the drain of the NMOS transistor N8; the gate and source of the NMOS transistor N8 are respectively connected to the storage node Q, the ground line and the drain of the NMOS transistor N8. The gate, source, and drain of the NMOS transistor N9 are connected to the signal line MAX of the corresponding column, the storage node QB, and the drain of the NMOS transistor N10, respectively. The gate and source of the NMOS transistor N10 are connected to the signal line MAXB and the storage node Q of the corresponding column, respectively. The gate, source, and drain of the NMOS transistor N11 are connected to the drain of the NMOS transistor N10, the ground line, and the drain of the PMOS transistor P4, respectively. The gate and source of the PMOS transistor P3 are connected to the signal line ENB_COMPARE of the corresponding column and the source of the PMOS transistor P4, and the gate of the PMOS transistor P4 is connected to the gate of the NMOS transistor N11.

[0026] Continue to refer to Figure 2 In this embodiment, the 6T-SRAM memory cell includes PMOS transistors P1 and P2 and NMOS transistors N1 to N4. The PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 are anti-phase cross-coupled to form storage nodes Q and QB. The NMOS transistor N3 serves as a transmission transistor between the storage node Q and the bit line BL. The NMOS transistor N4 serves as a transmission transistor between the storage node QB and the bit line BLB. The gates of the NMOS transistors N3 and NMOS transistors N4 are connected to the same word line WL.

[0027] Reference Figure 1 The input ports A and B of the carry-propagating full adder FA and the power supply VDD are connected to the corresponding storage node QB, the signal line MAX of the corresponding column, and the output terminal EXID of the NOR gate of the corresponding row, respectively. The output terminal S of the carry-propagating full adder FA is used to output the shift amount SHIFT.

[0028] Reference Figure 3 Within the same row, the drain of the PMOS transistor P4 in the previous-stage 15T-SRAM memory cell is connected to the gate of the NMOS transistor N8 (the drain of the PMOS transistor P3) in the next-stage 15T-SRAM memory cell. The gate of the NMOS transistor N8 and the drain of the PMOS transistor P3 are used to receive the input signal EN_COMPARE. That is, except for the 15T-SRAM memory cells in the first row, the input signal EN_COMPARE for each 15T-SRAM memory cell in subsequent rows is provided by the corresponding 15T-SRAM memory cell in the previous row (specifically, the drain of the PMOS transistor P4 and the drain of the NMOS transistor N11). The input signal EN_COMPARE for each 15T-SRAM memory cell in the first row is externally input.

[0029] The carry output terminal Cout of the carry propagation full adder FA at the previous stage is connected to the carry input terminal Cin of the carry propagation full adder FA at the next stage.

[0030] In the aforementioned SRAM-based floating-point exponent comparison circuit, each column of exponent arithmetic units corresponds to a bit in the exponent. Each exponent arithmetic unit in the same row is used to store a different bit of the same exponent. Consequently, exponent arithmetic units in different rows store different exponents to be compared. The signal on signal line MAX represents the maximum value between the different exponents, i.e., the maximum exponent. The carry-propagation full adder FA can then perform a two's complement addition operation of QB + MAX + carry, i.e., calculating the shift amount SHIFT by subtracting the maximum exponent from the current exponent.

[0031] In this embodiment, to address the 8-bit exponent width consistency between the BF16 and FP32 floating-point formats, the array adopts a 64-row × 8-column topology to implement data storage, parallel exception detection, dynamic maximum value comparison, and shift calculation for 64 sets of 8-bit exponent values. It outputs an 8-bit exponent maximum value, MAX<7:0>, and 64 shift values, SHIFT1 to 64<7:0>.

[0032] It should be noted that the SRAM-based floating-point exponent comparison circuit further includes a control module CTRL for generating control signals EN_SPARE, EN_COMPARE, ENB_COMPARE, etc., and a pre-charge module PRE_CHARGE for pre-charging the MAXB signal line.

[0033] The calculation principle of the SRAM-based floating-point exponent comparison circuit in this embodiment is described below.

[0034] like Figure 2 As shown, the exponential operation unit is integrated with 6T-SRAM storage units to form a 15T-SRAM storage unit. Each 15T-SRAM storage unit stores a single-bit exponent. The 15T-SRAM storage units are cascaded to form a storage array with an exponential maximum comparison function, realizing maximum value comparison between multiple groups of exponents.

[0035] In floating-point data representation, the all-zero or all-one configuration of the exponent storage value is a special state defined by the IEEE 754 standard, which usually corresponds to abnormal numerical representation situations. Specifically, an all-zero exponent field may represent a denormalized number or zero value, reflecting that the data is approaching the minimum representable threshold of the floating point; the all-one exponent field is used to mark infinity or non-number (NaN), which is commonly seen in scenarios such as operation overflow, illegal operations (such as zero division or negative square root), and data integrity loss. The exponent comparison circuit in this embodiment adopts an abnormal value detection mechanism:

[0036] First, the parallel sensing circuit built into the storage unit (NMOS transistors N5, N6, N9, N10 and N11, PMOS transistors P3 and P4, and signal lines ALL_0 and ALL_1) performs a real-time status scan of the index storage values ​​in each row of the storage array. When an abnormal configuration of all zeros or all ones is detected, the abnormal identification signal EXID (active low) is immediately activated, and the operation control unit is triggered to terminate the subsequent processing flow of the data in that row. If the exponent field is within the valid value range, EXID is maintained at a high level, allowing the data to enter the standard operation channel. Specifically, for a row of stored values, when the values ​​stored in the row are all zeros, the NMOS transistors N5 in all 15T-SRAM cells in the row are turned off, and the signal line ALL_0 in the row has no discharge path and remains at a high level; when the values ​​stored in the row are all ones, the NMOS transistors N6 in all 15T-SRAM cells in the row are turned off, and the signal line ALL_1 in the row has no discharge path and remains at a high level; a NOR operation is performed on the signal lines ALL_0 and ALL_1, and when at least one of them remains at a high level, the NOR gate output EXID outputs a low level; when the values ​​stored in the row are not all zeros or all ones, both the signal lines ALL_0 and ALL_1 are discharged through transistors N5 and N6 to the low level applied by the ENB_SPARE signal line, and the NOR operation result EXID outputs a high level.

[0037] During the comparison and maximum value search phase, the circuit uses a dynamic priority comparison architecture to achieve efficient parallel processing. After all valid index data is synchronously read out from the storage unit, bit-level comparison is performed step by step from the most significant bit (MSB) to the least significant bit (LSB) according to the binary weight. To ensure the determinism of the comparison process, the circuit introduces a step-by-step elimination mechanism: in each bit comparison cycle, if an index does not reach the maximum value at the current bit level, its corresponding data path will be immediately closed to avoid redundant participation in subsequent bit-level comparisons. Specifically, Figure 2 , taking the comparison of four 4-bit exponents 0111, 1101, 1100, and 1001 as an example:

[0038] For the highest bit comparison, that is, the first column, the stored values ​​are 0, 1, 1, and 1 respectively. For the stored value 0, the NMOS tube N7 in the 15T-SRAM storage unit is turned off. For the stored value 1, the NMOS tube N7 in the 15T-SRAM storage unit is turned on. When the signal line EN_COMPARE is valid at a high level, the NMOS tube N8 in the 15T-SRAM storage unit of this column is turned on. Therefore, the MAXB of this column is discharged to a low level through N7 and N8 in the 15T-SRAM with a stored value of 1, and the MAX of this column outputs a high level. Therefore, the NMOS transistor N9 in the 15T-SRAM in this column is turned on and N10 is turned off. For the stored value 0, the PMOS transistor P4 in the corresponding 15T-SRAM is turned off and the NMOS transistor N11 is turned on, causing the NMOS transistor N8 in the next bit-level 15T-SRAM (first row, second column) to be turned off, the comparison path is closed, and it does not participate in the subsequent bit-level comparison; for the stored value 1, the PMOS transistor P4 in the corresponding 15T-SRAM is turned on and the NMOS transistor N11 is turned off, causing the NMOS transistor N8 in the next bit-level 15T-SRAM to be turned on and continue the subsequent bit-level comparison.

[0039] Continuing with the comparison of the next highest bit, the second column, the stored values ​​are 1, 1, 1, and 0. Because the NMOS transistor N8 in the 15T-SRAM in the first row and second column is turned off during the highest bit comparison, the first stored value 1 is not compared in this bit-level comparison. The values ​​that are compared are 1, 1, and 0. A similar comparison is performed, and the maximum value MAX in this column is output as a high level, and subsequent bit-level comparisons in the fourth row are turned off.

[0040] The third column is compared, and the stored values ​​are 1, 0, 0, 0. Due to the progressive elimination mechanism, the first and fourth rows are not compared, so the comparison values ​​are 0, 0, and the maximum value of this column, MAX, is output as a low level. Similarly, the maximum value of the fourth column, MAX, is output as a high level. The final maximum value of the four 4-bit exponents is 1101.

[0041] The redundant skip calculation process utilizes a conditional trigger mechanism: when the parallel sensing circuit identifies an abnormal state (all zeros or all ones) in the exponent field, it immediately generates a low-level abnormality identification signal, EXID. This signal is applied to the VDD supply of the carry-propagating full adder FA corresponding to the UEB, terminating the shift calculation for that row and avoiding redundant calculation of abnormal data. For valid exponent values, EXID remains high, activating the full adder to perform a two's complement subtraction operation. Specifically, the complement of the original exponent value (i.e., storage node QB) and the global maximum value MAX are input to the carry-propagating full adder FA, and an equivalent subtraction calculation is achieved through two's complement addition. The carry-propagating full adder FA's local bit and output S represent the shift amount, and the carry signal Cout is propagated to the high bit through a cascade structure, ultimately generating the complete shift amount code SHIFT.

[0042] As follows, the calculation process of the SRAM-based floating-point exponent comparison circuit in this embodiment is further described through an example.

[0043] like Figure 3 As shown, taking 4 groups of 4-bit index comparison as an example, each storage unit stores a 1-bit index, and each row stores a 4-bit index, where "1" represents the stored information is a high level and "0" represents the stored information is a low level. Figure 3 The four 4-bit exponents in the example are 0111, 1101, 1100, and 1001 respectively.

[0044] First, abnormal value detection is performed. The ALL_0 and ALL_1 signal lines of each row are precharged to a high level. Then, the ENB_SPARE signal line is pulled down to a low level. At this time, abnormal value detection is performed. There are three situations:

[0045] 1. If the index storage information is all 0, there is no discharge path for the corresponding ALL_0 signal line, so the pre-charge high level is maintained.

[0046] 2. If the index storage information is all 1, there is no discharge path for the corresponding ALL_1 signal line, so the pre-charge high level is maintained.

[0047] 3. The index stores both 0 and 1 information, so both ALL_0 and ALL_1 signal lines have discharge paths and are therefore discharged to a high level.

[0048] ALL_0 and ALL_1 perform a NOT operation and output an exception identification signal EXID. If the exponent storage information is all 0s or all 1s, the exception identification signal EXID is low. If the exponent storage information contains both 0s and 1s, the exception identification signal EXID is high. The exponent values ​​shown in the legend are not abnormal values, so the output exception identification signal EXID is high.

[0049] Then, compare the maximum value of the index, turn on PRE_COMPARE low level, precharge the MAXB signal line of each column, precharge it to high level, then turn on EN_COMPARE high level, compare the maximum value of the index storage information of the first column, since the storage information is 0, 1, 1, 1, then MAXB <3> The memory cell with the stored information 1 is discharged to a low level, MAXB <3> The output of the inverter is high, that is, the maximum value MAX of the column index is obtained. <3> =1; Enable ENB_COMPARE <3> Low level, because the first column has the maximum index MAX <3> =1, so the subsequent comparison enable of the first row ROW0 is turned off through the auxiliary circuit (N9, N10, N11, P3, P4). Specifically, MAX <3> =1, the NMOS transistor N9 in the first row and first column 15T-SRAM is turned on and N10 is turned off. Since the stored value is 0, the PMOS transistor P4 in the 15T-SRAM is turned off and the NMOS transistor N11 is turned on, causing the NMOS transistor N8 in the next bit level (first row and second column) 15T-SRAM to be turned off, the comparison path is closed, and it does not participate in the subsequent bit level comparison. The next exponential maximum comparison only involves the second row ROW1, the third row ROW2, and the fourth row ROW3; the exponential maximum comparison of the second column is performed. Since the stored information is 1, 1, and 0 respectively, MAXB <2> Discharge to low level, MAX <2> Output high level, that is, the maximum value of the second column MAX <2> =1, turn off the subsequent comparison of ROW3; compare the maximum index value of the third column. Since the stored information is 0, 0, MAX <1> There is no discharge path, maintain precharge high level, MAX <1> Output low level, that is, the maximum value MAX in the third column <1> =0; compare the maximum value of the index of the fourth column. Since the stored information is 1 and 0, MAX <0> Discharge to low level, MAX <0> Output high level, that is, the maximum value MAX in the fourth column <0> = 1. The maximum value of the four 4-bit indices in the legend is 1101.

[0050] In summary, the SRAM-based floating-point exponent comparison circuit provided in this embodiment integrates comparison and addition functions by adding auxiliary transistors (NMOS transistors N5 to N11 and PMOS transistors P3 and P4) to a traditional memory array. This allows for in-memory exponent comparison to find the maximum value and subtraction to determine the shift amount, reducing data migration power consumption compared to traditional exponent calculation methods. Furthermore, it detects abnormal exponent values ​​during the exponent readout phase and dynamically skips redundant shift calculations based on the detected results, optimizing energy consumption. Compared to some existing exponent comparison circuits that use single-bit serial comparison, the proposed exponent comparison circuit implements high-speed parallel maximum value comparison and subtraction to determine the shift amount, providing a low-power and efficient parallel solution for floating-point exponent processing. This solves the low computational efficiency issue currently faced by floating-point exponent comparison circuits.

[0051] In this embodiment, a floating-point in-memory calculation circuit is also provided, including an exponent array, an input mantissa array, a weight mantissa array and a peripheral circuit; the exponent array is an SRAM-based floating-point exponent comparison circuit provided in this embodiment.

[0052] Each row of the exponent array is used to store the exponent of a floating point number in bits and to perform comparison calculations on different exponents and output a shift amount.

[0053] Each row of the input mantissa array is used to store the mantissa of the input floating-point number bit by bit, and each row of the weight mantissa array is used to store the mantissa of the weight floating-point number bit by bit, and the product of the mantissa of the input floating-point number and the weight floating-point number is realized by in-memory calculation.

[0054] The peripheral circuit includes a shifter, an adder tree and a normalization module; wherein the shifter performs a right shift operation on the mantissa of the input floating-point number and the mantissa of the weighted floating-point number of the corresponding row according to the shift amount; the adder tree is used to accumulate the mantissa products of the input floating-point numbers and the weighted floating-point numbers of different rows to obtain the mantissa sum; the normalization module generates a floating-point multiplication and accumulation result that meets the specifications based on the maximum exponent and the mantissa sum.

[0055] The above floating-point in-memory calculation circuit can realize multiplication and accumulation operations between multiple groups of multi-bit floating-point input data and multi-bit floating-point weight data.

[0056] Reference Figure 4 In this embodiment, to implement floating-point operations, the SRAM array in the floating-point in-memory calculation circuit is divided into three parts: the exponent array EMEM, the input mantissa array IMMEM, and the weight mantissa array WMMEM. Rows 0 to 31 of the exponent array EMEM are used to store the exponent portion of the input floating-point number bit by bit, and rows 32 to 63 are used to store the exponent portion of the weight floating-point number bit by bit. The exponent array uses its own logic to compare the maximum exponent value with the near-memory calculation unit and calculate the shift amount by difference. Each row of the input mantissa array is used to store the mantissa portion of the input floating-point number bit by bit, and each row of the weight mantissa array is used to store the mantissa portion of the weight floating-point number bit by bit. In-memory calculations are used to perform multiplication operations with the input mantissa.

[0057] The peripheral circuitry includes a shifter, an adder tree, and a normalization module. The shifter performs a right shift operation on the floating-point mantissa portion stored in the input mantissa array and the weight mantissa array of the corresponding row according to the shift amount. The adder tree accumulates the partial products of the input mantissa array and the weight mantissa array to obtain the mantissa sum. The normalization module generates a standardized floating-point multiplication and accumulation result based on the maximum exponent and the mantissa sum.

[0058] The specific working process is as follows:

[0059] Phase 1: exponent pre-alignment and shift generation.

[0060] 1. Exponent Storage and Parallel Comparison: The exponent of the input floating-point number is stored bit-by-bit in an exponent array (EMEM) with rows 0 to 31 and columns 8 by 8. The exponent of the weighted floating-point number is stored bit-by-bit in an exponent array with rows 31 to 63 and columns 8 by 8. Each storage unit integrates a 15T-SRAM comparison circuit, which performs exception detection and bit-by-bit parallel comparison. The system scans each bit from the most significant bit (MSB) to the least significant bit (LSB) using a dynamic priority elimination mechanism. If a row's current bit level is not the maximum, the comparison path for subsequent bits is closed. The final global exponent maximum value, Emax, is output, and the abnormal exponent is marked (all 0s / all 1s). The EXID signal is asserted to terminate the operation on the abnormal row.

[0061] 2. Calculate the shift amount by two's complement subtraction: For the valid exponent row (EXID=1), the two's complement of Emax and the exponent values ​​in the exponent array are input into the full adder chain. The subtraction operation is realized through two's complement conversion. The local bit and the output S directly represent the mantissa shift amount. The carry bit Cout is passed to the high bit through the cascade structure, and finally the complete shift amount code is generated.

[0062] The second stage: dynamic alignment of the mantissa and in-memory multiplication.

[0063] 3. Mantissa shift operation: The input mantissa array (IMMEM) and the weight mantissa array (WMMEM) store 23 bits (FP32) or 7 bits (BF16) of mantissas per row. The shifter performs a right shift operation on the corresponding row of the mantissa array according to the shift amount to align it to the Emax exponent base.

[0064] 4. In-memory multiplication and accumulation: After alignment, IMMEM and WMMEM activate the in-memory calculation mode to implement the mantissa weight multiplication. The product is output to the adder tree to perform accumulation operation and output the final mantissa sum.

[0065] The third stage: standardization.

[0066] 5. Combine the sign bit, exponent bit, and mantissa bits according to the IEEE 754 format and output the normalized floating-point result.

[0067] This embodiment further provides a chip, which integrates the SRAM-based floating-point exponent comparison circuit provided in this embodiment.

[0068] This embodiment also provides an electronic device that implements floating-point operations using the chip provided in this embodiment.

[0069] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0070] Obviously, the accompanying drawings are merely examples or embodiments of the present application. A person skilled in the art can also apply the present application to other similar situations based on these drawings without inventive effort. Furthermore, it is understandable that, although the work involved in this development process may be complex and lengthy, certain design, manufacturing, or production changes based on the technical content disclosed in this application are merely routine technical means for a person skilled in the art and should not be considered to constitute a deficiency in the disclosure of the present application.

Claims

1. A floating-point exponent comparison circuit based on SRAM, characterized in that: The invention comprises a plurality of exponential operation units distributed in an array, each exponential operation unit comprising a carry propagation full adder and a 15T-SRAM storage unit; The 15T-SRAM memory cells in the same row have the same set of signal lines ALL_0, ALL_1 and ENB_SPARE, and ALL_0 and ALL_1 in the same group are connected to the two input terminals of the same NOR gate. The 15T-SRAM memory cells in the same column have the same set of signal lines MAXB and ENB_COMPARE, and MAXB is connected to the signal line MAX through an inverter. The 15T-SRAM memory cell includes a 6T-SRAM memory cell and NMOS transistors N5 to N11 and PMOS transistors P3 and P4. The 6T-SRAM memory cell has storage nodes Q and QB; the gate, source and drain of N5 are connected to Q, ENB_SPARE and ALL_0 of the corresponding row respectively; the gate, source and drain of N6 are connected to QB, ENB_SPARE and ALL_1 of the corresponding row respectively; the gate, source and drain of N7 are connected to Q, ground and The drain of N8, the gate and source of N8 are connected to the drain of P3 and the MAXB of the corresponding column respectively; the gate, source and drain of N9 are connected to the MAX, QB and drain of the corresponding column respectively; the gate and source of N10 are connected to the MAXB and Q of the corresponding column respectively; the gate, source and drain of N11 are connected to the drain of N10, the ground line and the drain of P4 respectively; the gate and source of P3 are connected to the ENB_COMPARE of the corresponding column and the source of P4 respectively, and the gate of P4 is connected to the gate of N11; The input ports A and B of the carry propagation full adder and the power supply terminal VDD are connected to the corresponding QB, the MAX of the corresponding column and the output of the NOR gate of the corresponding row respectively; In the same line, the drain of P4 in the previous level 15T-SRAM storage unit is connected to the gate of N8 in the next level 15T-SRAM storage unit, and the carry output Cout of the previous level carry propagation full adder is connected to the carry input Cin of the next level carry propagation full adder.

2. The SRAM-based floating-point exponent comparison circuit according to claim 1, wherein: The 6T-SRAM storage cell includes PMOS transistors P1 and P2 and NMOS transistors N1 to N4. P1, P2, N1 and N2 are anti-phase cross-coupled to form storage nodes Q and QB. N3 serves as a transmission transistor between the storage node Q and the bit line BL. N4 serves as a transmission transistor between the storage node QB and the bit line BLB. The gates of N3 and N4 are connected to the same word line WL.

3. The SRAM-based floating-point exponent comparison circuit according to claim 1, wherein: MAXB is also connected to the power supply through a switch tube and pre-charged by the power supply.

4. The SRAM-based floating-point exponent comparison circuit according to claim 1, wherein: The exponential operation units are distributed in an array of 64 rows and 8 columns.

5. The SRAM-based floating-point exponent comparison circuit according to claim 1, wherein: Each exponential operation unit in the same row is used to store different bits of an exponent, and the exponential operation units in different rows respectively store different exponents to be compared.

6. The SRAM-based floating-point exponent comparison circuit according to claim 5, wherein: It can detect all 0s or all 1s of the index and stop the all 0s or all 1s of the index from participating in the index comparison calculation.

7. A floating-point in-memory calculation circuit, characterized in that: including an exponent array, an input mantissa array, a weight mantissa array and peripheral circuits; The exponent array is an SRAM-based floating-point exponent comparison circuit according to any one of claims 1 to 6.

8. The floating-point in-memory calculation circuit according to claim 7, wherein: Each row of the exponent array is used to store the exponent of the floating point number in bits and to perform comparison calculations of different exponents and output a shift amount; Each row of the input mantissa array is used to store the mantissa of the input floating-point number bit by bit, and each row of the weight mantissa array is used to store the mantissa of the weight floating-point number bit by bit, and the product of the mantissa of the input floating-point number and the weight floating-point number is realized by in-memory calculation; The peripheral circuits include shifters, adder trees, and normalization modules; Among them, the shifter performs a right shift operation on the mantissa of the input floating-point number and the mantissa of the weight floating-point number of the corresponding row according to the shift amount; the adder tree is used to accumulate the mantissa products of the input floating-point numbers and the weight floating-point numbers of different rows to obtain the mantissa sum; the normalization module generates a floating-point multiplication and accumulation result that meets the specifications based on the maximum value of the exponent and the mantissa sum.

9. A chip, characterized in that: The invention integrates the SRAM-based floating-point exponent comparison circuit according to any one of claims 1 to 6.

10. An electronic device, characterized in that: The chip according to claim 9 is used to implement floating-point operations.

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