Address mapping method, device, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides an address mapping method, device, electronic device and readable storage medium. When binary translation is performed on a source memory access instruction of a client, a target state mark corresponding to the client physical address to be accessed is determined based on a state mark area in a host virtual memory space. When the target state mark matches the target memory access operation indicated by the source memory access instruction, a host virtual mapping address corresponding to the client physical address to be accessed in the host virtual memory space is determined based on a direct address mapping rule. The target memory access operation is performed on the target host physical address corresponding to the host virtual mapping address. In this way, the host virtual mapping address corresponding to the client physical address to be accessed is directly determined by the direct address mapping rule without the need for retrieval and traversal, which can reduce the overhead in the address mapping process, improve the efficiency of address conversion, and reduce the number of interactions between the client and the host.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an address mapping method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation enables programs from one client machine to be executed on the central processing unit (CPU) of another host machine. Depending on the translation target, binary translation can be divided into system-level translation and user-level translation. Specifically, during system-level translation, the guest virtual address (GVA) is first converted to a guest physical address (GPA) by traversing the multi-level page tables in the client machine. The GPA is then converted to a host virtual address (HVA).

[0003] In related technologies, address translation from GVA to GPA is often accomplished by QEMU traversing the multi-level page tables in the client. At the same time, QEMU maintains a client physical address space with a tree structure. Each node in the tree structure represents a memory region (MemoryRegion), which contains mapping information from GPA to HVA. By searching and traversing the tree structure, the memory region corresponding to the GPA can be obtained, and the HVA can be determined based on the GPA-to-HVA mapping information contained in the memory region. However, this address mapping process requires multiple searches and traversals of the tree structure nodes, resulting in low address mapping efficiency. Summary of the Invention

[0004] To overcome the problems existing in the related art, the present invention provides an address mapping method, device, electronic device and readable storage medium.

[0005] In a first aspect, the present invention provides an address mapping method, the method comprising:

[0006] In the case of performing binary translation on a source memory access instruction of the client, determining a target state flag corresponding to a guest physical address to be accessed based on a state flag area in a virtual memory space of the host machine; the guest physical address to be accessed is obtained based on a guest virtual address to be accessed indicated by the source memory access instruction;

[0007] In a case where the target state flag matches the target memory access operation indicated by the source memory access instruction, determining a host machine virtual mapping address corresponding to the client physical address to be accessed based on a direct address mapping rule; the direct address mapping rule is used to describe a mapping relationship established by linear operation between a target physical memory space of the client and a target virtual memory space in the host machine virtual memory space;

[0008] The target memory access operation is performed on the target host machine physical address corresponding to the host machine virtual mapping address.

[0009] In a second aspect, the present invention provides an address mapping device, the device comprising:

[0010] A first determining module is configured to determine, when performing binary translation on a source memory access instruction of the client, a target status flag corresponding to a client physical address to be accessed based on a status flag area in a virtual memory space of the host machine; the client physical address to be accessed is obtained based on a client virtual address to be accessed indicated by the source memory access instruction;

[0011] a second determining module configured to determine, when the target state flag matches the target memory access operation indicated by the source memory access instruction, a host virtual mapping address corresponding to the client physical address to be accessed based on a direct address mapping rule; the direct address mapping rule being configured to describe a mapping relationship established by linear operation between a target physical memory space of the client and a target virtual memory space in the host virtual memory space;

[0012] The first execution module is configured to execute the target memory access operation on the target host machine physical address corresponding to the host machine virtual mapping address.

[0013] In a third aspect, the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the address mapping method described in any one of the first aspects is implemented.

[0014] In a fourth aspect, the present invention provides a readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the steps in the address mapping method in any one of the embodiments of the first aspect above.

[0015] In an embodiment of the present invention, when a source memory access instruction of a client is binary translated, a target status tag corresponding to a client physical address to be accessed is determined based on a status tag area in a host virtual memory space; the client physical address to be accessed is obtained based on the client virtual address to be accessed indicated by the source memory access instruction; when the target status tag matches the target memory access operation indicated by the source memory access instruction, a host virtual mapping address corresponding to the client physical address to be accessed in the host virtual memory space is determined based on a direct address mapping rule; the direct address mapping rule is used to describe a mapping relationship established by linear operations between the target physical memory space of the client and the target virtual memory space in the host virtual memory space; and a target memory access operation is performed on the target host physical address corresponding to the host virtual mapping address. In this way, through direct address mapping rules, the host virtual mapping address corresponding to the guest physical address to be accessed can be directly determined. The binary translator can efficiently perform binary translation and execution of guest instructions, ensuring correct memory access between different instruction set architectures (ISAs) and achieving correct mapping between the source instruction set address space corresponding to the guest and the target instruction set address space corresponding to the host. This avoids the performance overhead caused by multiple search traversals and memory accesses. By eliminating the need for multiple search traversals, the overhead in the address mapping process is reduced, the efficiency of address translation is improved, and the overall operating efficiency and performance of the system are enhanced. This, in turn, reduces CPU usage, memory access latency, and the number of interactions between the guest and host. Furthermore, embodiments of the present invention decouple the translation processes between the GVA, GPA, and HVA hierarchically by first determining the guest physical address to be accessed based on the guest virtual address to be accessed, and then determining the host virtual mapping address corresponding to the guest physical address to be accessed. This ensures that the same physical memory can be accessed by the GVAs of different processes while also ensuring that the guest physical address can be correctly mapped to the host address space. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 This is a flowchart of the steps of an address mapping method provided by an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the correspondence between client physical pages and status marks provided by an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of address mapping of a continuous target physical memory space provided by an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of address mapping of a non-contiguous target physical memory space provided by an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of an optimized address mapping method provided by an embodiment of the present invention;

[0022] Figure 6 This is a structural diagram of an address mapping device provided by an embodiment of the present invention;

[0023] Figure 7 This is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0025] Binary translation technology is a key area of ​​computing, primarily used in areas such as software compatibility, architecture simulation, program analysis, and debugging. It involves various aspects of compilation, operating systems, and architecture. Binary translation can convert a source program running on one ISA (Instruction Set Architecture) platform (called the guest platform) into a target program running on another ISA platform (called the host platform). For example, this allows an x86 program to run on a Long Arch platform, thus enabling cross-ISA program simulation. The term "guest" typically refers to the source platform (or guest platform) of the simulated program, while the term "host" refers to the target platform (or host platform) on which the binary translation system itself runs. This means that the binary translation system can simulate the client program on the host machine.

[0026] Figure 1 This is a flowchart of the steps of an address mapping method provided by an embodiment of the present invention. Figure 1 As shown, the method may include:

[0027] Step 101. When performing binary translation on the source memory access instruction of the client, determine the target status mark corresponding to the physical address of the client to be accessed based on the status mark area in the virtual memory space of the host machine; the physical address of the client to be accessed is obtained based on the virtual address of the client to be accessed indicated by the source memory access instruction.

[0028] In an embodiment of the present invention, the host virtual memory space can be an address space larger than the actual physical memory provided by the host operating system to applications using virtual memory technology. The host virtual memory space is divided into a target virtual memory space and a status flag area. The target virtual memory space is a continuous memory space that simulates the mapping of the client's physical memory space within the host virtual memory space. The status flag area contains status flags for each client's physical page. The binary translator maintains the status of the client physical page based on the status flags of each client physical page. The status flags can be identified using data of a preset flag size. For example, 8 bits can be used as the status flag for a physical page. Different bit combinations can represent different states of the client physical page, such as write-prohibited, read-prohibited, non-direct read / write, the client physical page being a memory-mapped input / output (MMIO) memory area, and / or the client physical page being a self-modify code (SMC) area. If the MMIO memory area cannot be directly accessed and requires special marking to prevent direct memory access, the status flag corresponding to the client physical page should indicate that it is an MMIO memory area and non-direct read / write. If the SMC area cannot be written to, the status flag corresponding to the client physical page should mark it as an SMC area and prohibit write operations. Each physical page corresponds to a preset flag size, for example, 8 bits (1 byte) of status flag data. All status flag data is stored in a continuous memory area, namely the status flag area. Each bit in the status flag data has independent semantics, used to represent different access permissions or status characteristics of the client physical page. Different bit positions can be freely configured to represent different meanings. For example, a bit can be set as a write-prohibit flag. When set, this flag indicates that the corresponding client physical page is prohibited from write operations. Another bit can be set as a read-prohibit flag to restrict read access to the physical page. A non-direct read / write flag can also be set to indicate that the physical page is in a special access-restricted state. For example, using 00000001 as the status flag indicates that the write status of the client physical page is prohibited, but this is not limited in the embodiments of the present invention.

[0029] It is understood that the storage format of the status flags stored in the status flag area can be customized as needed, and the embodiments of the present invention do not impose any restrictions on this. The status flag area can be a flat memory area, that is, there is no segmentation, partitioning, priority order, etc.

[0030] In the case of binary translation of the client's source memory access instruction, it is necessary to correctly process the memory access instructions in the source instruction set corresponding to the client to ensure that they can correctly access the memory space of the target instruction set corresponding to the host. First, the guest virtual address to be accessed indicated by the source memory access instruction is converted into the guest physical address to be accessed. For example, the guest physical address corresponding to the guest virtual address to be accessed can be determined by traversing the client page table as the guest physical address to be accessed. Based on the status mark area in the host virtual memory space, the target status mark corresponding to the guest physical address to be accessed is determined. The guest physical address to be accessed refers to the guest physical address (GPA) in the client obtained by converting the guest virtual address to be accessed indicated by the source memory access instruction of the client.

[0031] During system-level binary translation, guest virtual memory emulation involves two aspects: first, emulating the guest's physical address space, including memory areas such as random access memory (RAM), read-only memory (ROM), and memory-mapped I / O (MMIO); and second, emulating the guest's virtual-to-real address translation, specifically, the GVA to GPA address translation. The complete address translation involved in a guest's source memory access instruction involves translating from GVA to GPA, then to HVA, and finally to the host physical address (HPA). The host operating system can handle the HVA to HPA translation, while a binary translator (such as the QEMU binary translator) can perform the GVA to GPA to HVA translation. Specifically, in a virtualized environment, translating guest virtual addresses to host physical addresses requires a complex mapping process. These mapping processes include mapping the guest virtual address (GVA) to the guest physical address (GPA), and mapping the GPA to the host physical address (HPA). The GPA acts as a bridge in a virtualized environment, connecting the guest's virtual address space and the host's physical address space.

[0032] Based on the guest physical address of the memory to be accessed of the source memory access instruction, a storage location of a status flag corresponding to the guest physical address to be accessed can be determined. Based on the storage location, data of a preset flag size is read from a status flag area as a target status flag for the client physical page corresponding to the guest physical address to be accessed. The target status flag is used to describe the status of the client physical page corresponding to the guest physical address to be accessed.

[0033] Optionally, step 101 may include the following steps:

[0034] Step 201: Determine a status mark address based on a status mark base address and a target index value of the status mark area; the target index value is determined based on the client physical address to be accessed and a preset index relationship, and the preset index relationship is determined based on the client's physical page size.

[0035] In an embodiment of the present invention, a status mark address is determined based on a status mark base address and a target index value of a status mark area. The status mark base address of the status mark area may be the starting address of the status mark area in the host machine's virtual memory space. When searching for a target status mark corresponding to a client physical address to be accessed in the status mark area, the search may be performed based on the target index value. The target index value is determined based on the client physical address to be accessed and a preset index relationship, wherein the preset index relationship is determined based on the client machine's physical page size. The target index value is used to index an address related to the client physical address to be accessed but located in a different memory area of ​​the host machine's virtual memory space, thereby locating and accessing the status mark address where the target status mark corresponding to the client physical address to be accessed is located. The preset index relationship may be used to describe the relationship between the client physical address and the index value of the status mark data. The preset index relationship may be a bitwise operation. In other words, the client physical address and the index value of the status mark data may be converted via a bitwise operation. The index value of the status mark data may be obtained by performing a bitwise operation based on the client physical address. Accordingly, the target index value is obtained by performing a bitwise operation based on the client physical address to be accessed. Bitwise operations can include right shifts, where the number of shifts can be determined by the guest physical page size. For example, the guest physical page size is typically 4KB, and the page offset requires 12 bits (from 0 to 4095). Under the paging mechanism, a guest physical page is divided into two parts: a page number and an intra-page offset. When processing a guest physical address (GPA), to extract the status tag data associated with that guest physical page through bitwise operations, the intra-page offset portion of the GPA must be removed to obtain the target index value. The status tag data corresponding to the guest physical page can then be determined based on the status tag base address. For a 4KB guest physical page size, the number of shifts can be 12 bits. After obtaining the target index value, the target index value is added to the status tag base address to determine the status tag address where the target status tag is located. The status tag address is the location of the target status tag in the status tag area. For example, when the client physical page size is 4KB, the number of shift bits of the bit operation in the preset index relationship can be 12 bits, and the status mark base address is SFbase. Then the target index value can be the client physical address (GPA) of the memory to be accessed>>12, that is, the GPA is shifted right by 12 bits. For the target status mark of the client physical page where the memory physical address GPA to be accessed is located, its corresponding status mark address can be determined based on SFbase+(GPA>>12).

[0036] Step 202: Read the target status mark from the status mark area based on the status mark address and a preset mark size.

[0037] In an embodiment of the present invention, since the size of the status flag data in the status flag area is a preset size, the status flag data of the preset size can be read from the status flag area based on the status flag address as the target status flag. For example, the status flag data of the preset size can be sequentially read from the status flag address in the status flag area to obtain or set the status flag of the physical page. For example, 8 bits of data can be read from SFbase+(GPA>>12) as the target status flag.

[0038] For example, for each client physical page in the target physical memory space of the client, the corresponding status flag is stored in the status flag area. For example, the corresponding relationship between a 4KB client physical page in the target physical memory space and an 8-bit status flag in the status flag area can be as follows: Figure 2 shown.

[0039] In an embodiment of the present invention, the status mark address can be determined through the target index value, and then the target status mark can be directly read in the status mark area. Compared with the existing technology of obtaining the status mark data of the client physical page by traversing the tree structure, the convenience and efficiency of data acquisition are improved.

[0040] Step 102: When the target status flag matches the target memory access operation indicated by the source memory access instruction, determine the host virtual mapping address corresponding to the client physical address to be accessed based on the direct address mapping rule; the direct address mapping rule is used to describe the mapping relationship established by linear operation between the target physical memory space of the client and the target virtual memory space in the host virtual memory space.

[0041] In an embodiment of the present invention, since the target status mark can represent the state of the client physical page corresponding to the client physical address to be accessed, the memory access permission of the client physical address to be accessed can be determined based on the target status mark. The target status mark is matched with the target memory access operation to determine whether the target status mark matches the target memory access operation. The target memory access operation refers to the memory access operation indicated by the source memory access instruction, such as a read operation or a write operation. Since the target status mark corresponding to the client physical page can accurately reflect and indicate whether the target memory access operation performed on the page is legal or expected, by matching the target status mark with the target memory access operation, it can be determined whether the target memory access operation can be legally executed. The matching of the target status mark and the target memory access operation can be specifically reflected in that the memory access permission of the target memory access operation to the client physical page corresponding to the client physical address to be accessed should be consistent with the memory access permission represented by the target status mark. For example, if the target memory access operation is a write operation and the memory access permission indicated by the target status tag indicates that write operations are allowed, then the target status tag and the target memory access operation match. If the target memory access operation is a write operation and the memory access permission indicated by the target status tag indicates that write operations are not allowed or read-only, then the target status tag and the target memory access operation do not match. If the target status tag and the target memory access operation match, the target memory access operation can be executed. If the target status tag and the target memory access operation do not match, an exception is triggered, and the binary translator intercepts the target memory access operation and handles the exception first.

[0042] When the target status flag matches the target memory access operation, the host virtual mapping address corresponding to the client physical address to be accessed is determined based on the direct address mapping rule. The host virtual mapping address belongs to the host virtual memory space. The direct address mapping rule is used to describe the direct mapping relationship established by linear operation between the target virtual memory space in the host virtual memory space and the target physical memory space of the client, that is, there is a fixed linear relationship between the target virtual memory space in the host virtual memory space and the target physical memory space of the client. The client physical address in the target virtual memory space and the virtual mapping address in the target virtual memory space can be directly converted through linear operation based on the direct address mapping rule. Based on the direct address mapping rule, the host virtual mapping address corresponding to the client physical address to be accessed in the target virtual memory space can be determined. Exemplarily, the direct address mapping rule can be a simple linear operation, and the address mapping can be completed by only one addition operation. For example, the host virtual mapping address is directly obtained by directly calculating the starting mapping address of the target virtual memory space divided in the host plus the client physical address to be accessed.

[0043] Step 103: Execute the target memory access operation on the target host machine physical address corresponding to the host machine virtual mapping address.

[0044] In an embodiment of the present invention, when the host virtual mapping address is determined, it is necessary to convert the host virtual mapping address into a target host physical address of the host, and then perform a target memory access operation on the target host physical address. For example, the host virtual mapping address can be converted by the host operating system, for example, by traversing the host page table to determine the host physical address corresponding to the host virtual mapping address as the target host physical address.

[0045] To sum up, in an embodiment of the present invention, when a source memory access instruction of a client is binary translated, a target status mark corresponding to the client physical address to be accessed is determined based on a status mark area in a virtual memory space of a host machine; the client physical address to be accessed is obtained based on the client virtual address to be accessed indicated by the source memory access instruction; when the target status mark matches the target memory access operation indicated by the source memory access instruction, a host virtual mapping address corresponding to the client physical address to be accessed in the virtual memory space of the host machine is determined based on a direct address mapping rule; the direct address mapping rule is used to describe a mapping relationship between a target physical memory space of the client and a target virtual memory space in the virtual memory space of the host machine, established through linear operations; and a target memory access operation is performed on the target host physical address corresponding to the host virtual mapping address. In this way, through direct address mapping rules, the host virtual mapping address corresponding to the client physical address to be accessed can be directly determined. The binary translator can efficiently perform binary translation and execution of client instructions, ensuring correct memory access between different instruction set architectures (ISAs) and achieving correct mapping between the source instruction set address space corresponding to the client and the target instruction set address space corresponding to the host. This avoids the performance overhead caused by multiple search traversals and memory accesses, eliminates the need for multiple search traversals, reduces the overhead in the address mapping process, improves the efficiency of address translation, and enhances the overall operating efficiency and performance of the system. This, in turn, reduces CPU usage, reduces memory access latency, and reduces the number of interactions between the client and the host.

[0046] Furthermore, the embodiment of the present invention first determines the client physical address of the memory to be accessed based on the client virtual address of the memory to be accessed, and then determines the host virtual mapping address corresponding to the client physical address of the memory to be accessed, thereby hierarchically decoupling the conversion processes between GVA, GPA, and HVA. This ensures that the same physical memory can be accessed by the GVAs of different processes while also ensuring that the client physical address can be correctly mapped to the host address space. In a shared memory scenario, this avoids the problem of address conversion errors and data sharing caused by different GVAs being mapped to different HVAs when multiple processes access the same physical memory through different virtual addresses.

[0047] Optionally, the embodiment of the present invention may further include the following steps:

[0048] Step 301: Apply for the target virtual memory space that matches the target physical memory space in the host machine virtual memory space; the target virtual memory space is a continuous memory space.

[0049] In an embodiment of the present invention, in order to achieve efficient simulation and direct mapping of the client's physical memory space, a method of demarcating a continuous memory area in the host virtual address (HVA) space can be adopted to construct a simulation environment corresponding to the guest physical address (GPA) space. Specifically, under the host operating system memory management framework, a specific memory allocation mechanism (for example, calling the memory allocation interface provided by the operating system or using a specific memory pool management strategy) is used to apply for a section of HVA space with a clear starting address and size. The HVA space obtained by this application is specially configured to simulate the client's physical memory space, that is, it is directly mapped to the client's GPA space. During the mapping process, a one-to-one correspondence is established between the HVA space address and the GPA space address expected by the client, so that logically, operations on the HVA space are equivalent to operations on the client's physical memory space.

[0050] As a software entity running on the host machine, the binary translator can directly access the guest's physical memory contents using the HVA space, which has been applied for and configured as GPA space, without requiring complex address translation or additional memory access operations. Through this direct mapping mechanism, the binary translator can efficiently translate and execute guest code, avoiding the performance overhead associated with multiple layers of address translation and memory access in traditional methods, significantly improving the overall system efficiency and performance.

[0051] In an embodiment of the present invention, a unified, continuous host virtual address space is used to simulate the client's target physical memory space. This ensures a fixed offset between the client physical address and the host virtual mapping address, resulting in a direct linear computational relationship between the client physical address and the host virtual mapping address. This allows the determination of a direct address mapping rule between the guest physical address (GPA) and the host virtual mapping address (HVA). A target virtual memory space matching the client's target physical memory space is pre-requested in the host virtual memory space. The target physical memory space is the entire physical memory space corresponding to the client and can be either continuous or non-contiguous. Based on the size of the memory range formed by the starting address (or lowest address) and ending address (or highest address) of the target physical memory space, a continuous host virtual memory space of the same size as the memory range is requested in the host virtual memory space as the target virtual memory space.

[0052] In the case that the target physical memory space is a continuous memory space, the size of the memory range formed between the starting address (or lowest address) and the ending address (or highest address) of the target physical memory space is equal to the actual size of the target physical memory space. In this case, a host virtual memory space with the same size as the target physical memory space can be directly applied in the host virtual memory space as the target virtual memory space. For example, Figure 3 As shown, for an actual size of the target physical memory space of 0-4G, a 4G continuous host virtual memory space can be applied for in the host virtual memory space as the target virtual memory space.

[0053] In the case where the target physical memory space includes at least two non-contiguous memory segments, that is, the target physical memory space is non-contiguous, step 301 may include the following steps:

[0054] Step 401: Apply for a continuous host virtual memory space that meets the target size in the host virtual memory space as the target virtual memory space; the target size is determined based on the memory range size formed by the starting address of the first memory segment and the ending address of the last memory segment in the at least two non-contiguous memory segments.

[0055] In an embodiment of the present invention, when the target physical memory space includes at least two non-contiguous memory segments, the size of the memory range formed between the starting address (or lowest address) and the ending address (or highest address) of the target physical memory space is not equal to the actual size of the target physical memory space. Therefore, the target size of the memory range formed between the starting address (or lowest address) and the ending address (or highest address) of the target physical memory space can be determined first, and a continuous host virtual memory space that meets the target size can be applied in the host virtual memory space as the target virtual memory space. For example, it can be as follows Figure 4 As shown, the target physical memory space of the client contains at least two non-contiguous memory segments, namely 0-3G and 4G-5G. The target size of the memory range formed by the starting address (or lowest address) and the ending address (or highest address) of the target physical memory space is 5G. Then, a 5G continuous host virtual memory space can be applied for in the host virtual memory space as the target virtual memory space.

[0056] In an embodiment of the present invention, when the target physical memory space contains at least two non-contiguous memory segments, by applying for a continuous host virtual memory space of the target size, the target virtual memory space can still cover the entire target physical memory space, thereby realizing a direct mapping relationship between the client physical address and the host virtual mapping address, ensuring that the host virtual mapping address can be determined based on the direct address mapping rule.

[0057] Step 302: Map the target physical memory space and the target virtual memory space one by one, and determine the direct address mapping rule.

[0058] In an embodiment of the present invention, a one-to-one mapping is performed between the guest physical addresses in the target physical memory space and the virtual mapping addresses in the target virtual memory space, while the starting address of the target virtual memory space is recorded as the starting mapping address. Exemplarily, the one-to-one mapping operation is performed between the target physical memory space and the target virtual memory space, with the mapping being performed using physical pages as the basic unit. The specific steps may be as follows: first, the target physical memory space is partitioned into multiple physical pages of fixed size and with unique physical addresses; concurrently, the target virtual memory space is partitioned accordingly, generating the same number of virtual pages as the physical pages, each virtual page also having a unique virtual address. The physical pages of the target physical memory space can then be sequentially mapped one-to-one with the physical pages of the target virtual memory space. During the binary translation process, when accessing the target physical memory space, the host virtual mapping address (virtual page) corresponding to the guest physical address (physical page) to be accessed is calculated according to direct address mapping rules, thereby achieving a precise one-to-one mapping between the target physical memory space and the target virtual memory space at the physical page level.

[0059] Since the memory range formed by the starting address (or lowest address) and the ending address (or highest address) of the target physical memory space is the same size as the target virtual memory space, after mapping the client physical address in the target physical memory space and the virtual mapping address in the target virtual memory space one by one with physical pages as the basic unit, the virtual mapping address can be directly calculated based on the starting mapping address and the client physical address. Therefore, it can be determined that the direct address mapping rule is that the virtual mapping address of the host machine is determined by directly performing linear operations based on the target calculation formula, the starting mapping address corresponding to the target virtual memory space, and the client physical address. For example, assuming that the starting mapping address is RAMbase, the target calculation formula is virtual mapping address = client physical address + RAMbase. For example Figure 3 as well as Figure 4 As shown, the fixed mapping relationship between the virtual mapping address and the guest physical address can be calculated through the offset value RAMbase.

[0060] In an embodiment of the present invention, by completing the simulation of the target physical memory space of the client within the virtual memory space of the host machine, constructing a fixed offset relationship between the virtual mapping address and the client physical address, and determining the direct address mapping rules, the mapping relationship between the virtual mapping address and the client physical address can be simplified, thereby accelerating the conversion process from the client physical address to the virtual mapping address.

[0061] Optionally, step 102 may include the following steps:

[0062] Step 501: Calculate a virtual mapping address corresponding to the client physical address to be accessed based on the client physical address to be accessed, the starting mapping address, and the target calculation formula.

[0063] Step 502: Determine the virtual mapping address as the host machine virtual mapping address.

[0064] In an embodiment of the present invention, based on the client physical address of the memory to be accessed and the starting mapping address, the virtual mapping address corresponding to the client physical address of the memory to be accessed can be directly calculated, and the virtual mapping address can be directly determined as the host virtual mapping address corresponding to the client physical address of the memory to be accessed. Exemplarily, the target calculation formula corresponding to the direct address mapping rule can be HVA (virtual mapping address) = GPA (client physical address) + RAMbase. It can be understood that when the starting mapping address RAMbase of the target virtual memory space is 0, the target calculation formula corresponding to the direct address mapping rule can be further simplified to HVA (virtual mapping address) = GPA (client physical address). In this way, the host virtual mapping address is directly calculated through the target calculation formula, the client physical address of the memory to be accessed, and the starting mapping address, which accelerates the address conversion process and improves the address conversion efficiency.

[0065] Optionally, after step 102, the embodiment of the present invention may further include the following steps:

[0066] Step 601: Cache the first mapping relationship between the to-be-accessed guest virtual address and the host virtual mapping address, and the target status flag into a designated cache space.

[0067] In an embodiment of the present invention, after determining the host virtual mapping address corresponding to the guest physical address to be accessed, the address mapping process from the guest virtual address to be accessed (GVA) to the guest physical address to be accessed (GPA) and then to the host virtual mapping address (HVA) is completed. Therefore, in order to further improve the efficiency of address mapping, the first mapping relationship between the guest virtual address to be accessed and the host virtual mapping address, as well as the target state flag corresponding to the guest physical address to be accessed, can be cached in a designated cache space. For example, the guest virtual address to be accessed, the host virtual mapping address, and the target state flag can be stored as a table entry in the designated cache space. The designated cache space can be a high-speed cache component in hardware or a data space corresponding to a cache data structure using a software-based translation lookaside buffer (TLB).

[0068] In an embodiment of the present invention, by caching the first mapping relationship between the client virtual address to be accessed and the host virtual mapping address and the target status mark in the designated cache space, it is convenient to directly determine the host virtual mapping address and the target status mark in the designated cache space when performing address conversion on the client virtual address to be accessed, thereby improving the execution efficiency of the address conversion and further accelerating the address conversion process.

[0069] Optionally, before step 101, the embodiment of the present invention may include the following steps:

[0070] Step 701: Based on the client virtual address to be accessed, search within multiple sets of table entries stored in the specified cache space to obtain a target search result; any table entry contains a mapping relationship between the client's client virtual address and the host's virtual mapping address, as well as a status mark of the client physical address corresponding to the client virtual address.

[0071] In an embodiment of the present invention, based on a client virtual address to be accessed, a table entry matching the client virtual address to be accessed is searched for in multiple sets of entries stored in a designated cache space. Each entry contains a mapping relationship between the client virtual address of the client and the virtual mapping address of the host machine, as well as a status flag for the client physical address corresponding to the client virtual address. That is, each entry contains a set of the client virtual address of the client, the virtual mapping address of the host machine, and the status flag for the client physical address corresponding to the client virtual address. It is understood that the target storage format of the status flag in the designated cache space is determined based on the data format supported by the designated cache space. Accordingly, the status flag stored in the designated cache space can be the same as the status flag stored in the status flag area, or can be obtained by format conversion of the status flag stored in the status flag area. This is not limited in the embodiment of the present invention. For example, the status flag in the status flag area can be 8-bit data, and accordingly, the status flag stored in the designated cache space is also 8-bit data. The status flag in the status flag area can also be in other formats. After reading the status flag from the status flag area, the status flag can be converted to a data format supported by the designated cache space, and the format-converted status flag is then stored as the content of the table entry in the designated cache space.

[0072] When any target table entry contains the virtual address of the client to be accessed, it indicates that the target table entry matches the virtual address of the client to be accessed, that is, the target table entry contains the mapping relationship between the virtual address of the client to be accessed and the virtual mapping address of the host machine and the status mark corresponding to the physical address of the client to be accessed corresponding to the virtual address of the client to be accessed. Therefore, the search is successful, and the target search result obtained is the target table entry.

[0073] When none of the table entries contain the client virtual address to be accessed, it represents the first mapping relationship between the client virtual address to be accessed and its corresponding host virtual mapping address that is not cached in the specified cache space, and the corresponding status mark. Then, there is no table entry in the specified cache space that matches the client virtual address to be accessed, the search fails, and the target search result is obtained.

[0074] Step 702: When the target search result indicates a search failure, executing the step of determining the target status mark corresponding to the client physical address to be accessed based on the status mark area in the host virtual memory space.

[0075] In the embodiment of the present invention, when the target search result indicates a search failure, step 101 is executed, that is, determining the host virtual mapping address by using a direct address mapping rule and determining the target status mark based on the status mark area.

[0076] Step 703: If the target search result indicates that the search is successful, determine the target status flag and the host virtual mapping address based on the target table entry indicated by the target search result.

[0077] In an embodiment of the present invention, when the target search result indicates that the search is successful, it indicates the first mapping relationship between the client virtual address to be accessed and its corresponding host virtual mapping address in the cache in the specified cache space and the target status mark, then the target status mark and the host virtual mapping address can be directly determined based on the target table entry indicated by the target search result. According to the target status mark, it is determined whether the target memory access operation can be performed on the target host physical address corresponding to the host virtual mapping address. Exemplarily, when the target status mark matches the target memory access operation, the target memory access operation can be performed on the target host physical address corresponding to the host virtual mapping address; when the target status mark does not match the target memory access operation, the target memory access operation is not performed on the target host physical address corresponding to the host virtual mapping address, and an exception is triggered.

[0078] In an embodiment of the present invention, by first searching in the specified cache space, if the search is successful, the target status mark and the host virtual mapping address can be directly determined, thereby improving the address conversion efficiency to a certain extent; if the search fails, the host virtual mapping address can be determined based on the direct address mapping rule and the target status mark can be determined based on the status mark area. The address conversion method provided by the embodiment of the present invention is combined with the address cache mechanism to speed up the address memory access efficiency.

[0079] Optionally, the embodiment of the present invention may further include the following steps:

[0080] Step 801: When the target state flag corresponding to the client physical address to be accessed indicates that the client physical address to be accessed belongs to a memory-mapped input / output memory area, stop executing the target memory access operation and trigger an exception.

[0081] In an embodiment of the present invention, when the client physical address to be accessed belongs to a memory-mapped input-output memory area, since the MMIO memory area cannot directly access memory, a special mark is required to avoid direct memory access. In this case, at least the status mark corresponding to the client physical address to be accessed will be set to the MMIO memory area at the corresponding position in the status mark area to mark the special memory access permission of the address. Therefore, in the case where the target status mark corresponding to the client physical address to be accessed indicates that the client physical address to be accessed belongs to a memory-mapped input-output memory area (MMIO), since the MMIO memory area cannot directly access memory, the target status mark and the target status mark do not match. Therefore, it is necessary to stop the target memory access operation and trigger an exception. Exemplarily, the corresponding software device simulation interface in the binary translator can be called, for example, the interface function of the corresponding IO device is called to access the client physical address to be accessed.

[0082] Step 802: When the target state flag corresponding to the client physical address to be accessed indicates that the client physical address to be accessed belongs to a self-modifying code region and the target memory access operation is a write operation, stop executing the target memory access operation and trigger an exception.

[0083] In an embodiment of the present invention, when the client physical address to be accessed belongs to a self-modifying code region, since the SMC region cannot perform write operations, the status flag corresponding to the client physical address to be accessed is at least set to the SMC region at the corresponding position in the status flag area to mark the address as having special memory access permissions. Therefore, if the target status flag corresponding to the client physical address to be accessed indicates that the client physical address to be accessed belongs to a self-modifying code region (SMC), since the SMC region cannot perform write operations, if the target memory access operation is a write operation, the target status flag and the target status flag will not match. Therefore, the target memory access operation needs to be stopped and an exception triggered. Exemplarily, the binary translator needs to perform SMC-related processing to complete the client's memory access. For example, the binary translator will cache the translated code (translated target instruction) corresponding to the host machine and determine whether the target memory access operation (write operation for the client physical address to be accessed) violates the consistency between the translated code (translated target instruction) corresponding to the host machine and the client's source code (source memory access instruction). If so, the binary translator needs to invalidate the translated code (translated target instruction) to ensure correctness.

[0084] In an embodiment of the present invention, by specifically managing memory access permissions for the SMC area and MMIO area in the binary translation scenario and setting corresponding status marks, the particularity and importance of these two areas in the binary translation process are fully taken into account, and memory access operations can be controlled more accurately, effectively avoiding various problems caused by illegal memory access. For the SMC area, it can prevent malicious code from making inappropriate modifications to the self-modifying code, avoiding system vulnerabilities or malicious attacks caused by arbitrary tampering with the code. For the MMIO area, it can prevent unauthorized read and write operations, avoid misoperation of hardware devices, ensure the normal operation of hardware devices and data security, thereby improving the security of the binary translation system as a whole.

[0085] Furthermore, during the binary translation process, the code in the SMC area may be dynamically modified, and access to the MMIO area requires interaction with hardware devices. The embodiments of the present invention can accurately identify and handle these special cases in the binary translation process, ensuring the correctness and efficiency of binary translation.

[0086] In one possible implementation, if the designated cache space corresponds to a cache data structure using a software Translation Lookaside Buffer (TLB), in other words, if the address cache mechanism is implemented based on a software TLB, then if a target lookup result obtained during a lookup of the designated cache space indicates a lookup failure, this indicates a software TLB entry miss. This software TLB entry miss can be caused by either the absence of an entry in the designated cache space that matches the target virtual address of the memory to be accessed, or a mismatch between the target status flag and the target memory access operation indicated by the source memory access instruction. Therefore, a determination can be made first as to whether a match is found for the target entry. If a match is found, indicating a lookup failure due to a mismatch between the target status flag and the target memory access operation indicated by the source memory access instruction, an exception is triggered and handled accordingly. For example, if the target physical address corresponding to the target virtual address of the memory to be accessed is an MMIO region, the corresponding IO device emulation interface in the binary translator can be first invoked to perform the target memory access operation on the target physical address of the memory to be accessed. If no match is found for the target entry, the operation in step 101 is then executed.

[0087] In another possible embodiment, if the designated cache space is a high-speed cache component in hardware, such as an MMU, in other words, the address cache mechanism is implemented based on a hardware TLB. Then, when the target search result obtained by searching the designated cache space indicates a search failure, it represents a hardware TLB table entry missing. The hardware TLB table entry missing may be caused by the fact that there is no table entry in the designated cache space that matches the client virtual address to be accessed. In this case, the operation of step 101 can be directly performed. When the target search result is a search success, if the target status flag in the target table entry does not match the target memory access operation indicated by the source memory access instruction, a hardware TLB exception will be triggered. At this time, the exception can be handled accordingly. For example, if the client physical address to be accessed corresponding to the client virtual address to be accessed is an MMIO area, the corresponding IO device simulation interface in the binary translator can be called first to perform the target memory access operation on the client physical address to be accessed.

[0088] For example, Figure 5 A specific schematic diagram of an address mapping method is shown in FIG. Figure 5 As shown, the address mapping process may include determining the virtual mapping address of the host machine corresponding to the client physical address through the client page table traversal, then determining the status of the client physical page through the status mark corresponding to the client physical address, and then performing a mapping relationship between the client virtual address and the virtual mapping address of the host machine and caching of the status mark in a designated cache space. In an embodiment of the present invention, the host machine virtual mapping address is determined based on a direct address mapping rule through direct mapping between the target physical memory space of the client machine and the target virtual memory space of the host machine. At the same time, by setting a flat status mark area in the host machine virtual memory space, the target status mark can be read directly and quickly. At the same time, in the address caching mechanism, combined with the method of determining the host machine virtual mapping address based on the direct address mapping rule, adaptive improvements are made to different address mapping stages, effectively improving the address conversion efficiency and address memory access efficiency.

[0089] Figure 6 FIG. 1 is a schematic diagram of the structure of an address mapping device provided by an embodiment of the present invention. Figure 6 As shown, the device may specifically include:

[0090] A first determining module 901 is configured to determine, when performing binary translation on a source memory access instruction of the client, a target status flag corresponding to a guest physical address to be accessed based on a status flag area in a virtual memory space of the host machine; the guest physical address to be accessed is obtained based on a guest virtual address to be accessed indicated by the source memory access instruction;

[0091] A second determining module 902 is configured to determine, when the target state flag matches the target memory access operation indicated by the source memory access instruction, a host virtual mapping address corresponding to the client physical address to be accessed based on a direct address mapping rule; the direct address mapping rule is configured to describe a mapping relationship established by linear operation between a target physical memory space of the client and a target virtual memory space in the host virtual memory space;

[0092] The first execution module 903 is configured to execute the target memory access operation on the target host machine physical address corresponding to the host machine virtual mapping address.

[0093] An embodiment of the present invention provides an address mapping device, which, when performing binary translation on a source memory access instruction of a client, determines a target status tag corresponding to a client physical address to be accessed based on a status tag area in a host virtual memory space; the client physical address to be accessed is obtained based on the client virtual address to be accessed indicated by the source memory access instruction; when the target status tag matches the target memory access operation indicated by the source memory access instruction, determines a host virtual mapping address in the host virtual memory space corresponding to the client physical address to be accessed; the direct address mapping rule is used to describe a mapping relationship established by linear operations between the target physical memory space of the client and the target virtual memory space in the host virtual memory space; and performs a target memory access operation on the target host physical address corresponding to the host virtual mapping address. In this way, through direct address mapping rules, the host virtual mapping address corresponding to the client physical address to be accessed can be directly determined. The binary translator can efficiently perform binary translation and execution of client instructions, ensuring correct memory access between different instruction set architectures (ISAs) and achieving correct mapping between the source instruction set address space corresponding to the client and the target instruction set address space corresponding to the host. This avoids the performance overhead caused by multiple search traversals and memory accesses, eliminates the need for multiple search traversals, reduces the overhead in the address mapping process, improves the efficiency of address translation, and enhances the overall operating efficiency and performance of the system. This, in turn, reduces CPU usage, reduces memory access latency, and reduces the number of interactions between the client and the host.

[0094] Furthermore, the embodiment of the present invention first determines the client physical address of the memory to be accessed based on the client virtual address of the memory to be accessed, and then determines the host virtual mapping address corresponding to the client physical address of the memory to be accessed, thereby hierarchically decoupling the conversion processes between GVA, GPA, and HVA. This ensures that the same physical memory can be accessed by the GVAs of different processes while also ensuring that the client physical address can be correctly mapped to the host address space. In a shared memory scenario, this avoids the problem of address conversion errors and data sharing caused by different GVAs being mapped to different HVAs when multiple processes access the same physical memory through different virtual addresses.

[0095] Optionally, the device further comprises:

[0096] A first application module is configured to apply for the target virtual memory space that matches the target physical memory space in the host machine virtual memory space; the target virtual memory space is a continuous memory space;

[0097] The first mapping module is used to map the target physical memory space and the target virtual memory space one by one, and determine the direct address mapping rule.

[0098] Optionally, the direct address mapping rule is that the virtual mapping address of the host machine is determined based on a target calculation formula, a starting mapping address corresponding to the target virtual memory space, and a client physical address; and the second determining module 902 includes:

[0099] A first calculation module is configured to calculate a virtual mapping address corresponding to the client physical address to be accessed based on the client physical address to be accessed, the starting mapping address and the target calculation formula;

[0100] The first determining submodule is configured to determine the virtual mapping address as the host machine virtual mapping address.

[0101] Optionally, the device further comprises:

[0102] The first cache module is used to cache the first mapping relationship between the client virtual address to be accessed and the host virtual mapping address, and the target state mark into a designated cache space.

[0103] Optionally, the device further comprises:

[0104] A first search module is configured to search multiple sets of entries stored in a designated cache space based on the client virtual address to be accessed, to obtain a target search result; wherein any entry includes a mapping relationship between the client virtual address of the client and the virtual mapping address of the host machine, and a status flag of the client physical address corresponding to the client virtual address;

[0105] A first execution module is configured to, when the target search result indicates a search failure, execute the step of determining a target status mark corresponding to a client physical address to be accessed based on the status mark area in the host virtual memory space;

[0106] A third determining module is configured to determine the target state flag and the host machine virtual mapping address based on the target table entry indicated by the target search result when the target search result indicates that the search is successful.

[0107] Optionally, the first determining module 901 includes:

[0108] a second determining submodule, configured to determine a status mark address based on a status mark base address and a target index value of the status mark area; the target index value being determined based on the client physical address to be accessed and a preset index relationship, wherein the preset index relationship is determined based on a physical page size of the client;

[0109] The first reading module is configured to read the target status mark from the status mark area based on the status mark address and a preset mark size.

[0110] Optionally, when the target physical memory space includes at least two non-contiguous memory segments, the first application module includes:

[0111] The first application sub-module is used to apply for a continuous host virtual memory space that meets the target size in the host virtual memory space as the target virtual memory space; the target size is determined based on the memory range size formed by the starting address of the first memory segment and the ending address of the last memory segment in the at least two non-contiguous memory segments.

[0112] Optionally, the device further comprises:

[0113] A first processing module is configured to stop executing the target memory access operation and trigger an exception if the target state flag corresponding to the client physical address to be accessed indicates that the client physical address to be accessed belongs to a memory-mapped input / output memory area;

[0114] The second processing module is configured to stop executing the target memory access operation and trigger an exception if the target status mark corresponding to the client physical address to be accessed indicates that the client physical address to be accessed belongs to a self-modifying code area and the target memory access operation is a write operation.

[0115] The present invention also provides an electronic device, see Figure 7, including: a processor 1001, a memory 1002, and a computer program 10021 stored in the memory and executable on the processor, wherein the processor implements the address mapping method of the aforementioned embodiment when executing the program.

[0116] The present invention also provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute the address mapping method of the aforementioned embodiment.

[0117] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0118] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general-purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing this type of system. In addition, the present invention is not directed to any specific programming language. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the above description of specific languages ​​is for the purpose of disclosing the best mode of the present invention.

[0119] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0120] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0121] Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively modified and installed in one or more devices different from the embodiments. The modules, units, or components in the embodiments can be combined into a single module, unit, or component, and furthermore, they can be divided into multiple sub-modules, sub-units, or sub-components. All features disclosed in this specification (including the accompanying claims, abstract, and drawings), and all processes or units of any method or device disclosed therein, can be combined in any combination, unless at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0122] The various component embodiments of the present invention may be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will appreciate that in practice, a microprocessor or digital signal processor (DSP) may be used to implement some or all of the functions of some or all of the components of the sorting device according to the present invention. The present invention may also be implemented as an apparatus or device program for performing part or all of the methods described herein. Such a program implementing the present invention may be stored on a computer-readable medium or in the form of one or more signals. Such signals may be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0123] It should be noted that the above embodiments illustrate rather than limit the invention, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising several different elements and by means of appropriately programmed computers. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0124] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0125] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0127] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An address mapping method, characterized in that: The method comprises: In the case of performing binary translation on a source memory access instruction of the client, determining a target state flag corresponding to a guest physical address to be accessed based on a state flag area in a virtual memory space of the host machine; the guest physical address to be accessed is obtained based on a guest virtual address to be accessed indicated by the source memory access instruction; In a case where the target state flag matches the target memory access operation indicated by the source memory access instruction, determining a host machine virtual mapping address corresponding to the client physical address to be accessed based on a direct address mapping rule; the direct address mapping rule is used to describe a mapping relationship established by linear operation between a target physical memory space of the client and a target virtual memory space in the host machine virtual memory space; Executing the target memory access operation on the target host machine physical address corresponding to the host machine virtual mapping address; The step of determining a target status mark corresponding to a client physical address to be accessed based on a status mark area in a host virtual memory space includes: Determining a status mark address based on a status mark base address and a target index value of the status mark area; the target index value is determined based on the client physical address to be accessed and a preset index relationship, and the preset index relationship is determined based on a physical page size of the client; The target status flag is read from the status flag area based on the status flag address and a preset flag size.

2. The method according to claim 1, characterized in that The method further comprises: Applying for the target virtual memory space that matches the target physical memory space in the host machine virtual memory space; the target virtual memory space is a continuous memory space; The target physical memory space and the target virtual memory space are mapped one by one, and the direct address mapping rule is determined.

3. The method according to claim 2, characterized in that The direct address mapping rule is that the virtual mapping address of the host machine is determined based on a target calculation formula, a starting mapping address corresponding to the target virtual memory space, and a guest physical address; and determining the host machine virtual mapping address corresponding to the guest physical address to be accessed based on the direct address mapping rule includes: Calculating a virtual mapping address corresponding to the client physical address to be accessed based on the client physical address to be accessed, the starting mapping address, and the target calculation formula; The virtual mapping address is determined as the host machine virtual mapping address.

4. The method according to claim 1, wherein After determining the host machine virtual mapping address corresponding to the client physical address to be accessed based on the direct address mapping rule, the method further includes: The first mapping relationship between the to-be-accessed client virtual address and the host machine virtual mapping address, and the target state mark are correspondingly cached in a designated cache space.

5. The method according to claim 1, wherein Before determining the target status mark corresponding to the client physical address to be accessed based on the status mark area in the host virtual memory space, the method further includes: Based on the client virtual address to be accessed, a search is performed in multiple sets of table entries stored in a designated cache space to obtain a target search result; any table entry contains a mapping relationship between the client virtual address of the client and the virtual mapping address of the host machine and a status flag of the client physical address corresponding to the client virtual address; If the target search result indicates a search failure, performing the step of determining the target status mark corresponding to the client physical address to be accessed based on the status mark area in the host virtual memory space; In a case where the target search result indicates that the search is successful, the target state flag and the host virtual mapping address are determined based on the target table entry indicated by the target search result.

6. The method according to claim 2, characterized in that In a case where the target physical memory space includes at least two non-contiguous memory segments, applying for the target virtual memory space matching the target physical memory space in the host virtual memory space includes: A continuous host virtual memory space that meets the target size is applied for in the host virtual memory space as the target virtual memory space; the target size is determined based on the memory range size formed by the starting address of the first memory segment and the ending address of the last memory segment in the at least two non-contiguous memory segments.

7. The method according to claim 1, characterized in that The method further comprises: When the target state flag corresponding to the client physical address to be accessed indicates that the client physical address to be accessed belongs to a memory-mapped input / output memory area, stopping execution of the target memory access operation and triggering an exception; When the target state flag corresponding to the client physical address to be accessed indicates that the client physical address to be accessed belongs to a self-modifying code region and the target memory access operation is a write operation, execution of the target memory access operation is stopped and an exception is triggered.

8. An address mapping device, characterized in that: The device comprises: A first determining module is configured to determine, when performing binary translation on a source memory access instruction of the client, a target status flag corresponding to a client physical address to be accessed based on a status flag area in a virtual memory space of the host machine; the client physical address to be accessed is obtained based on a client virtual address to be accessed indicated by the source memory access instruction; a second determining module configured to determine, when the target state flag matches the target memory access operation indicated by the source memory access instruction, a host virtual mapping address corresponding to the client physical address to be accessed based on a direct address mapping rule; the direct address mapping rule being configured to describe a mapping relationship established by linear operation between a target physical memory space of the client and a target virtual memory space in the host virtual memory space; A first execution module, configured to execute the target memory access operation on the target host machine physical address corresponding to the host machine virtual mapping address; The first determining module includes: a second determining submodule, configured to determine a status mark address based on a status mark base address and a target index value of the status mark area; the target index value being determined based on the client physical address to be accessed and a preset index relationship, wherein the preset index relationship is determined based on a physical page size of the client; The first reading module is configured to read the target status mark from the status mark area based on the status mark address and a preset mark size.

9. The device according to claim 8, characterized in that The device further comprises: A first application module is configured to apply for the target virtual memory space that matches the target physical memory space in the host machine virtual memory space; the target virtual memory space is a continuous memory space; The first mapping module is configured to map the target physical memory space to the target virtual memory space one by one and determine the direct address mapping rule.

10. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the address mapping method according to any one of claims 1 to 7 when executing the program.

11. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the address mapping method according to any one of claims 1 to 7.

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