DNA (Deoxyribose Nucleic Acid) data storage hardware accelerated reading system and device based on heterogeneous calculation

Abstract

The invention discloses a DNA data storage hardware accelerated reading system and device based on heterogeneous calculation. The system comprises a base sequence mapping module, a splicing and recovery module and a control module in a CPU, a first off-chip memory and a second off-chip memory in a static area of an FPGA, and an RAM read / write interface and a DNA data storage recovery kernel in a dynamic area. A DNA sequencing data file is converted into a bit sequence through the base sequence mapping module, and the control module calls the PCIe interface to transmit the bit sequence to the first off-chip memory and generates an acceleration kernel startup control signal; a DNA data storage recovery kernel calls a bit sequence, a code word sequence is obtained after primer sequence recognition, label verification, majority voting judgment, effective sequence screening, de-interleaving and LDPC decoding and stored in a first off-chip memory, a control module reads the code word sequence from the first off-chip memory and transmits the code word sequence to a splicing and recovery module to be recombined, and the splicing and recovery module recovers the code word sequence. And reconstructing to obtain an original file corresponding to the DNA sequencing data file.

Description

Technical Field

[0001] The present invention relates to the technical field of DNA data storage and rapid data readout, and more particularly to a DNA data storage hardware accelerated readout system and device based on heterogeneous computing. Background Art

[0002] With the explosive growth of global data, traditional storage media face enormous challenges in meeting large-scale storage demands. Synthetic DNA, due to its ultra-high storage density, long-term stability, low energy consumption, and low maintenance costs, has become a promising long-term data storage medium. However, in large-scale parallel synthesis, DNA synthesis remains limited to relatively short sequences, typically less than 300 nt. Therefore, most DNA storage systems adopt a distributed strategy, partitioning data into multiple sub-blocks, each encoded as an independent DNA molecule. For example, storing 1 TB of data may require approximately 30 billion unique DNA strands.

[0003] Efficient data retrieval from DNA storage relies on highly redundant sequencing to ensure accuracy and completeness. This process generates a large number of sequencing reads through parallel output, which poses a huge computational challenge that traditional architectures cannot cope with. In addition, traditional clustering and multiple sequence alignment (MSA) algorithms incur a large computational cost when processing a large number of sequencing reads. To facilitate sequence identification, each DNA chain is assigned a unique label sequence, which is usually encoded with an error correction code (ECC) to enhance error resistance. Although ECC-based label decoding can reduce complexity to a certain extent, the computational burden is still heavy in large-scale storage situations. Therefore, achieving high-throughput and low-latency DNA data retrieval remains a severe challenge.

[0004] Traditional CPU-based architectures are increasingly unable to meet the intensive computational demands of DNA data readout. Heterogeneous computing, integrating multiple accelerators such as CPUs, GPUs, and FPGAs, has emerged as a promising approach. It overcomes the performance bottlenecks of single-processor architectures under high workloads. Recently, several studies have explored heterogeneous computing approaches to accelerate local sequence alignment and MSA in DNA readout. For example, Smith-Waterman (SW) alignment, due to its high computational complexity, has been hardware-accelerated on FPGAs. Parallel processing models for MSA on CPU-GPU heterogeneous platforms have been proposed. To facilitate large-scale DNA storage verification, an FPGA-based edit distance calculation accelerator and a DNA storage heterogeneous architecture simulation platform (DNA Storage Simulator, DNAssim) have been developed. However, existing work primarily focuses on accelerating individual tasks such as edit distance calculation, lacking integrated hardware acceleration solutions for the entire DNA readout pipeline. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the existing technology and propose a DNA data storage hardware acceleration readout system and device based on heterogeneous computing. By adopting a task-level pipeline mechanism, key tasks such as primer sequence identification, label verification, valid sequence screening, majority voting judgment and LDPC decoding in the DNA data readout process are optimized, thereby achieving acceleration of the DNA data readout process.

[0006] The objectives of the present invention are achieved through the following technical solutions.

[0007] A DNA data storage hardware-accelerated data readout system based on heterogeneous computing includes a base sequence mapping module, a splicing and recovery module, and a control module within a CPU, as well as a first off-chip memory in a static area of an FPGA, a second off-chip memory, a RAM read / write interface with a dynamic area, and a DNA data storage recovery core. The control module uses a PCIe interface to perform data transmission with the first off-chip memory and controls the DNA data storage recovery core. The DNA data storage recovery core performs data transmission with the first off-chip memory and the second off-chip memory respectively through the RAM read / write interface.

[0008] The DNA sequencing data file is processed by the base sequence mapping module to obtain a bit sequence; the control module transmits the bit sequence to the first off-chip memory through the PCIe interface, and generates an acceleration core startup control signal and transmits it to the DNA data storage recovery core; after receiving the signal, the DNA data storage recovery core reads the bit sequence in the first off-chip memory, and recovers the codeword sequence after primer sequence recognition, label verification, majority voting judgment, valid sequence screening, deinterleaving, and LDPC decoding, and stores it in the first off-chip memory; the control module reads the recovered codeword sequence from the first off-chip memory through the PCIe interface, inputs it into the splicing and recovery module to recombine it, and reconstructs the original file corresponding to the DNA sequencing data file; wherein, the second off-chip memory is used to store data generated during the data processing of the DNA data storage recovery core.

[0009] Furthermore, the DNA data storage and recovery core includes a first data buffer, a second data buffer, a third data buffer, a memory write interface, a copy number counting memory, two primer sequence recognition modules, two label check modules, a majority voting decision module, a valid sequence screening module, two deinterleaving modules and an LDPC decoding module;

[0010] The bit sequence in the first off-chip memory is cached in a first data buffer, and the cached bit sequence is divided into two groups and respectively input into two primer sequence recognition modules for recognition and calculation of primer numbers, and the primer numbers, valid signals, original labels, and data partial sequences are output. The valid signals, original labels, and data partial sequences output by each primer sequence recognition module are all used as inputs of the corresponding label verification module, and the labels are verified and the verified valid signals, label information bits, and data partial sequences are output. The primer numbers output by the two primer sequence recognition modules and the valid signals, label information bits, and data partial sequences output by the two label verification modules are all stored in the second data buffer; the memory write interface calculates a write address based on the label information bits and primer numbers stored in the second data buffer and writes the data partial sequence into the second off-chip memory; the copy number counting memory is addressed based on the label information bits and primer numbers output by the second data buffer and counts up the count value;

[0011] The majority voting judgment module sequentially reads the data portion sequence in the second off-chip memory and performs majority voting judgment based on the count value in the replica number counting memory to obtain a consensus sequence, an erasure mark sequence, and a valid signal. The valid sequence screening module performs data screening on the consensus sequence and the erasure mark sequence based on the valid signal of the majority voting judgment module;

[0012] The consensus sequence and erasure mark sequence output by the majority voting judgment module are respectively used as inputs of the two deinterleaving modules, and the valid signal output by the valid sequence screening module is used as the common input of the two deinterleaving modules. The codeword sequence containing errors, the erasure mark sequence, and the valid signal output by the two deinterleaving modules are all input into the LDPC decoding module for error correction decoding. The final codeword sequence and valid signal are output and stored in the third data buffer, and finally the output is stored in the first off-chip memory.

[0013] 10. The DNA data storage hardware-accelerated data readout system based on heterogeneous computing according to claim 2, wherein each of the primer sequence recognition modules comprises a first splitting unit, a second splitting unit, n Hamming distance calculation units, a multi-level comparison network unit, a reverse complementary sequence calculation unit, a modulo 2 calculation unit, and a comparator;

[0014] The first splitting unit splits the input bit sequence into a front-end primer sequence, a label and a data portion sequence; the input of each of the Hamming distance calculation units is the front-end primer sequence output by the first splitting unit, and the output is a Hamming distance value; the Hamming distance values output by all the Hamming distance calculation units are input into the multi-stage comparison network unit, and after multi-stage comparison processing, the output is the minimum Hamming distance value and its corresponding primer number; the minimum Hamming distance value and the set threshold are used as the input of the comparator, and when the minimum Hamming distance value is less than the set threshold, the comparator is set to output a high level as the effective signal output of the primer sequence recognition module; the modulo 2 calculation unit The input is a primer number obtained by the primer sequence recognition module, and the output is a selection signal of a two-choice selector; the reverse complementary sequence calculation unit includes a first register, a second register, and a two-choice selector, the first register is used to store the label and data part sequence output by the first splitting unit, and its reverse complementary sequence is calculated by combinational logic and stored in the second register, the two-choice selector selects to output the label and data part sequence stored in the first register or the reverse complementary sequence stored in the second register according to the selection signal output by the modulo 2 calculation unit; the data output by the two-choice selector is split into the original label and data part sequence by the second splitting unit.

[0015] Furthermore, each of the label verification modules includes a syndrome calculation unit, an AND gate, a first bit selector unit, a third register, and a fourth register; the syndrome calculation unit includes five multi-input XOR gates and a five-input OR gate, the input of the OR gate being the output of the five XOR gates, and the output of the OR gate serving as the output of the syndrome calculation unit; the original label output by the primer sequence recognition module is subjected to Hamming code verification by the syndrome calculation unit to obtain a verification success signal; the valid signal output by the primer sequence recognition module is stored in the third register, and the valid signal stored in the third register and the verification success signal output by the syndrome calculation unit are subjected to an AND gate operation to output a valid signal; the data partial sequence output by the primer sequence recognition module is stored and output by the fourth register; the original label output by the primer sequence recognition module is directly bit-selected by the first bit selector unit to obtain the label information bit output by the label verification module.

[0016] Furthermore, the majority voting decision module includes a bit splicing / splitting unit, a state machine, a two-to-one selector, a second shift unit, a sixth register, a seventh register, a second bit selection unit, and m majority voting decision calculation units; each of the majority voting decision calculation units includes a fifth register, a parallel addition tree, an OR gate, a first comparator, a second comparator, a third comparator, and a first shift unit;

[0017] The bit splicing / splitting unit reads the data partial sequence in the second off-chip memory and splits it into four data partial sequences with a bit width of m, and each data partial sequence with a bit width of m is further split into m 1-bit signals and input into m majority voting calculation units respectively;

[0018] Each of the majority voting decision calculation units uses a parallel addition tree to calculate and sum the four 1-bit wide inputs, and accumulates the results in its own fifth register; in each clock cycle, the output of the parallel addition tree is added to the value of the fifth register and stored in the fifth register; in the fourth clock cycle of a voting cycle, the value in the fifth register is shifted left by 1 bit by the first shift unit to obtain the shift data V N , V N and the number of copies C stored in the sixth register N After comparison by the first comparator, the output of the first comparator is Q[i], which represents the i-th bit of the consensus sequence, i∈[0,m-1];

[0019] Each of the majority voting decision calculation units calculates the erasure mark in the fourth clock cycle of a voting decision cycle; the number of copies C in the sixth register N and "0" as the input of the third comparator. If the comparison result is equal, the third comparator outputs a high level, indicating that there is no copy of the current data sequence, otherwise it outputs a low level; the shift data V N With the copy number C in the sixth register N as the input of the second comparator, if the comparison result is equal, the output of the second comparator is a high level, otherwise the output is a low level; the outputs of the second comparator and the third comparator are used as the input of the OR gate, and the output result of the OR gate is E[i], which represents the i-th bit mark of the erasure mark sequence, i∈[0,m-1];

[0020] The bit splicing / splitting unit combines the m-way signal Q[i] and the m-way signal E[i] with a bit width of 1 into an m-bit-wide consensus sequence and an m-bit-wide erasure mark sequence, respectively, as the output of the majority voting decision module;

[0021] After every 4 clock cycles, the state machine outputs a valid signal set to a high level as a valid signal output by the entire majority voting decision module; after every 16 voting decision cycles, the state machine updates the address output to the copy number counting memory, and at the same time, the state machine outputs a high-level selection signal with a bit width of 1 to the two-to-one selector, and the seventh register outputs and saves the count value of the copy number counting memory; after every 1 voting decision cycle, the state machine outputs a low-level selection signal to the two-to-one selector, and the value of the seventh register is shifted right by 4 bits through the second shift unit, and the result is rewritten into the seventh register; the second bit selection unit performs a bit selection operation on the lower 4 bits of the seventh register and outputs a copy number C with a bit width of 4. N , and the number of copies C N Write to the sixth register.

[0022] Furthermore, the effective sequence screening module includes an AND gate, a RAM address counter, and a RAM; the depth of the RAM is 2 19 , the bit width is 1, where the address corresponding to the invalid label stores "0", and the address corresponding to the valid label stores "1". The valid signal output by the majority voting judgment module is used as the input of the RAM address counter. The RAM address counter counts up to the RAM according to the input valid signal. If the RAM output is "1", the label is valid. The output of the RAM and the valid signal output by the majority voting judgment module are used as the input of the AND gate. The valid signal output by the AND gate is used as the output of the valid sequence screening module.

[0023] Furthermore, each of the deinterleaving modules includes a write address generator, a read address generator, a first RAM, a second RAM, a parallel-to-serial converter, a serial-to-parallel converter, a write selection state machine, a read selection state machine, and a two-to-one data selector;

[0024] The consensus sequence output by the majority voting judgment module and the valid signal output by the valid sequence screening module are input to the parallel-to-serial converter of the first deinterleaving module, and the serial-to-parallel converter of the first deinterleaving module outputs the codeword sequence containing errors and the valid signal; the erasure mark sequence output by the majority voting judgment module and the valid signal output by the valid sequence screening module are input to the parallel-to-serial converter of the second deinterleaving module, and the serial-to-parallel converter of the second deinterleaving module outputs the deinterleaved erasure mark sequence;

[0025] In each of the deinterleaving modules, the write address generator generates a single-bit address for writing a column into the first RAM and the second RAM, and the read address generator generates a column-by-column address for reading the first RAM and the second RAM; the write selection state machine is used to control the write enable signals of the first RAM and the second RAM, and switch the write path according to the full / empty state of the first RAM and the second RAM; the read selection state machine outputs a selection signal to the two-to-one data selector, and controls the two-to-one data selector to select the corresponding first RAM or second RAM output as the input of the serial-to-parallel converter according to the full / empty state of the first RAM and the second RAM; the first RAM and the second RAM are both simple dual-port RAMs, used to store an interleaved matrix of 180 rows and 360 columns, with a depth of 64,800 and a bit width of 1; the write data width of the first RAM and the second RAM is 1 bit, and the read data width is 8 bits; the output of the parallel-to-serial converter is single-bit serial data, and the serial-to-parallel converter converts the 8-bit data read from the first RAM or the second RAM into a parallel 360-bit output;

[0026] In each of the deinterleaving modules, when the first RAM is fully written with 64,800 bits, the first RAM write enable signal of the write selection state machine is set to 0, and the second RAM write enable signal is set to 1. The selection signal of the read selection state machine controls the two-to-one selector to select the first RAM. The read address generator reads the address of the first RAM column by column in sequence. The write selection state machine and the read state machine alternately control the write enable signals of the first RAM and the second RAM in this cycle.

[0027] 11. The DNA data storage hardware accelerated data readout system based on heterogeneous computing according to claim 2, wherein the LDPC decoding module includes a log-likelihood ratio calculation unit, a check node calculation unit, a variable node calculation unit, a variable node address control unit, a check node address control unit, a first RAM memory, a second RAM memory, a third RAM memory, and a decision unit;

[0028] The codeword sequence containing errors, the erasure mark sequence, and the valid signal output by the two deinterleaving modules are input to the log-likelihood ratio calculation unit to calculate and output the log-likelihood ratio;

[0029] The first RAM memory stores log-likelihood ratios, the second RAM memory stores extrinsic information passed from the check node to the variable node, and the third RAM memory stores extrinsic information passed from the variable node to the check node;

[0030] The variable node calculation unit calculates and outputs the extrinsic information transmitted from the variable node to the check node based on the log-likelihood ratio stored in the first RAM memory and the extrinsic information transmitted from the check node to the variable node stored in the second RAM memory, and outputs the posterior probability information of the variable node to the decision unit;

[0031] The check node calculation unit calculates and outputs the extrinsic information transmitted from the check node to the variable node based on the extrinsic information transmitted from the variable node to the check node stored in the third memory;

[0032] The check node address control unit controls the write address of the second RAM memory and the read address of the third RAM memory during the calculation process of the check node calculation unit; the variable node address control unit controls the read address of the first RAM memory and the second RAM memory, and simultaneously controls the read address of the third RAM memory when the variable node calculation unit performs calculation;

[0033] The decision unit is used to decide and verify the posterior probability information of the variable node, and output the decoding result if the verification passes, to obtain the final codeword sequence and valid signal, and store them in the third data buffer.

[0034] A DNA data storage hardware-accelerated data readout device based on heterogeneous computing includes a computing server and an FPGA accelerator card. The computing server stores and runs a software program that implements a base sequence mapping module, a splicing and recovery module, and a control module of the DNA data storage hardware-accelerated data readout system based on heterogeneous computing. The FPGA in the FPGA accelerator card is divided into a static area and a dynamic area. The static area includes the first and second off-chip memories in the DNA data storage hardware-accelerated data readout system based on heterogeneous computing, and the dynamic area includes the RAM read / write interface and the DNA data storage recovery kernel in the DNA data storage hardware-accelerated data readout system based on heterogeneous computing.

[0035] The DNA sequencing data file is processed by the base sequence mapping module to obtain a bit sequence; the control module calls the PCIe interface to transmit the bit sequence to the first off-chip memory, and generates an acceleration core startup control signal to transmit to the DNA data storage recovery core; the DNA data storage recovery core calls the bit sequence in the first off-chip memory, and recovers the codeword sequence after primer sequence recognition, label verification, majority voting judgment, valid sequence screening, deinterleaving, and LDPC decoding. The codeword sequence is stored in the first off-chip memory via the RAM read / write interface; the control module reads the recovered codeword sequence from the first off-chip memory, transmits it to the splicing and recovery module to recombine it, and reconstructs the original file corresponding to the DNA sequencing data file.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] The present invention significantly improves the efficiency of DNA sequence recognition and clustering by splitting the computational process of primer identification and label verification into multiple combinational logic calculation steps and adopting a pipeline beat processing method. A majority voting judgment module suitable for DNA storage is designed, the deinterleaving module is optimized using a ping-pong structure, and an efficient LDPC decoding module is introduced to further improve computing performance with a multi-module task-level pipeline architecture. In particular, to address the problem of discontinuous labels after encoding, a lookup table structure that saves more RAM resources is proposed, which optimizes storage and computing efficiency. This new FPGA-based heterogeneous computing architecture can efficiently accelerate the DNA data storage and readout process, and has significant performance advantages compared to pure software implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a principle block diagram of the DNA data storage hardware accelerated data readout system and device based on heterogeneous computing of the present invention;

[0039] Figure 2 The overall architecture block diagram of the DNA data storage and recovery core designed for the present invention;

[0040] Figure 3 A schematic diagram of the architecture of the primer sequence recognition module designed for the present invention;

[0041] Figure 4 A schematic diagram of the architecture of the label verification module designed for the present invention;

[0042] Figure 5 A schematic diagram of the architecture of the majority voting decision module designed for the present invention;

[0043] Figure 6 A schematic diagram of the architecture of the effective sequence screening module designed for the present invention;

[0044] Figure 7 A schematic diagram of the architecture of the de-interleaving module designed for the present invention;

[0045] Figure 8 Schematic diagram of the architecture of the LDPC decoding module designed for the present invention;

[0046] Figure 9 Flowchart of the coding scheme for the LDPC decoding module designed for the present invention;

[0047] Figure 10(a) shows the error rates of the majority voting decision scheme designed by the present invention under different total error rates;

[0048] Figure 10(b) shows the error rate of the majority voting decision scheme designed by the present invention at different coverage rates;

[0049] Figure 11 A comparison chart of the recovery success rates between hardware and software implementations at different total error rates in the present invention;

[0050] Figure 12 This is a comparison chart of the recovery success rates of hardware implementation and software implementation under different coverage rates in the present invention. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention are described in further detail below.

[0052] To address the computational challenges associated with reading short DNA data from storage, this paper proposes a DNA data storage hardware acceleration data readout system based on heterogeneous computing, combining CPUs and FPGAs. This system aims to accelerate key computational tasks during DNA readout. Based on a novel FPGA-based heterogeneous computing architecture, this paper accelerates key computational tasks during DNA storage readout, thereby speeding up data readout execution throughout the DNA data storage system.

[0053] like Figure 1 As shown, the DNA data storage hardware-accelerated data readout system and device based on heterogeneous computing of the present invention mainly includes a base sequence mapping module, a splicing and recovery module, and a control module within the CPU, as well as a first off-chip memory in the static area of the FPGA, a second off-chip memory, a RAM read / write interface with the dynamic area, and a DNA data storage recovery kernel. The control module uses the PCIe interface to perform data transmission with the first off-chip memory and calls the DNA data storage recovery kernel. The DNA data storage recovery kernel performs data transmission with the first off-chip memory and the second off-chip memory respectively through the RAM read / write interface.

[0054] The DNA sequencing data file (FASTQ format) is processed by the base sequence mapping module, and a bit sequence is obtained from the base sequence after demapping. The control module calls the PCIe interface to transfer the bit sequence to the first off-chip memory, and generates an acceleration kernel startup control signal to transmit it to the DNA data storage recovery kernel. After receiving the signal, the DNA data storage recovery kernel calls the bit sequence in the first off-chip memory, and recovers the code word sequence after primer sequence recognition, label verification, majority voting judgment, valid sequence screening, deinterleaving, and LDPC decoding processing. The code word sequence is stored in the specified position of the first off-chip memory via the RAM read / write interface. The control module reads the recovered code word sequence from the first off-chip memory, transmits it to the splicing and recovery module to recombine it, and reconstructs the original file corresponding to the DNA sequencing data file. Among them, the second off-chip memory is used to store data generated during the data processing of the DNA data storage recovery kernel.

[0055] The DNA data storage and recovery kernel executes multiple logical operation units within the module and uses the task-level pipeline structure between modules to process the sequencing data step by step. Figure 2 As shown, the DNA data storage and recovery core includes a first data buffer, a second data buffer, a third data buffer, a memory write interface, a copy number counting memory, two primer sequence recognition modules, two label verification modules, a majority voting judgment module, a valid sequence screening module, two deinterleaving modules and an LDPC decoding module.

[0056] The bit sequence in the first off-chip memory is cached in a first data buffer. The cached bit sequence is divided into two groups (e.g., two groups of 256-bit wide bit sequences), which are respectively input into two primer sequence recognition modules for identification and calculation of primer numbers. The primer numbers, valid signals, original labels, and data partial sequences are outputted respectively. The valid signals, original labels, and data partial sequences outputted by each primer sequence recognition module are inputted into the corresponding label verification module, which verifies the labels and outputs the verified valid signals, label information bits, and data partial sequences. The primer numbers outputted by the two primer sequence recognition modules and the valid signals, label information bits, and data partial sequences outputted by the two label verification modules are all stored in the second data buffer. The memory write interface calculates the write address based on the label information bits and primer numbers stored in the second data buffer and writes the data partial sequence into the second off-chip memory. The copy number counting memory addresses the label information bits and primer numbers outputted by the second data buffer and counts up the count value. The bit width of the replica count memory may be 64, and the depth may be 393,216, wherein the 64-bit width may be divided into 4-bit widths to store the count values of multiple replicas, and the upper limit may be 15.

[0057] The majority voting judgment module sequentially reads the data portion sequence in the second off-chip memory and performs a majority voting judgment based on the count value in the replica number counting memory. The majority voting judgment module outputs a consensus sequence, an erasure mark sequence, and a valid signal. The valid sequence screening module performs data screening on the consensus sequence and the erasure mark sequence based on the valid signal of the majority voting judgment module.

[0058] The consensus sequence and erasure mark sequence output by the majority voting judgment module are respectively used as inputs of the two deinterleaving modules, and the valid signal output by the valid sequence screening module is used as the common input of the two deinterleaving modules. The codeword sequence containing errors, the erasure mark sequence, and the valid signal output by the two deinterleaving modules are all input into the LDPC decoding module for error correction decoding. The LDPC decoding module outputs the final codeword sequence and valid signal and stores them in the third data buffer, and finally the output is stored in the first off-chip memory.

[0059] like Figure 3 As shown, each primer sequence recognition module includes a first splitting unit, a second splitting unit, n (n=24 in the figure) Hamming distance calculation units, a multi-level comparison network unit, a reverse complementary sequence calculation unit, a modulo 2 calculation unit, and a comparator F.

[0060] The first splitting unit splits the input bit sequence into a front primer sequence, a label and a data portion sequence. For example, the first splitting unit input may be a 256-bit bit sequence, and the output may be a bit sequence with a bit width of W. p =40 front primer sequence and 144 bit width label and data part sequence.

[0061] The input of each of the Hamming distance calculation units is the front-end primer sequence output by the first splitting unit, and the output is the Hamming distance value D1, D2, ..., D n , and the bit width d of the Hamming distance value can be 5. Each of the Hamming distance calculation units includes an XOR gate calculation array, an OR gate calculation array, and a parallel addition tree. The XOR gate calculation array can be composed of 40 XOR gates, and the OR gate calculation array can be composed of 20 OR gates. Each OR gate performs an OR operation on the output signals of two XOR gates. The parallel addition tree can be composed of 9 5-bit adders for summing the output results of the OR gate calculation array.

[0062] The input of the multi-level comparison network unit is the Hamming distance values D1, D2, ..., D between the forward primer sequence and the reference primer sequence output by all Hamming distance calculation units. n , each bit width can be 5. After multi-level comparison processing, the output of the multi-level comparison network unit is the minimum Hamming distance value and its corresponding primer number.

[0063] The multi-level comparison network unit includes multiple levels of binary selectors and comparators. The figure shows 5 levels. If the number of Hamming distance calculation units n=24, then the first level includes 12 comparators C1~C12 and 24 binary selectors a1~a24, the second level includes 6 comparators C13~C18 and 12 binary selectors b1~b12, the third level includes 3 comparators and 6 binary selectors, the fourth level includes 2 comparators and 4 binary selectors, and the fifth level includes 1 comparator C24 and 2 binary selectors e1 and e2. In each level of comparison, one comparator corresponds to two binary selectors. The input of each comparator in the first level is the Hamming distance value D1~D 24 The output of each comparator is the enable terminal of the corresponding two-to-one selector. The input of the two-to-one selector a1~a12 is the Hamming distance value D1~D n Two of them output the smaller Hamming distance value. The inputs to the two-choice selectors a13-a24 are two of the primer numbers 1-24, and the output is the primer number of the one with the smaller Hamming distance value. The second, third, and fourth stages are cascaded sequentially according to the circuit structure of the first stage. The fifth-stage comparator inputs are the minimum and second-smallest Hamming distance values output by the fourth stage, and the inputs to the two-choice selector e2 are the primer numbers corresponding to the minimum and second-smallest Hamming distance values output by the fourth stage. After performing multiple comparisons, the multi-stage comparison network unit ultimately selects the primer number with the minimum Hamming distance value among its n inputs and its corresponding primer number as its output.

[0064] The minimum Hamming distance value is compared with the set threshold D thr As the input of the comparator F, when the minimum Hamming distance value is less than the set threshold, the comparator F is set to output a high level as the valid signal output of the primer sequence recognition module. The input of the modulo 2 calculation unit is the primer number obtained by the primer sequence recognition module, and the output is the selection signal of the two-choice selector G in the reverse complementary sequence calculation unit, with a bit width of 1.

[0065] The reverse complementary sequence calculation unit includes a first register, a second register, and a two-to-one selector G. The bit width f of the first register and the second register can both be 144. The first register is used to store the label and data part sequence output by the first splitting unit, and calculate its reverse complementary sequence through combinational logic and save it in the second register. The two-to-one selector G selects to output the label and data part sequence saved in the first register or the reverse complementary sequence saved in the second register based on the selection signal output by the modulo 2 calculation unit; for example, if the input selection signal is 0, the label and data part sequence saved in the first register is output, and if the input selection signal is 1, the reverse complementary sequence saved in the second register is output. The data output by the two-to-one selector is split into two parts, the original label and data part sequence, by the second splitting unit.

[0066] like Figure 4 As shown, each of the label check modules includes a syndrome calculation unit, an AND gate, a first bit selector unit, a third register, and a fourth register. The syndrome calculation unit includes five multi-input exclusive OR gates XOR1 to XOR5 and a five-input OR gate. The inputs of the OR gate are the outputs of the five exclusive OR gates, and the output of the OR gate serves as the output of the syndrome calculation unit.

[0067] The original label (bit width can be 24) output by the primer sequence recognition module is Hamming-code checked by the syndrome calculation unit, resulting in a verification success signal (bit width can be 1). The valid signal (bit width can be 1) output by the primer sequence recognition module is stored in a third register. The valid signal stored in the third register and the verification success signal output by the syndrome calculation unit are combined through an AND gate to output a valid signal (bit width can be 1). The data portion sequence (bit width can be 120) output by the primer sequence recognition module is stored and output by a fourth register. The original label output by the primer sequence recognition module is directly bit-selected by the first selection unit, resulting in the label information bit output by the label verification module.

[0068] like Figure 5 As shown, the majority voting decision module includes a bit splicing / splitting unit, a state machine, a two-to-one selector, a second shift unit, a sixth register, a seventh register, a second bit selection unit, and m (m=120 in the figure) majority voting decision calculation units. Each of the majority voting decision calculation units includes a fifth register G0, a parallel addition tree, an OR gate OR, a first comparator, a second comparator, a third comparator, and a first shift unit.

[0069] The majority voting decision unit module processes 4 data part sequences per clock cycle and completes the majority voting calculation of k data part sequences within four consecutive clock cycles, k∈[0,15]. The bit splicing / splitting unit reads the data part sequence in the second off-chip memory (the bit width can be 512) and splits it into four data part sequences with a bit width of m. Each data part sequence with a bit width of m is further split into m 1-bit signals and input into m majority voting calculation units respectively. S 1 [i] represents the i-th bit of the first data segment sequence, i∈[0,119].

[0070] Each of the majority voting decision calculation units uses a parallel adder tree to calculate and sum four 1-bit-wide inputs, and the results are accumulated in its own fifth register. The parallel adder tree is composed of four adders A1 to A4. Two adders A1 and A2 sum the four input signals with a bit width of 1 in pairs, and the third adder A3 sums the outputs of adders A1 and A2. In each clock cycle, the output of the parallel adder tree and the value of the fifth register are added and summed through adder A4 and stored in the fifth register. In the fourth clock cycle of a voting cycle, the value in the fifth register is shifted left by 1 bit through the first shift unit to obtain the shift data V N , V N and the number of copies C stored in the sixth register N After comparison by the first comparator, if V N >C N If it is greater than, the comparator output is set to 1, otherwise it is set to 0. The output of the first comparator is Q[i], which represents the i-th bit of the consensus sequence, i∈[0,m-1].

[0071] Each of the majority voting decision calculation units calculates the erase flag in the fourth clock cycle of a voting decision cycle. N is 0, the number of copies C in the sixth register N and "0" as the input of the third comparator. If the comparison result is equal, the third comparator outputs a high level, indicating that there is no copy of the current data part sequence, otherwise it outputs a low level. N With the copy number C in the sixth register N As the input of the second comparator, if the comparison result is equal, the second comparator outputs a high level, otherwise it outputs a low level. The outputs of the second comparator and the third comparator serve as the input of the OR gate, and the output result of the OR gate is E[i], which represents the i-th bit mark of the erasure mark sequence, i∈[0,m-1].

[0072] The bit splicing / splitting unit merges the m-way signal Q[i] and the m-way signal E[i] with a bit width of 1 into an m-bit-wide consensus sequence and an m-bit-wide erasure mark sequence, respectively, as the output of the majority voting decision module.

[0073] After every 4 clock cycles, the state machine outputs a valid signal set to a high level as a valid signal output by the entire majority voting decision module. After every 16 voting decision cycles, the state machine updates the address (bit width can be 19) output to the replica number counting memory, and at the same time, the state machine outputs a high-level selection signal with a bit width of 1 to the two-to-one selector G0, and the seventh register outputs and saves the count value of the replica number counting memory; after every 1 voting decision cycle, the state machine outputs a low-level selection signal to the two-to-one selector G0, and the value of the seventh register is shifted right by 4 bits through the second shift unit, and the result is rewritten into the seventh register. The second bit selection unit performs a bit selection operation on the lower 4 bits of the seventh register and outputs a replica number C with a bit width of 4. N , and the number of copies C N Write to the sixth register.

[0074] like Figure 6 As shown, the effective sequence screening module includes an AND gate, a RAM address counter, and a RAM. The depth of the RAM is 2 19 , with a bit width of 1, where the address corresponding to an invalid label stores "0" and the address corresponding to a valid label stores "1". The valid signal output by the majority voting judgment module serves as the input of the RAM address counter. The RAM address counter counts up to the RAM based on the input valid signal. If the RAM output is "1", the label is valid. The RAM output and the valid signal output by the majority voting judgment module serve as the input of the AND gate. The valid signal output by the AND gate serves as the output of the valid sequence screening module.

[0075] like Figure 7 As shown, each of the deinterleaving modules includes a write address generator, a read address generator, a first RAM, a second RAM, a parallel-to-serial converter, a serial-to-parallel converter, a write selection state machine, a read selection state machine, and a two-to-one data selector g1.

[0076] The consensus sequence output by the majority voting decision module and the valid signal output by the valid sequence screening module are input to the parallel-to-serial converter of the first deinterleaving module. The serial-to-parallel converter of the first deinterleaving module outputs the codeword sequence containing errors and the valid signal. The erasure marker sequence output by the majority voting decision module and the valid signal output by the valid sequence screening module are input to the parallel-to-serial converter of the second deinterleaving module. The serial-to-parallel converter of the second deinterleaving module outputs the deinterleaved erasure marker sequence. The outputs of the parallel-to-serial converters in both deinterleaving modules are single-bit serial data.

[0077] In each deinterleaving module, the first RAM and the second RAM are both simple dual-port RAMs, used to store an interleaved matrix with 180 rows and 360 columns, with a depth of 64,800 and a bit width of 1. The first and second RAMs have a write data width of 1 bit and a read data width of 8 bits. The write address generator generates single-bit addresses for writing columns to the first and second RAMs, and the read address generator generates column-by-column addresses for reading from the first and second RAMs. The write select state machine controls the write enable signals of the first and second RAMs, switching the write path based on the full / empty status of the first and second RAMs. The read select state machine outputs a select signal to the two-to-one data selector g1, which controls the two-to-one data selector g1 to select the corresponding first or second RAM output as the input of the serial-to-parallel converter based on the full / empty status of the first and second RAMs. The serial-to-parallel converter converts the 8-bit data read from the first or second RAM into a parallel 360-bit output.

[0078] In each of the deinterleaving modules, the write selection state machine and the read state machine both use a "ping-pong" operation data flow control method. When the first RAM is fully written with 64,800 bits, the first RAM write enable signal of the write selection state machine is set to 0, and the second RAM write enable signal is set to 1. The selection signal of the read selection state machine controls the two-to-one selector g1 to select the first RAM. The read address generator reads the address of the first RAM in sequence by column. The write selection state machine and the read state machine use this as a cycle to alternately control the write enable signals of the first RAM and the second RAM.

[0079] like Figure 8 As shown, the LDPC decoding module includes a log-likelihood ratio calculation unit, a check node calculation unit, a variable node calculation unit, a variable node address control unit, a check node address control unit, a first RAM memory, a second RAM memory, a third RAM memory, and a decision unit.

[0080] The LDPC decoding module is based on a partially parallel hierarchical implementation of the normalized minimum sum algorithm. The error-containing codeword sequence (bit width can be 360), the erasure marker sequence (bit width can be 360), and the valid signal output by the two deinterleaving modules are input into the log-likelihood ratio calculation unit, which calculates and outputs the log-likelihood ratio (bit width can be 1800). The log-likelihood ratio is quantized using a 5-bit fixed-point decimal, with the sign bit and integer bit occupying 1 bit and the fractional bit occupying 3 bits.

[0081] The first RAM memory stores log-likelihood ratios, the second RAM memory stores extrinsic information transmitted from the check node to the variable node, and the third RAM memory stores extrinsic information transmitted from the variable node to the check node.

[0082] The variable node calculation unit calculates and outputs the extrinsic information passed from the variable node to the check node based on the log-likelihood ratio stored in the first RAM memory and the extrinsic information passed from the check node to the variable node stored in the second RAM memory. The extrinsic information passed from the variable node to the check node is saved in the third RAM memory, and the posterior probability information of the variable node is output to the decision unit at the same time.

[0083] The check node calculation unit calculates and outputs the extrinsic information transmitted from the check node to the variable node based on the extrinsic information transmitted from the variable node to the check node stored in the third memory, and the extrinsic information transmitted from the check node to the variable node is saved in the second RAM memory.

[0084] The check node address control unit controls the write address of the second RAM memory and the read address of the third RAM memory when the check node calculation unit performs calculations; the variable node address control unit controls the read addresses of the first RAM memory and the second RAM memory, and simultaneously controls the read address of the third RAM memory when the variable node calculation unit performs calculations.

[0085] The decision unit is used to decide and verify the posterior probability information of the variable node, and output the decoding result if the verification passes, to obtain the final codeword sequence and valid signal, and store them in the third data buffer.

[0086] Based on the technical principles of the above-mentioned DNA data storage hardware-accelerated data readout system, the present invention proposes a DNA data storage hardware-accelerated data readout device based on heterogeneous computing, including a computing server and an FPGA acceleration card. Through the coordinated operation of these two parts, the complete DNA data storage readout process from sequencing data input to original file recovery can be efficiently realized.

[0087] The software programs stored and executed by the CPU within the computing server implement the base sequence mapping module, splicing and recovery module, and control module in the aforementioned DNA data storage hardware-accelerated data readout system based on heterogeneous computing. The CPU is responsible for processing sequencing data, managing data transfer between off-chip RAM, and controlling kernel execution.

[0088] The FPGA within the FPGA accelerator card is divided into a static area and a dynamic area. The static area includes the first and second off-chip memories in the heterogeneous computing-based DNA data storage hardware accelerated data readout system. The dynamic area includes the RAM read / write interface and DNA data storage recovery kernel in the heterogeneous computing-based DNA data storage hardware accelerated data readout system. This area can be implemented on the Alveo U200 FPGA accelerator card and is designed to accelerate key computational steps in the DNA data readout process. Specific embodiments

[0090] This embodiment can illustrate the feasibility of the DNA data storage hardware accelerated data readout system and device based on heterogeneous computing provided by the present invention.

[0091] This embodiment verifies the acceleration effect of heterogeneous computing based on a large-scale oligonucleotide pool storage mode. First, an LDPC-based encoding scheme is designed for the oligonucleotide pool. In order to correct the high insertion / deletion and substitution errors in DNA storage, the binary data to be stored is divided into data blocks of fixed length, and each data block is error-corrected using LDPC encoding. Subsequently, the encoded codewords are interleaved in rows and columns to enhance the error correction capability for long burst errors caused by sequence loss during storage. Then, the interleaved codewords are mapped to DNA sequences according to the base mapping rules {(00)→A, (01)→T, (10)→G, (11)→C}. In addition, in order to facilitate the identification of sequencing reads during the recovery process, unique label sequences are added to both ends of each DNA sequence. Finally, primers are added to both ends of the sequence.

[0092] Specifically, LDPC (64800, 54000) coding was used, and the coded data was interleaved using a 360×180 interleaving matrix. After interleaving, each LDPC codeword was divided into 120 bits and mapped to 60 nucleotides, resulting in 540 sets of payload sequences. Using this coding method, a total of 9,240 LDPC codewords were encoded, generating 4,989,600 DNA sequences with a total storage capacity of 59.4MB. Figure 9 As shown in Figure 2, a method was designed to distinguish different DNA sequences using primer sequences and label sequences. These large-scale DNA sequences were divided into 12 groups, corresponding to 12 different primer pairs, each corresponding to 415,800 oligonucleotide molecules. A set of 12-nucleotide label sequences was designed for each oligonucleotide pool. A shortened Hamming code (Hamming (24,19)) was used to encode a 19-bit binary number into 24 bits and then map it to a 12-nucleotide base sequence. The first 415,800 label sequences with homologous multimer lengths less than or equal to 3 were used in the generated label set, and a unique label was assigned to each DNA molecule.

[0093] Table 1 summarizes the resource utilization of each functional module for DNA storage readout in the DNA data storage and recovery core designed by the present invention. The initial log-likelihood ratio of the LDPC decoding module is quantized using a 5-bit fixed-point decimal, and each check node uses a 7-bit quantization storage with a parallel degree of 360. The resource consumption of this module accounts for 85% of the total kernel consumption and is mainly used to implement a partially layered LDPC parallel iterative decoding algorithm. The replica count memory consumes 31.6% of the on-chip block RAM resources and is mainly used to store 12 primer pools, each corresponding to 0 to 2 19 -1 The number of sequencing copies within the address range. In addition to the main modules that implement the DNA storage and decoding process, the data flow interface and memory read and write interface between modules also consume some resources.

[0094] Table 1 Resource usage of each module in the DNA data storage recovery kernel

[0095]

[0096] In order to further evaluate the proposed heterogeneous acceleration system (i.e. Figure 1 The performance of the system shown in the figure is tested in this embodiment under different error rates and sequencing coverage. First, the hardware acceleration platform is built using data center FPGA acceleration boards, especially Alveo U200 series acceleration cards. The computing server is developed using the Vitis unified software platform. The computing server is equipped with Intel Gold 5220R CPU (2.2GHz) with 96 cores and 256GB of memory.

[0097] Then, a channel simulation model was established to simulate sequencing data with different error rates. The model incorporated insertion, deletion, and substitution error rates to reflect common sequencing noise, using P i 、P d and P s In order to more accurately reflect the heterogeneity of sequencing coverage in real DNA data storage scenarios, the number of DNA copies generated during sequencing is simulated by the Poisson distribution function. sum =P i +P d +P s .

[0098] This embodiment evaluates the recovery performance under real-world conditions, as shown in Figures 10(a) and 10(b). Based on the proposed DNA storage channel simulation model, multiple data sets were generated using random input data at different coverages and total base error rates. Four total base error rates (1.2%, 1.5%, 1.8%, and 2.1%) were simulated under a fixed sequencing coverage of 15x. When the total base error rate was below 1.8%, the codeword error rate after majority voting remained within the correctable range of the LDPC decoder. When the total base error rate was 2.1%, the codeword error rate reached 1.9%, exceeding the error correction capability and resulting in decoding failure. At an error rate of 1%, data recovery experiments were conducted at four different coverages: 7x, 8x, 9x, and 10x. When the coverage reached 9x, the codeword error rate after majority voting remained within the correctable range of the LDPC decoder.

[0099] Figure 11 The performance of the heterogeneous acceleration system established was evaluated based on pure software implementation. Figure 1 A software testing program for the functional consistency of the heterogeneous acceleration system in the

[15] was used. 100 independent experiments were conducted on both the software and hardware implementations at different total base error rates, with an average sequencing coverage of 25x. The experimental results demonstrated that the system can tolerate a total base error rate of up to 2% at 25x coverage. Furthermore, the hardware-accelerated heterogeneous solution demonstrated recovery performance comparable to its software counterpart, validating the system's effectiveness and reliability under typical sequencing error conditions.

[0100] Figure 12 The error-free recovery rate at different sequencing coverages is presented, assuming a fixed total base error rate of 1%. The results demonstrate that the proposed heterogeneous platform can achieve a minimum coverage of 10x for error-free data recovery at a 1% total base error rate. Performance comparisons with software implementations demonstrate that the heterogeneous acceleration platform provides comparable read reliability.

[0101] To validate the acceleration performance of the heterogeneous computing acceleration kernel (i.e., the DNA data storage recovery kernel), the execution time of the heterogeneous computing acceleration kernel and CPU software implementation was tested using sequencing datasets with varying total base error rates and average coverage. Kernel execution time was measured on the host by recording clock times before and after kernel execution. The test dataset consisted of sequencing reads generated from 12 oligonucleotide pools, each containing 415,800 DNA sequences, resulting in a total of 4,989,600 reference sequences. Simulated sequencing data for testing was generated at three base error rates (0.006, 0.01, and 0.015) and three coverages (15×, 20×, and 25×). These combinations of base error rates and coverages have been previously validated to support successful recovery and are used here to compare execution speeds.

[0102] As shown in Table 2, the acceleration system always achieves at least two orders of magnitude speedup over the CPU software implementation, and even achieves higher gains at high error rates. sum =0.015, 15×coverage), the acceleration peak can reach 373.1 times.

[0103] Table 2 Comparison of time consumption between CPU software implementation and hardware FPGA implementation at different error rates and average coverage

[0104]

[0105] Although the functions and working processes of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific functions and working processes. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which are all protected by the present invention.

Claims

1. A DNA data storage hardware accelerated data readout system based on heterogeneous computing, characterized in that: It includes a base sequence mapping module, a splicing and recovery module, a control module in the CPU, a first off-chip memory in the static area of the FPGA, a second off-chip memory and a RAM read / write interface in the dynamic area, and a DNA data storage and recovery core; The control module performs data transmission with the first memory chip by calling the PCIe interface and controls the DNA data storage recovery core, and the DNA data storage recovery core performs data transmission with the first external memory chip and the second external memory chip respectively through the RAM read / write interface; The DNA sequencing data file is processed by the base sequence mapping module to obtain a bit sequence; the control module transmits the bit sequence to the first off-chip memory through the PCIe interface, and generates an acceleration kernel startup control signal to transmit to the DNA data storage and recovery kernel; After receiving the signal, the DNA data storage and recovery core reads the bit sequence in the first off-chip memory, and recovers the codeword sequence after primer sequence recognition, label verification, majority voting judgment, valid sequence screening, deinterleaving, and LDPC decoding, and stores it in the first off-chip memory; the control module reads the recovered codeword sequence from the first off-chip memory through the PCIe interface, inputs it into the splicing and recovery module to recombine it, and reconstructs the original file corresponding to the DNA sequencing data file; wherein, the second off-chip memory is used to store data generated during the data processing of the DNA data storage and recovery core.

2. The DNA data storage hardware accelerated data readout system based on heterogeneous computing according to claim 1, characterized in that: The DNA data storage and recovery core includes a first data buffer, a second data buffer, a third data buffer, a memory write interface, a copy number counting memory, two primer sequence recognition modules, two label check modules, a majority voting decision module, a valid sequence screening module, two deinterleaving modules and an LDPC decoding module; The bit sequence in the first off-chip memory is cached in a first data buffer, and the cached bit sequence is divided into two groups and respectively input into two primer sequence recognition modules for recognition and calculation of primer numbers, and the primer numbers, valid signals, original labels, and data partial sequences are output. The valid signals, original labels, and data partial sequences output by each primer sequence recognition module are all used as inputs of the corresponding label verification module, and the labels are verified and the verified valid signals, label information bits, and data partial sequences are output. The primer numbers output by the two primer sequence recognition modules and the valid signals, label information bits, and data partial sequences output by the two label verification modules are all stored in the second data buffer; the memory write interface calculates a write address based on the label information bits and primer numbers stored in the second data buffer and writes the data partial sequence into the second off-chip memory; the copy number counting memory is addressed based on the label information bits and primer numbers output by the second data buffer and counts up the count value; The majority voting judgment module sequentially reads the data portion sequence in the second off-chip memory and performs majority voting judgment based on the count value in the replica number counting memory to obtain a consensus sequence, an erasure mark sequence, and a valid signal. The valid sequence screening module performs data screening on the consensus sequence and the erasure mark sequence based on the valid signal of the majority voting judgment module; The consensus sequence and erasure mark sequence output by the majority voting judgment module are respectively used as inputs of the two deinterleaving modules, and the valid signal output by the valid sequence screening module is used as the common input of the two deinterleaving modules. The codeword sequence containing errors, the erasure mark sequence, and the valid signal output by the two deinterleaving modules are all input into the LDPC decoding module for error correction decoding. The final codeword sequence and valid signal are output and stored in the third data buffer, and finally the output is stored in the first off-chip memory.

3. The DNA data storage hardware accelerated data readout system based on heterogeneous computing according to claim 2, characterized in that: Each of the primer sequence recognition modules includes a first splitting unit, a second splitting unit, n Hamming distance calculation units, a multi-level comparison network unit, a reverse complementary sequence calculation unit, a modulo 2 calculation unit, and a comparator; The first splitting unit splits the input bit sequence into a front-end primer sequence, a label and a data portion sequence; the input of each of the Hamming distance calculation units is the front-end primer sequence output by the first splitting unit, and the output is a Hamming distance value; the Hamming distance values output by all the Hamming distance calculation units are input into the multi-stage comparison network unit, and after multi-stage comparison processing, the output is the minimum Hamming distance value and its corresponding primer number; the minimum Hamming distance value and the set threshold are used as the input of the comparator, and when the minimum Hamming distance value is less than the set threshold, the comparator is set to output a high level as the effective signal output of the primer sequence recognition module; the modulo 2 calculation unit The input is a primer number obtained by the primer sequence recognition module, and the output is a selection signal of a two-choice selector; the reverse complementary sequence calculation unit includes a first register, a second register, and a two-choice selector, the first register is used to store the label and data part sequence output by the first splitting unit, and its reverse complementary sequence is calculated by combinational logic and stored in the second register, the two-choice selector selects to output the label and data part sequence stored in the first register or the reverse complementary sequence stored in the second register according to the selection signal output by the modulo 2 calculation unit; the data output by the two-choice selector is split into the original label and data part sequence by the second splitting unit.

4. The DNA data storage hardware accelerated data readout system based on heterogeneous computing according to claim 2, characterized in that: Each of the label check modules includes a syndrome calculation unit, an AND gate, a first selector unit, a third register, and a fourth register; the syndrome calculation unit includes five multi-input XOR gates and one five-input OR gate, the input of the OR gate is the output of the five XOR gates, and the output of the OR gate serves as the output of the syndrome calculation unit; The original label output by the primer sequence recognition module is subjected to Hamming code verification by the syndrome calculation unit to obtain a verification success signal; The valid signal output by the primer sequence recognition module is stored in the third register, and the valid signal stored in the third register and the verification success signal output by the syndrome calculation unit are subjected to an AND gate operation to output a valid signal; The data partial sequence output by the primer sequence recognition module is stored and output via the fourth register; The original label output by the primer sequence recognition module is directly bit-selected by the first bit selection unit to obtain the label information bit output by the label verification module.

5. The DNA data storage hardware accelerated data readout system based on heterogeneous computing according to claim 1, characterized in that: The majority voting decision module includes a bit splicing / splitting unit, a state machine, a two-to-one selector, a second shift unit, a sixth register, a seventh register, a second bit selection unit, and m majority voting decision calculation units; each of the majority voting decision calculation units includes a fifth register, a parallel addition tree, an OR gate, a first comparator, a second comparator, a third comparator, and a first shift unit; The bit splicing / splitting unit reads the data partial sequence in the second off-chip memory and splits it into four data partial sequences with a bit width of m, and each data partial sequence with a bit width of m is further split into m 1-bit signals and input into m majority voting calculation units respectively; Each of the majority voting decision calculation units uses a parallel addition tree to calculate and sum the four 1-bit wide inputs, and accumulates the results in its own fifth register; in each clock cycle, the output of the parallel addition tree is added to the value of the fifth register and stored in the fifth register; in the fourth clock cycle of a voting cycle, the value in the fifth register is shifted left by 1 bit by the first shift unit to obtain the shift data V N , V N and the number of copies C stored in the sixth register N After comparison by the first comparator, the output of the first comparator is Q[i], which represents the i-th bit of the consensus sequence, i∈[0,m-1]; Each of the majority voting decision calculation units calculates the erasure mark in the fourth clock cycle of a voting decision cycle; the number of copies C in the sixth register N and "0" as the input of the third comparator. If the comparison result is equal, the third comparator outputs a high level, indicating that there is no copy of the current data sequence, otherwise it outputs a low level; the shift data V N With the copy number C in the sixth register N as the input of the second comparator, if the comparison result is equal, the output of the second comparator is a high level, otherwise the output is a low level; the outputs of the second comparator and the third comparator are used as the input of the OR gate, and the output result of the OR gate is E[i], which represents the i-th bit mark of the erasure mark sequence, i∈[0,m-1]; The bit splicing / splitting unit combines the m-way signal Q[i] and the m-way signal E[i] with a bit width of 1 into an m-bit-wide consensus sequence and an m-bit-wide erasure mark sequence, respectively, as the output of the majority voting decision module; After every 4 clock cycles, the state machine outputs a valid signal set to a high level as a valid signal output by the entire majority voting decision module; after every 16 voting decision cycles, the state machine updates the address output to the copy number counting memory, and at the same time, the state machine outputs a high-level selection signal with a bit width of 1 to the two-to-one selector, and the seventh register outputs and saves the count value of the copy number counting memory; after every 1 voting decision cycle, the state machine outputs a low-level selection signal to the two-to-one selector, and the value of the seventh register is shifted right by 4 bits through the second shift unit, and the result is rewritten into the seventh register; the second bit selection unit performs a bit selection operation on the lower 4 bits of the seventh register and outputs a copy number C with a bit width of 4. N , and the number of copies C N Write to the sixth register.

6. The DNA data storage hardware accelerated data readout system based on heterogeneous computing according to claim 2, characterized in that: The effective sequence screening module includes an AND gate, a RAM address counter, and a RAM; the depth of the RAM is 2 19 , the bit width is 1, where the address corresponding to the invalid label stores "0", and the address corresponding to the valid label stores "1". The valid signal output by the majority voting judgment module is used as the input of the RAM address counter. The RAM address counter counts up to the RAM according to the input valid signal. If the RAM output is "1", the label is valid. The output of the RAM and the valid signal output by the majority voting judgment module are used as the input of the AND gate. The valid signal output by the AND gate is used as the output of the valid sequence screening module.

7. The DNA data storage hardware accelerated data readout system based on heterogeneous computing according to claim 2, characterized in that: Each of the deinterleaving modules includes a write address generator, a read address generator, a first RAM, a second RAM, a parallel-to-serial converter, a serial-to-parallel converter, a write selection state machine, a read selection state machine, and a two-to-one data selector; The consensus sequence output by the majority voting judgment module and the valid signal output by the valid sequence screening module are input to the parallel-to-serial converter of the first deinterleaving module, and the serial-to-parallel converter of the first deinterleaving module outputs the codeword sequence containing errors and the valid signal; the erasure mark sequence output by the majority voting judgment module and the valid signal output by the valid sequence screening module are input to the parallel-to-serial converter of the second deinterleaving module, and the serial-to-parallel converter of the second deinterleaving module outputs the deinterleaved erasure mark sequence; In each of the deinterleaving modules, the write address generator generates an address for writing a single bit into the first RAM and the second RAM in columns, and the read address generator generates an address for reading the first RAM and the second RAM in columns; The write selection state machine is used to control the write enable signals of the first RAM and the second RAM, and switch the write path according to the full / empty state of the first RAM and the second RAM; the read selection state machine outputs a selection signal to the two-or-one data selector, and controls the two-or-one data selector to select the corresponding first RAM or second RAM output as the input of the serial-to-parallel converter according to the full / empty state of the first RAM and the second RAM; The first RAM and the second RAM are both simple dual-port RAMs, used to store an interleaved matrix of 180 rows and 360 columns, with a depth of 64,800 and a bit width of 1. The first RAM and the second RAM both have a write data width of 1 bit and a read data width of 8 bits. The parallel-to-serial converter outputs single-bit serial data, and the serial-to-parallel converter converts 8-bit data read from the first RAM or the second RAM into a parallel 360-bit output. In each of the deinterleaving modules, when the first RAM is fully written with 64,800 bits, the first RAM write enable signal of the write selection state machine is set to 0, and the second RAM write enable signal is set to 1. The selection signal of the read selection state machine controls the two-to-one selector to select the first RAM. The read address generator reads the address of the first RAM column by column in sequence. The write selection state machine and the read state machine alternately control the write enable signals of the first RAM and the second RAM in this cycle.

8. The DNA data storage hardware accelerated data readout system based on heterogeneous computing according to claim 2, characterized in that: The LDPC decoding module includes a log-likelihood ratio calculation unit, a check node calculation unit, a variable node calculation unit, a variable node address control unit, a check node address control unit, a first RAM memory, a second RAM memory, a third RAM memory, and a decision unit; The codeword sequence containing errors, the erasure mark sequence, and the valid signal output by the two deinterleaving modules are input to the log-likelihood ratio calculation unit to calculate and output the log-likelihood ratio; The first RAM memory stores log-likelihood ratios, the second RAM memory stores extrinsic information passed from the check node to the variable node, and the third RAM memory stores extrinsic information passed from the variable node to the check node; The variable node calculation unit calculates and outputs the extrinsic information transmitted from the variable node to the check node based on the log-likelihood ratio stored in the first RAM memory and the extrinsic information transmitted from the check node to the variable node stored in the second RAM memory, and outputs the posterior probability information of the variable node to the decision unit; The check node calculation unit calculates and outputs the extrinsic information transmitted from the check node to the variable node based on the extrinsic information transmitted from the variable node to the check node stored in the third memory; The check node address control unit controls the write address of the second RAM memory and the read address of the third RAM memory during the calculation process performed by the check node calculation unit; The variable node address control unit controls the read addresses of the first RAM memory and the second RAM memory, and simultaneously controls the read address of the third RAM memory when the variable node calculation unit performs calculation; The decision unit is used to decide and verify the posterior probability information of the variable node, and output the decoding result if the verification passes, to obtain the final codeword sequence and valid signal, and store them in the third data buffer.

9. A DNA data storage hardware accelerated data readout device based on heterogeneous computing, characterized in that: It comprises a computing server and an FPGA acceleration card; the software program stored and run by the CPU in the computing server implements the base sequence mapping module, the splicing and recovery module, and the control module of the DNA data storage hardware accelerated data readout system based on heterogeneous computing as described in any one of claims 1 to 8; the FPGA in the FPGA acceleration card is divided into a static area and a dynamic area, the static area includes the first off-chip memory and the second off-chip memory in the DNA data storage hardware accelerated data readout system based on heterogeneous computing as described in any one of claims 1 to 8, and the dynamic area includes the RAM read / write interface and the DNA data storage recovery kernel in the DNA data storage hardware accelerated data readout system based on heterogeneous computing as described in any one of claims 1 to 8; The DNA sequencing data file is processed by the base sequence mapping module to obtain a bit sequence; the control module calls the PCIe interface to transmit the bit sequence to the first off-chip memory, and generates an acceleration core startup control signal to transmit to the DNA data storage recovery core; the DNA data storage recovery core calls the bit sequence in the first off-chip memory, and recovers the codeword sequence after primer sequence recognition, label verification, majority voting judgment, valid sequence screening, deinterleaving, and LDPC decoding. The codeword sequence is stored in the first off-chip memory via the RAM read / write interface; the control module reads the recovered codeword sequence from the first off-chip memory, transmits it to the splicing and recovery module to recombine it, and reconstructs the original file corresponding to the DNA sequencing data file.

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