Multi-core cache consistency method and device, electronic equipment and storage medium

Abstract

The invention provides a multi-core cache consistency maintenance method and device, electronic equipment and a storage medium, and is applied to a multi-core system comprising a plurality of nodes, the nodes comprise at least two cores, each core comprises a first-level cache, and the plurality of cores of the same node share a second-level cache comprising a directory for recording cache line states; the method comprises the steps that a request core sends a first request to a first target core; the request core and the first target core are the same or different cores in the same node; when the first-level cache of the first target core is hit and the cache line state meets the target request requirement, the request core is responded, and the original state of the cache line is maintained; when the first-level cache of the first target core is not hit or the first-level cache is hit but the cache line state does not meet the request requirement, the request core sends a second request to other cores of the same node or a second-level cache of the node; and according to a request result, responding to a request core, and adjusting cache line states in a first-level cache and a second-level cache in the node.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a multi-core cache consistency method, device, electronic device, and storage medium. Background Art

[0002] With the rapid development of big data, artificial intelligence, and high-performance computing technologies, the demand for computer computing power is increasing. Multi-core processors, by integrating multiple processing cores, significantly enhance parallel computing capabilities and have become a core technology for modern computer systems. However, the widespread use of multi-core processors also brings with it the core challenge of cache coherence management. In a multi-core system, each core is equipped with a private cache to reduce main memory access latency. However, when multiple cores access shared data, it is necessary to ensure that the data versions in all caches are consistent. Failure to do so can lead to program execution errors or system crashes. Therefore, cache coherence protocols are key technologies for ensuring the correctness and performance of multi-core systems.

[0003] Currently, mainstream cache coherence solutions include the snoop bus protocol and the directory-based protocol. The snoop bus protocol enables inter-core communication through a shared bus and maintains coherence using write-through or write-invalidate mechanisms. The directory-based protocol uses a centralized directory to track the status of each memory block in the cache, requiring core read and write requests to be queried and coordinated through the directory. However, as the number of cores in multi-core processors continues to increase, both approaches face increasing communication or hardware resource costs, resulting in excessively high cache coherence maintenance costs and hindering overall system efficiency. Summary of the Invention

[0004] The present disclosure provides a multi-core cache consistency method, device, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a multi-core cache consistency method is provided. The method is applied to a multi-core system, wherein the multi-core system includes multiple nodes, each node includes at least two cores, the core includes a first-level cache, and multiple cores of the same node share a second-level cache; the first-level cache and the second-level cache each include cache lines, and the second-level cache includes a directory that records corresponding cache line states; the method includes:

[0006] A first request sent by a requesting core to a first target core; the requesting core and the first target core are the same or different cores in the same node;

[0007] When the first-level cache of the first target core hits and the state of its cache line meets the target request requirement, respond to the requesting core and maintain the original state of the cache line;

[0008] When the first target core's L1 cache misses or the L1 cache hits but the cache line state does not meet the request requirement, the requesting core simultaneously sends a second request to other cores of the same node or the L2 cache of the node;

[0009] According to the request result, the requesting core is responded to and the status of the cache lines in the corresponding first-level cache and second-level cache in the node is adjusted.

[0010] In one embodiment, when the first-level cache of the first target core hits and the state of its cache line meets the target request requirement, responding to the requesting core includes:

[0011] The first target core's L1 cache includes the target information indicated by the first request, and when the cache line state of the L1 cache is consistent with the target request requirement, the target information is obtained from the cache line and fed back to the requesting core.

[0012] In one embodiment, responding to the requesting core and adjusting the states of cache lines in the corresponding first-level cache and second-level cache in the node according to the request result includes:

[0013] When there is a first-level cache hit of the second target core in the other cores and its cache line status meets the target request requirements, respond to the requesting core and adjust the status of the cache lines in the first-level cache and the second-level cache in the first target core and / or the second target core.

[0014] In one embodiment, responding to the requesting core and adjusting the states of cache lines in the corresponding first-level cache and second-level cache in the node according to the request result includes:

[0015] When the L1 caches of all other cores in the node miss or the L1 cache hits but the cache line status thereof does not meet the target request requirement, the node waits for a reply response from the L2 cache.

[0016] In one embodiment, the secondary cache reply response includes:

[0017] When the L2 cache hits and its cache line status meets the target request requirement, the requesting core is responded to and the status of the cache lines in the L2 cache and the L1 cache in the first target core are adjusted.

[0018] In one embodiment, the multi-core system further includes a master node, the master node managing a globally shared level 3 cache; the level 2 cache reply response further includes:

[0019] When the L2 cache misses or the L2 cache hits but its cache line status does not meet the target request requirement, the L2 cache sends a third request to the master node to query whether the global directory in the L3 cache hits.

[0020] In one embodiment, when the global directory corresponding to the third-level cache in the master node is hit and its cache line status meets the target request requirement, the method includes:

[0021] The master node sends a listening request to all nodes that have the target information. After receiving listening responses from all nodes, the master node responds to the request core and adjusts the status of the cache lines in the third-level cache and the global directory as well as the cache lines in the first-level cache and the second-level cache in the corresponding node.

[0022] In one embodiment, when the global directory corresponding to the third-level cache in the master node misses or hits but the cache line status does not meet the target request requirement, the method includes:

[0023] The master node obtains target information from the memory, and backfills the target information to the third-level cache, the second-level cache and the first-level cache, and adjusts the status of the cache lines and the global directory in the third-level cache and the cache lines in the first-level cache and the second-level cache in the corresponding node.

[0024] According to a second aspect of the present disclosure, a multi-core cache consistency device is provided. The device is applied to a multi-core system, wherein the multi-core system includes multiple nodes, each node includes at least two cores, the core includes a first-level cache, and multiple cores of the same node share a second-level cache; the first-level cache and the second-level cache each include cache lines, and the second-level cache includes a directory that records corresponding cache line states; the device includes:

[0025] A sending module, configured to send a first request from a requesting core to a first target core; the requesting core and the first target core may be the same or different cores in the same node;

[0026] a processing module, configured to respond to the requesting core and maintain the original state of the cache line when the first target core's first-level cache hits and the state of its cache line meets the target request requirement;

[0027] The sending module is further configured to, when the first target core's level 1 cache misses or the level 1 cache hits but the cache line state does not meet the request requirement, the requesting core simultaneously sends a second request to other cores of the same node or the level 2 cache of the node;

[0028] The processing module is further configured to respond to the requesting core and adjust the states of cache lines in the corresponding first-level cache and second-level cache in the node according to the request result.

[0029] In one embodiment, the processing module includes a first processing unit; the first processing unit is configured to:

[0030] The first target core's L1 cache includes the target information indicated by the first request, and when the cache line state of the L1 cache is consistent with the target request requirement, the target information is obtained from the cache line and fed back to the requesting core.

[0031] In one embodiment, the processing module further includes a second processing unit; the second processing unit is configured to:

[0032] When there is a first-level cache hit of the second target core in the other cores and its cache line status meets the target request requirements, respond to the requesting core and adjust the status of the cache lines in the first-level cache and the second-level cache in the first target core and / or the second target core.

[0033] In one embodiment, the second processing unit is further configured to:

[0034] When the L1 caches of all other cores in the node miss or the L1 cache hits but the cache line status thereof does not meet the target request requirement, the node waits for a reply response from the L2 cache.

[0035] In one embodiment, the second processing unit includes a processing sub-unit configured to:

[0036] When the L2 cache hits and its cache line status meets the target request requirement, the requesting core is responded to and the status of the cache lines in the L2 cache and the L1 cache in the first target core are adjusted.

[0037] In one embodiment, the multi-core system further includes a master node, which manages a globally shared L3 cache; and the processing sub-unit is further configured to:

[0038] When the L2 cache misses or the L2 cache hits but its cache line status does not meet the target request requirement, the L2 cache sends a third request to the master node to query whether the global directory in the L3 cache hits.

[0039] In one possible implementation manner, when the global directory corresponding to the L3 cache in the master node is hit and the cache line status thereof meets the target request requirement, the processing sub-unit is specifically configured to:

[0040] The master node sends a listening request to all nodes that have the target information. After receiving listening responses from all nodes, the master node responds to the request core and adjusts the status of the cache lines in the third-level cache and the global directory as well as the cache lines in the first-level cache and the second-level cache in the corresponding node.

[0041] In one embodiment, when the global directory corresponding to the L3 cache in the master node misses or hits but the cache line status does not meet the target request requirement, the processing subunit is specifically configured to:

[0042] The master node obtains target information from the memory, and backfills the target information to the third-level cache, the second-level cache and the first-level cache, and adjusts the status of the cache lines and the global directory in the third-level cache and the cache lines in the first-level cache and the second-level cache in the corresponding node.

[0043] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0044] at least one processor; and

[0045] a memory communicatively connected to the at least one processor; wherein,

[0046] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0047] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0048] The present invention discloses a multi-core cache consistency maintenance method, device, electronic device and storage medium. The method is applied to a multi-core system, the system includes multiple nodes, each node includes at least two cores, the core includes a first-level cache, and multiple cores of the same node share a second-level cache; the first-level cache and the second-level cache both include cache lines, and the second-level cache includes a directory recording the corresponding cache line status; the method includes: a first request sent by a requesting core to a first target core; the requesting core and the first target core are the same or different cores in the same node; when the first-level cache of the first target core hits and the status of its cache line meets the target request requirements, responding to the requesting core and maintaining the original status of the cache line; when the first-level cache of the first target core misses or the first-level cache hits but the cache line status does not meet the request requirements, the requesting core simultaneously sends a second request to other cores of the same node or the second-level cache of the node; according to the request result, responding to the requesting core and adjusting the status of the cache lines in the corresponding first-level cache and second-level cache in the node. This method optimizes the cache access and consistency maintenance processes, sets up a directory in the secondary cache to record the cache line status to achieve cache consistency within the node, thereby eliminating the need to set up an additional directory in the node and reducing unnecessary communication overhead. At the same time, it also improves the cache consistency management efficiency of the multi-core system and optimizes hardware resource utilization.

[0049] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0051] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0052] Figure 1 A schematic diagram of the architecture of a multi-core system according to an embodiment of the present disclosure is shown;

[0053] Figure 2 The schematic diagram shows the implementation process of the multi-core cache consistency method of the embodiment of the present disclosure. Figure 1 ;

[0054] Figure 3 The schematic diagram shows the implementation process of the multi-core cache consistency method of the embodiment of the present disclosure. Figure 2 ;

[0055] Figure 4a The schematic diagram of the structure of the initial state of the multi-core cache in the embodiment of the present disclosure is shown. Figure 1 ;

[0056] Figure 4b The schematic diagram of the structure of the initial state of the multi-core cache in the embodiment of the present disclosure is shown. Figure 2 ;

[0057] Figure 5 A schematic diagram of the structure of a multi-core cache consistency device according to an embodiment of the present disclosure is shown;

[0058] Figure 6 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0059] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0060] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0062] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations.

[0063] A multi-core system is one that integrates multiple processing cores on a single processor chip. Each core can independently execute program instructions. This architecture allows the system to handle multiple tasks in parallel, making it better able to support multi-threaded applications.

[0064] The master node is the core node responsible for management, coordination, and control in a distributed system. It is responsible for allocating and scheduling tasks, ensuring that all slave nodes operate in an orderly manner. The master node also maintains the overall system status and handles data consistency and synchronization issues.

[0065] Cache coherence is a crucial mechanism for ensuring accurate and consistent data across caches in multi-processor or multi-core systems. Because different processor cores may have their own independent caches, when one core modifies data, it is necessary to ensure that the relevant data in other caches is also updated to avoid data inconsistencies that can lead to program errors. Through specific protocols (such as the MESI protocol), the system monitors cache status and synchronizes data when it changes, ensuring that each core sees consistent data and ensuring correct program execution.

[0066] The first-level cache, or L1 cache, is the fastest cache within the core. It's typically divided into two parts: the instruction cache and the data cache. The instruction cache stores instructions that the core is about to execute, while the data cache stores frequently accessed data. While the L1 cache has a smaller capacity, it can provide the core with the required instructions and data in a fraction of the time.

[0067] The second-level cache is L2 cache, which is slightly slower than the first-level cache but has a larger capacity. It is used to store data and instructions that the core may access frequently in the near future. The existence of the second-level cache can effectively reduce the number of times the core accesses memory.

[0068] The third-level cache, or L3 cache, is a larger, relatively slow shared cache in multi-core processors. The presence of the L3 cache increases the probability of cache hits and reduces the frequency of memory accesses.

[0069] A cache line is the smallest block of data in a cache. It is a storage space created by the core in memory to improve memory access speed. When the core performs an instruction operation, it first checks whether the required data is in the cache line. If so, it directly operates on the data.

[0070] The present disclosure relates to a multi-core cache consistency method, which aims to solve the problem of cache consistency in a multi-core system. With the development of multi-core processors, the cache consistency problem has become increasingly prominent. Traditional monitoring bus methods and directory methods have performance bottlenecks when processing high concurrency and high load environments. The present disclosure proposes a multi-core cache consistency maintenance mechanism that reduces cross-node communication overhead and improves cache consistency maintenance efficiency by performing cache consistency request and response processing within the nodes of a multi-core system.

[0071] Specifically, the present disclosure provides a multi-core cache consistency method for use in a multi-core system. Figure 1 As shown, the multi-core system includes multiple nodes, each node includes at least two cores, the core includes a first-level cache (L1 cache), and multiple cores of the same node share a second-level cache (L2 cache); the first-level cache and the second-level cache both include cache lines, and the second-level cache includes a directory that records the status of the corresponding cache line; as shown Figure 2 As shown, the method includes:

[0072] Step 101: A requesting core sends a first request to a first target core; the requesting core and the first target core are the same or different cores in the same node.

[0073] In this example, the requesting core is the processing unit in a node that initiates the data access request. The first target core is the core within the same node that the requesting core prioritizes by default. This can be the requesting core itself or another core within the same node. The first request sent by the requesting core to the first target core includes a read / write operation.

[0074] Step 102: When the first-level cache of the first target core hits and the state of its cache line meets the target request requirement, respond to the requesting core and maintain the original state of the cache line.

[0075] In this example, the L1 cache in a core is private to that core and is used only to record data and state within that core. When a hit occurs in the L1 cache of the first target core and its cache line state meets the request requirements, the first target core can directly return the data to the requesting core while maintaining the original cache line state.

[0076] For example, as a preferred embodiment, the cache line status of the first-level cache can be managed using the status in the MESI protocol. The MESI protocol includes four states: Modified, Exclusive, Shared, and Invalid. The requesting core needs to read data and the cache line status of the first target core is shared, or the requesting core needs to write data and the cache line status of the first target core is exclusive, the first target core returns the data directly to the requesting core and maintains the original state of the cache line. In this way, through the mechanism of information priority processing within the node, taking advantage of the low-latency communication between cores within the node, data requests are resolved preferentially in a local range.

[0077] It should be noted that the cache consistency method in this disclosure is applicable to cache consistency protocols such as MSI, MESI, MESIF, MOESI, CHI, CCIX, ACE, etc., and is not limited to a certain established protocol. For different protocols, the status of the cache lines recorded in the secondary cache is different.

[0078] Step 103: When the first target core's L1 cache misses or the L1 cache hits but the cache line status does not meet the request requirement, the requesting core simultaneously sends a second request to other cores of the same node or the L2 cache of the node.

[0079] In this example, when the first target core's L1 cache misses, or when the L1 cache hits but its cache line status doesn't meet the request requirements, the requesting core simultaneously sends a second request to the other cores on the same node and the node's L2 cache. Where the cache line status doesn't meet the request requirements, the requesting core's first request is for an exclusive write, but the target core's cache line status is shared or invalid. In this case, by distributing the second request in parallel to the other cores on the same node and the node's L2 cache, the intra-node query latency is reduced to a single communication cycle, allowing for faster access to the request results.

[0080] Step 104: respond to the requesting core and adjust the status of the cache lines in the corresponding first-level cache and second-level cache in the node according to the request result.

[0081] In this example, based on the response to the second request (e.g., a L1 cache hit and a state that meets the requirements in another core, or a L2 cache hit and a directory state match), the requesting core receives the target information. Simultaneously with the response from another core or the L2 cache to the requesting core, the L2 cache directory updates the state of the corresponding L1 and L2 cache lines. This dynamic state adjustment ensures that the cache line state within the node is consistent with the requested operation, thus achieving cache coherence within the node.

[0082] The present disclosure provides a multi-core cache consistency maintenance method, which is applied to a multi-core system. The system includes multiple nodes, each node includes at least two cores, the core includes a first-level cache, and multiple cores of the same node share a second-level cache; the first-level cache and the second-level cache both include cache lines, and the second-level cache includes a directory that records the corresponding cache line status; the method includes: a first request sent by a requesting core to a first target core; the requesting core and the first target core are the same or different cores in the same node; when the first-level cache of the first target core hits and the status of its cache line meets the target request requirements, responding to the requesting core and maintaining the original status of the cache line; when the first-level cache of the first target core misses or the first-level cache hits but the cache line status does not meet the request requirements, the requesting core simultaneously sends a second request to other cores of the same node or the second-level cache of the node; based on the request result, responding to the requesting core and adjusting the status of the cache lines in the corresponding first-level cache and second-level cache in the node. This method optimizes the cache access and consistency maintenance processes, sets up a directory in the secondary cache to record the cache line status to achieve cache consistency within the node, thereby eliminating the need to set up an additional directory in the node and reducing unnecessary communication overhead. At the same time, it also improves the cache consistency management efficiency of the multi-core system and optimizes hardware resource utilization.

[0083] In one example, when the first-level cache of the first target core hits and the state of its cache line meets the target request requirements, responding to the requesting core includes: when the first-level cache of the first target core includes the target information indicated by the first request, and the cache line state of the first-level cache is consistent with the target request requirements, obtaining the target information from the cache line and feeding back the target information to the requesting core.

[0084] In this example, when the first target core's L1 cache hits and the cache line state meets the request requirements, the first target core's L1 cache already contains the target information required for the request, and the cache line state is completely consistent with the state required by the target request. Target information includes either target information or target state. At this point, the first target core retrieves the target information from its cache line and feeds it back to the requesting core, while maintaining the original cache line state, without triggering a state transition or other core / cache coordination operations.

[0085] For example, if the first request is a shared read request, that is, the requesting core needs to read the target information and the target request requires a shared state S, and the cache line state of the first target core is already S, then the target information is directly obtained from the cache line and returned to avoid triggering a secondary cache query or state degradation.

[0086] For another example, if the first request is an exclusive write request, that is, the requesting core needs to write the target information and the target request requires exclusive state E, and the cache line state of the first target core is E, then the write permission is directly authorized, so there is no need to invalidate the copies in other cores.

[0087] In one example, responding to the requesting core and adjusting the status of the cache lines in the corresponding first-level cache and second-level cache in the node based on the request result includes: when there is a first-level cache hit of the second target core in the other cores and its cache line status meets the target request requirements, responding to the requesting core and adjusting the status of the cache lines in the first-level cache and second-level cache in the first target core and / or the second target core.

[0088] In this example, when there is a first-level cache hit of a second target core (other cores in the same node except the first target core) among the other cores and its cache line status meets the target request requirements, the second target core extracts the target information from its first-level cache and returns it to the requesting core; at the same time, the corresponding cache line status in the first-level cache and the second-level cache in the first target core and / or the second target core is synchronously updated according to the request type.

[0089] For example, if the first request is a shared read request, the cache line state of the first target core is invalid state I but the first request is not hit, and the second request is sent to other cores and the secondary cache; when the cache line of the second target core is hit and the state meets the target request requirements, the target information is first obtained and returned from its first-level cache, and the cache line state of the second target core is maintained in the shared state S. At the same time, the cache line state of the first target core is upgraded from I to S through the directory of the second-level cache to allow data sharing.

[0090] For another example, if the first request is an exclusive write request, and if the cache line state of the first target core is in the shared state S and the first request is missed, a second request is sent to other cores and the secondary cache; when the cache line of the second target core hits and the state meets the target request requirements, the target information is first obtained and returned from its primary cache, and at the same time, the cache line of the second target core is set to the invalid state I through the directory of the secondary cache. If the first target core is the requesting core, the cache line state of the first target core is set to the exclusive state E. If the first target core is not the requesting core, the cache line of the first target core is set to the invalid state I to ensure that the requesting core has the latest copy of the exclusive data.

[0091] In one example, based on the request result, responding to the requesting core and adjusting the status of the cache lines in the corresponding first-level cache and second-level cache in the node include: when the first-level cache of all other cores in the node misses or the first-level cache hits but its cache line status does not meet the target request requirements, waiting for the second-level cache to reply.

[0092] In this example, because the requesting core simultaneously sends a second request to all other cores and the L2 cache in the node, if any of the other cores in the node experience a L1 cache miss or a cache line hit but the cache line status doesn't meet the target request requirements, the system triggers the intra-node L2 cache coordination mechanism: the requesting core suspends its query of other cores, and the shared L2 cache responds uniformly based on the data information recorded in its cache line. The specific response process will be described in detail in subsequent embodiments.

[0093] In one example, the L2 cache reply response includes: when the L2 cache hits and its cache line status meets the target request requirements, responding to the requesting core and adjusting the status of the cache lines in the L2 cache and the L1 cache in the first target core.

[0094] In this example, when the L2 cache hits and its cache line state meets the target request requirements, the L2 cache returns the data directly to the requesting core and adjusts the state of the corresponding cache line in its directory. Since the second target core is not involved in this process, only the states of the cache lines in the L2 cache and the first target core's L1 cache need to be adjusted, ensuring that the requesting core has exclusive access to the latest copy of the data.

[0095] For example, when the requesting core is the first target core and its cache behavior is in shared state S, and the first request is an exclusive write operation, if the L2 cache hits and its cache line state meets the target request requirements (i.e., cache behavior is in exclusive state E), the system performs the following operations: the L2 cache directly returns the data to the requesting core and switches the exclusive state association of the data in its directory to the requesting core, that is, adjusting the shared state S of the first target core to exclusive state E, to ensure that the requesting core has exclusive access to the latest copy. During this process, other cores (such as the second target core) do not cache the data or their cache state is invalid, so no state adjustment is required.

[0096] In one example, if Figure 1 As shown, the multi-core system also includes a master node, which manages the globally shared third-level cache; the second-level cache reply response also includes: when the second-level cache misses or the second-level cache hits but its cache line status does not meet the target request requirements, the second-level cache sends a third request to the master node to query whether the global directory in the third-level cache is hit.

[0097] In this example, the multi-core system manages the globally shared L3 cache through the master node, forming a hierarchical cache consistency architecture: when the L2 cache within the node misses the target information or hits but the cache line status does not meet the request requirements, the L2 cache sends a third request to the master node, and the master node coordinates across nodes based on the global directory of the L3 cache. After receiving the request, the master node locates the cache status of the data in other nodes through the global directory. If there is a valid copy, the monitoring mechanism is triggered and the data is routed to the requesting node; if the data is not cached in any node, it is loaded from the memory and backfilled to the L2 cache and L1 cache of the requesting node step by step. The specific process will be described in detail in subsequent embodiments.

[0098] In one example, when the global directory corresponding to the third-level cache in the master node hits and its cache line status meets the target request requirements, the method includes: the master node sends a listening request to all nodes that have the target information, and after collecting the listening responses of all nodes, responds to the request core and adjusts the status of the cache line and global directory in the third-level cache and the cache lines in the first-level cache and the second-level cache in the corresponding node.

[0099] In this example, when the global directory corresponding to the third-level cache in the master node is hit and its cache line status meets the target request requirements, the multi-core system completes cross-node consistency maintenance through global coordination of the master node. Specifically: the master node determines all nodes under its jurisdiction that have the target information from the global directory and sends a monitoring request, requiring the node holding the target information to feedback a monitoring response to the master node. After the master node collects the monitoring responses from all nodes, it confirms the node that has the target information and feeds back the target information to the requesting core, and at the same time adjusts the cache line and global directory in the third-level cache and the status of the first-level cache and the second-level cache in the node that has the target information.

[0100] For example, the requesting core needs to modify the target information. The master node discovers through the global directory of the three-level cache that the target information exists in the second-level cache of a certain node and the status is shared state S. The master node synchronously sends a listening request to all nodes with the target information in the jurisdiction area. The node returns the S status of the target information, while other nodes that do not have the target information can return "no data". After receiving all the responses, the master node backfills the target information from the node to the requesting core, and forces the second-level cache of the node and the first-level cache of the associated core to set the cache line status of the target information from shared state S to invalid state I. Finally, the exclusive target information of the requesting core is marked in the global directory and the modification operation is performed.

[0101] In one example, when the global directory corresponding to the third-level cache in the master node misses or hits but its cache line status does not meet the target request requirements, the method includes: the master node obtains target information from the memory, and backfills the target information to the third-level cache, the second-level cache and the first-level cache, and adjusts the status of the cache lines and the global directory in the third-level cache and the cache lines in the first-level cache and the second-level cache in the corresponding node.

[0102] In this example, when the global directory corresponding to the third-level cache in the master node misses or hits but its cache line status does not meet the request requirements, the system achieves the target information response and global cache consistency through hierarchical backfilling of the master node. Specifically:

[0103] The master node directly obtains the target information from the memory and backfills it to the third-level cache, the second-level cache of the requesting node, and the first-level cache of the requesting core step by step. At the same time, it adjusts the cache line of the third-level cache and the status of the target information in the global directory and associates it with the first-level cache and second-level cache of the requesting node; if other nodes have copies of the target information, the master node also adjusts its second-level cache and the first-level cache of the associated core to transfer the data status.

[0104] For example, when the requesting core needs to modify the target information and the L3 cache misses, the master node loads the target information from the memory and writes it to the L3 cache, L2 cache, and L1 cache in sequence, marking it as exclusive state E, and invalidating any shared copies that may exist in other nodes.

[0105] In one example, combining Figure 3 The overall implementation process of this solution is described through a complete embodiment:

[0106] The first step is the request initiation phase:

[0107] The requesting core initiates the first request to the target core. The requesting core initiates a data access request to the first target core (the core in the priority node) within the same node, including the target address, operation type (read / write), and permission requirements (such as shared read or exclusive write).

[0108] The second step is the first target core cache status judgment stage:

[0109] 1. Determine whether the cache of the target core is hit.

[0110] 2. If a hit occurs, determine whether the L1 cache line state matches the target request state based on the directory.

[0111] 3. If it matches, reply to the requesting core and maintain the state of the L1 cache line.

[0112] 4. If there is a miss or the hit does not match, a second request is made to other cores and L2 caches on the same node to determine whether the L1 cache and L2 cache of other cores hit.

[0113] The third step is the cache status judgment phase of the second target core and L2 cache:

[0114] 1. Determine whether the L1 cache of other cores in the same node is hit.

[0115] 2. If a hit occurs, determine whether the L1 cache line status matches the target request status based on the directory.

[0116] 3. If it matches, reply to the requesting core's response, modify the state of the L1 cache line of the first target core, and modify the state of the L1 cache lines of other cores as appropriate.

[0117] 4. If there is a miss or the hit does not match, continue with the subsequent process (i.e., wait for the response from the L2 cache).

[0118] 5. If the L2 cache hits, determine whether the L2 cache line status matches the target request status based on the directory.

[0119] 6. If it matches, reply to the requesting core and change the target core L1 cache line state.

[0120] 7. If there is no hit or the hit does not match, continue the subsequent process (initiate a third request to the master node).

[0121] The fourth step is the master node global directory judgment stage:

[0122] 1. Determine whether the L3 cache line hits based on the global directory.

[0123] 2. If the L3 cache line hits, determine whether the L3 cache line state matches the target request state based on the directory.

[0124] 3. If it matches, the master node initiates a monitoring request to all nodes that have the target information.

[0125] 4. Collect the monitoring responses of each node and reply to the request core; and change the L1 cache line status of the core of the corresponding node and the L2 cache line status of the node as well as the cache line status in the global directory and L3.

[0126] 5. If there is a miss or the hit does not match, fetch the data from the memory to the L3 cache, and backfill the cache line to the L2 cache and L1 cache; at the same time, change the L1 cache line state of the core of the corresponding node and the L2 cache line state of the node as well as the cache line state in the global directory and L3.

[0127] The technical solution disclosed in the present invention can reduce the hardware overhead required for setting up an additional directory within a node by utilizing the L2 cache to implement the directory function. At the same time, the cores within the node can communicate directly. If the data happens to be in the same node and the cache line status meets the requirements, each core can directly reply with a response. There is no need to wait for the L2 cache status to be queried before sending a monitoring request to each core. Only after each core replies to the monitoring response can a response be sent to the requesting core, thereby shortening the transaction processing process, improving the transaction processing speed, and thus improving processing efficiency.

[0128] In addition, with the computer's software allocation, the same or related tasks are assigned to the same node. In this way, the probability of processing related data within the same node will be much greater than the cores in other nodes. Most of the data that need to maintain cache consistency can be completed within the node, which can greatly improve the efficiency of cache consistency maintenance.

[0129] In one example, the implementation process of the multi-core cache consistency is described in detail in combination with the following embodiments.

[0130] First, the MESI protocol is adopted in the embodiment. The MESI protocol contains 4 states: Modified (M): This state indicates that the data in the cache line has been modified and is inconsistent with the data in the main memory; Exclusive (E): This state indicates that the data in the cache line is valid, and there is no such data in the cache of other CPUs. Shared (S): This state indicates that this line of data is cached in the caches of multiple CPUs, and the data in the cache is consistent with the data in the memory. Invalid (I): This state indicates that the data in the current cache line is invalid. The multi-core system architecture takes 2 nodes with 2 cores in each node as an example. The system cache design follows the traditional cache architecture, in which the L2 cache is specially designed to set the L2 cache state and the L1 cache line state of the two cores on each cache line; the global directory records the state of each node.

[0131] Example 1: Figure 4a The initial state of the cache is shown in Figure 4a Take Node 1 on the left in the middle as an example: When Core 1 initiates a shared read request for a cache line, the request is transmitted to Core 2 and the L2 cache within this node. After receiving the request, Core 2 checks its L1 cache state and finds that it is in the shared state S, which matches Core 1's request. Therefore, Core 2 directly sends the cache line data to Core 1. After Core 1 obtains the data, its L1 cache state changes to the shared state S, allowing it to use the data. At the same time, after receiving the request, the L2 cache updates its own cache state to E, S, S.

[0132] Core 1 then initiates an exclusive request for the cache line, which is sent to Core 2. Core 2 checks its L1 cache state and finds it is still in the Shared state (S), which does not meet the requirements for the Exclusive state (E). Core 2 changes its cache line state to the Invalid state (I). After receiving the exclusive request, the L2 cache checks its cache state (E), which meets the requirements. It then responds to Core 1, granting it the Exclusive state (E) and updating its L2 cache state to E, E, I.

[0133] When data is shared within a node, requests can be responded to immediately, completing the operation in just two steps, significantly shortening the transaction process. Even if a directory is not set up within the core, the L2 cache can take on some of the directory's functions by recording the status of each L1 cache in the L2 cache.

[0134] Example 2: Figure 4b The cache is shown in its initial state.

[0135] When Core 1 initiates a shared read request for a cache line, the request is transmitted to Core 2 and the L2 cache within the node. After receiving the request, Core 2 checks its L1 cache state and confirms that it is in the shared state S, which matches Core 1's request. Therefore, Core 2 directly sends the cache line data to Core 1. After Core 1 obtains the data, its L1 cache state changes to the shared state S, allowing it to use the data. Meanwhile, upon receiving the request, the L2 cache updates its own cache state to S, S, S.

[0136] Core 1 then initiates an exclusive request for the cache line, which is sent to Core 2. Core 2 checks its L1 cache state and finds it's still in the Shared state (S), which doesn't meet the requirements for the Exclusive state (E). Therefore, Core 2 changes its cache line state to the Invalid state (I). Upon receiving the exclusive request, the L2 cache checks its own state (S), which also doesn't meet the requirements for the request from Core 1. Therefore, the L2 cache sends the request to the master node. The master node finds that the cache states of both Node 1 and Node 2 are S, so it sends a snoop request to Node 2, changing its cache state to the Invalid state (I). After receiving the snoop request, Node 2 sends the request to Core 3 within its own node, also changing its cache state to the Invalid state (I). After Core 1 responds with a snoop response, the L2 cache in Node 2 updates its cache state to I, I, I and sends a snoop response back to the master node. Upon receiving the snoop response, the master node changes its directory state to E, I and sends a response back to Node 1's L2 cache, changing its cache state to E. The L2 cache state in node 1 is then updated to E, E, I, and a response is sent to core 1 that initiated the request, allowing it to obtain the exclusive state E.

[0137] When a core request cannot be satisfied within a node, it must be sent to another node, which can lengthen the response time. Therefore, software strategies should be used to allocate identical or similar tasks to the same node to improve overall data processing efficiency.

[0138] The present disclosure also provides a multi-core cache consistency device, such as Figure 5 As shown, the device is applied to a multi-core system, the multi-core system includes multiple nodes, each node includes at least two cores, the core includes a first-level cache, and multiple cores of the same node share a second-level cache; the first-level cache and the second-level cache both include cache lines, and the second-level cache includes a directory that records the status of the corresponding cache line; the device includes:

[0139] A sending module, configured to send a first request from a requesting core to a first target core; the requesting core and the first target core may be the same or different cores in the same node;

[0140] a processing module, configured to respond to the requesting core and maintain the original state of the cache line when the first target core's first-level cache hits and the state of its cache line meets the target request requirement;

[0141] The sending module is further configured to, when the first target core's level 1 cache misses or the level 1 cache hits but the cache line state does not meet the request requirement, the requesting core simultaneously sends a second request to other cores of the same node or the level 2 cache of the node;

[0142] The processing module is further configured to respond to the requesting core and adjust the states of cache lines in the corresponding first-level cache and second-level cache in the node according to the request result.

[0143] In one example, the processing module includes a first processing unit; the first processing unit is configured to:

[0144] The first target core's L1 cache includes the target information indicated by the first request, and when the cache line state of the L1 cache is consistent with the target request requirement, the target information is obtained from the cache line and fed back to the requesting core.

[0145] In one example, the processing module further includes a second processing unit; the second processing unit is configured to:

[0146] When there is a first-level cache hit of the second target core in the other cores and its cache line status meets the target request requirements, respond to the requesting core and adjust the status of the cache lines in the first-level cache and the second-level cache in the first target core and / or the second target core.

[0147] In one example, the second processing unit is further configured to:

[0148] When the L1 caches of all other cores in the node miss or the L1 cache hits but the cache line status thereof does not meet the target request requirement, the node waits for a reply response from the L2 cache.

[0149] In one example, the second processing unit includes a processing subunit configured to:

[0150] When the L2 cache hits and its cache line status meets the target request requirement, the requesting core is responded to and the status of the cache lines in the L2 cache and the L1 cache in the first target core are adjusted.

[0151] In one example, the multi-core system further includes a master node, which manages a globally shared L3 cache; and the processing sub-unit is further configured to:

[0152] When the L2 cache misses or the L2 cache hits but its cache line status does not meet the target request requirement, the L2 cache sends a third request to the master node to query whether the global directory in the L3 cache hits.

[0153] In one example, when the global directory corresponding to the L3 cache in the master node is hit and the cache line status thereof meets the target request requirement, the processing sub-unit is specifically configured to:

[0154] The master node sends a listening request to all nodes that have the target information. After receiving listening responses from all nodes, the master node responds to the request core and adjusts the status of the cache lines in the third-level cache and the global directory as well as the cache lines in the first-level cache and the second-level cache in the corresponding node.

[0155] In one example, when the global directory corresponding to the L3 cache in the master node misses or hits but the cache line status thereof does not meet the target request requirement, the processing subunit is specifically configured to:

[0156] The master node obtains target information from the memory, and backfills the target information to the third-level cache, the second-level cache and the first-level cache, and adjusts the status of the cache lines and the global directory in the third-level cache and the cache lines in the first-level cache and the second-level cache in the corresponding node.

[0157] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0158] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0159] like Figure 6As shown, electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. Various programs and data required for the operation of device 600 can also be stored in RAM 603. Computing unit 601, ROM 602, and RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to bus 604.

[0160] Various components in device 600 are connected to I / O interface 605, including an input unit 606, such as a keyboard, mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a magnetic disk, optical disk, etc.; and a communication unit 609, such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows device 600 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0161] The computing unit 601 can be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as the multi-core cache consistency method. For example, in some embodiments, the multi-core cache consistency method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the computing unit 601, one or more steps of the multi-core cache consistency method described above can be performed. Alternatively, in other embodiments, the computing unit 601 can be configured to perform the multi-core cache consistency method by any other appropriate means (e.g., by means of firmware).

[0162] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0163] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0164] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0165] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0166] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0167] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0168] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0169] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0170] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A multi-core cache consistency method, characterized in that: The method is applied to a multi-core system, wherein the multi-core system includes multiple nodes, each node includes at least two cores, the core includes a first-level cache, and multiple cores of the same node share a second-level cache; The first-level cache and the second-level cache both include cache lines, and the second-level cache includes a directory that records the status of the corresponding cache lines; the method includes: A first request sent by a requesting core to a first target core; the requesting core and the first target core are the same or different cores in the same node; When the first-level cache of the first target core hits and the state of its cache line meets the target request requirement, respond to the requesting core and maintain the original state of the cache line; When the first target core's L1 cache misses or the L1 cache hits but the cache line state does not meet the request requirement, the requesting core simultaneously sends a second request to other cores of the same node or the L2 cache of the node; According to the request result, the requesting core is responded to and the status of the cache lines in the corresponding first-level cache and second-level cache in the node is adjusted.

2. The method according to claim 1, characterized in that When the first-level cache of the first target core hits and the state of its cache line meets the target request requirement, responding to the requesting core includes: The first target core's L1 cache includes the target information indicated by the first request, and when the cache line state of the L1 cache is consistent with the target request requirement, the target information is obtained from the cache line and fed back to the requesting core.

3. The method according to claim 1, characterized in that The step of responding to the requesting core and adjusting the states of cache lines in the corresponding first-level cache and second-level cache in the node according to the request result includes: When there is a first-level cache hit of the second target core in the other cores and its cache line status meets the target request requirements, respond to the requesting core and adjust the status of the cache lines in the first-level cache and the second-level cache in the first target core and / or the second target core.

4. The method according to claim 2, characterized in that The step of responding to the requesting core and adjusting the states of cache lines in the corresponding first-level cache and second-level cache in the node according to the request result includes: When the L1 caches of all other cores in the node miss or the L1 cache hits but the cache line status thereof does not meet the target request requirement, the node waits for a reply response from the L2 cache.

5. The method according to claim 4, characterized in that The secondary cache reply response includes: When the L2 cache hits and its cache line status meets the target request requirement, the requesting core is responded to and the status of the cache lines in the L2 cache and the L1 cache in the first target core are adjusted.

6. The method according to claim 4, characterized in that The multi-core system further includes a master node, which manages a globally shared L3 cache; The secondary cache reply response further includes: When the L2 cache misses or the L2 cache hits but its cache line status does not meet the target request requirement, the L2 cache sends a third request to the master node to query whether the global directory in the L3 cache hits.

7. The method according to claim 6, characterized in that When the global directory corresponding to the third-level cache in the master node is hit and the cache line state thereof meets the target request requirement, the method includes: The master node sends a listening request to all nodes that have the target information. After receiving listening responses from all nodes, the master node responds to the request core and adjusts the status of the cache lines in the third-level cache and the global directory as well as the cache lines in the first-level cache and the second-level cache in the corresponding node.

8. The method according to claim 6, characterized in that When the global directory corresponding to the third-level cache in the master node misses or hits but the cache line state does not meet the target request requirement, the method includes: The master node obtains target information from the memory, and backfills the target information to the third-level cache, the second-level cache and the first-level cache, and adjusts the status of the cache lines and the global directory in the third-level cache and the cache lines in the first-level cache and the second-level cache in the corresponding node.

9. A multi-core cache consistency device, characterized in that: The device is applied to a multi-core system, wherein the multi-core system includes multiple nodes, each node includes at least two cores, the core includes a first-level cache, and multiple cores of the same node share a second-level cache; The first-level cache and the second-level cache both include cache lines, and the second-level cache includes a directory that records the status of the corresponding cache lines; the device includes: A sending module, configured to send a first request from a requesting core to a first target core; the requesting core and the first target core may be the same or different cores in the same node; a processing module, configured to respond to the requesting core and maintain the original state of the cache line when the first target core's first-level cache hits and the state of its cache line meets the target request requirement; The sending module is further configured to, when the first target core's level 1 cache misses or the level 1 cache hits but the cache line state does not meet the request requirement, the requesting core simultaneously sends a second request to other cores of the same node or the level 2 cache of the node; The processing module is further configured to respond to the requesting core and adjust the states of cache lines in the corresponding first-level cache and second-level cache in the node according to the request result.

10. The device according to claim 9, characterized in that The processing module includes a first processing unit; the first processing unit is configured to: The first target core's L1 cache includes the target information indicated by the first request, and when the cache line state of the L1 cache is consistent with the target request requirement, the target information is obtained from the cache line and fed back to the requesting core.

11. The device according to claim 9, characterized in that The processing module further includes a second processing unit; the second processing unit is configured to: When there is a first-level cache hit of the second target core in the other cores and its cache line status meets the target request requirements, respond to the requesting core and adjust the status of the cache lines in the first-level cache and the second-level cache in the first target core and / or the second target core.

12. The device according to claim 11, characterized in that The second processing unit is further configured to: When the L1 caches of all other cores in the node miss or the L1 cache hits but the cache line status thereof does not meet the target request requirement, the node waits for a reply response from the L2 cache.

13. The device according to claim 12, characterized in that The second processing unit includes a processing subunit, configured to: When the L2 cache hits and its cache line status meets the target request requirement, the requesting core is responded to and the status of the cache lines in the L2 cache and the L1 cache in the first target core are adjusted.

14. The device according to claim 12, characterized in that The multi-core system further includes a master node, which manages a globally shared L3 cache; and the processing sub-unit is further configured to: When the L2 cache misses or the L2 cache hits but its cache line status does not meet the target request requirement, the L2 cache sends a third request to the master node to query whether the global directory in the L3 cache hits.

15. The device according to claim 14, characterized in that When the global directory corresponding to the third-level cache in the master node is hit and the cache line status thereof meets the target request requirement, the processing sub-unit is specifically configured to: The master node sends a listening request to all nodes that have the target information. After receiving listening responses from all nodes, the master node responds to the request core and adjusts the status of the cache lines in the third-level cache and the global directory as well as the cache lines in the first-level cache and the second-level cache in the corresponding node.

16. The device according to claim 14, characterized in that When the global directory corresponding to the third-level cache in the master node is missed or hit but the cache line status thereof does not meet the target request requirement, the processing sub-unit is specifically configured to: The master node obtains target information from the memory, and backfills the target information to the third-level cache, the second-level cache and the first-level cache, and adjusts the status of the cache lines and the global directory in the third-level cache and the cache lines in the first-level cache and the second-level cache in the corresponding node.

17. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

18. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 8.

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