Inter-core communication method based on logic soft bus

Abstract

The invention relates to the field of digital signal processing, and provides an inter-core communication method based on a logic soft bus. According to the method, an inter-core communication configuration file and a logic soft bus controller are initialized, packaging of a data receiving and sending interface and routing management of a decision-making center are carried out, application software does not care about which core the data is sent to, and only care about which task the data is sent to, so that inter-core communication between the application software and a bottom layer can be thoroughly decoupled; according to the method, interconnection and intercommunication among multiple tasks deployed in different cores are achieved, a simple, easy-to-use, convenient and flexible data interaction mode is provided for communication among the tasks of the multiple cores, tedious and repeated development work is avoided, and the problems that an existing inter-core communication method is poor in flexibility and universality, large in transplantation difficulty, limited in data transmission length and the like are solved.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and in particular to an inter-core communication method based on a logic soft bus. Background Art

[0002] Multi-core DSP (Digital Signal Processing) processors, with their powerful floating-point computing capabilities and rich bus interfaces, have been widely used in fields such as avionics, communications systems, machine vision, and radar. In digital signal processing, multi-core processors typically operate in AMP (Asymmetric Multi-Processing) mode, allowing each core of the processor to independently run different applications and operating systems. This ensures both security and real-time performance of signal processing systems through parallel computing.

[0003] However, independent programming between cores also complicates inter-core communication and interaction. Existing inter-core communication methods typically utilize shared memory and inter-core interrupts. Developers must manually allocate shared memory resources within their programs and consider critical resource protection. This consideration must be repeated with each additional set of inter-core communication. Due to the lack of a unified inter-core communication framework, changes to the digital signal processing workflow or data content necessitate redevelopment and re-debugging of the inter-core communication components. This lacks flexibility, makes porting difficult, and makes it difficult to adapt to the complex and ever-changing digital signal processing workflow.

[0004] While common Sys / Bios and reWorks operating systems offer inter-core communication methods such as Event Notify and Message Passing, these methods are complex to use and have limited data lengths. In digital signal processing, inter-core communication often requires large amounts of data and places high demands on real-time performance.

[0005] Therefore, in digital signal processing, there is an urgent need for an inter-core communication framework that is simple to use, universally configurable, and easy to port and expand. Summary of the Invention

[0006] In view of the problems of poor flexibility and versatility, great porting difficulty, and limited data transmission length in existing inter-core communication methods, the present invention provides an inter-core communication method based on a logic soft bus.

[0007] The present invention provides an inter-core communication method based on a logic soft bus, comprising:

[0008] Complete the initialization configuration of the inter-core communication logic soft bus in the main core and obtain the inter-core communication configuration file;

[0009] Parsing the configuration file to obtain a topology for inter-core communication, establishing an inter-core communication connection relationship based on the topology, generating a routing table for inter-core data transmission, applying for shared memory resources for inter-core communication for each group of inter-core communications, and applying for a dedicated data exchange channel and creating a message queue for each group of inter-core communications based on the information in the configuration file; simultaneously creating a logical soft bus controller for inter-core communication, and completing initialization configuration;

[0010] The inter-core communication logic soft bus provides a standardized data transmission interface for application software. After the application software calls this data transmission interface, the data transmission module queries the routing table through the decision center to obtain the bus controller handle that matches the destination task. Based on the query of the message queue status in the corresponding data transmission dedicated channel, the data to be sent is pushed into the message queue.

[0011] The inter-core communication logic soft bus provides a standardized data receiving interface for application software. In the data receiving module, the decision center queries the routing table to obtain the bus controller handle that matches the destination task, and obtains the data to be received from the message queue based on the query status of the message queue in the corresponding data transmission dedicated channel.

[0012] In some embodiments, the configuration parameters in the configuration file are presented in a tabular form, and the configuration parameters for each group of inter-core communication include name, source core number, destination core number, source task name, destination task name, maximum length of a single transmission, maximum number of messages and trigger method.

[0013] In some embodiments, the configuration parameters are defined as follows:

[0014] The source core number and destination core number are the processor cores where the data sender and data receiver are located respectively;

[0015] The source task and destination task names represent the application software tasks of the data sender and data receiver respectively;

[0016] There are two triggering modes: query and interrupt;

[0017] The maximum length of a single transmission indicates the maximum length of each data transmission or reception;

[0018] The maximum number of messages indicates the maximum number of messages that can be cached.

[0019] In some embodiments, the definition of the dedicated data exchange channel includes a data readable identification address, a data writable identification address, a data content transmission address, and a maximum length of data transmission; wherein a message queue is created in the data transmission address space.

[0020] In some embodiments, the message queue is implemented by a linked list, including a queue head pointer, a queue tail pointer, a queue empty flag, and a queue full flag; the message queue can complete the functions of message queue initialization, message enqueue, message dequeue, message clearing, and querying the empty / full status of the message queue.

[0021] In some embodiments, when the data sending module and the data receiving module are called, a spin lock is used before and after operating the bus controller to protect the data.

[0022] In some embodiments, when the data sending module is called, if the trigger mode configured in the bus controller is interrupt, a corresponding inter-core interrupt is sent to the destination core; otherwise, no interrupt is sent.

[0023] In some embodiments, when the data receiving module is called, if the trigger mode configured in the bus controller is interrupt, data is checked in the interrupt callback function; otherwise, data is checked in the destination task using a polling method.

[0024] In some embodiments, when calling the data sending module and the data receiving module, the decision center needs to determine whether the destination task and the current task are on different cores:

[0025] If the destination task and the current task are not on the same core, the inter-core data sending module and data receiving module are called to complete the data transmission;

[0026] If the destination task and the current task are on the same core, the operating system's message queue is directly called to complete the data transfer between tasks.

[0027] In some embodiments, the message queue status refers to a message queue empty or full status;

[0028] When calling the data sending module, if the message queue status is not full, the data to be sent is pushed into the message queue;

[0029] When the data receiving module is called, if the message queue state is not empty, the data to be received is obtained from the message queue.

[0030] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0031] The present invention initializes the inter-core communication configuration file and the logical soft bus controller, as well as the encapsulation of the data transceiver interface and the routing management of the decision center. The application software does not care which core the data is sent to, but only cares which task the data is sent to. In this way, the application software can be completely decoupled from the underlying inter-core communication, and the interconnection between multiple tasks deployed on different cores can be achieved. It provides a simple, easy-to-use, convenient and flexible data interaction method for communication between multi-core tasks, avoids tedious and repetitive development work, and solves the problems of poor flexibility and versatility of existing inter-core communication methods, great porting difficulty, and limited data transmission length. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a flow chart of an inter-core communication method based on a logical soft bus proposed in an embodiment of the present invention.

[0033] Figure 2 Schematic diagram of the topology of inter-core communication in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0036] In view of the problems of poor flexibility and versatility, difficult porting, and limited data transmission length in existing inter-core communication methods, such as Figure 1 As shown, an embodiment of the present invention proposes an inter-core communication method based on a logic soft bus, comprising the following steps:

[0037] Step 1: Generate inter-core communication configuration file

[0038] Specifically, according to the business requirements of the application software and in combination with the characteristics of the multi-core processor, the initialization configuration of the inter-core communication logic soft bus is completed in the main core to obtain a configuration file for the inter-core communication.

[0039] In this embodiment, the configuration parameters in the configuration file are presented in a tabular form. The configuration parameters for each group of inter-core communication include name, source core number, destination core number, source task name, destination task name, maximum length of a single transmission, maximum number of messages and triggering method, etc.

[0040] The configuration parameters are defined as follows:

[0041] The source core number and destination core number are the processor cores where the data sender and data receiver are located respectively;

[0042] The source task and destination task names represent the application software tasks of the data sender and data receiver respectively;

[0043] There are two triggering modes: query and interrupt;

[0044] The maximum length of a single transmission indicates the maximum length of each data transmission or reception;

[0045] The maximum number of messages indicates the maximum number of messages that can be cached.

[0046] Step 2: Initialize the logical soft bus controller

[0047] Specifically, the configuration file is parsed to obtain the topological structure of inter-core communication, the inter-core communication connection relationship is established according to the topological structure, a routing table for inter-core data transmission is generated, and shared memory resources for inter-core communication are applied for each group of inter-core communication. According to the information in the configuration file, a dedicated channel for data exchange is applied for each group of inter-core communication and a message queue is created; at the same time, a logical soft bus controller for inter-core communication is created, and the initialization configuration is completed.

[0048] In this embodiment, the definition of the dedicated data exchange channel includes a data readable identification address, a data writable identification address, a data content transmission address, and a maximum data transmission length. A message queue is created in the data transmission address space.

[0049] In this embodiment, the message queue is implemented by a linked list, including a queue head pointer, a queue tail pointer, a queue empty flag, and a queue full flag; the message queue can complete functions such as message queue initialization, message enqueue, message dequeue, message clearing, and querying the empty / full status of the message queue.

[0050] Step 3: Data transmission

[0051] Specifically, the inter-core communication logic soft bus provides a standardized data sending interface for the application software. After the application software calls the data sending interface, the data sending module queries the routing table through the decision center to obtain the bus controller handle that matches the destination task, and based on the query of the message queue status in the corresponding data transmission dedicated channel, for example, when the message queue status is not full, the data to be sent is pushed into the message queue.

[0052] If the trigger mode configured in the bus controller is interrupt, a corresponding inter-core interrupt is sent to the destination core; otherwise, no interrupt is sent.

[0053] In this embodiment, the input data of the data sending interface includes the destination task name, the pointer of the data to be sent, and the data length.

[0054] In this embodiment, in order to prevent data anomalies caused by multiple tasks operating the bus controller of the same destination task at the same time, a spin lock is used before and after operating the bus controller to protect the data.

[0055] Step 4: Data reception

[0056] Specifically, the inter-core communication logic soft bus provides a standardized data receiving interface for the application software. In the data receiving module, the decision center queries the routing table to obtain the bus controller handle that matches the destination task, and based on the query of the message queue status in the corresponding data transmission dedicated channel, for example, when the message queue status is non-empty, the data to be received is obtained from the message queue.

[0057] If the trigger mode configured in the bus controller is interrupt, the data is checked in the interrupt callback function; otherwise, the data is checked in the destination task using a polling method.

[0058] In this embodiment, the data received by the data receiving interface includes: a received data pointer and a received data length.

[0059] In this embodiment, the decision center determines whether to use the inter-core logical soft bus controller for data transmission and retrieves the corresponding bus controller handle based on the destination task name and the routing table. Specifically, when the current task needs to send data, the decision center retrieves the corresponding bus controller handle based on the destination task name and the data transmission routing table, ultimately invoking the data transmission module to complete the data transmission. When the current task needs to receive data, it retrieves the data by querying the message queue of the current task's bus controller.

[0060] For data reception and transmission, the decision center needs to determine whether the destination task and the current task are on different cores:

[0061] If the destination task and the current task are not on the same core, the inter-core data sending module and data receiving module are called to complete the data transmission;

[0062] If the destination task and the current task are on the same core, the operating system's message queue is directly called to complete the data transfer between tasks.

[0063] From the above, it can be seen that the present invention initializes the inter-core communication configuration file and the logical soft bus controller, as well as the encapsulation of the data transceiver interface and the routing management of the decision center. The application software does not care which core the data is sent to, it only cares which task the data is sent to. In this way, the application software can be completely decoupled from the underlying inter-core communication, and the interconnection between multiple tasks deployed on different cores can be achieved. It provides a simple, easy-to-use, convenient and flexible data interaction method for communication between multi-core tasks, and solves the problems of poor flexibility and versatility of existing inter-core communication methods, great difficulty in porting, and limited data transmission length.

[0064] The following is an application example:

[0065] Taking the domestic chip FT-M6678 as an example, using the Ruihua operating system: two tasks named "Task1" and "Task2" are created in core 0, and the task priority is 172. Two tasks named "Task3" and "Task4" are created in core 1, and the task priority is 173. The two tasks "Task1" and "Task2" need to send 2MB and 1MB of data to "Task3" and "Task4" respectively in a 20ms cycle, with a data sending interval of 10ms between the two tasks.

[0066] In core 0, an inter-core communication configuration file is generated. According to the communication requirements of the tasks in core 0 and core 1, the configuration parameters in the generated configuration file are shown in Table 1.

[0067] Table 1, Configuration parameters in the inter-core communication configuration file:

[0068]

[0069]

[0070] After generating the inter-core communication configuration file, the inter-core communication topology structure under this business scenario is obtained as follows: Figure 2As shown in the figure. After generating the inter-core communication configuration file, the data sending module is called in tasks "Task1" and "Task2" respectively to complete the data transmission. In tasks "Task3" and "Task4", the data from tasks "Task1" and "Task2" are checked through periodic queries. The query interval is 100us. Taking the communication scenario between tasks "Task1" and "Task3" as an example, the inter-core communication process is as follows: Figure 1 shown.

[0071] The time synchronization between the two cores is achieved by sending a time synchronization interrupt to both cores 0 and 1 simultaneously from the chip. After starting data transmission between cores 0 and 1, the serial port prints the data transmission time in core 0 and the data reception time in core 1. The data transmission time and transmission correctness are compared to determine the correctness of the data transmission. The test results are shown in Table 2.

[0072] Table 2, test results statistics:

[0073]

[0074] From the above verification, it can be seen that the present invention provides a simple, easy-to-use, flexible and efficient inter-core communication framework that can realize real-time and reliable data transmission between multiple cores and multiple tasks.

[0075] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for inter-core communication based on a logic soft bus, characterized in that: include: Complete the initialization configuration of the inter-core communication logic soft bus in the main core and obtain the inter-core communication configuration file; Parsing the configuration file to obtain a topology for inter-core communication, establishing an inter-core communication connection relationship based on the topology, generating a routing table for inter-core data transmission, applying for shared memory resources for inter-core communication for each group of inter-core communications, and applying for a dedicated data exchange channel and creating a message queue for each group of inter-core communications based on the information in the configuration file; simultaneously creating a logical soft bus controller for inter-core communication, and completing initialization configuration; The inter-core communication logic soft bus provides a standardized data transmission interface for application software. After the application software calls this data transmission interface, the data transmission module queries the routing table through the decision center to obtain the bus controller handle that matches the destination task. Based on the query of the message queue status in the corresponding data transmission dedicated channel, the data to be sent is pushed into the message queue. The inter-core communication logic soft bus provides a standardized data receiving interface for application software. In the data receiving module, the decision center queries the routing table to obtain the bus controller handle that matches the destination task, and obtains the data to be received from the message queue based on the query status of the message queue in the corresponding data transmission dedicated channel.

2. The inter-core communication method based on a logic soft bus according to claim 1, characterized in that: The configuration parameters in the configuration file are presented in a table. The configuration parameters for each group of inter-core communication include name, source core number, destination core number, source task name, destination task name, maximum length of a single transmission, maximum number of messages and triggering method.

3. The inter-core communication method based on a logic soft bus according to claim 2, characterized in that: The configuration parameters are defined as follows: The source core number and destination core number are the processor cores where the data sender and data receiver are located respectively; The source task and destination task names represent the application software tasks of the data sender and data receiver respectively; There are two triggering modes: query and interrupt; The maximum length of a single transmission indicates the maximum length of each data transmission or reception; The maximum number of messages indicates the maximum number of messages that can be cached.

4. The inter-core communication method based on a logic soft bus according to claim 1, characterized in that: The definition of the dedicated data exchange channel includes a data readable identification address, a data writable identification address, a data content transmission address, and a maximum length of data transmission; wherein, a message queue is created in the data transmission address space.

5. The inter-core communication method based on a logic soft bus according to claim 1, characterized in that: The message queue is implemented by a linked list, including a queue head pointer, a queue tail pointer, a queue empty flag, and a queue full flag; the message queue can complete the functions of message queue initialization, message queue entry, message dequeue, message clearing, and querying the empty / full status of the message queue.

6. The inter-core communication method based on a logic soft bus according to claim 1, characterized in that: When calling the data sending module and the data receiving module, a spin lock is used before and after operating the bus controller to complete data protection.

7. The inter-core communication method based on a logic soft bus according to claim 1, characterized in that: When the data sending module is called, if the trigger mode configured in the bus controller is interrupt, the corresponding inter-core interrupt is sent to the destination core; otherwise, no interrupt is sent.

8. The inter-core communication method based on a logic soft bus according to claim 1, characterized in that: When calling the data receiving module, if the trigger mode configured in the bus controller is interrupt, the data is checked in the interrupt callback function; otherwise, the data is checked in the destination task using polling.

9. The inter-core communication method based on a logic soft bus according to claim 1, characterized in that: When calling the data sending module and the data receiving module, the decision center needs to determine whether the destination task and the current task are on different cores: If the destination task and the current task are not on the same core, the inter-core data sending module and data receiving module are called to complete the data transmission; If the destination task and the current task are on the same core, the operating system's message queue is directly called to complete the data transfer between tasks.

10. The inter-core communication method based on a logic soft bus according to claim 1, characterized in that: The message queue status refers to whether the message queue is empty or full; When calling the data sending module, if the message queue status is not full, the data to be sent is pushed into the message queue; When the data receiving module is called, if the message queue state is not empty, the data to be received is obtained from the message queue.

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