Separated three-dimensional processor

Abstract

A separate three-dimensional processor (100) includes a first chip (100a) and a second chip (100b). The first chip (100a) includes a three-dimensional memory (3D-M) array (170) and an on-chip peripheral circuit component thereof, and the second chip (100b) includes a logic circuit (180) and an off-chip peripheral circuit component (190) of the 3D-M array (170). The number of rear-end wiring layers of the first chip (100a) is greater than the number of rear-end wiring layers of the second chip (100b); the resistivity of at least a portion of the back-end wiring layer of the on-chip peripheral circuit assembly is greater than the resistivity of the same back-end wiring layer of the off-chip peripheral circuit assembly (190).

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly, to processors. Background Art

[0002] Processors (including CPUs, GPUs, and FPGAs) are widely used in mathematical computing, computer simulation, programmable gate arrays, pattern processing, neural networks, and other fields. Traditional processor chips are based on two-dimensional integration, with their logic circuits (such as arithmetic logic units and control units) and storage circuits (internal memory, including RAM for cache and ROM for storing lookup tables) located on the same plane (i.e., the surface of the semiconductor substrate). Because the primary function of processor chips is arithmetic and logical operations, their internal memory capacity is very small, resulting in limited performance.

[0003] With the advent of three-dimensional memory (3D-M), the various difficulties encountered by traditional processors and their architectures have been largely resolved. 3D-M's memory elements are distributed in three dimensions, stacked perpendicular to the substrate. Chinese Patent 02131089.0 (Authorization Publication Number: CN 1285125C; Grant Date: November 15, 2006) proposes a 3D-M-based processor (i.e., a three-dimensional processor) that integrates logic circuitry into the substrate beneath the 3D-M array, forming an integrated three-dimensional processor. This integrated three-dimensional processor resides on a single three-dimensional processor chip.

[0004] Figure 1A-1B FIG. 8 shows an integrated three-dimensional processor 80, which includes a 3D-M array 77 and an integrated logic circuit 78. The 3D-M array 77 stores data, and the logic circuit 78 processes at least part of the data stored in the 3D-M array 77. In the three-dimensional processor chip, the chip area occupied by the memory array 77 is the array area 70, and the chip area outside the array area 70 is the non-array area 71 ( Figure 1A-1B ). The array region 70 includes a substrate circuit 0K and a 3D-M array 77 stacked on the substrate circuit 0K ( Figure 1B). The substrate circuit 0K is formed on the semiconductor substrate 0 and below the 3D-M array 77. It contains transistors 0t and substrate interconnects 0i. Transistors 0t are formed in the semiconductor substrate 0 and are electrically coupled to each other via substrate interconnects 0i. The substrate interconnects 0i contain two interconnect layers 0m1-0m2, each of which (e.g., 0m1) contains multiple interconnects (e.g., 0m) in the same physical plane. The 3D-M array 77 contains four address line layers 0a1-0a4, each of which (e.g., 0a1) contains multiple address lines (e.g., 1a) in the same physical plane. These address line layers 0a1-0a4 form two storage layers 16A and 16B. The storage layer 16A is stacked above the substrate circuit 0K, and the storage layer 16B is stacked above the storage layer 16A. The storage element (e.g., 7aa) is located at the intersection of two address lines (e.g., 1a, 2a). The memory layers 16A and 16B are electrically coupled to the substrate circuit OK through the contact channel holes 1av and 3av, respectively.

[0005] The non-array area 71 also contains part of the substrate circuit OK ( Figure 1B Since the non-array area 71 does not contain the 3D-M array 77, the number of back-end-of-line (BEOL) layers is much smaller than that of the array area 70. In this specification, the back-end-of-line layer is an independent conductive layer of the back-end process (excluding the channel hole). Figure 1B In the example, array region 70 contains six back-end wiring layers, including two interconnect layers 0m1-0m2 for substrate circuit 0i and four address line layers 0a1-0a4 for memory array 77. Non-array region 71, on the other hand, contains only two back-end wiring layers, including two interconnect layers 0m1-0m2 for substrate circuit 0i. In non-array region 71, space 72 on substrate circuit OK contains neither memory cells nor interconnects, effectively wasting this space.

[0006] The array area 70 includes a plurality of 3D-M arrays 77 and their associated local peripheral circuits 75 and logic circuits 78 ( Figure 1A ). Local peripheral circuits 75 and logic circuits 78 are formed in substrate 0, and are located near the projection of the 3D-M array 77 on substrate 0. Since the 3D-M array 77 is stacked on the local peripheral circuits 75 and logic circuits 78, they are not located in substrate 0 and are indicated here by dotted lines. On the other hand, the non-array area 71 contains the global peripheral circuits 73 of the 3D-M array 77, which are formed in substrate 0 and are located outside the projection of all 3D-M arrays 77 on substrate 0. The local peripheral circuits 75 and the global peripheral circuits 73 are collectively referred to as peripheral circuits 79. The peripheral circuits 73, 75, and 79 located in the same chip 80 as the 3D-M array 77 are called on-chip peripheral circuit components.

[0007] In a three-dimensional processor chip 80, the non-array area 71 occupies a significant portion of the chip area. Currently, the non-array area 71 occupies approximately 30% of the chip area; this proportion increases further with larger memory capacities. Consequently, the array efficiency of the integrated three-dimensional processor 80 is relatively low. In this specification, array efficiency is defined as the ratio of the total projected area of the 3D-M array 77 on substrate 0 to the total chip area.

[0008] The mainstream view of integrated circuits is that greater integration is better, meaning that integration reduces costs and improves performance. Traditional integrated circuits tend to favor monolithic integration, where all circuit components are integrated into a single chip. Monolithic integration works well for two-dimensional circuits, but it no longer works well for three-dimensional circuits—especially when three-dimensional circuits (such as three-dimensional memory) are mixed with two-dimensional circuits. In this specification, a two-dimensional circuit refers to a circuit whose active components (such as transistors and memory cells) are distributed on a two-dimensional plane (such as the front surface of a semiconductor substrate); a three-dimensional circuit refers to a circuit whose active components (such as transistors and memory cells) are distributed in a three-dimensional space (stacked perpendicular to the front surface of the semiconductor substrate).

[0009] When applied to the integration of 3D and 2D circuits, single-chip integration has multiple drawbacks. First, due to incompatible back-end processes, blind integration would require the complex processes used to manufacture the 3D-M array 77 to be used to manufacture the logic circuits 78 and peripheral circuits 79. Furthermore, the integrated 3D processor chip 80 has low array efficiency, which increases the overall cost of the 3D processor chip 80.

[0010] Secondly, because 3D-M array 77 has very high process requirements, the back-end process of 3D processor chip 80 needs to optimize 3D-M array 77, which inevitably sacrifices the performance of logic circuit 78 and peripheral circuit 79 to a certain extent. For the integrated 3D processor 80, logic circuit 78 and peripheral circuit 79 can only contain a few (e.g., two) interconnect layers 0m1-0m2 contained in substrate interconnect layer 0i, or use slower, high-temperature interconnect materials (materials that can withstand the high-temperature back-end process required to manufacture 3D-M array 77, such as tungsten). This will reduce the overall performance of 3D processor chip 80.

[0011] Finally, with single-chip integration, the chip area occupied by logic circuit 78 is limited by the projected area of 3D-M array 77 on the substrate, resulting in limited processing functionality. Furthermore, because logic circuit 78 is fixedly integrated with 3D-M array 77, three-dimensional processor 80 can only perform fixed functions. If 3D processor 80 were to implement additional functions, the entire 3D processor 80 (including its 3D-M array 77 and logic circuit 78) would need to be redesigned and manufactured, which would be time-consuming and costly. Summary of the Invention

[0012] The main purpose of the present invention is to provide a three-dimensional processor with lower overall cost.

[0013] Another object of the present invention is to provide a three-dimensional processor with better overall performance.

[0014] Another object of the present invention is to provide a three-dimensional processor with more powerful and flexible functions.

[0015] To achieve these and other objectives, the present invention adheres to a design principle that differs significantly from traditional processors: partitioning the computing system by dimension, rather than function, thereby de-integrating three-dimensional and two-dimensional circuits. Specifically, the three-dimensional and two-dimensional circuits are separated into separate chips whenever possible, allowing for independent optimization. Accordingly, the present invention provides a separated three-dimensional processor (100), characterized by comprising: a plurality of storage and computing units (abbreviated as storage and computing units) (100aa-100mn), each storage and computing unit (100ij) comprising at least one three-dimensional memory (3D-M) array (170) and a logic circuit (180); a first chip (100a) and a second chip (100b), wherein the first chip (100a) comprises the 3D-M array (170), and the second chip (100b) comprises at least a portion of the logic circuit (180) and at least one peripheral circuit component (190) of the 3D-M array (170); and the first chip (100a) and the second chip (100b) are electrically coupled via a plurality of inter-chip connections (160). In brief, the first chip is a memory chip comprising a plurality of functional layers; the second chip is a logic chip comprising only one functional layer.

[0016] A separate three-dimensional processor differs from an integrated three-dimensional processor in that, in an integrated three-dimensional processor, all peripheral circuit components of the 3D-M array are located on the same chip as the 3D-M array. In a separate three-dimensional processor, however, at least one peripheral circuit component of the 3D-M array is located on a second chip, not on the first chip. These peripheral circuit components located on the second chip are referred to as off-chip peripheral circuit components. During design, the separate three-dimensional processor employs a circuit partitioning strategy that ensures the second chip contains as many off-chip peripheral circuit components as possible. This partitioning significantly improves the array efficiency of the first chip. Note that, although the first chip contains the 3D-M array, because it lacks off-chip peripheral circuit components, it cannot function properly as a standalone memory chip. For example, its performance does not meet industry standards for similar memory chips.

[0017] In a separate 3D processor, since the first and second chips can be designed and manufactured separately, they can have distinct back-end architectures. Because the back-end architecture of the second chip can be independently optimized, its off-chip peripheral circuit components and logic circuits offer lower costs and superior performance than similar circuits in an integrated 3D processor. The following compares separate and integrated 3D processors.

[0018] First, because the first chip does not contain at least some peripheral circuits and logic circuits, its array efficiency is higher. Furthermore, as a two-dimensional circuit, the second chip 100b has far fewer back-end wiring layers than an integrated three-dimensional processor and can be manufactured using standard back-end processes. Since wafer cost is generally proportional to the number of back-end wiring layers, the wafer cost of the second chip is significantly lower than that of an integrated three-dimensional processor. Therefore, the total chip cost of a separate three-dimensional processor (including the first and second chips) is lower than that of an integrated three-dimensional processor (containing only one chip). Even taking into account additional bonding costs, the overall cost of a separate three-dimensional processor is lower than that of an integrated three-dimensional processor.

[0019] Secondly, because they can be individually optimized, the off-chip peripheral circuit components and logic circuits in the separated three-dimensional processor perform better than similar circuits in the integrated three-dimensional processor. In one embodiment, the number of interconnect layers in the second chip (containing the off-chip peripheral circuit components) (e.g., four or more) is greater than the number of interconnect layers (e.g., two) in the substrate circuitry (containing the on-chip peripheral circuit components) in the integrated three-dimensional processor (or the first chip). In another embodiment, the second chip uses high-performance interconnect materials (e.g., copper) rather than the high-temperature interconnect materials (e.g., tungsten) used in the integrated three-dimensional processor (or the first chip). As a result, the overall performance of the separated three-dimensional processor is superior to that of the integrated three-dimensional processor.

[0020] Finally, in an integrated 3D processor, since the logic circuitry is confined to a single chip (e.g., within the projected area of the 3D-M array on the substrate), it has limited area and functionality. In contrast, in a discrete 3D processor, since the logic circuitry can be formed on two chips (the first portion of the logic circuitry is located within the projected area of the 3D-M array on the substrate in the first chip, and the second portion of the logic circuitry is located on the second chip), the larger area affords the discrete 3D processor greater processing power. Furthermore, since the second chip is designed and manufactured separately, it offers greater design and production flexibility. By combining the same first chip with a second chip with different functionality, processing functions tailored to different application scenarios can be implemented. Furthermore, these different processing functions can be implemented within a shorter design cycle and budget. Therefore, discrete 3D processors offer greater functionality and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A is a circuit layout diagram of an integrated three-dimensional processor (prior art); Figure 1B is a cross-sectional view of the three-dimensional processor.

[0022] Figure 2A-2C This is an overall introduction to a separate three-dimensional processor: Figure 2A This is its circuit diagram; Figure 2B It is a circuit block diagram of a storage and calculation unit; Figure 2C A diagram of the circuit layout of two chips in a separated three-dimensional processor.

[0023] Figures 3A-3D is a cross-sectional view of four separate three-dimensional processors.

[0024] Figures 4A-4D These are cross-sectional views of four types of first chips.

[0025] Figure 5 is a cross-sectional view of a second chip.

[0026] Figure 6A is a circuit layout diagram of a first chip; Figure 6BA-Figure 6BB These are the circuit layout diagrams of the two second chips.

[0027] Figures 7A-7C This is the circuit block diagram of the three storage and computing units.

[0028] Figures 8A-8C This is a circuit layout diagram of the three storage computing units in the first and second chips.

[0029] Figure 9 It is a circuit block diagram of a storage and computing unit in a three-dimensional model processor.

[0030] Figure 10 It is a circuit block diagram of the storage and computing unit in a three-dimensional neural network processor.

[0031] Note that these figures are schematic diagrams only and are not drawn to scale. Some dimensions and structures may be exaggerated or reduced for clarity and convenience. In different embodiments, letter suffixes following a number represent different instances of the same type of structure; the same number prefix represents the same or similar structure.

[0032] In this specification, “ / ” represents the relationship of “and” or “or”. “Memory” refers to any semiconductor-based information storage device that can store information permanently or temporarily. “Memory array” is a collection of all memory cells that share at least one address line. “Circuit in substrate” means that the active elements of the circuit (such as transistors, memory cells) are located in the substrate, although the interconnections connecting the active elements in the circuit may be located above the substrate. “Circuit on substrate” means that the active elements of the circuit (such as transistors, memory cells) and their interconnections are all located above the substrate. “Electrical coupling” means any form of coupling that can transmit electrical signals from one element to another. “Pattern” can refer to either an abstract pattern or a physical manifestation of a pattern (i.e., data associated with the pattern), and this specification does not distinguish between them. DETAILED DESCRIPTION

[0033] Figure 2A-2C The present invention provides an overall introduction to a separation three-dimensional processor 100 . Figure 2A The following is a block diagram of its circuit. The isolated 3D processor 100 not only processes data but also stores it. More importantly, a large portion of the data it processes is stored locally and very close to the processor. The isolated 3D processor 100 includes a storage array consisting of mxn storage units 100aa-100mn. For example, storage unit 100ij has an input 110 and an output 120 ( Figure 2B Generally speaking, a three-dimensional processor 100 may contain tens of thousands of storage computing units 100aa-100mn, supporting large-scale parallel computing.

[0034] Figure 2B The circuit block diagram of the storage unit 100ij is shown. The storage unit 100ij includes a storage circuit 170 and a logic circuit 180, which are connected via a plurality of inter-chip connections 160 (see Figures 3A-3D ) are electrically coupled. The storage circuit 170 includes at least one 3D-M array. The 3D-M array stores data, and the logic circuit 180 processes part of the data. Since the 3D-M array 170 and the logic circuit 180 are not located in the same chip (see Figure 2C ), the 3D-M array 170 is represented by a dotted line.

[0035] Figure 2CThe figure shows a specific implementation of a split three-dimensional processor 100, which includes at least one first chip (also referred to as a memory chip) 100a and at least one second chip (also referred to as a logic chip) 100b. The first chip 100a includes three-dimensional circuitry, in this embodiment, a 3D-M array 170. In some embodiments, the first chip 100a may also include on-chip peripheral circuit components of the 3D-M array 170. The second chip 100b includes two-dimensional circuitry, in this embodiment, logic circuitry 180 and a peripheral circuit component 190 of the 3D-M array 170. Inter-chip connections 160 provide electrical coupling between the first chip 100a and the second chip 100b. Because the peripheral circuit component 190 is located on a different chip from the 3D-M array 170, it is referred to as an off-chip peripheral circuit component. Note that some logic circuitry may be located within the first chip 100a, for example, integrated beneath the 3D-M array 170. For simplicity, in this specification, unless otherwise specified, the logic circuit refers to the logic circuit 180 located on the second chip 100 b.

[0036] The circuit partitioning strategy employed by the separate 3D processor 100 is to ensure that the second chip 100b contains as many off-chip peripheral circuit components 190 as possible. Peripheral circuit components 190 are integral components of the memory chip; without them, a memory chip (such as the first chip 100a) cannot independently implement basic memory functions (e.g., its performance may not meet industry standards for similar memory chips). Typical peripheral circuit components 190 may include an address decoder, a read amplifier circuit, a write circuit, a read voltage generator circuit, a write voltage generator circuit, a data buffer, or portions thereof.

[0037] Because the read / write voltage is generally different from the external power supply voltage, a read / write voltage generation circuit is required to convert the external power supply voltage into the read / write voltage for the 3D-M array 170. A DC-DC converter is preferably used as the voltage generator. DC-DC converters include boosters and bucks. A booster's output voltage is higher than the input voltage, while a buck's output voltage is lower than the input voltage. Examples of boosters include charge pumps and boost converters. Examples of buck converters include low dropout regulators and buck converters.

[0038] Figures 3A-3D is a cross-sectional view of four separate 3D processors 100, which focuses on various implementations of the inter-chip connections 160. Figure 3AIn the embodiment, the first chip 100a and the second chip 100b are stacked, i.e., stacked perpendicular to the chip surfaces. The front surfaces (i.e., the surfaces containing circuitry) of the first chip 100a and the second chip 100b are both facing upward (in the +z direction), and the chips are connected 160 via bonding wires 160w.

[0039] exist Figure 3B In this embodiment, the first chip 100a and the second chip 100b are bonded face-to-face. Specifically, the first chip 100a faces up (in the +z direction), while the second chip 100b is flipped so that its face-down (in the -z direction). Micro-bumps 160x connect the first and second chips 100a and 100b to each other, creating an inter-chip connection 160. In this embodiment, the first and second chips 100a and 100b have the same chip area and are aligned on all sides. For example, the left edge of the first chip 100a is aligned with the left edge of the second chip 100b, and the right edge of the first chip 100a is aligned with the right edge of the second chip 100b. This is because the separate three-dimensional processor 100 is formed by dicing from bonded wafers, where a first wafer containing the first chip 100a and a second wafer containing the second chip 100b are aligned and bonded to each other.

[0040] Figure 3C The embodiment contains two memory chips 100a1, 100a2 and a logic chip 100b. To avoid confusion, in the figure, the first chip is referred to as the memory chip 100a1, 100a2, and the second chip is referred to as the logic chip 100b. The memory chips 100a1, 100a2 each contain multiple 3D-M arrays; they are stacked on each other and electrically coupled through through-silicon vias (TSVs) 160y. The stacked memory chips 100a1, 100a2 and the logic chip 100b are electrically coupled through micro solder joints 160x. TSVs 160y and micro solder joints 160x are inter-chip connections 160. In this embodiment, the logic circuit 180 in the logic chip 100b processes the data stored in the two memory chips 100a1, 100a2. Figure 3B Similar to the embodiment in FIG. 1 , the first chip 100 a and the second chip 100 b in this embodiment have the same chip area; all their edges are aligned.

[0041] Figure 3DHybrid bonding is employed. Specifically, a first insulating dielectric 168a is formed on the front surface of the first chip 100a, and then a plurality of first via holes 160za are formed in the first insulating dielectric 168a. Furthermore, a second insulating dielectric 168b is also formed on the front surface of the second chip 100b, and then a plurality of second via holes 160zb are formed in the second insulating dielectric 168b. After flipping the second chip 100b, the first via holes 160za and the second via holes 160zb are aligned, and the first and second chips 100a and 100b are bonded together. Accordingly, the first and second chips 100a and 100b achieve an inter-chip connection 160 through the electrically contacted first and second via holes 160za and 160zb. Because the via holes 160za and 160zb are formed using standard chip manufacturing processes, they can be very small and numerous. Therefore, a high-bandwidth inter-chip connection 160 can be formed between the first chip 100a and the second chip 100b. In this embodiment, the vias 160za and 160zb are collectively referred to as vertical interconnect access (VIA). Figure 3B Similar to the embodiment in FIG. 1 , the first chip 100a and the second chip 100b in this embodiment have the same chip area, and all their edges are aligned. In the above embodiment, the distance between the storage circuit 170 and the logic circuit 180 is relatively close (compared to the traditional von Neumann architecture). Figure 3B-3D Examples - especially Figure 3C-3D In the embodiment, the number of inter-chip connections (TSV or VIA) 160 is huge, which can achieve ultra-wide bandwidth between the memory circuit 170 and the logic circuit 180. Coupled with massively parallel processing ( Figure 2A ), the separated three-dimensional processor 100 has excellent performance.

[0042] Figures 4A-4D 1 is a cross-sectional view of four first chips 100 a , wherein the 3D-M array 170 adopts monolithic integration, that is, its memory cells are stacked on each other in a vertical direction without any semiconductor substrate between the memory cells.

[0043] According to its physical structure, 3D-M is divided into three-dimensional horizontal memory (3D-M H ) and three-dimensional vertical memory (3D-M V ). 3D-M H All address lines in 3D-M are horizontal, and its memory cells form multiple horizontal memory layers, which are stacked vertically on the substrate circuit.H A typical example is 3D-XPoint. V At least one set of address lines is vertical, and its memory cells form multiple vertical memory strings, which are arranged side by side on the substrate circuit. V A typical example is 3D-NAND. H Faster speed, and 3D-M V Greater storage density.

[0044] Based on the length of time information can be stored, 3D-M is divided into 3D-RAM (3D random access memory) and 3D-ROM (3D read-only memory). 3D-RAM can temporarily store information and is primarily used for caching; 3D-ROM can store information long-term. Many 3D-ROMs can be rewritten, forming a type of non-volatile memory (NVM).

[0045] Based on its programmability, 3D-M is divided into three-dimensional writable memory (3D-W) and three-dimensional printed memory (3D-P). The information stored in 3D-W is recorded through electrical programming. Based on the number of times it can be programmed, 3D-W is further divided into three-dimensional one-time programmable memory (3D-OTP) and three-dimensional multiple-time programmable memory (3D-MTP, including repeated programming). Common 3D-MTPs are 3D-XPoint and 3D-NAND. Other 3D-MTPs include memristors, resistive random access memory (RRAM), phase change memory (PCM), programmable metallization cells (PMC), and conductive bridging random access memory (CBRAM).

[0046] The information stored in 3D-P is recorded by printing during the factory production process (imprinting method). This information is permanently fixed and cannot be changed after leaving the factory. Imprinting methods can include photolithography, nanoimprinting, electron beam lithography (e-beam lithography), DUV scanning lithography, and laser programming. Common 3D-P technologies include three-dimensional mask-programmable read-only memory (3D-MPROM), which uses photolithography to program data through a mask. Because it does not require electrical programming, 3D-P memory cells can be biased at a higher voltage during read operations. Therefore, 3D-P read speeds are faster than 3D-W.

[0047] Figure 4A-4B The first chip 100a in the embodiment includes a substrate circuit 0Ka and a 3D-M stacked on the substrate circuit 0Ka. H Array 170. Substrate circuit 0Ka includes transistors 0t and interconnects 0ia. Transistors 0t are formed in a first semiconductor substrate 0a and are electrically coupled to each other via substrate interconnects 0ia. Substrate interconnects 0ia include two interconnect layers 0m1a-0m2a, each of which (e.g., 0m1a) contains multiple interconnects (e.g., 0m) in the same physical plane. 3D-M H The array 170 contains four address line layers 0a1a-0a4a, and each address line layer (such as 0a1a) contains multiple address lines (such as 1a) in the same physical plane. These address line layers 0a1a-0a4a form two storage layers 16A and 16B. Among them, the storage layer 16A is stacked on the substrate circuit 0Ka, and the storage layer 16B is stacked on the storage layer 16A. The storage element (such as 7aa) is located at the intersection of the two address lines (such as 1a and 2a). The storage layers 16A and 16B are connected to the substrate circuit 0Ka through contact channel holes 1av and 3av respectively to achieve intra-chip connection 150. The contact channel holes 1av and 3av contain multiple channel holes, each channel hole penetrates at least one insulating layer and is electrically coupled to the channel holes above and below it. Figure 4A-4B In the substrate circuit 0Ka, there are 3D-M H At least part of the peripheral circuits of the array 170. In some embodiments, the substrate circuit OKa may include part of the logic circuit.

[0048] Figure 4A 3D-M HArray 170 is a 3D-W. Its memory cell 7aa contains a programming film 5 and a diode film 6. The programming film 5 can be an antifuse film (programmable once, used in 3D-OTP) or a resistive RAM (RRAM) film (reprogrammable, used in 3D-MTP). The diode film 6 has the following general characteristics: its resistance is low at a read voltage; its resistance is high when the applied voltage is lower than the read voltage or in the opposite direction of the read voltage. The diode film can be a PiN diode or a metal oxide (such as TiO2) diode.

[0049] Figure 4B 3D-M H Array 170 is a 3D-P. It contains at least two types of memory cells: high-resistance memory cells 7ab and low-resistance memory cells 7ac. Low-resistance memory cells 7ac contain a diode film 6, similar to the diode film 6 in 3D-W. High-resistance memory cells 7ab also contain a high-resistance film 9, which is an insulating film (e.g., silicon oxide / silicon nitride). During the production process, high-resistance film 9 is physically removed from low-resistance memory cells 7ac.

[0050] Figure 4C-4D The first chip 100a in the embodiment includes a substrate circuit 0Ka and a 3D-M stacked on the substrate circuit 0Ka. V Array 170. Substrate circuit 0Ka and Figure 4A-4B In some embodiments, 3D-M V There is no substrate circuit 0Ka below the array 170. 3D-M V Array 170 includes multiple vertically stacked horizontal address line layers 0a1a-0a8a, each horizontal address line layer (such as 0a5a) contains multiple horizontal address lines (such as 15) in the same physical plane. V Array 170 also includes a set of vertical address lines that are perpendicular to substrate 0a (ie, in the +z direction). 3D-M V The storage density of the semiconductor memory is the highest. Figure 4C-4D 3D-M V The on-chip connections 150 for electrically coupling the array 170 to the substrate circuit 0Ka are not shown, but are well known to those skilled in the art.

[0051] Figure 4C 3D-M VThe array 170 uses transistors or transistor-like devices as storage elements. It contains multiple vertical and side-by-side storage strings 16X and 16Y. Each storage string (such as 16Y) contains multiple vertically stacked storage elements (such as 18ay-18hy). Each storage element (such as 18fy) contains a vertical transistor, which contains a gate (for horizontal address lines) 15, a storage film 17 and a vertical channel (for vertical address lines) 19. The storage film 17 can contain composite films such as silicon oxide-silicon nitride-silicon oxide, silicon oxide-polysilicon-silicon oxide, etc. The 3D-M V The array 170 is a 3D-NAND, and its manufacturing process is well known to those skilled in the art.

[0052] Figure 4D 3D-M V The array 170 uses diodes or diode-like devices as memory cells. It contains multiple vertical memory strings 16U-16W arranged side by side. Each memory string 16U contains multiple vertically stacked memory cells 18au-18hu. V Array 170 contains multiple vertically stacked horizontal address lines (word lines) 15. After etching multiple memory wells 11 that penetrate these horizontal address lines 15, the sidewalls of the memory wells 11 are covered with a programming film 13 and filled with a conductive material to form vertical address lines 19 (bit lines). The conductive material can be a metal or a doped semiconductor. Memory cells 18au-18hu are formed at the intersections of word lines 15 and bit lines 19. The programming film 13 can be one-time programming (OTP, such as an antifuse film) or multi-time programming (MTP, such as a RRAM film).

[0053] To reduce mutual interference between memory cells, a diode is preferably formed between word line 15 and bit line 19. In one embodiment, the programming film 13 itself can have certain diode electrical characteristics. In another embodiment, a separate diode film (not shown) can be deposited on the sidewalls of the memory well 11. In a third embodiment, a built-in diode (such as a PN diode or Schottky diode) can be naturally formed between word line 15 and bit line 19. For details on the built-in diode, please refer to Chinese patent application 201811117502.7 (filing date: September 20, 2018).

[0054] exist Figures 4A-4D In the embodiment, the number of back-end connection layers (N A ) is the total number of back-end connection layers in the chip area where the 3D-M array 170 is located (calculated from the surface of the substrate 0a, excluding the channel hole layer). For example, Figure 4A-4B Chinese N A 6 (0m1a-0m2a, 0a1a-0a4a), Figure 4CChinese N A is 10 (0m1a-0m2a, 0a1a-0a8a), Figure 4D Chinese N A is 11 (0m1a-0m2a, 0a1a-0a8a, BL1). The thickness of the back-end wiring layer of the 3D-M array 170 (T A ) is the height from the substrate surface 0a to the highest interconnect line in the chip area where the 3D-M array 170 is located.

[0055] Figure 5 The second chip 100b in the embodiment is a conventional two-dimensional circuit 0Kb, which contains only a standard back-end structure and is used to implement the logic circuit 180 and the off-chip peripheral circuit component 190. The second chip 100b contains transistors 0t and interconnects 0ib. The transistors 0t are formed in the second semiconductor substrate 0b and are electrically coupled to each other via the interconnects 0ib. In this embodiment, the interconnects 0ib contain four interconnect layers 0m1b-0m4b, each of which (e.g., 0m1b) contains multiple interconnects (e.g., 0m) in the same physical plane. Figures 4A-4D Similarly, the number of back-end connection layers of the logic circuit 180 (N L ) is the total number of back-end connection layers in the chip area where the logic circuit 180 is located (calculated from the surface of the substrate 0b, excluding the channel hole layer); the height of the back-end connection layer of the logic circuit 180 (T L ) is the height from the surface of the substrate 0b to the highest interconnection line in the chip region where the logic circuit 180 is located. Similarly, the number of back-end connection layers of the peripheral circuit component 190 (N P ) is the total number of back-end connection layers in the chip area where the off-chip peripheral circuit component 190 is located (calculated from the surface of the substrate 0b, excluding the channel hole layer); the height of the back-end connection layer of the off-chip peripheral circuit component 190 (T P ) is the height from the surface of the substrate 0b to the highest interconnect line in the chip region where the off-chip peripheral circuit component 190 is located. Note that although the logic circuit 180 and the off-chip peripheral circuit component 190 are both located in the second chip 100b, the number of their back-end connection layers (N L 、N P ) are not necessarily the same; the thickness of the back-end wiring layer (T L 、T P ) are not necessarily the same.

[0056] In order to determine whether it is necessary to perform disintegration, the first chip 100a ( Figures 4A-4D ) and the second chip 100b ( Figure 5 ) of the back-end structure. The number of back-end wiring layers in the first chip 100a (N a ) is greater than the number of back-end connection layers in the second chip 100b (N bFor example, Figure 4A-4B The first chip 100a has six back-end connection layers (0m1a-0m2a, 0a1a-0a4a), Figure 4C-4D The first chip 100a has ten back-end connection layers (0m1a-0m2a, 0a1a-0a8a), the number of which is greater than Figure 5 Even if we only count the number of address line layers in the first chip 100a, it is greater than or equal to the number of back-end connection layers in the second chip 100b. V For array 170, the number of address line layers in the first chip 100a (approximately equal to the number of all memory cells in the memory string, greater than 100 layers) is much greater than the number of back-end connection layers in the second chip 100b (eg, four layers), at least twice as much.

[0057] In addition to comparing the number of back-end connection layers (N) between the first chip 100a and the second chip 100b, the need for disintegration can also be determined by comparing the number of back-end connection layers (N) or thickness (T) of the three core components (3D-M array 170, logic circuit 180, and off-chip peripheral circuit assembly 190) within the three-dimensional processor 100. There are two situations: A) If the difference in the number of back-end connection layers between the 3D-M array 170 and the off-chip peripheral circuit assembly 190 is much greater than the difference in the number of back-end connection layers between the logic circuit 180 and the off-chip peripheral circuit assembly 190 (i.e., |N|). A -N P |>>|N L -N P |, preferably greater than 3 times), then it makes sense to disintegrate (split) the 3D-M array 170 and the off-chip peripheral circuit component 190 into two chips. B) If the difference in back-end wiring thickness between the 3D-M array 170 and the off-chip peripheral circuit component 190 is greater than the difference in back-end wiring thickness between the logic circuit 180 and the off-chip peripheral circuit component 190 (i.e., |T A -T P |>|T L -T P |), then disintegrating (splitting) the 3D-M array 170 and the off-chip peripheral circuit components 190 into two separate chips also has positive implications. Clearly, even if the memory array 170 is not 3D-M, as long as it meets conditions A) or B) above, it is suitable for disintegration. By comparison, the back-end structure of conventional DRAM memory (whose memory cell capacitors have a three-dimensional structure) differs significantly from that of the logic and peripheral circuits, making it also suitable for disintegration.

[0058] In the separate 3D processor 100, because the first chip 100a and the second chip 100b can be designed and manufactured separately, they can have distinct back-end structures. Because the back-end structure of the second chip 100b can be independently optimized, its off-chip peripheral circuit components 190 and logic circuits 180 have lower costs and higher performance than similar circuits in the integrated 3D processor 80.

[0059] First, because the first chip 100a does not contain off-chip peripheral circuit components 190 and logic circuits 180, its array efficiency is relatively high. Furthermore, as a two-dimensional circuit, the second chip 100b has far fewer back-end wiring layers than the integrated three-dimensional processor 80 and can be manufactured using conventional processes. Since wafer cost is generally proportional to the number of back-end wiring layers, the wafer cost of the second chip 100b is significantly lower than that of the integrated three-dimensional processor 80. Therefore, the total chip cost of the separate three-dimensional processor 100 (comprising the first and second chips 100a and 100b) is lower than that of the integrated three-dimensional processor 80 (containing only one chip). Even taking into account the additional bonding costs, the overall cost of the separate three-dimensional processor 100 is still lower.

[0060] Secondly, because they can be optimized individually, the performance of the off-chip peripheral circuit components 190 and logic circuits 180 in the separated three-dimensional processor 100 is better than that of the same circuits in the integrated three-dimensional processor 80. In one embodiment, the number of interconnect layers in the interconnect lines 0ib of the second chip 100b is greater than the number of interconnect layers in the substrate interconnect lines 0ia (including on-chip peripheral circuits) of the first chip 100a. For example, Figure 5 The second chip 100b has four interconnection layers (0m1b-0m4b), which is greater than Figures 4A-4D The first chip 100a (which may contain on-chip peripheral circuit components) has two interconnection line layers (0m1a-0m2a). Therefore, the circuit layout of the second chip 100b is easier than that of the first chip 100a. In another embodiment, the second chip 100b (containing logic circuit 180 and off-chip peripheral circuit 190) can use high-speed interconnection line materials (such as copper), while the first chip 100a (containing on-chip peripheral circuit) can only use high-temperature interconnection line materials (such as tungsten). Because the resistivity of at least part of the back-end connection layer in the on-chip peripheral circuit component is greater than the resistivity of the same back-end connection layer in the off-chip peripheral circuit component (190), the speed of the on-chip peripheral circuit component is slower.

[0061] Finally, in the integrated three-dimensional processor 80, since the logic circuit 78 is confined to one chip 80 (e.g. Figure 1AIn the 3D-M array 77, the area is limited and the function is also limited. In contrast, in the separated 3D processor 100, since the logic circuit 180 can be formed in two chips 100a and 100b (for example, the first part of the logic circuit is located in Figure 6A Below the 3D-M array 170ij of the first chip 100a, similar Figure 1A The logic circuit 78 is located below the 3D-M array 77; the second part of the logic circuit is located Figure 6BA The larger area of the second chip 100b gives the 3D processor 100 greater processing power. Furthermore, since the second chip is designed and manufactured separately, it offers greater flexibility in design and production. By combining the identical first chip 100a with the second chip 100b, which has different functions, processing functions suitable for different application scenarios can be implemented. Furthermore, these different processing functions can be implemented within a shorter design cycle and with a smaller design budget. As a result, the separate 3D processor 100 is more powerful and flexible.

[0062] Figures 6A-6BB The circuit layout diagrams of the first and second chips 100a and 100b in the two separate three-dimensional processors 100 are shown in FIG. Figure 2C More details are shown. This embodiment corresponds to Figure 7A and Figure 8A Those skilled in the art can easily generalize it to Figure 7B and Figure 8B ,as well as Figure 7C and Figure 8C In the embodiment of .

[0063] Figure 6A A first chip 100a is shown, which contains a plurality of 3D-M arrays 170aa-170mn. Figure 6BA The second chip 100b is shown, which includes a plurality of logic circuits 180aa-180mn and a global peripheral circuit component 190G. The global peripheral circuit component 190G is located outside the projection of all 3D-M arrays 170aa-170mn on the second chip 100b. Figure 6A and Figure 6BA The three-dimensional processor 100 adopts the "full alignment" technology, that is, the circuit layout on the two chips 100a and 100b meets the following requirements: when the two chips 100a and 100b are stacked, each logic circuit (such as 180ij) is vertically aligned and electrically coupled with at least one 3D-M array (such as 170ij) (see Figures 8A-8C Since each logic circuit (such as 180ij) can have multiple 3D-M arrays (such as 170ijA-170ijD) aligned with (see Figure 8B-Figure 8C), the period of the logic circuit (such as 180ij) on the second chip 100b is an integer multiple of the period of the 3D-M array (such as 170ij) on the first chip 100a.

[0064] Figure 6BB Another second chip 100b is shown, which also contains a plurality of local peripheral circuit components 190aa-190mn. Obviously, Figure 6A and Figure 6BB The 3D processor 100 can also use a "full alignment" technique. In which each local peripheral circuit component 190aa-190mn is vertically aligned and electrically coupled to a 3D-M array (such as 170ij). In addition to the local peripheral circuit components 190aa-190mn, Figure 6BB The embodiment in FIG. 1 may also include a global peripheral circuit component 190G. In this specification, all local peripheral circuit components 190aa-190mn and the global peripheral circuit component 190G are collectively referred to as off-chip peripheral circuit components 190.

[0065] exist Figures 6A-6BB In this embodiment, the local peripheral circuit component (e.g., 190ij) typically includes a portion of an address decoder, a portion of a read amplifier circuit, or a portion of a write circuit, and performs at least a portion of read and write operations on the memory cells in each 3D-M array (e.g., 170ij). The global peripheral circuit component 190G typically includes a read voltage generation circuit, a write voltage generation circuit, or a data buffer, and generates read / write voltages. Of course, the division between these local and global peripheral circuit components is not absolute. For example, the local peripheral circuit component may include at least a portion of a read / write voltage generation circuit.

[0066] Figures 7A-8C Represents three types of storage computing units 100ij. Figures 7A-7C The circuit diagram is as follows (for simplicity, the peripheral circuit components 190ij are Figures 7A-7C not shown); Figures 8A-8C In these embodiments, one logic circuit 180ij serves different numbers of 3D-M arrays 170ij.

[0067] Figure 7A The logic circuit 180ij in serves a 3D-M array 170ij: it processes the data stored in the 3D-M array 170ij. Figure 7B The logic circuit 180ij in serves the four storage arrays 170ijA-170ijD: it processes the data stored in the 3D-M arrays 170ijA-170jiD. Figure 7CThe logic circuit 180ij in the eight storage arrays 170ijA-170ijD and 170ijW-170ijZ serves: it processes the data stored in the 3D-M arrays 170ijA-170ijD and 170ijW-170ijZ. Figures 8A-8C It can be seen that the logic circuit 180ij serving more 3D-M arrays 170ij generally occupies a larger chip area and has a stronger function. Figures 7A-7C In the example, since the 3D-M array 170ij and the logic circuit 180ij are located in different chips (see Figure 2C and Figures 6A-6BB ), the 3D-M array 170ij is represented by a dotted line.

[0068] Figures 8A-8C The circuit layout of the second chip 100 b and the projection (indicated by a dotted line) of the 3D-M array 170 (located in the first chip 100 a ) on the second chip 100 b are shown. Figure 8A The embodiment corresponds to Figure 7A In this embodiment, the logic circuit 180ij and the local peripheral circuit component 190ij in the storage computing unit 100ij are located in the second semiconductor substrate 0b of the second chip 100b. The logic circuit 180ij and the off-chip peripheral circuit component 190ij are at least partially covered by the 3D-M array 170ij.

[0069] In this embodiment, the period of the logic circuit 180ij is equal to the period of the 3D-M array 170ij and the area cannot exceed the projected area of the 3D-M array 170ij on the second chip 100b, so the function is limited. This embodiment is more suitable for implementing relatively simple data processing. Figure 8B-Figure 8C Two complex logic circuits 180 are disclosed.

[0070] Figure 8B The embodiment corresponds to Figure 7B In this embodiment, the logic circuit 180ij and off-chip peripheral circuit components 190ij of the storage computing unit 100ij are located in the second chip 100b and are at least partially covered by the four 3D-M arrays 170ijA-170ijD. Under the four 3D-M arrays 170ijA-170ijD, the logic circuit 180ji can be freely arranged. Figure 8B The cycle of the logic circuit 180ij is Figure 8A The 3D-M array 170ij has twice the period and four times the area, so it can implement more complex processing functions.

[0071] Figure 8C The embodiment corresponds to Figure 7CIn this embodiment, the logic circuit 180ij and the off-chip peripheral circuit component 190ij in the storage computing unit 100ij are located in the second chip 100b. These eight 3D-M arrays 170ijA-170ijD, 170ijW-170ijZ are divided into two groups 170ijSA and 170ijSB. Each group (such as 170ijSA) includes four 3D-M arrays (such as 170ijA-170ijD). Below the four 3D-M arrays 170ijA-170ijD of the first group 170SA, the first logic circuit component 180ijA can be freely arranged. Similarly, below the four 3D-M arrays 170ijW-170ijZ of the second group 170ijSB, the second logic circuit component 180ijB can be freely arranged. The first logic circuit component 180ijA and the second logic circuit component 180ijB constitute the logic circuit 180ij. In this embodiment, gaps (such as G) are left between adjacent off-chip peripheral circuit components to form wiring channels 182, 184, and 186 for electrical coupling between different logic circuit components 180ijA and 180ijB, or between different logic circuits. Figure 8C The cycle of the logic circuit 180ij is Figure 8A The 3D-M array 170ij has four times the period (x direction) and eight times the area, so it can achieve more complex processing functions.

[0072] exist Figures 8A-8C In the embodiment, each storage computing unit (100ij) occupies a first area on the first chip (100a) and a second area on the second chip (100b), and the first and second areas substantially overlap. Specifically, all 3D-M arrays (170) in each storage computing unit (100ij) occupy the first area, and all logic circuits (180) and all off-chip peripheral circuit components (190) occupy the second area. A projection of the first area on the second chip (100b) is substantially the same as the second area.

[0073] The "discrete three-dimensional processor (3D-P)" proposed in this invention and the "discrete three-dimensional memory (3D-M)" (CN103765516B, etc.) in the prior art are both based on the concept of "disintegration." Discrete 3D-P is a further development of discrete 3D-M. First, discrete 3D-M and discrete 3D-P belong to different fields (memory and processor). Applying disintegration to processors allows for the reconfiguration of computing systems, a technical effect that was unforeseen and unachievable with discrete 3D-M. Second, discrete 3D-P solves a new problem introduced by discrete 3D-M. It's worth reviewing the evolution of three-dimensional integration technology (from "integrated 3D-M" to "discrete 3D-M" and then to "discrete 3D-P"): Initially, the array efficiency of integrated 3D-M chips was low, at approximately 70% (the 3D-M array and peripheral circuitry occupied approximately 70% and 30% of the area, respectively). To improve the array efficiency of the 3D-M chip, the separation 3D-M removes the peripheral circuit from the 3D-M chip, forming two chips (3D-M array chip + peripheral circuit chip). This measure increases the array efficiency of the 3D-M array chip to ~90%. However, the peripheral circuit only occupies ~20% of the area of the second chip (see Figures 8A-8C As a result, a large portion of the peripheral circuit chip area is left unused and wasted, a new problem that prior art techniques fail to address. By forming logic (processing) circuitry in these vacant areas, separate 3D-P not only better utilizes the peripheral circuit chip area but also delivers significant performance improvements by embedding processing power within 3D-M. More importantly, because the logic circuits are manufactured simultaneously with the peripheral circuits, these advantages come at no additional cost.

[0074] The separated three-dimensional processor 100 can be applied to fields such as mathematical calculation, computer simulation, programmable computing arrays, pattern processing, and neural network processing. For specific examples, please refer to the parent application of this case (CN111290994B). Figure 9-10 Only its application in pattern processing and neural network processing is introduced.

[0075] When used for pattern processing, the separate 3D processor 100 can be used as a 3D pattern processor. Figure 9 The storage unit 100ij includes a mode storage circuit 170 and a mode processing circuit 180PPC (i.e., the logic circuit 180 is the mode processing circuit 180PPC), which are electrically coupled via an inter-chip connection 160 ( Figures 3A-3D The pattern storage circuit 170 includes a 3D-M array 170, which stores at least part of the pattern; the pattern processing circuit 180PPC processes the pattern.

[0076] The separated three-dimensional pattern processor 100 can be implemented in two ways - a processor-like method and a memory-like method. The processor-like three-dimensional pattern processor 100 is a three-dimensional processor with its own retrieval pattern library, which can use its locally stored retrieval pattern to perform pattern processing on the target pattern from the input 110. Specifically, the retrieval pattern library (such as a virus library, a keyword library, an acoustic / language model library, an image model library, etc.) is stored in the 3D-M array 170; the input data 110 includes the target pattern (such as a network data packet, a computer file, big data, voice data, image data, etc.); the pattern processing circuit 180PPC performs pattern processing on the target pattern according to the retrieval pattern. Due to the large number of storage and computing units 100ij (tens of thousands, Figure 9 ) supports massively parallel processing, and the chip-to-chip connections 160 have large bandwidth ( Figure 3B-3D ), the three-dimensional processor 100 has a fast retrieval speed and high efficiency.

[0077] The memory-like three-dimensional pattern processor 100 is a three-dimensional memory with built-in pattern processing capabilities. Its primary function is to store a target pattern library, and its secondary function is to retrieve the stored target patterns using a retrieval pattern from input 110. Specifically, the target pattern library (such as computer files on a hard drive, a large data database, a voice archive, or an image archive) is stored and distributed in the 3D-M array 170; the input data 110 is a retrieval pattern (such as a virus identifier, a keyword, an acoustic / language model, an image model, etc.); and the pattern processing circuit 180PPC performs pattern processing on the target pattern based on the retrieval pattern. Due to the large number of storage and computing units 100ij (tens of thousands, Figure 2A ) supports massively parallel processing, and the chip-to-chip connections 160 have large bandwidth ( Figure 3B-3D ), the pattern processing speed of the three-dimensional memory 100 is fast and efficient.

[0078] Like flash memory, multiple three-dimensional memories 100 with built-in pattern processing capabilities can be packaged into memory cards (such as SD cards and TF cards) or solid-state drives (SSDs) to store target pattern libraries containing massive amounts of data. Crucially, they also include built-in pattern processing (e.g., retrieval) capabilities. Because each storage and computing unit 100ij includes its own pattern processing circuit 180PPC, it only needs to retrieve target patterns stored in the local 3D-M array 170 (located within the same storage and computing unit 100ij). Therefore, regardless of the capacity of the memory card or SSD, the retrieval time is close to that required to retrieve a single 3D-M array 170. In other words, the database retrieval time is independent of the database capacity and is typically in the order of seconds.

[0079] In contrast, in a traditional von Neumann architecture, the processor (CPU) and memory (hard disk) are physically separated. Database retrieval first requires reading the database from the hard disk. Due to the limited bandwidth of the system bus between the CPU and the hard disk, database retrieval time is limited by the database readout time. Therefore, database retrieval time is proportional to the size of the database. Generally speaking, depending on the size of the database, retrieval time can range from minutes to hours, or even longer. In contrast, the three-dimensional memory 100, with its built-in pattern processing capabilities, offers significant advantages in database retrieval.

[0080] When the 3D memory 100, which has built-in pattern processing capabilities, performs pattern processing on a large database (i.e., a target pattern library), the pattern processing circuit 180PPC only needs to perform a portion of the pattern processing. For example, the pattern processing circuit 180PPC only needs to perform simple preliminary pattern processing (such as string matching and code matching) on the database. The remaining data (i.e., the target pattern) after this preliminary pattern processing is then sent via output 120 to a more powerful external processor (such as a CPU or GPU) for final pattern processing. Because most of the data in the database is filtered out by the simple pattern processing, the data output from the 3D memory 100 only represents a small portion of the entire database, significantly reducing bandwidth pressure on output 120.

[0081] The separate 3D processor 100 can also be used as a 3D neural network processor. Figure 10 The storage unit 100ij includes a neural storage circuit 170 and a neural computing circuit 180NPC (the logic circuit 180 is the neural computing circuit 180NPC), which are electrically coupled via an inter-chip connection 160 ( Figures 3A-3D The neural storage circuit 170 includes a 3D-M array that stores at least part of the synaptic weights; the neural computing circuit 180NPC performs neural computing using the synaptic weights.

[0082] It should be understood that the present invention may be modified in form and detail without departing from the spirit and scope of the present invention, and this does not prevent it from applying the spirit of the present invention. For example, the processor in the present invention may be a central processing unit (CPU), a controller or microcontroller, a digital signal processor (DSP), a graphics processing unit (GPU), a network security processor, an encryption / decryption processor, an encoding / decoding processor, a neural network processor, an artificial intelligence (AI) processor, etc. Furthermore, the 3D-M array 170 in this specification can be extended to any semiconductor memory array 170, as long as the back-end structure of the memory array 170 (first chip 100a) is significantly different from the back-end structure of the logic circuit 180 and the off-chip peripheral circuit component 190 (second chip 100b) (e.g., a different number of back-end wiring layers; different back-end wiring layer thicknesses; or, 170 includes a three-dimensional structure while 180 and 190 only include a standard back-end structure). Furthermore, the logic circuit 180 in this specification can also be extended to any non-memory circuit 180, as long as the non-memory circuit 180 is not a peripheral circuit of the memory array 170. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

1. A separate three-dimensional processor (100), characterized in that contain: A plurality of storage and computing units (100aa-100mn), each storage and computing unit (100ij) comprising at least one storage array (170) and a non-storage circuit (180), wherein the non-storage circuit (180) is electrically coupled to the storage array (170) but is not a peripheral circuit of the storage array (170); A first chip (100a), wherein the first chip (100a) contains a storage array (170) in the plurality of storage and computing units (100aa-100mn) and on-chip peripheral circuit components thereof; A second chip (100b), the second chip (100b) containing the non-storage circuit (180) in the plurality of storage and computing units (100aa-100mn) and an off-chip peripheral circuit component (190) of the storage array (170); a plurality of inter-chip connections (160) electrically coupling the first chip (100a) and the second chip (100b); The number of back-end connection layers of the storage array (170) is greater than the number of back-end connection layers of the non-storage circuit (180); the number of back-end connection layers of the storage array (170) is greater than the number of back-end connection layers of the off-chip peripheral circuit component (190); and the resistivity of at least part of the back-end connection layers of the on-chip peripheral circuit component is greater than the resistivity of the same back-end connection layers of the off-chip peripheral circuit component (190).

2. A separate three-dimensional processor (100), characterized in that contain: A plurality of storage computing units (100aa-100mn), each storage computing unit (100ij) comprising a non-storage circuit (180), at least one storage array (170) and its on-chip peripheral circuit components and off-chip peripheral circuit components (190); the on-chip peripheral circuit components and the off-chip peripheral circuit components (190) are peripheral circuits of the storage array (170), and the non-storage circuit (180) is not a peripheral circuit of the storage array (170); A first chip (100a), wherein the first chip (100a) contains a storage array (170) and on-chip peripheral circuit components in the plurality of storage and computing units (100aa-100mn); A second chip (100b), the second chip (100b) comprising a non-storage circuit (180) and an off-chip peripheral circuit component (190) in the plurality of storage and computing units (100aa-100mn); a plurality of inter-chip connections (160) electrically coupling the first chip (100a) and the second chip (100b); The number of back-end connection layers of the storage array (170) is greater than the number of back-end connection layers of the non-storage circuit (180); the number of back-end connection layers of the storage array (170) is greater than the number of back-end connection layers of the off-chip peripheral circuit component (190); and the resistivity of at least part of the back-end connection layers of the on-chip peripheral circuit component is greater than the resistivity of the same back-end connection layers of the off-chip peripheral circuit component (190).

3. The separate three-dimensional processor (100) according to claim 1 or 2, further characterized by: The first chip (100a) and the second chip (100b) are stacked vertically.

4. The separate three-dimensional processor (100) according to claim 3, further characterized by: The storage array (170) is a random access memory (RAM) array or a non-volatile memory (NVM) array.

5. The separate three-dimensional processor (100) according to claim 3, further characterized by: The non-storage circuit (180) is a logic circuit or a processing circuit.

6. The separate three-dimensional processor (100) according to claim 3, further characterized by: The first chip (100a) and the second chip (100b) have the same chip area.

7. The separate three-dimensional processor (100) according to claim 3, further characterized by: All edges of the first chip (100a) and the second chip (100b) are aligned.

8. The separate three-dimensional processor (100) according to claim 3, further characterized by: Each storage computing unit (100ij) occupies a first area on the first chip (100a) and a second area on the second chip (100b), and the first and second areas substantially overlap.

9. The separate three-dimensional processor (100) according to claim 8, further characterized by: The storage array (170) is a random access memory (RAM) array or a non-volatile memory (NVM) array.

10. The separate three-dimensional processor (100) according to claim 8, further characterized by: The non-storage circuit (180) is a logic circuit or a processing circuit.

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