Very low frequency circuit frequency response parameter calibration system

Abstract

A very low frequency circuit frequency response parameter calibration system is suitable for high-precision frequency response calibration of a signal processing circuit working in a frequency range of 300 Hz to 100 kHz. The system comprises a signal acquisition module and an FPGA. The signal acquisition module comprises three synchronous acquisition channels, two output channels of a to-be-calibrated circuit, and a GPIO outputting a calibration signal of the FPGA. The FPGA is configured to generate a calibration signal after receiving a configuration instruction of an upper computer system. The calibration signal is divided into three paths: one path enters a very low frequency signal acquisition module as a reference signal for calibration comparison; the other two paths are injected into two input channels of the to-be-calibrated circuit to drive the to-be-calibrated circuit to generate corresponding outputs; the three sampling channels of the very low frequency signal acquisition module are synchronously controlled to start data acquisition and complete isochronous sampling tasks, ensuring the synchronization of the three paths of data in the time domain; after sampling is completed, the three-channel data is preprocessed, and then the preprocessed data is uploaded to the upper computer system for visual processing.

Description

Technical Field

[0001] This invention belongs to the field of very low frequency (VLF) wave detection and application technology, specifically relating to a VLF circuit frequency response parameter calibration system. This system is used to improve the frequency response accuracy and system stability of VLF signal detection equipment in the VLF band, and is suitable for high-precision signal calibration and performance evaluation in geophysical exploration, space environment monitoring, bioelectrical signal analysis, and other VLF signal application scenarios. Background Technology

[0002] In the detection and application of extremely low frequency (ELF / VLF) signals, the frequency response characteristics of electronic systems have a crucial impact on overall signal quality and data accuracy. This frequency band typically covers the range of approximately 0.1 Hz to 30 kHz, characterized by slow signal fluctuations and extremely weak energy, making it highly susceptible to environmental noise, electromagnetic interference, geomagnetic disturbances, and system background noise. Accurate measurement and analysis within this band rely on stable and predictable frequency response characteristics in each component of the signal acquisition chain (such as preamplifiers, voltage followers, filters, and analog-to-digital converters). Traditional calibration methods often rely on manually injecting standard excitation signals for point-by-point comparison. However, in the ELF range, generating standard signal sources is difficult, response times are long, and system noise levels are high, resulting in low efficiency and poor stability in the calibration process, making it difficult to meet the scientific and engineering requirements of high sensitivity and long-term operation.

[0003] Currently, most commercially available frequency response testing systems are geared towards electronic circuits in the audio frequency band and above, with limited testing capabilities for very low frequency (VLF) signals. This is especially true when dealing with signals characterized by long periods, low amplitudes, and non-steady-state fluctuations. Traditional testing methods such as frequency sweeping and excitation response analysis often suffer from insufficient accuracy and severe noise masking. Furthermore, during long-period measurements, environmental changes, component drift, and power supply fluctuations cause dynamic changes in the system's frequency response characteristics over time. Inaccurate frequency response models directly lead to deviations in amplitude and phase estimations, consequently affecting the reliability of the entire signal processing chain. For example, in geophysical exploration, VLF signals are used to detect changes in subsurface media or geostress activity; their subtle characteristics require high-precision frequency response control for accurate extraction. Therefore, there is an urgent need to develop dedicated frequency response parameter calibration techniques suitable for this frequency band to improve the accuracy of detection equipment and the robustness of the system.

[0004] With the widespread application of very low frequency (VLF) detection technology in multiple disciplines, such as space environment monitoring, bioelectrical signal research, structural health monitoring, and power system fault analysis, higher demands are placed on signal quality, data stability, and repeatability. Complex application scenarios pose challenges to the stability and consistency of circuit frequency response. Traditional static calibration methods struggle to address sensor performance differences, parameter drift caused by environmental disturbances, and accuracy consistency issues in multi-channel parallel computation. Therefore, a frequency response parameter calibration technology with automated control strategies is urgently needed to achieve accurate identification and correction of circuit response characteristics. The implementation of this technology will not only help improve the overall performance of measurement systems in VLF applications but also provide solid technical support for the standardization, modularization, and intelligentization of VLF detection equipment. Summary of the Invention

[0005] This invention proposes a very low frequency circuit frequency response parameter calibration system, which is suitable for high-precision frequency response calibration of signal processing circuits operating in the frequency range of 300 Hz to 100 kHz.

[0006] Firstly, a very low frequency (VLF) circuit frequency response parameter calibration system is proposed, comprising a VLF signal acquisition module and an FPGA. The VLF signal acquisition module includes three synchronous acquisition channels. The first and second channels of the three synchronous acquisition channels are respectively used to connect to the two output channels of the circuit to be calibrated, and the third channel is connected to the GPIO of the FPGA output calibration signal. The FPGA is configured to: generate a calibration signal after receiving the configuration command from the computer system. This calibration signal is divided into three paths: one path enters the VLF signal acquisition module as a reference signal for calibration comparison; the other two paths are respectively injected into the two input channels of the circuit to be calibrated, driving them to generate corresponding outputs; the FPGA synchronously controls the three sampling channels of the VLF signal acquisition module, starts data acquisition and completes isochronous sampling tasks to ensure the synchronization of the three data in the time domain; after sampling, the FPGA preprocesses the three channel data and then uploads the preprocessed data to the computer system for visualization processing.

[0007] The FPGA preprocesses the three-channel data by first performing a fast Fourier transform or a short-time Fourier transform, followed by amplitude extraction, phase calculation, and fundamental frequency identification.

[0008] The calibration signal is a square wave signal or an m-sequence.

[0009] Secondly, a host computer is proposed, comprising: a processor; a memory; and one or more program modules, wherein the one or more program modules are stored in the memory and configured to be executed by the processor, and the one or more program modules include instructions for performing the following steps: obtaining a parameter range for a calibration process set by the user; sending configuration instructions to the FPGA of the very low frequency circuit frequency response parameter calibration system to cause the FPGA to generate calibration signals according to the set parameter range; and preprocessing the data collected by the three sampling channels; and obtaining the preprocessed data from the FPGA for visualization processing.

[0010] The parameter range includes the start and end range of the calibration frequency, the frequency interval mode, the sampling duration of each frequency point, and the amplitude of the calibration signal.

[0011] The visualization process includes: based on the fundamental frequency point identification results, energy integration is performed within a certain bandwidth near the frequency point in the spectrum results of the three synchronous acquisition channels to obtain the signal strength. Subsequently, the signal strength and phase information of the first and second channels are compared with the reference signal acquired by the third channel to extract the frequency response characteristic parameters of the circuit to be calibrated at that frequency. By comparing the signals of the first and second channels with the reference signal respectively, the frequency response difference curve of the circuit to be calibrated at that frequency point is constructed. After the frequency response parameters of all frequency points are extracted, a set of frequency response curves is formed.

[0012] Thirdly, a readable storage medium is proposed, which stores a program that, when run on a host computer, executes the following steps: obtaining the parameter range of the calibration process set by the user; sending configuration instructions to the FPGA of the very low frequency circuit frequency response parameter calibration system, causing the FPGA to generate calibration signals according to the set parameter range; and preprocessing the data collected by the three sampling channels; obtaining the preprocessed data from the FPGA and performing visualization processing. The specific method for visualization processing is described in the second aspect above.

[0013] The very low frequency (VLF) circuit frequency response parameter calibration system proposed in this invention has significant advantages in structural design, functional implementation, and performance. Traditional frequency response calibration often relies on manual comparison using a single-channel cascaded reference source or simplified modeling methods, which are insufficient to address the characteristics of VLF signals, such as weak energy, slow response, and high noise content. Existing technologies often cannot simultaneously measure the input and output signals, leading to significant systematic errors in frequency response extraction, especially in multi-channel measurement or dynamic calibration scenarios where accuracy and stability are insufficient. The system of this invention employs a three-channel synchronous acquisition structure, with one channel acquiring the input reference signal and the other two channels acquiring the dual-channel output of the circuit being calibrated. This enables closed-loop response analysis of the signal path at the same time and frequency point, significantly improving measurement accuracy and consistency of frequency response modeling. Simultaneously, the excitation control and data processing logic are implemented using an FPGA, integrating the acquisition, comparison, and analysis processes into an automated workflow, effectively improving calibration efficiency and supporting frequency scanning response analysis and online real-time calibration. In addition, this system supports batch device calibration, frequency point customization, and graphical presentation of host computer response. It has good scalability and engineering application value, and is particularly suitable for fields such as geophysics, electromagnetic detection, and biomedicine, which have extremely high requirements for the calibration accuracy of very low frequency signals. Attached Figure Description

[0014] Figure 1 This is a block diagram of a very low frequency circuit calibration system according to an embodiment of the present invention.

[0015] Figure 2 This is a flowchart of very low frequency circuit calibration according to an embodiment of the present invention.

[0016] Figure 3 It is a signal source generated by an FPGA according to an embodiment of the present invention.

[0017] Figure 4 It is a calibration channel signal acquired by an FPGA according to an embodiment of the present invention.

[0018] Figure 5 This is a time-frequency diagram of a reference signal and a circuit response signal according to an embodiment of the present invention.

[0019] Figure 6 This is the amplitude-frequency response result of the reference signal and the circuit response signal according to an embodiment of the present invention.

[0020] Figure 7 The result is the frequency response curve of the channel to be calibrated according to an embodiment of the present invention. Detailed Implementation

[0021] Figure 1 A block diagram of a very low frequency circuit frequency response parameter calibration system (hereinafter referred to as the "calibration system") is shown. Figure 1 As shown, the system includes a very low frequency (VLF) signal acquisition module, an FPGA control module, and a host computer. The VLF signal acquisition module has a three-channel structure. The FPGA control module and the host computer form a bidirectional communication link for system configuration and data feedback. The calibration signal (i.e., the excitation signal) is injected into the input terminal of the circuit to be calibrated and the acquisition module through independent paths, forming a closed-loop measurement structure to ensure the consistency and real-time performance of the data comparison.

[0022] The very low frequency (VLF) circuit to be calibrated is the object under test, typically comprising two signal processing channels. These channels receive the calibration signal generated by the FPGA control module and output the signal data after the circuit under test has responded. Each channel may contain preamplifier, filter, impedance matching, and other modules. During calibration, both channels simultaneously receive the same standard excitation signal to ensure the synchronization and comparability of the response parameters. The circuit structure of this module is usually complex and its frequency response characteristics may be affected by factors such as environmental temperature drift and power supply disturbances. Therefore, periodic or real-time response correction is required using the system of this invention.

[0023] The very low frequency (VLF) signal acquisition module is a key measurement component in the system. It features three synchronous acquisition channels, connected to the two output channels (Channel 1 and Channel 2) of the circuit to be calibrated, and the direct output channel (Channel 3) of the calibration signal source generated by the FPGA control module. This module achieves high-precision analog-to-digital conversion (ADC) with a sampling accuracy of 16 or 24 bits, effectively suppressing background noise, and possessing microsecond-level synchronization performance between channels to ensure isochronous acquisition and processing of weak signals. The advantage of the three-channel design is that it can not only acquire the response results of the circuit being calibrated but also compare the input signal itself (i.e., the excitation signal) in real time, thereby eliminating measurement errors caused by uncertainties at the excitation end.

[0024] The FPGA control module is used for system logic coordination, data preprocessing, and communication scheduling. This module receives data streams from the three-channel acquisition module. During the calibration process, the FPGA controls the switching of calibration signal frequencies according to a preset sequence, organizes the sampling process, and calculates the frequency response function of each channel in real time. Its core processing includes functions such as synchronous sampling control, Fast Fourier Transform (FFT), phase-locked loop detection, and gain-phase difference calculation. The processing results are transmitted to the host computer via the FPGA, enabling online response evaluation and storage. On the other hand, the FPGA is used as a signal source in this system, and the generated calibration signals are simultaneously output to the circuit to be calibrated (channels 1 and 2) and the acquisition module (channel 3) via GPIO.

[0025] The three-channel signals acquired in the time domain (including the output signal of the circuit under test and the reference signal) are converted into a frequency domain representation, and the frequency components of the signals are extracted. Using FFT, the injection frequency of the calibration signal (such as the fundamental frequency and harmonics of a square wave) can be clearly identified, and the dominant frequency component of the output signal of the circuit under test can be separated. In the frequency domain, FFT can directly acquire the amplitude and phase spectra of the signal. The output strength of the circuit under test at a specific frequency point (such as voltage amplitude) is quantified by extracting the amplitude. The phase offset of the signal under test relative to the reference signal is determined by calculating the phase, providing a data basis for subsequent phase difference analysis. The fundamental frequency (dominant frequency) of the signal is located by FFT, eliminating harmonic interference and ensuring that subsequent analysis focuses on the target frequency point (such as the injection frequency of the calibration signal). Phase-locked loop (PLL) detection technology is used to synchronize the phase of the signal under test with the reference signal (calibration signal), suppressing noise and extracting signal components with the same frequency as the reference signal. The feedback mechanism of the PLL is adjusted in real time to ensure that the system can adapt to dynamic changes during frequency switching of the calibration signal (such as the phase tracking requirements during frequency scanning).

[0026] By calculating the gain difference (amplitude ratio) and phase difference (phase shift) between the output signal of the circuit to be calibrated and the reference signal, the frequency response function of the circuit to be calibrated at a specific frequency point can be constructed.

[0027] The host computer, serving as the system's human-machine interface terminal, handles system configuration and data visualization. Users can set parameters such as calibration frequency range, sampling length, and channel selection through the interface, and start or stop the calibration process. After receiving real-time data uploaded by the FPGA, the host computer automatically performs result analysis and generates charts, including gain response curves and phase response curves. It also supports saving the data as a structured frequency response model file for subsequent error compensation or performance tracking. The host computer can also remotely interact with external databases or calibration signal sources, improving the system's scalability and manageability.

[0028] The calibration signal input path generated by the FPGA provides a highly stable, frequency-controllable reference signal for the entire system. This signal is split into three parts after input: one path enters the acquisition module through channel 3 as a reference; the other two paths are injected into the two input channels of the circuit to be calibrated, driving them to generate corresponding outputs. Through this three-channel design, the system can acquire and compare the input and output signals simultaneously, eliminating measurement deviations caused by time delays, amplitude instability, and other factors, thus achieving true dynamic calibration.

[0029] Figure 2 A method for calibrating the frequency response parameters of a very low frequency circuit using the aforementioned calibration system is demonstrated.

[0030] 2.1. The host computer first sets the parameter range for the entire calibration process, including the start and end range of the calibration frequency, the frequency interval mode (such as logarithmic or linear distribution), the sampling duration of each frequency point, the excitation amplitude, and the circuit channel number. After setting, the host computer sends a configuration command to the FPGA to set the mode parameters of the calibration signal.

[0031] 2.2 After receiving instructions from the host computer, the FPGA module controls the signal source to generate a square wave excitation signal at the target frequency according to the set mode. This excitation signal serves as a standard calibration signal and is output through the GPIO port, splitting into three paths: two paths serve as excitation signals, injected into the first and second channels of the circuit to be calibrated, respectively, to drive them to generate response signals; the third path is directly input to the third channel of the signal acquisition module as a reference signal for calibration and comparison.

[0032] Since GPIO can only output high and low levels, it is necessary to discuss the form of the excitation signal. There are two main feasible solutions: Option 1: Generate a square wave sweep signal with specified parameters. Starting from the lower cutoff frequency, generate a square wave signal with a 50% duty cycle point by point, either linearly or logarithmically. In this option, since the square wave signal consists of the fundamental frequency and various harmonics, after obtaining the reference signal and response signal, it is necessary to extract the fundamental frequency signal from the signal spectrum and obtain the signal strength through energy integration. Since the calculation is relatively complex, it is often necessary to process it on a host computer to obtain the calibration result. However, the advantage is that the signal frequency points are discrete, easy to extract, and have little impact from the accuracy of the transmitting source clock. It can also accurately measure the phase frequency characteristics of the signal to be calibrated. Option 2: Generate a pseudo-random sequence of a specific order (such as an M-sequence) at a specified sampling rate. This option utilizes the white noise characteristic of the M-sequence. After performing an N-point FFT on an N-order M-sequence, its amplitude-frequency characteristic is constant. Therefore, the amplitude-frequency characteristic of the signal to be calibrated can be directly obtained by performing an FFT on the response signal. Due to the simplicity of the calculation method, the final calibration result can be directly calculated using an FPGA. Furthermore, the sampling rate and calibration frequency upper limit can be higher, and the time spent on a single calibration is shorter. However, this method requires high accuracy of the transmitter clock and is often only applicable to devices with the same transmitter and receiver source. It also cannot accurately measure the phase-frequency characteristics. Considering all factors, the first signal generation scheme (square wave sweep frequency signal scheme) is recommended.

[0033] 2.3. The circuit to be calibrated, to which the injected signal is received, receives the standard excitation signal and generates an output response signal based on its own frequency response characteristics. This output signal is sent to the acquisition module through the first and second channels, while the reference signal enters the acquisition module through the third channel. At this time, the FPGA synchronously controls the three sampling channels of the acquisition module, starts data acquisition, and completes the isochronous sampling task to ensure the synchronization of the three data streams in the time domain.

[0034] 2.4. After sampling, the FPGA preprocesses the three-channel data by performing a Fast Fourier Transform (FFT) or a Short-Time Fourier Transform (STFT), followed by amplitude extraction, phase calculation, and frequency identification. The preprocessed data is then uploaded to the host computer for further processing and calculation.

[0035] 2.5. The preprocessed data results are uploaded to the host computer, which further visualizes the sampling results. First, based on the fundamental frequency identification result, the host computer performs energy integration within a certain bandwidth near the frequency point in the spectrum results of the three sampling channels to obtain the signal strength. Then, it performs difference analysis on the signal strength and phase information of the first and second channels with the reference signal acquired from the third channel to extract the frequency response characteristic parameters of the circuit under test, such as gain, phase shift, and group delay, of the input signal at that frequency. By comparing the signals of the first and second channels with the reference signal, the host computer constructs a frequency response difference curve of the circuit to be calibrated at that frequency point. This curve reflects the amplitude-frequency and phase-frequency response characteristics of the circuit at the current frequency, providing a basis for subsequent error compensation or performance adjustment.

[0036] 2.6 The above process constitutes a complete calibration step for a single frequency point. The system will automatically and cyclically execute the above steps according to a predetermined frequency sweep sequence until the response parameters of all frequency points are extracted. Finally, the host computer will generate a complete set of frequency response curves, and can further fit them to obtain a system response model or derive a parameter compensation table for system compensation, anomaly monitoring, or automatic identification.

[0037] The present invention also provides an embodiment of a host computer. The host computer includes a processor and a memory. The memory is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor is used to execute the non-transitory computer-readable instructions, which, when executed by the processor, can perform steps 2.1 and 2.5 in the calibration method described above. The memory and the processor can be interconnected via a bus system and / or other forms of connection mechanisms.

[0038] For example, a processor can be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit with data processing and / or program execution capabilities. A processor can be a general-purpose processor or a special-purpose processor, and it can control other components in the computer to perform desired functions.

[0039] For example, memory can include any combination of one or more computer program products, which can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact optical disc read-only memory (CD-ROM), USB storage, flash memory, etc. One or more computer program modules can be stored on the computer-readable storage medium, and the processor can run one or more computer program modules to implement various functions of the computer.

[0040] This invention also provides a readable storage medium for storing a program that, when executed by a host computer, can implement steps 2.1 and 2.5 of the aforementioned calibration method. When the software program in the host computer of this invention is sold or used as an independent product, it can be stored in a readable storage medium. For relevant descriptions of the storage medium, please refer to the corresponding description of the host computer's memory above; further details will not be repeated here.

[0041] Application Examples: In this embodiment, the FPGA control module generates a set of linear sweep square wave signals with a frequency range of 100 Hz to 100 kHz. The sweep period is set to 1.0 second to ensure that the entire frequency band is covered within a specified time. The generated square wave signals are output through GPIO pins and directly acquired through the third sampling channel as a standard reference signal. Figure 3 The waveform of the standard reference signal in the time domain is shown. The periodic characteristics that change linearly with time can be clearly observed, showing the continuous change of the square wave frequency from low to high.

[0042] To achieve dynamic evaluation of the system's frequency response, this embodiment selects a typical first-order RC low-pass filter as the calibration circuit. The swept square wave signal output from the FPGA passes through this low-pass filter circuit, where its frequency characteristics modulate the signal, resulting in a change in response. The signal processed by the circuit is acquired by the first sampling channel, and its waveform is shown below. Figure 4 As shown, it is evident that the amplitude envelope of the output waveform decays over time, especially in the high-frequency range, where the energy of the output signal decreases rapidly, consistent with the suppression characteristics of a low-pass filter for high-frequency signals.

[0043] To further analyze the energy distribution of the reference and response signals as frequency changes, short-time Fourier transform (STFT) is used to perform time-frequency analysis on the two signals. Figure 5The time-frequency plots of the reference signal and the response signal are shown separately. It can be observed from the plots that the reference signal exhibits an ideal linear frequency growth trajectory, with its frequency components uniformly distributed over time; while in the response signal plot, the signal energy in the high-frequency region is significantly weakened, indicating that the high-frequency components are effectively attenuated after filtering. This result reflects the frequency-selective response characteristics of the circuit under test from a time-frequency perspective.

[0044] Furthermore, for each moment in the time-frequency graph, its dominant frequency (i.e., fundamental frequency point f) is identified, and a fixed bandwidth region (e.g., ±50Hz, total bandwidth 100Hz) is selected near this frequency. The energy integral value within this frequency band is calculated as the signal amplitude index A for the current moment. As the frequency sweep process is completed, the amplitude values ​​corresponding to each frequency point throughout the entire sweep cycle can be collected, and the frequency response curves of the reference signal and the response signal can be plotted separately, such as... Figure 6 As shown in the figure, the reference signal maintains a relatively balanced amplitude distribution across the entire frequency band, while the response signal exhibits a significant attenuation trend in the high-frequency region, further verifying the low-pass filtering characteristics of the tested RC circuit.

[0045] Finally, by calculating the difference between the two frequency response curves, the amplitude change of the response signal relative to the reference signal at each frequency point is obtained. This difference represents the frequency response function A(f) of the circuit to be calibrated. Figure 7 The final obtained amplitude-frequency response curve (f, A) of the circuit is shown. It can be intuitively observed from the figure that the RC circuit has a gain close to 0 dB in the low-frequency region. As the frequency increases, the gain gradually decreases, reaching an attenuation of approximately -25 dB at 100 kHz, exhibiting typical first-order low-pass response characteristics. This result is in high agreement with the theoretical model, verifying the high accuracy and consistency of the system's extraction of the circuit's frequency response characteristics. The calibration results not only accurately reflect the frequency selectivity of the circuit itself but also serve as an important basis for subsequent system response compensation, digital modeling, and error correction, further confirming the effectiveness and practical value of this invention in low-frequency circuit frequency response calibration.

[0046] This invention primarily addresses the need for high-precision extraction and modeling of the frequency response characteristics of analog circuits in the 300 Hz to 100 kHz frequency band. The system employs a three-channel synchronous acquisition structure, with two channels acquiring the output signal of the circuit to be calibrated and one channel acquiring the reference excitation signal, enabling parallel comparison and closed-loop analysis of input and output signals. The FPGA control module outputs a linear sweep square wave signal via GPIO to drive the circuit for frequency scanning and synchronously controls the three-channel sampling and data processing. Based on Short-Time Fourier Transform (STFT), the system performs time-frequency analysis of the signal, extracting the amplitude information of the dominant frequency component frequency by frequency to construct a complete frequency response curve. By comparing the amplitude-frequency characteristics of the reference signal and the response signal, the gain response of the circuit to be calibrated at different frequencies is accurately obtained, achieving quantitative modeling and error identification of the frequency response function. The proposed calibration method has advantages such as high automation, high identification accuracy, and strong anti-interference capability. It supports continuous testing at multiple frequency points and rapid fitting of the response function, and is suitable for online or offline calibration of various low-frequency analog circuits such as RC filters, preamplifiers, and sensor front-ends. Compared to traditional methods, this system introduces a reference signal channel design, effectively offsetting the errors in frequency response measurement caused by excitation source instability or system delay drift. Furthermore, it improves the overall efficiency of response extraction and data computation through FPGA embedded processing logic, enhancing the system's adaptability and reliability in complex application environments. This system is particularly suitable for applications with stringent frequency response characteristics, such as geophysical electromagnetic monitoring, low-frequency fault analysis in power systems, and biomedical signal acquisition. It can also serve as a standardized calibration tool for scientific research platforms or instrument factory testing, demonstrating broad application prospects and engineering promotion value.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A very low frequency circuit frequency response parameter calibration system, characterized in that, The system includes a very low frequency (VLF) signal acquisition module and an FPGA. The VLF signal acquisition module includes three synchronous acquisition channels. The first and second channels are respectively used to connect to the two output channels of the circuit to be calibrated, and the third channel is connected to the GPIO of the FPGA to output the calibration signal. The FPGA is configured as follows: After receiving the configuration command from the host computer, the FPGA generates a calibration signal. This calibration signal is divided into three paths: one path enters the very low frequency signal acquisition module as a reference signal for calibration and comparison, and the other two paths are injected into the two input channels of the circuit to be calibrated, respectively, to drive it to generate corresponding outputs. The FPGA synchronously controls the three synchronous sampling channels of the very low frequency signal acquisition module, starts data acquisition and completes the isochronous sampling task, ensuring the synchronization of the three data in the time domain; After sampling, the FPGA preprocesses the three-channel data and then uploads the preprocessed data to the host computer for visualization. The visualization includes: based on the fundamental frequency point identification result, performing energy integration within a certain bandwidth near the frequency point in the spectrum results of the three synchronous acquisition channels to obtain the signal strength; then performing difference analysis on the signal strength and phase information of the first and second channels with the reference signal acquired by the third channel to extract the frequency response characteristic parameters of the circuit to be calibrated at that frequency point; constructing the frequency response difference curve of the circuit to be calibrated at that frequency point by comparing the signals of the first and second channels with the reference signal respectively; and finally forming a set of frequency response curves after extracting the frequency response parameters of all frequency points.

2. The very low frequency circuit frequency response parameter calibration system according to claim 1, characterized in that, The FPGA preprocesses the three-channel data by first performing a fast Fourier transform or a short-time Fourier transform, followed by amplitude extraction, phase calculation, and fundamental frequency identification.

3. The very low frequency circuit frequency response parameter calibration system according to claim 1, characterized in that, The calibration signal is a square wave signal or an m-sequence.

4. A host computer, characterized in that, include: processor; Memory; as well as One or more program modules, stored in the memory and configured to be executed by the processor, the program modules including instructions for performing the following steps: Obtain the parameter range for the calibration process set by the user; Send a configuration command to the FPGA of the very low frequency circuit frequency response parameter calibration system according to any one of claims 1-3, so that the FPGA generates a calibration signal according to the set parameter range, and preprocesses the data acquired by the three synchronous acquisition channels. Acquire the preprocessed data from the FPGA and perform visualization processing.

5. The host computer according to claim 4, characterized in that, The parameter range includes the start and end range of the calibration frequency, the frequency interval mode, the sampling duration of each frequency point, and the amplitude of the calibration signal.

6. A readable storage medium, characterized in that, The readable storage medium stores a program that, when run on the host computer, performs the following steps: Obtain the parameter range for the calibration process set by the user; Send a configuration command to the FPGA of the very low frequency circuit frequency response parameter calibration system according to any one of claims 1-3, so that the FPGA generates a calibration signal according to the set parameter range, and preprocesses the data acquired by the three synchronous acquisition channels. Acquire the preprocessed data from the FPGA and perform visualization processing.

7. The readable storage medium according to claim 6, characterized in that, The parameter range includes the start and end range of the calibration frequency, the frequency interval mode, the sampling duration of each frequency point, and the amplitude of the calibration signal.

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