Accelerator device, computer system and data processing method

Abstract

The embodiments of the present application provide an accelerator device, a computer system, and a data processing method. The accelerator device includes an on-chip interconnect network, an on-chip cache, a memory controller, a device-side memory, and a computing unit. The on-chip interconnect network is communicatively connected to the computing unit, the on-chip interconnect network is communicatively connected to the on-chip cache, the on-chip interconnect network is communicatively connected to the memory controller, the memory controller is communicatively connected to the device-side memory, and the on-chip cache is communicatively connected to the computing unit. The on-chip interconnect network receives page data of database pages transmitted by the host via a cache coherence bus. The on-chip cache is used to store page metadata of the page data, and the device-side memory is used to store row data of the page data. During the filtering calculation process, the computing unit can quickly access the page metadata in the on-chip cache without having to access it from the host, thereby reducing access latency and improving the computing performance of the accelerator device.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an accelerator device, a computer system, and a data processing method. Background Art

[0002] With the vigorous development of emerging applications such as artificial intelligence, various applications have put forward unprecedented requirements on the computing performance of computing systems. Therefore, heterogeneous computing technology has emerged by introducing accelerator devices, which are connected to the host via a cache consistency bus. With the help of the massive computing units in the accelerator devices, the computing performance of the computing system can be effectively improved.

[0003] In related technologies, the data to be calculated is cached in the host-side memory. When the accelerator device needs to calculate the data to be calculated, it needs to first transfer the data to the accelerator device, calculate it, and then transmit the calculation result back to the host.

[0004] However, in database scenarios, due to the large amount of calculation, if the data to be calculated needs to be obtained from the host side memory every time calculation is performed, the memory access latency of the accelerator device is increased and the computing performance of the accelerator device is reduced. Summary of the Invention

[0005] The present application provides an accelerator device, a computer system, and a data processing method to reduce the memory access latency of the accelerator device and increase the computing performance of the accelerator device.

[0006] The present application provides an accelerator device 10, comprising:

[0007] On-chip interconnect network 103, on-chip cache 104, memory controller 105, device-side memory 106, and computing unit 107;

[0008] The on-chip interconnect network 103 is communicatively connected to the computing unit 107 , the on-chip interconnect network 103 is communicatively connected to the on-chip cache 104 , the on-chip interconnect network 103 is communicatively connected to the memory controller 105 , the memory controller 105 is communicatively connected to the device-side memory 106 , and the on-chip cache 104 is communicatively connected to the computing unit 107 ;

[0009] The on-chip interconnect network 103 is used to receive page data of the database page transmitted by the host 20 through the cache coherence bus 30; the on-chip cache 104 is used to store page meta information of the page data; the device-side memory 106 is used to store row data of the page data;

[0010] The computing unit 107 is configured to extract page meta information from the on-chip cache 104 ; read corresponding target row data from the device-side memory 106 by accessing the memory controller 105 ; and perform filtering calculations based on the target row data and the page meta information to obtain filtering calculation results.

[0011] The present application provides a computer system, comprising: a host 20 and the above-mentioned accelerator device 10;

[0012] The host 20 includes: a processor 201, an internal interconnect bus 202, a root agent module 203, a host memory controller 204, a host-side memory 205, an external memory controller 206, and an external storage device 207; the processor 201 has a processor cache 2011;

[0013] The processor 201 is communicatively connected to the internal interconnect bus 202, the external memory controller 206 is communicatively connected to the internal interconnect bus 202, the root agent module 203 is communicatively connected to the internal interconnect bus 202, the external memory controller 206 is communicatively connected to the external storage device 207, the root agent module 203 is communicatively connected to the accelerator device 10 via the cache coherence bus 30, the root agent module 203 is communicatively connected to the host memory controller 204, and the host memory controller 204 is communicatively connected to the host-side memory 205.

[0014] The present application provides a data processing method, which is applied to an accelerator device 10. The accelerator device 10 includes an on-chip interconnect network 103, an on-chip cache 104, a memory controller 105, a device-side memory 106, and a computing unit 107. The method includes:

[0015] The on-chip interconnection network 103 receives page data of the database page transmitted by the host 20 via the cache coherence bus 30;

[0016] The on-chip cache 104 receives the page meta information of the page data sent by the on-chip interconnection network 103 and stores the page meta information of the page data;

[0017] The device-side memory 106 receives row data of the page data sent by the on-chip interconnection network 103 and stores the row data of the page data;

[0018] The computing unit 107 extracts page meta information from the on-chip cache 104;

[0019] The calculation unit 107 reads the corresponding target row data from the device-side memory 106 by accessing the memory controller 105 ; performs filtering calculation according to the target row data and the page meta information to obtain a filtering calculation result.

[0020] Through the accelerator device, computer system, and data processing method provided by the embodiments of the present application, page data of database pages transmitted by the host through the cache consistency bus is received through the on-chip interconnect network, the on-chip cache is used to store page meta information of the page data, and the device-side memory is used to store row data of the page data. During the execution of filtering calculations, the computing unit can quickly access the page meta information in the on-chip cache without having to access it from the host, thereby reducing access latency and improving the computing performance of the accelerator device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 Schematic diagram of the structure of the accelerator device provided in the embodiment of the present application Figure 1 ;

[0023] Figure 2 Schematic diagram of the structure of the accelerator device provided in the embodiment of the present application Figure 2 ;

[0024] Figure 3 A schematic diagram of the architecture of a computer system provided in an embodiment of the present application;

[0025] Figure 4 Schematic diagram of the data processing method provided in this embodiment Figure 1 ;

[0026] Figure 5 Schematic diagram of the data processing method provided in this embodiment Figure 2 ;

[0027] Figure 6 A schematic diagram of the file reading process provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the file writing process provided in an embodiment of the present application;

[0029] Figure 8 A logical diagram of the preset computing task allocation rules provided in an embodiment of the present application;

[0030] Figure 9 A schematic diagram of cache attribute configuration provided in an embodiment of the present application;

[0031] Figure 10 A logical diagram of reading filtering calculation results provided in an embodiment of the present application;

[0032] Figure 11 A logical diagram of the filtering calculation provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0034] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0035] It should be noted that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like, indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely for ease of description and simplification of the present application. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present application. The terms "mounted," "connected," and "connected" should be interpreted broadly, and may include, for example, fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. The terms "parallel," "perpendicular," and "equal" encompass the described conditions and conditions similar to the described conditions, provided that the range of the similar conditions is within an acceptable range of deviation, as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances. With the vigorous development of emerging applications such as artificial intelligence, various applications have put forward unprecedented requirements on the computing performance of computing systems. Therefore, by introducing accelerator devices, heterogeneous computing technology connected to the host via a cache consistency bus has emerged. With the help of a large number of computing units in the accelerator devices, the computing performance of the computing system can be effectively improved.

[0036] In related technologies, the data to be calculated is cached in the host-side memory. When the accelerator device needs to calculate the data to be calculated, it needs to first transfer the data to the accelerator device, calculate it, and then transmit the calculation result back to the host.

[0037] However, in database scenarios, due to the large amount of calculation, if the data to be calculated needs to be obtained from the host side memory every time calculation is performed, the memory access latency of the accelerator device is increased and the computing performance of the accelerator device is reduced.

[0038] In order to solve the above technical problems, the following technical concept is proposed: since the data to be calculated is cached in the host and the calculation process is performed in the accelerator device, the inventors propose that the data to be calculated can be preferentially allocated to the cache in the accelerator device to reduce the memory access overhead of the accelerator device.

[0039] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0040] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the data processing method depends, the specific application environment architecture or specific hardware architecture is described here. Figure 1 , Figure 1 Schematic diagram of the structure of the accelerator device provided in the embodiment of the present application Figure 1 , the accelerator device 10 includes:

[0041] On-chip interconnect network 103 , on-chip cache 104 , memory controller 105 , device-side memory 106 , and computing unit 107 .

[0042] The on-chip interconnect network 103 is communicatively connected to the computing unit 107 , the on-chip interconnect network 103 is communicatively connected to the on-chip cache 104 , the on-chip interconnect network 103 is communicatively connected to the memory controller 105 , the memory controller 105 is communicatively connected to the device-side memory 106 , and the on-chip cache 104 is communicatively connected to the computing unit 107 .

[0043] Among them, the on-chip interconnection network 103 is used to receive page data of the database page transmitted by the host 20 through the cache consistency bus 30; the on-chip cache 104 is used to store page meta information of the page data; and the device-side memory 106 is used to store row data of the page data.

[0044] The computing unit 107 is configured to extract page meta information from the on-chip cache 104 ; read corresponding target row data from the device-side memory 106 by accessing the memory controller 105 ; and perform filtering calculations based on the target row data and the page meta information to obtain filtering calculation results.

[0045] The computing unit 107 writes the filtered calculation results into the device-side memory 106 via the on-chip interconnect 103. Compared to simply using the cache coherence bus and device-side memory to achieve host memory expansion, the computing unit can also perform extended calculations on page data to improve the host's computing efficiency.

[0046] In the accelerator device provided by the embodiment of the present application, the on-chip cache can directly obtain page meta information, and the device-side memory can directly obtain page data. During the filtering calculation process, the computing unit can quickly access the page meta information in the on-chip cache without accessing it from the host, thereby reducing access latency and improving the computing performance of the accelerator device.

[0047] In one possible implementation, Figure 2 As shown, Figure 2 Schematic diagram of the structure of the accelerator device provided in the embodiment of the present application Figure 2 , the computing unit 107 includes a row parser 1071 and a column filter 1072:

[0048] The row parser 1071 is communicatively connected to the on-chip cache 104 , and the row parser 1071 is communicatively connected to the column filter 1072 .

[0049] The row parser 1071 is used to extract page meta information from the on-chip cache 104 and process the page meta information to obtain a memory access sequence list and calculation related information.

[0050] The row parser 1071 is used to access the device-side memory 106 according to the memory access order list to read the corresponding target row data into the column filter 1072 , and pass the calculation related information to the column filter 1072 .

[0051] Column filter 1072 is used to perform filtering calculations based on the target row data and calculation-related information to obtain filtering calculation results. In the accelerator device provided in the embodiment of the present application, compared to the row parser extracting and processing the entire page data, the row parser only needs to quickly extract page meta information from the on-chip cache and, in combination with the column filter, reduce access latency and improve processing efficiency.

[0052] In one possible implementation, Figure 2 As shown, Figure 2 Schematic diagram of the structure of the accelerator device provided in the embodiment of the present application Figure 2 , the accelerator device 10 further includes:

[0053] Direct memory access controller 108 .

[0054] The direct memory access controller 108 is communicatively connected to the physical linker 101 , and the direct memory access controller 108 is communicatively connected to the on-chip cache 104 .

[0055] The direct memory access controller 108 is used to synchronize the page data corresponding to the filter calculation result from the device-side memory 106 to the host 20 .

[0056] Possibly, the direct memory access controller 108 may also proactively issue read and write requests to the host 20 and the device-side memory 106 to perform rapid data migration or copying between the host 20 and the device-side memory.

[0057] In one possible implementation, Figure 2 As shown, the accelerator device 10 further includes a physical linker 101 and a bridge 102. The physical linker 101 is in communication with the direct memory access controller 108, and the physical linker 101 is in communication with the bridge 102. The bridge 102 is in communication with the on-chip interconnect network 103. The physical linker 101 is used to parse messages from the cache coherence bus 30. The bridge 102 is used to convert messages between the message transmission protocol of the cache coherence bus 30 and the message transmission protocol of the on-chip interconnect network 103. It is also used to receive read and write access requests from the host 20 to the device-side memory 106 and the on-chip cache 104.

[0058] The accelerator device provided in the embodiment of the present application realizes fast synchronization of page data between the accelerator device and the host through a direct memory access controller, thereby reducing delay and improving data throughput.

[0059] Figure 3 The schematic diagram of the computer system architecture provided in the embodiment of the present application is as follows: Figure 3 As shown, the computer system provided in the embodiment of the present application includes a host 20 and an accelerator device 10:

[0060] The host 20 includes: a processor 201, an internal interconnect bus 202, a root agent module 203, a host memory controller 204, a host-side memory 205, an external memory controller 206 and an external storage device 207; the processor 201 has a processor cache 2011.

[0061] The processor 201 is communicatively connected to the internal interconnect bus 202, the external memory controller 206 is communicatively connected to the internal interconnect bus 202, the root agent module 203 is communicatively connected to the internal interconnect bus 202, the external memory controller 206 is communicatively connected to the external storage device 207, the root agent module 203 is communicatively connected to the accelerator device 10 via the cache coherence bus 30, the third segment of the root agent module 203 is communicatively connected to the host memory controller 204, and the host memory controller 204 is communicatively connected to the host-side memory 205.

[0062] The processor cache 2011 is used to cache data recently accessed by the processor. External storage devices 207 include, but are not limited to, solid-state drives (SSDs) and mechanical hard disks. The external memory controller 206 can initiate read and write access requests to the host-side memory 205 via the internal interconnect bus 202. The root agent module 203 maintains data consistency between the host-side memory 205, the device-side memory 106, and the processor cache 2011 via the cache coherence bus 30. The cache coherence bus 30 includes, but is not limited to, physical buses with cache coherence capabilities, such as Cache Coherent Interconnect for Accelerators (CCIX), Open Coherent Accelerator Processor Interface (OpenCAPI), and Compute Express Link (CXL). The host-side memory 205 includes, but is not limited to, storage devices such as double data rate synchronous dynamic random access memory (DDRAM), low-power double data rate memory (LPDDR), and high-bandwidth memory (HBM).

[0063] The computer system provided by the embodiments of the present application improves the computing efficiency of the computer system by performing extended calculations on page data through a computing unit, compared to simply using a cache coherent bus and device-side memory to expand the host's memory. A direct memory access controller is used to achieve rapid synchronization of page data between the accelerator device and the host, reducing latency and improving data throughput.

[0064] Figure 4 Schematic diagram of the data processing method provided in this embodiment Figure 1 ,like Figure 4 As shown, the data processing method is applied to an accelerator device 10, which includes an on-chip interconnect network 103, an on-chip cache 104, a memory controller 105, a device-side memory 106, and a computing unit 107. The method includes:

[0065] S401 , the on-chip interconnect network 103 receives page data of a database page transmitted by the host 20 through the cache coherence bus 30 .

[0066] S402 : The on-chip cache 104 receives the page meta information of the page data sent by the on-chip interconnection network 103 and stores the page meta information of the page data.

[0067] S403 : The device-side memory 106 receives the row data of the page data sent by the on-chip interconnection network 103 and stores the row data of the page data.

[0068] S404 , the computing unit 107 extracts page meta information from the on-chip cache 104 .

[0069] S405 , the calculation unit 107 reads the corresponding target row data from the device-side memory 106 by accessing the memory controller 105 ; performs filtering calculation according to the target row data and the page meta information to obtain a filtering calculation result.

[0070] The data processing method provided in the embodiment of the present application receives page data of a database page transmitted by a host through a cache consistency bus through an on-chip interconnect network. The on-chip cache is used to store page meta information of the page data, and the device-side memory is used to store row data of the page data. During the execution of filtering calculations, the computing unit can quickly access the page meta information in the on-chip cache without accessing it from the host, thereby reducing access latency and improving the computing performance of the accelerator device.

[0071] Figure 5 Schematic diagram of the data processing method provided in this embodiment Figure 2 , wherein the host includes a processor 201, a host-side memory 205, an external memory controller 206 and an external storage device 207; wherein the computing unit 107 includes a row parser 1071 and a column filter 1072, such as Figure 5 As shown, the method further includes:

[0072] S501: The processor 201 obtains a data processing instruction, where the data processing instruction is triggered by a user.

[0073] S502 : The processor 201 , in response to the data processing instruction, determines whether the corresponding computing task is to be executed by the accelerator device 10 or the host 20 according to a preset computing task allocation rule.

[0074] In a possible implementation, the processor 201 determines a corresponding computational complexity parameter according to the data processing instruction.

[0075] Processor 201, if the page data corresponding to the computing task is cached in the host side memory 205, the page data corresponding to the computing task is not cached in the device side memory 106, and the computing complexity parameter is less than or equal to the third preset threshold, then the computing task is assigned to the host 20 for execution.

[0076] Processor 201, if the page data corresponding to the computing task is not cached in the host side memory 205, the page data corresponding to the computing task is not cached in the device side memory 106, and the computing complexity parameter is less than or equal to the third preset threshold, then the computing task is assigned to the host 20 for execution.

[0077] The processor 201 allocates the computing task to the accelerator device 10 for execution if the page data corresponding to the computing task is cached in the host-side memory 205 and the page data corresponding to the computing task is cached in the device-side memory 106 .

[0078] Processor 201, if the page data corresponding to the computing task is cached in the host side memory 205, the page data corresponding to the computing task is not cached in the device side memory 106, and the computing complexity parameter is greater than the third preset threshold, then the computing task is assigned to the accelerator device 10 for execution.

[0079] The processor 201 allocates the computing task to the accelerator device 10 for execution if the page data corresponding to the computing task is not cached in the host-side memory 205 and the page data corresponding to the computing task is cached in the device-side memory 106 .

[0080] Processor 201, if the page data corresponding to the computing task is not cached in the host side memory 205, the page data corresponding to the computing task is not cached in the device side memory 106, and the computing complexity parameter is greater than the third preset threshold, then the computing task is assigned to the accelerator device 10 for execution.

[0081] Specifically, the above preset computing task allocation rules are as follows: Figure 8 As shown, Figure 8 A logical diagram of the preset computing task allocation rules provided in an embodiment of the present application.

[0082] The computational complexity parameter can be a Structured Query Language (SQL) computational complexity parameter. The number of required computations is determined based on the number of filter conditions in the SQL statement and the number of table fields to be parsed. Based on the processor and compute unit power indicators in the benchmark test, the computational complexity parameter is used to calculate the computational time required for the database page being queried in the processor and compute units.

[0083] The third preset threshold is set according to the computation time of the computation task in the computation unit and the processor. Optionally, the processor predicts the selection ratio parameter to obtain the predicted selection ratio parameter, and based on the predicted selection ratio parameter, predicts the amount of page data that needs to be accessed after the filtering calculation is completed, the host side memory access delay time, the accelerator device side memory access delay time, and the memory access delay time between the host and the speed device. Further, based on the amount of page data that needs to be accessed after the filtering calculation is completed, the host side memory access delay time, the accelerator device side memory access delay time, and the memory access delay time between the host and the speed device, the third preset threshold is determined.

[0084] S503, the processor 201, if it is determined that the accelerator device is to execute, allocates the page data of the database page corresponding to the data processing instruction to the memory page in the device-side memory 106 according to the preset memory allocation rule, and sends the data transmission instruction to the external memory controller 206.

[0085] It is possible that the processor 201 can query the key-value container corresponding to the page data based on the file name, and calculate the file offset parameter corresponding to the page data, and then query whether there is a memory page corresponding to the page data in the host side memory 205 or the device side memory 106 based on the corresponding key-value container and file offset parameter. If so, there is no need to send the data transfer instruction to the external memory controller 206.

[0086] In one possible embodiment, the processor 201 allocates the page data of the database page corresponding to the data processing instruction to the free memory page in the device-side memory 106 if there is a free memory page in the device-side memory 106; otherwise, the memory page with the least number of uses in the device-side memory 106 is released, or the memory page with the least number of uses in the device-side memory 106 is migrated to the host memory to obtain a free memory page, and the page data of the database page corresponding to the data processing instruction is allocated to the free memory page in the device-side memory 106.

[0087] In one possible embodiment, if there are no free memory pages in the device-side memory 106, the processor 201 uses a preset algorithm to identify infrequently used memory pages in the device-side memory 106, and migrates the infrequently used memory pages to the host-side memory 205 through the direct memory access controller 108 to obtain free memory pages, and allocates the page data of the database page corresponding to the data processing instruction to the free memory page in the device-side memory 106.

[0088] Exemplarily, the prediction algorithm may be a Least Recently Used (LRU) algorithm.

[0089] In a possible implementation, the processor 201 points the key-value container of the page meta information of the least used memory page to the key-value container, to indicate that the least used memory page is cached only in the host-side memory (205).

[0090] In a possible implementation manner, before S503, the method further includes:

[0091] The processor 201 configures the cache attribute of the on-chip cache 104 to be a non-cache attribute, so that the external storage device 207 can access the on-chip cache 104 .

[0092] S504, the external memory controller 206 sends the page meta information of the page data of the database page corresponding to the data processing instruction in the external storage device 207 to the on-chip cache 104 of the accelerator device 10 through the cache consistency bus 30 according to the data transmission instruction, and sends the row data of the page data to the device-side memory 106 of the accelerator device 10 through the cache consistency bus 30.

[0093] S505 , the processor 201 synchronizes the data processing instruction to the row parser 1071 .

[0094] S506 , the row parser 1071 extracts page meta information from the on-chip cache 104 according to the data processing instruction, and processes the page meta information to obtain a memory access sequence list and calculation related information.

[0095] In one possible implementation, Figure 11 As shown, Figure 11 The logic diagram of the filtering calculation provided by the embodiment of the present application includes: a row parser 1071 extracts page meta information of multiple rows from the on-chip cache 104 according to the data processing instruction.

[0096] The row parser 1071 performs parallel calculations on page meta information of multiple rows to obtain offset position parameters and field lengths.

[0097] Specifically, the row parser 1071 parses the starting position of each row of row data in the page data from the page meta information, and then parses the starting position of the target column data in the page data as an offset position parameter and a field length from the page meta information.

[0098] The row parser 1071 merges and calculates the offset position parameter and the field length based on the bus access bit width parameter of the accelerator device to obtain the memory access order list, the field valid bit mask and the logical row number corresponding to the target row data. The calculation related information includes the field length, the field valid bit mask and the logical row number.

[0099] Specifically, the row parser 1071 combines the offset position parameter and the field length to calculate the starting and ending positions of the target column data to be accessed. Based on the starting and ending positions of the target column data to be accessed and the bus access bit width parameter of the accelerator device, the row parser 1071 obtains a memory access sequence list. The bits within the starting and ending positions are set to 1 to serve as the field validity bit mask.

[0100] In one possible implementation, the row parser 1071 merges and calculates the offset position parameter and the field length based on the bus access bit width parameter of the accelerator device to obtain a memory access list. The row parser 1071 sorts the memory access list in address incrementing order to obtain a memory access sequence list.

[0101] S507 , the row parser 1071 accesses the device-side memory 106 according to the memory access order list to read the corresponding target row data into the column filter 1072 , and passes the calculation-related information to the column filter 1072 .

[0102] S508, column filter 1072, used to perform filtering calculation according to target row data and calculation related information to obtain filtering calculation results.

[0103] Specifically, the column filter 1072 accepts target row data of a bus bit width length at a time, extracts target column data from the target row data according to the field valid bit mask, performs filtering calculation on the target column data, and determines whether the target row data meets the filtering conditions according to the logical row number to obtain the filtering calculation result.

[0104] The data format of the filter calculation result is one of a bitmap format, an index format, and a tuple format.

[0105] Bitmap format: Uses one bit to represent each row of page data. A bit value of 1 indicates that the row meets the filter criteria; otherwise, it does not. For example, a database page is 8KB in size and can theoretically store up to 256 rows of data. A 256-bit bitmap is used to represent the filter calculation results for each row. After the processor reads the filter calculation results in bitmap format, it executes column parsing logic to find the target column field. This format is suitable for scenarios where a large number of results are returned.

[0106] Index format: This format uses row numbers and column offsets to represent the row numbers that meet the filter criteria and the offset values ​​of the columns selected by the selection clause within the page. After reading the index, the processor directly reads the columns based on the row numbers and column offsets without parsing the column positions. This format is suitable for scenarios with a high selectivity ratio, many columns, but a small number of selected columns.

[0107] Tuple format: The computing unit reorganizes the columns and fields that meet the conditions in a row into a row tuple data according to the storage format of the database row. The tuple header marks the valid length of the tuple data. The processor can directly read the tuple data as the row data corresponding to the filter calculation result. It is suitable for scenarios with a low selectivity ratio and a small number of selected columns and fields.

[0108] S509 : The processor 201 reads the filtering calculation result from the column filter 1072 .

[0109] In a possible implementation, S509 includes S5091-S5094:

[0110] S5091 , column filter 1072 , determines cache evaluation parameters corresponding to page data according to the filtering calculation result, where the page data includes row data that meets the filtering condition.

[0111] Specifically, the column filter 1072 counts the proportion of row data meeting the filtering conditions to page data, determines it as the selection ratio parameter, and counts the total length of the target column field in the row data meeting the filtering conditions, determines it as the field total length parameter.

[0112] S5092: The processor 201 reads cache evaluation parameters from the column filter 1072. The cache evaluation parameters include a field total length parameter and a selection ratio parameter.

[0113] In a possible implementation manner, before S5093, the process further includes:

[0114] If the page data is cached in the host memory 205 , the processor 201 reads the page data from the host memory 205 and reads the filtering calculation result in the index format or bitmap format from the column filter 1072 according to the field total length parameter.

[0115] Specifically, when the page data is cached in the host-side memory 205, since the processor 201 has better reading performance in the host-side memory 205 than in the device-side memory 106, the page data is read from the host-side memory 205. If the field total length parameter is greater than the first preset threshold, the processor 201 reads the filtering calculation result in the bitmap format from the column filter 1072; otherwise, the processor 201 reads the filtering calculation result in the index format from the column filter 1072.

[0116] S5093, processor 201, if the total field length parameter is greater than the first preset threshold, synchronizes the page data to the host side memory 205 through the direct memory access controller 108, and reads the filtering calculation result in the index format or bitmap format from the column filter 1072 according to the total field length parameter.

[0117] S5094, processor 201, if the field total length parameter is less than or equal to the first preset threshold, then read the filter calculation result from the column filter 1072 according to the selection ratio parameter, including: if the selection ratio parameter is greater than the second preset threshold, configure the cache attribute of the page data to maintain cache consistency with the host 20, and read the filter calculation result in the index format or bitmap format from the column filter 1072; otherwise, configure the cache attribute of the page data not to maintain cache consistency with the host 20, and read the filter calculation result in the tuple format from the column filter 1072.

[0118] Specifically, such as Figure 10 As shown, Figure 10 A logical diagram of reading the filtering calculation results provided in an embodiment of the present application is provided. The processor reads the filtering calculation results in different data formats according to the cache evaluation parameters, and reads the page data from the device side memory or the host side memory.

[0119] If the cache attribute of the configured page data is cache consistent with that of the host 20, then when the processor 201 reads the page data, the page data will enter the processor cache 2011. If the cache attribute of the configured page data is not cache consistent with that of the host 20, then when the processor 201 reads the page data, the page data will not enter the processor cache 2011. Figure 9 As shown, Figure 9 A schematic diagram of cache attribute configuration provided for an embodiment of the present application reduces the memory access latency of the accelerator device and improves the computing performance of the computer system by configuring the cache attributes of the device-side memory and on-chip cache, as well as the key-value container corresponding to the host-side memory page meta information.

[0120] In a possible implementation, the cache attribute of the page data in the host-side memory 205 is a read-only attribute, and further includes:

[0121] The processor 201 obtains a data write instruction. The data write instruction is triggered by a user and is used to write page data in the host-side memory 205 .

[0122] Processor 201, if the address pointed to by the key-value container corresponding to the page meta information of the page data in the host-side memory 205 is the address range corresponding to the device-side memory 106, then a synchronous write operation is performed on the page data in the host-side memory 205 and the corresponding page data in the device-side memory 106; otherwise, the read-only attribute corresponding to the cache attribute of the page data in the host-side memory 205 is canceled, and a write operation is performed on the page data in the host-side memory 205.

[0123] S510: The processor 201 executes a data processing instruction according to the filtering calculation result to obtain a processing result, and outputs the processing result.

[0124] In a possible implementation, the processor 201 obtains a page migration instruction triggered by a user, where the page migration instruction includes a file identifier, a migration page table, and a callback function.

[0125] The processor 201 determines a corresponding key-value container according to the file identifier.

[0126] The processor 201 allocates cache in the host-side memory 205 according to the migration page table and the key-value container, and migrates the page data corresponding to the migration page table from the device-side memory 106 to the host-side memory 205 through the direct memory access controller 108.

[0127] Processor 201 executes the callback function to feedback to the user that the page migration instruction is executed successfully.

[0128] The data processing method provided by the embodiment of the present application reduces the memory access waiting time of the computing unit and improves the performance of the computing unit by storing the page meta information that must be accessed in the on-chip high-speed cache with a higher read and write speed, and storing the row data that is accessed in small quantities in the device-side memory with a lower read and write speed. The computing task is decomposed into two parts: filtering calculation and result reading, which are completed by the accelerator device and the host processor respectively to give full play to their respective performance advantages. In addition, by caching evaluation parameters, filtering calculation results of different data formats are read from the column filter, and cache consistency of inconsistent page data is configured, so that the processor does not need to read redundant data that does not meet the filtering conditions, thereby improving the data processing efficiency of the computing system.

[0129] In addition, since the processor's reading performance in the host-side memory is lower than that in the device-side memory, when the page data is cached in the host-side memory, the processor gives priority to reading the page data from the host-side memory, reducing the processor's memory access latency.

[0130] Furthermore, by configuring the cache attribute of the page data in the host side memory as a read-only attribute, the processor is prevented from arbitrarily writing to the page data in the host side memory without synchronizing it to the accelerator device, thereby reducing a large amount of access overhead and improving the performance of the accelerator device.

[0131] Furthermore, by configuring the cache attribute of the on-chip cache to be a non-cache attribute, the external storage device can access the on-chip cache, thereby improving the access performance of the accelerator device to page data.

[0132] In addition, by presetting computing task allocation rules, computing tasks are dynamically allocated to the host or accelerator device for execution, thereby improving the computing efficiency of the computer system.

[0133] The row parser can simultaneously extract and process page meta information of multiple rows from the on-chip cache, thereby improving the computing performance of the accelerator device.

[0134] By sorting the memory access list and accessing the device side memory according to the memory access order list to read the corresponding target row data into the column filter, the memory access efficiency of the accelerator device is improved compared with random memory access.

[0135] By presetting memory allocation rules, page data is allocated to device-side memory first to reduce the access delay of accelerator devices during the calculation process.

[0136] Through a preset algorithm, infrequently used memory pages in the device-side memory are identified, and through a direct memory access controller, infrequently used memory pages are migrated to the host-side memory to obtain free memory pages, thereby improving the memory resource utilization of the computer system.

[0137] Through page migration instructions and direct memory access controller, data can be migrated between the host and accelerator devices at high speed.

[0138] By pointing the key-value container of the page meta information of the least used memory page to the key-value container, the access delay of the processor in repeatedly querying whether there is a cache in the device-side memory is reduced.

[0139] In one possible implementation, Figure 6 As shown, Figure 6 This is a flowchart of a file reading process provided in an embodiment of the present application. A user reads a file through a computer system provided in an embodiment of the present application, as shown in steps S601 to S608 below, including:

[0140] S601: Find a key-value container representing a file cache based on the file name. The processor can find the file's index number through the file path. Each file has a unique index number, and each index corresponds to a key-value container (usually a radix tree) representing the cache of the file page.

[0141] S602: The processor calculates the file page offset of the read offset position, including: the write function needs to pass the write offset of the file, and the write offset is divided by the size of the memory page and rounded to obtain the file page offset.

[0142] S603. The processor searches the key-value container for a corresponding memory page by searching the file page offset. This includes calling the search function of the key-value container, passing in the file page offset to check whether it is greater than 0. If the return value is greater than 0, it indicates the address of the memory page, and the process proceeds to step S604. Otherwise, the page does not exist, and the process proceeds to step S608.

[0143] S604: Determine whether there are free pages in the device side memory. If yes, execute S606; otherwise, execute S605.

[0144] S605: Release the least recently used page in the device-side memory.

[0145] S606: Allocate memory pages in the device side memory.

[0146] S607: Read data from the external storage device to the corresponding memory page of the device-side memory.

[0147] S608, copying the memory page content to the memory pointed to by the read function parameter, including: the user reads data through the read function, the function passes a parameter pointing to the target memory first address, and copies the data in the cache page to the memory first address parameter of the read function.

[0148] In one possible implementation, Figure 7 As shown, Figure 7 This is a flowchart of a file writing process provided in an embodiment of the present application. A user writes a file through the computer system provided in an embodiment of the present application. The following steps S701 to S718 include:

[0149] S701: Find a key-value container representing a file cache based on the file name. The processor can find the file's index number through the file path. Each file has a unique index number, and each index corresponds to a key-value container (usually a radix tree) representing the cache of the file page.

[0150] S702. The processor calculates the file page offset of the write offset position, including: the write function needs to pass the write offset of the file, and the write offset is divided by the size of the memory page and rounded to obtain the file page offset.

[0151] S703. The processor searches the key-value container for a corresponding memory page by searching the file page offset. This includes calling the search function of the key-value container, passing in the file page offset to check whether it is greater than 0. If the return value is greater than 0, it indicates the address of the memory page, and the process proceeds to step S710. Otherwise, the page does not exist, and the process proceeds to step S704.

[0152] S704: Determine whether there are free pages in the device side memory. If yes, execute S705; otherwise, execute S708.

[0153] S705: Allocate memory pages in the device memory.

[0154] S706: Determine whether the write length is greater than the memory page size. If so, execute S707; otherwise, execute S712.

[0155] S707. Copy the memory pointed to by the write function parameter to the memory page, including: the write function will pass in the memory where the source address is located, and copy the memory content where the source address is located to the page. The copy length is the length passed in by the write function parameter.

[0156] S708: Release the least recently used page in the device-side memory.

[0157] S709 , determine whether the page has a page copy in the host-side memory, if yes, execute S710 , otherwise execute S705 .

[0158] S710 , finding a page copy in the host-side memory, including: searching a key-value container for a corresponding value that is the host-side page meta-information according to the file offset in the page meta-information.

[0159] S711: For the page meta information in the host-side memory page copy, modify the key-value container pointer to point to the key-value container. This indicates that the file offset position is only cached on the host side.

[0160] S712: Read data from the external storage device to the memory page of the device-side memory.

[0161] S713: Determine whether the page belongs to the host side. If yes, execute S714; otherwise, execute S707.

[0162] S714. Copy the memory pointed to by the write function parameter to the memory page, including: the write function will pass in the memory where the source address is located, and copy the memory content where the source address is located to the page. The copy length is the length passed in by the write function parameter.

[0163] S715 , triggering a read-only exception handling function, including: setting the page attribute of the corresponding page to read-only, and triggering the read-only exception handling function when writing data to the address.

[0164] S716. In the read-only exception handling function, determine whether the page has a page copy in the device side memory. If so, execute S717; otherwise, execute S718.

[0165] S717 , find the page meta information of the page according to the key-value container pointer in the page meta information, then find the page copy in the device-side memory through the page meta information, and execute S707 .

[0166] S718: Cancel the read-only attribute of the page. If it is found that the key-value container pointer in the host-side memory page meta-information does not point to the device-side memory address range, it means that the memory copy of the page in the device-side memory has been released and no data synchronization is required, so the read-only attribute of the page is canceled.

[0167] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0168] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0169] The accelerator device, computer system, and data processing method provided by the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. An accelerator device (10), characterized in that include: On-chip interconnect network (103), on-chip cache (104), memory controller (105), device-side memory (106), and computing unit (107); The on-chip interconnect network (103) is communicatively connected to the computing unit (107), the on-chip interconnect network (103) is communicatively connected to the on-chip cache (104), the on-chip interconnect network (103) is communicatively connected to the memory controller (105), the memory controller (105) is communicatively connected to the device-side memory (106), and the on-chip cache (104) is communicatively connected to the computing unit (107); The on-chip interconnection network (103) is used to receive page data of a database page transmitted by a host (20) via a cache coherence bus (30); the on-chip cache (104) is used to store page meta information of the page data; and the device-side memory (106) is used to store row data of the page data. The computing unit (107) is configured to extract page meta information from the on-chip cache (104); read corresponding target row data from the device-side memory (106) by accessing the memory controller (105); and perform filtering calculations based on the target row data and the page meta information to obtain filtering calculation results.

2. The accelerator device (10) according to claim 1, characterized in that wherein the computing unit (107) includes a row parser (1071) and a column filter (1072); The row parser (1071) is in communication with the on-chip cache (104), and the row parser (1071) is in communication with the column filter (1072); The row parser (1071) is used to extract page meta information from the on-chip cache (104), and process the page meta information to obtain a memory access sequence list and calculation related information; The row parser (1071) is used to access the device-side memory (106) according to the memory access order list to read the corresponding target row data into the column filter (1072), and pass the calculation related information to the column filter (1072); The column filter (1072) is used to perform filtering calculation according to the target row data and the calculation related information to obtain filtering calculation results.

3. The accelerator device (10) according to claim 1, characterized in that Also includes: Direct Memory Access Controller (108); The direct memory access controller (108) is communicatively connected to the on-chip cache (104); The direct memory access controller (108) is used to synchronize page data corresponding to the filter calculation result from the device side memory (106) to the host (20).

4. A computer system, characterized in that: include: A host (20) and an accelerator device (10) according to any one of claims 1 to 3; The host (20) includes: a processor (201), an internal interconnect bus (202), a root agent module (203), a host memory controller (204), a host-side memory (205), an external memory controller (206) and an external storage device (207); the processor (201) has a processor cache (2011); The processor (201) is communicatively connected to the internal interconnect bus (202), the external memory controller (206) is communicatively connected to the internal interconnect bus (202), the root agent module (203) is communicatively connected to the internal interconnect bus (202), the external memory controller (206) is communicatively connected to the external storage device (207), the root agent module (203) is communicatively connected to the accelerator device (10) via a cache coherence bus (30), the third segment of the root agent module (203) is communicatively connected to the host memory controller (204), and the host memory controller (204) is communicatively connected to the host-side memory (205).

5. A data processing method, characterized in that: Applied to an accelerator device (10), the accelerator device (10) includes an on-chip interconnect network (103), an on-chip cache (104), a memory controller (105), a device-side memory (106), and a computing unit (107), the method comprising: An on-chip interconnection network (103) receives page data of a database page transmitted by a host (20) via a cache coherence bus (30); An on-chip cache (104) receives page meta information of the page data sent by the on-chip interconnection network (103) and stores the page meta information of the page data; The device-side memory (106) receives the row data of the page data sent by the on-chip interconnection network (103) and stores the row data of the page data; The computing unit (107) extracts page meta information from the on-chip cache (104); The calculation unit (107) reads the corresponding target row data from the device side memory (106) by accessing the memory controller (105); performs filtering calculation according to the target row data and the page meta information to obtain a filtering calculation result.

6. The data processing method according to claim 5, characterized in that: The host comprises a processor (201), a host-side memory (205), an external memory controller (206), and an external storage device (207); the computing unit (107) comprises a row parser (1071) and a column filter (1072); The method further comprises: The processor (201) obtains a data processing instruction, wherein the data processing instruction is triggered by a user; The processor (201), in response to the data processing instruction, determines whether the corresponding computing task is to be executed by the accelerator device (10) or the host (20) according to a preset computing task allocation rule; The processor (201), if it is determined that the accelerator device is to execute, allocates the page data of the database page corresponding to the data processing instruction to the memory page in the device-side memory (106) according to the preset memory allocation rule, and sends the data transmission instruction to the external memory controller (206); The external memory controller (206) sends page meta information of the page data of the database page corresponding to the database processing instruction in the external storage device (207) to the on-chip cache (104) of the accelerator device (10) through the cache coherence bus (30) according to the data transmission instruction, and sends row data of the page data to the device-side memory (106) of the accelerator device (10) through the cache coherence bus (30); The processor (201) synchronizes the data processing instructions to the line parser (1071); The row parser (1071) extracts page meta information from the on-chip cache (104) according to the data processing instruction, and processes the page meta information to obtain a memory access sequence list and calculation related information; The row parser (1071) accesses the device-side memory (106) according to the memory access order list to read the corresponding target row data into the column filter (1072), and passes the calculation related information to the column filter (1072); The column filter (1072) is used to perform filtering calculation according to the target row data and the calculation related information to obtain filtering calculation results; The processor (201) reads the filtering calculation result from the column filter (1072); The processor (201) executes a data processing instruction according to the filtering calculation result to obtain a processing result, and outputs the processing result.

7. The data processing method according to claim 6, characterized in that: The processor (201) reads the filtering calculation result from the column filter (1072), including: The column filter (1072) determines, based on the filtering calculation result, a cache evaluation parameter corresponding to the page data, the page data including row data that meets the filtering condition; The processor (201) reads the cache evaluation parameters from the column filter (1072), wherein the cache evaluation parameters include a field total length parameter and a selection ratio parameter; The processor (201) synchronizes the page data to the host-side memory (205) through a direct memory access controller (108) if the field total length parameter is greater than a first preset threshold, and reads the filtering calculation result in an index format or a bitmap format from the column filter (1072) according to the field total length parameter; The processor (201) reads the filtering calculation result from the column filter (1072) according to the selection ratio parameter if the field total length parameter is less than or equal to a first preset threshold value, including: if the selection ratio parameter is greater than a second preset threshold value, configuring the cache attribute of the page data to maintain cache consistency with the host (20), and reading the filtering calculation result in an index format or a bitmap format from the column filter (1072); otherwise configuring the cache attribute of the page data not to maintain cache consistency with the host (20), and reading the filtering calculation result in a tuple format from the column filter (1072).

8. The method according to claim 7, characterized in that The processor (201), if the field total length parameter is greater than a first preset threshold, synchronizes the page data to the host side memory (205), and reads the filtering calculation result in the index format or the bitmap format from the column filter (1072), further comprising: The processor (201) reads the page data from the host side memory (205) if the page data is cached in the host side memory (205), and reads the filtering calculation result in the index format or the bitmap format from the column filter (1072) according to the field total length parameter.

9. The method according to claim 7 or 8, characterized in that The cache attribute of the page data in the host side memory (205) is a read-only attribute, and further includes: The processor (201) obtains a data write instruction, wherein the data write instruction is triggered by a user and is used to perform a write operation on the page data in the host-side memory (205); The processor (201) performs a synchronous write operation on the page data in the host-side memory (205) and the corresponding page data in the device-side memory (106) if the address pointed to by the key-value container corresponding to the page meta information of the page data in the host-side memory (205) is the address range corresponding to the device-side memory (106); otherwise, cancels the read-only attribute corresponding to the cache attribute of the page data in the host-side memory (205) and performs a write operation on the page data in the host-side memory (205).

10. The method according to claim 6, characterized in that Before the page meta information of the page data of the database page corresponding to the database processing instruction in the external storage device (207) is sent to the on-chip cache (104) of the accelerator device (10) through the cache coherence bus (30) according to the data transmission instruction, the method further includes: The processor (201) configures the cache attribute of the on-chip cache (104) to be a non-cache attribute, so that the external storage device (207) can access the on-chip cache (104).

11. The method according to claim 6, characterized in that The processor (201), in response to the data processing instruction, determines whether the corresponding computing task is to be executed by the accelerator device or the host according to a preset computing task allocation rule, including: The processor (201) determines a corresponding computational complexity parameter according to the data processing instruction; The processor (201) allocates the computing task to the host (20) for execution if the page data corresponding to the computing task is cached in the host-side memory (205), the page data corresponding to the computing task is not cached in the device-side memory (106), and the computing complexity parameter is less than or equal to a third preset threshold; The processor (201) allocates the computing task to the host (20) for execution if the page data corresponding to the computing task is not cached in the host-side memory (205), the page data corresponding to the computing task is not cached in the device-side memory (106), and the computing complexity parameter is less than or equal to a third preset threshold; The processor (201) allocates the computing task to the accelerator device (10) for execution if the page data corresponding to the computing task is cached in the host-side memory (205) and the page data corresponding to the computing task is cached in the device-side memory (106); The processor (201) allocates the computing task to the accelerator device (10) for execution if the page data corresponding to the computing task is cached in the host-side memory (205), the page data corresponding to the computing task is not cached in the device-side memory (106), and the computing complexity parameter is greater than a third preset threshold; The processor (201) allocates the computing task to the accelerator device (10) for execution if the page data corresponding to the computing task is not cached in the host-side memory (205) and the page data corresponding to the computing task is cached in the device-side memory (106); The processor (201) allocates the computing task to the accelerator device (10) for execution if the page data corresponding to the computing task is not cached in the host-side memory (205), the page data corresponding to the computing task is not cached in the device-side memory (106), and the computing complexity parameter is greater than a third preset threshold.

12. The method according to claim 6, characterized in that The row parser (1071) extracts page meta information from the on-chip cache (104) according to the data processing instruction, and processes the page meta information to obtain a memory access sequence list and calculation related information, including: The row parser (1071) extracts page meta information of a plurality of rows from the on-chip cache (104) according to the data processing instruction; The line parser (1071) performs parallel calculations on the page meta information of multiple lines to obtain offset position parameters and field lengths; The row parser (1071) performs a merge calculation on the offset position parameter and the field length based on the bus access bit width parameter of the accelerator device to obtain a memory access order list, a field valid bit mask and a logical row number corresponding to the target row data, wherein the calculation related information includes the field length, the field valid bit mask and the logical row number.

13. The method according to claim 12, characterized in that The line parser (1071) performs a merge calculation on the offset position parameter and the field length based on the bus access bit width parameter of the accelerator device to obtain a memory access sequence list, including: The line parser (1071) performs a merge calculation on the offset position parameter and the field length based on the bus access bit width parameter of the accelerator device to obtain a memory access list; The row parser (1071) sorts the memory access list in the order of increasing addresses to obtain a memory access sequence list.

14. The method according to claim 6, characterized in that The allocating the page data of the database page corresponding to the data processing instruction to the memory page in the device side memory (106) according to the preset memory allocation rule includes: The processor (201) allocates the page data of the database page corresponding to the data processing instruction to the free memory page in the device-side memory (106) if there is a free memory page in the device-side memory (106); otherwise, releases the memory page with the least number of uses in the device-side memory (106), or migrates the memory page with the least number of uses in the device-side memory (106) to the host memory to obtain a free memory page, and allocates the page data of the database page corresponding to the data processing instruction to the free memory page in the device-side memory (106).

15. The method according to claim 14, characterized in that Also includes: The processor (201) identifies infrequently used memory pages in the device-side memory (106) through a preset algorithm if no free memory pages exist in the device-side memory (106), and migrates the infrequently used memory pages to the host-side memory (205) through a direct memory access controller (108) to obtain free memory pages, and allocates page data of the database page corresponding to the data processing instruction to the free memory pages in the device-side memory (106).

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