Cross-clock multi-module integrated FPGA real-time signal processing structure and method

Abstract

The invention discloses a cross-clock multi-module integrated FPGA (Field Programmable Gate Array) real-time signal processing structure and a cross-clock multi-module integrated FPGA real-time signal processing method, and the technical scheme of the invention not only can improve the efficiency and the real-time performance of the existing FPGA signal processing and ensure the continuity of the signal, but also can have universality for problem scenes with high real-time performance requirements and different data processing models and modules, and can be widely applied to the field of data processing. The method is especially suitable for the fields of signal detection, image processing, communication, radar and the like, and has a wide application prospect. According to the method, an integrated learning concept is introduced to integrate a plurality of same real-time processing modules to realize synchronization of reasoning time and integer multiple data frame generation time, so that the aim of uninterruptedly outputting reasoning results in high real time is fulfilled. According to the invention, a plurality of processing modules are integrated into the system through integrated design, and the real-time processing capability of the whole system is improved through FPGA parallel computing and cross-clock domain frequency raising, so that large-scale signal data can be efficiently and quickly processed in a high-real-time task.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, is a module framework for improving the real-time performance of real-time signal processing, and relates to a cross-clock multi-module integrated FPGA real-time signal processing structure and method. Background Art

[0002] FPGAs, due to their flexibility, high performance, low latency, and customizability, have been widely used in the field of real-time signal processing in communications. With the continuous advancement of signal processing technology, the difficulty and complexity of implementing real-time signal processing modules are bound to affect the high timeliness of FPGAs, leading to a mismatch between the requirements of real-time signal processing scenarios. Currently, improving FPGA performance in real-time signal processing mainly relies on optimizing individual modules, such as increasing clock frequency, compression accuracy, and hardware acceleration design. However, these approaches offer limited efficiency gains when processing complex tasks, and are particularly prone to bottlenecks when processing large amounts of real-time data. Currently, most real-time signal processing modules are unable to output an inference result within a single data frame to meet high real-time requirements. Therefore, external memory is still required to cache data. However, in complex communication systems, this undoubtedly increases access time for external devices and hardware costs. Furthermore, blindly increasing clock frequency can lead to difficulties in FPGA wiring and reduced execution performance. More critically, systems that can output results within a single data frame often lack the corresponding output processing methods to fully recover the continuous waveform. Therefore, the development of a new real-time signal processing module framework is urgently needed.

[0003] Ensemble learning is a method in machine learning that improves overall performance by collaborating multiple sub-models. Its core concept is to combine the strengths of multiple models to offset the shortcomings of a single model. Inspired by this concept, we have achieved a breakthrough in real-time signal processing performance by integrating multiple lightweight processing modules into FPGAs and enabling them to work together. Summary of the Invention

[0004] The present invention addresses the aforementioned shortcomings by providing a cross-clock, multi-module integrated FPGA real-time signal processing structure and method. This invention integrates multiple lightweight processing modules within the FPGA, creating an efficient modular parallel processing framework. Each lightweight submodule acts as a "weak classifier" in ensemble learning. These modules work collaboratively via a unified hardware bus to achieve real-time processing of complex signals.

[0005] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0006] A cross-clock multi-module integrated FPGA real-time signal processing structure includes a real-time acquisition module, a real-time processing module, an acquisition module main frequency clock, and a real-time output module. The real-time acquisition module is used to acquire data in real time. The real-time acquisition module and the real-time output module are both connected to the acquisition module main frequency clock signal. The real-time processing module includes a first asynchronous data FIFO, an integration module, a frequency-increasing high-speed clock, and a second asynchronous data FIFO. The real-time acquisition module can input data into the integration module via the first asynchronous data FIFO, and the integration module can output processed data to the real-time output module via the second asynchronous data FIFO. The input end of the first asynchronous data FIFO and the output end of the second asynchronous data FIFO are connected to the acquisition module main frequency clock signal, and the output end of the first asynchronous data FIFO and the input end of the second asynchronous data FIFO are connected to the frequency-increasing high-speed clock signal. The frequency of the frequency-increasing high-speed clock is higher than the acquisition module main frequency clock. The integration module is provided with multiple lightweight submodules, each of which processes a portion of the data and splices the processed data before outputting it via the second asynchronous data FIFO.

[0007] To optimize the above technical solutions, specific measures taken also include:

[0008] Each lightweight sub-module has the same processing structure and parameters, and the lightweight sub-modules realize coordinated data transmission and processing through the hardware bus.

[0009] A cross-clock multi-module integrated FPGA real-time signal processing method, using the above-mentioned cross-clock multi-module integrated FPGA real-time signal processing structure, includes the following steps:

[0010] Step 1: Lightweight the real-time processing module by compressing its weights and parameters from high-precision floating-point representation to low-precision floating-point representation;

[0011] Step 2: The real-time acquisition module acquires data in real time at the frequency set by the acquisition module main frequency clock and transmits it to the real-time processing module. The real-time processing module outputs the processed data and records the initial acquisition data frame output frequency and the result data frame output frequency;

[0012] Step 3: Increase the clock frequency of the real-time processing module by increasing the high-speed clock frequency, so that the output frequency of the result data frame of the real-time processing module is synchronized with the acquisition data frame frequency of the k input real-time processing modules;

[0013] Step 4: Increase the number of lightweight submodules to k in the integrated module, with each k data frames forming a cycle. Every n*k+i data frames are input into the i-th lightweight submodule for calculation, where n is a natural number.

[0014] Step 5: Output the data frames generated by the lightweight submodule across the clock domain via the second asynchronous data FIFO and splice them into continuous data frames;

[0015] Step 6: The real-time output module receives the spliced continuous data frames and outputs the processed result as an oscillographic real-time signal.

[0016] In step 1, the real-time processing module is lightweighted, and the weights and parameters therein are compressed from 32-bit floating point numbers to 8-bit floating point numbers.

[0017] In step 2, the real-time acquisition module runs at the main frequency f0. The real-time acquisition module collects and outputs N data as a collection data frame, and the real-time output module outputs M data as a result data frame. The output frequency f1 of the collection data frame that needs to be recorded is expressed as follows:

[0018]

[0019] The initial result data frame is generated at a frequency of f out , due to the complexity of model processing relative to data acquisition, f out <f1。

[0020] The specific method of step 3 is: within the limited range of onboard hardware resources, the real-time processing module is up-converted. The up-converting factor x is expressed as follows:

[0021] f' out =x*f out

[0022] Among them, f' out The frequency of the data frame output after upconversion is increased to the point where the moment when the real-time processing module outputs the result is aligned with the moment when the k-th acquired data frame is acquired, thereby compressing the original data frame output time to k times the acquired data frame output time.

[0023] In step 4, k lightweight submodules process data so that the real-time processing module data frame output frequency is:

[0024] f o ” ut =k*x*f out .

[0025] In step 5, if the length of the spliced continuous data frame output by the second asynchronous data FIFO is consistent with the length of the collected data frame, the output end of the second asynchronous data FIFO is connected to the signal collection end clock; if the length of the spliced continuous data frame is inconsistent with the length of the collected data frame, the output end of the second asynchronous data FIFO adopts the clock frequency f2:

[0026]

[0027] At this time, the length of the spliced continuous data frames is consistent with the length of the acquired data frames.

[0028] The first asynchronous data FIFO and the second asynchronous data FIFO are both AXI Stream Data FIFOs.

[0029] The first asynchronous data FIFO and the second asynchronous data FIFO are connected to the real-time acquisition module, the real-time output module and the integration module signal by using an AXI-Stream data bus.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] First, the present invention integrates multiple real-time processing models to jointly handle a problem, transforming pipeline-style parallel threads into multi-module parallel threads, which is equivalent to expanding the bit width of the data processed at one time. In this way, the present invention can further improve the time efficiency of the real-time processing module.

[0032] Second, this invention introduces lightweight module model research theory, and the lightweight sub-module parameter sharing design significantly reduces storage requirements. Compared with traditional real-time processing modules, the acceleration effect is faster and hardware resource space is saved.

[0033] Third, the integrated processing module designed in the present invention improves the speed of signal processing while ensuring performance, completes the mapping of module addition to frequency multiplication, and reduces dependence on high-frequency clocks.

[0034] Fourth, it has wide applicability to real-time processing modules that can meet hardware requirements and can be extended to achievable lightweight neural network processing modules, providing new solutions to real-time requirements in actual communication scenarios.

[0035] Fifth, even if the onboard resources cannot meet the requirements of integrating modules with the corresponding multiples of synchronized data frames after frequency conversion, timeliness can be improved by integrating modules with fewer than the specified multiples and connecting to external cache devices using the frequency conversion-integration-frequency conversion framework in this article.

[0036] Sixth, the independent operation capability of each module of the present invention enables the system to have stronger anti-interference capability against abnormal signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is the overall flow chart of the present invention;

[0038] Figure 2 It is the overall framework diagram of the present invention;

[0039] Figure 3 It is a module initial data input processing diagram of the present invention;

[0040] Figure 4 It is a diagram of module frequency conversion and input data frame synchronization using the present invention;

[0041] Figure 5 This is an overall architecture diagram using signal anomaly detection as an example using the present invention.

[0042] The reference numerals are: real-time acquisition module 1, real-time processing module 2, first asynchronous data FIFO 21, integration module 22, lightweight sub-module 22a, frequency-upgraded high-speed clock 23, second asynchronous data FIFO 24, acquisition module main frequency clock 3, and real-time output module 4. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is described and illustrated below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely used to explain this application and are not intended to limit this application. Based on the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without making any creative efforts are within the scope of protection of this application.

[0044] Obviously, the drawings described below are merely examples or embodiments of the present application. Those skilled in the art can, without inventive effort, apply the present application to other similar scenarios based on these drawings. Furthermore, it is also understood that, although the effort involved in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, changes in design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as an insufficiency of the content disclosed in this application.

[0045] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments unless there is a conflict.

[0046] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "a", "an", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or units (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The words "multiple" / "several" used in this application refer to two or more. "And / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, or B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0047] This paper proposes a cross-clock, multi-module integrated FPGA real-time signal processing architecture and method. Inspired by the concept of ensemble learning, multiple lightweight sub-modules 22a are integrated into the FPGA, creating an efficient modular parallel processing framework. Each lightweight sub-module 22a acts as a "weak classifier" in ensemble learning. These lightweight sub-modules 22a work together via a unified hardware bus to achieve real-time processing of complex signals.

[0048] Unlike traditional hardware design approaches that optimize single modules, this invention significantly improves the parallelism and real-time performance of signal processing through modular integration, while reducing resource consumption. This design achieves a synergistic enhancement effect similar to ensemble learning at the hardware level, providing a new technical approach for real-time signal processing with significant advantages in timeliness.

[0049] The complete technical method of the present invention comprises the following steps:

[0050] Step 1: Perform lightweight processing on the real-time processing module 2, compressing the weights and parameters therein from high-precision floating-point representation to low-precision floating-point representation; reducing the complexity of model calculations and increasing the processing frequency of data frames per second.

[0051] Step 2: The real-time acquisition module 1 acquires data in real time at the frequency set by the acquisition module main frequency clock 3 and transmits it to the real-time processing module 2. The real-time processing module 2 outputs the processed data and records the initial acquisition data frame output frequency and the result data frame output frequency;

[0052] Step 3: Increase the clock frequency of the real-time processing module 2 by increasing the high-speed clock 23, so that the output frequency of the result data frame of the real-time processing module 2 is synchronized with the frequency of the collected data frames of the k input real-time processing modules 2;

[0053] Step 4: Increase the number of lightweight submodules 22a to k in the integrated module, with each k data frames forming a cycle, and inputting each n*k+i data frames into the i-th lightweight submodule 22a for calculation, where n is a natural number;

[0054] Step 5: The data frames generated by the lightweight submodule 22a are output across clock domains via the second asynchronous data FIFO and spliced into continuous data frames;

[0055] Step 6: The real-time output module 4 receives the spliced continuous data frames and outputs the processed result as an oscillographic real-time signal.

[0056] The invention will be further described below with reference to the accompanying drawings.

[0057] Combined with attachment Figure 1 The specific steps of the method of the present invention are described as follows.

[0058] Step 1: Lightweight processing of real-time processing module 2:

[0059] By lightweighting the real-time processing module 2 and compressing its weights and parameters from floating-point representation (such as 32 bits) to lower precision (such as 8 bits), it can significantly reduce computing and storage resource consumption, while reducing power consumption and increasing processing speed. Drawing on the knowledge of lightweight neural network models, the applicable parts are processed using lightweight methods such as network structure analysis, model pruning, low-rank decomposition, knowledge distillation, and parameter quantization. While ensuring the accuracy loss range under a certain signal-to-noise ratio, the module's computational complexity is reduced, thereby increasing the frequency of output data frames. At the same time, Xilinx's AXI-Stream streaming data bus is used to achieve efficient data transmission. This bus supports burst transmission mode and is very suitable for the transmission of large-scale continuous data streams. Handshake control is performed through simple valid signals, reducing additional logic overhead.

[0060] Step 2: Real-time acquisition module 1 acquires data and transmits it to real-time processing module 2. Real-time processing module 2 outputs processed data and records the initial acquisition data frame output frequency and the result data frame output frequency:

[0061] In the signal detection scenario, the real-time acquisition module 1 operates at the main frequency f0. After configuring the registers, the real-time acquisition module 1 collects and outputs N data as a data frame, and the real-time processing module 2 outputs M data as a result data frame. Then, the data frame output frequency f1 to be recorded is expressed as follows:

[0062]

[0063] As shown in the appendix Figure 3 As shown, the data frame is read out by the lightweight processing module IP core after being clipped by the synchronous clock data buffer. The data buffers used in this invention are all AXI Stream Data FIFOs. AXI Stream Data FIFO is a data buffer commonly used in FPGA development based on the AXI-Stream protocol. It can serve as an independent clock domain to connect two modules operating at different frequencies. In the current step, it is used as a synchronous data buffer. The model data deployed on the FPGA all adopts full-chip mapping to improve the timeliness and perform model processing, thereby obtaining the initial result data frame with a frequency of f out . Due to the complexity of model processing compared to data acquisition, f out < f1. Therefore, it is necessary to increase the clock frequency of the processing module to increase the frequency of the result data frame output by model processing.

[0064] Step 3, increase the clock frequency of the real-time processing module 2 by the up-converted high-speed clock 23:

[0065] Replace the synchronous data FIFO with an asynchronous data FIFO to enable cross-clock domain operation of the module. Considering the hardware conditions of the on-board clock resources and the operation efficiency of the module, by increasing the clock frequency, the output frequency of the model processing results is accelerated, thereby improving the timeliness of the hardware. As shown in the appendix Figure 4 As shown, within the limit of the on-board hardware resources, the frequency is increased until the moment when the model processing result is output is aligned with the clock of the kth acquired data frame (k = 4 in the legend). The read frequency of the asynchronous data FIFO is significantly faster than the write frequency. Both the write and read ports use the AXI-Stream data bus, and each burst transfers N data, which is aligned with the N data of the input data frame. After the AXI-Stream data bus successfully shakes hands between the slave and the master within one clock cycle, data transfer occurs within one clock cycle. Since the read clock is faster than the write clock, each data written at the acquisition end will be immediately read out. After reading out the data of a data frame, it is immediately input to the module for processing. In this way, the delay of the data input module is only one clock cycle after frequency conversion, thus achieving almost delay-free data frame transfer, so the time required for bus transmission can be ignored.

[0066] As shown in the attached figure, by increasing the frequency, the original data frame output time is compressed to k times the acquisition data frame output time. The frequency increase coefficient x is expressed as follows:

[0067] f' out =x*f out

[0068] At this time, the data frame frequency f' after the upconversion out ,The number of real-time processing modules 2 that need to be integrated is calculated.

[0069] Step 4: Increase the number of lightweight submodules 22a to k in the integrated module:

[0070] Increase the number of lightweight submodules 22a to k, Figure 5 As shown, it is integrated into the model framework. The attached figure shows anomaly detection for a disturbed continuous time-domain signal. The readout module in the framework uses the AXI-Stream bus to achieve high-speed data stream transmission, thereby reducing the data transmission delay and making the time occupied by this process negligible. In the high-real-time problem scenario, the data stream is transmitted continuously, so every k data frames constitutes a cycle, and every n*k+i (n is 1, 2, 3, ...) data frames are input into the i-th lightweight sub-module 22a in the framework for calculation. First, the parameters required by the lightweight sub-module 22a to be integrated are defined as parameter constants in the FPGA. Because these lightweight sub-modules 22a have the same processing structure and parameters, the parameters called by each lightweight sub-module 22a are consistent. These integrated lightweight sub-modules 22a do not need to store parameters repeatedly in their respective modules, but instead use shared parameters. This saves storage resources and completes the parameter deployment of the k-fold model. At the same time, both parameter and data caches are fully mapped on-chip, avoiding the increase in external memory access time.

[0071] Since the frequency increase in step 3 aligns the model processing time with the time length of the data frame, the time to process k data frames is exactly synchronized with the time of the k data frames generated by the acquisition end, further improving the timeliness of the module and eliminating the need to worry about data cache overflow. Therefore, the data FIFO used only requires the size of one data frame, reducing the use of logical resources. In this way, the model can be input in the order in which the data frames arrive, thereby outputting k data frames of processing results after the arrival delay of the kth data frame, obtaining a highly real-time model framework. The final result data frame output frequency expression is as follows:

[0072] f o ” ut =k*x*f out

[0073] The data frame output frequency obtained by the original frequency doubling is increased by k times. By adding a real-time processing model, the data frame processing output frequency is mapped from addition to multiplication. In the present invention, multiple lightweight sub-modules 22a are designed as independent hardware units, and each module focuses on processing different parts or specific features of the signal, which is consistent with the idea that the "individual model" in integrated learning focuses on different data characteristics. By integrating the output results of these modules, the FPGA significantly improves the overall performance. In addition, the present invention adopts a module parameter sharing design, so that the parameters of all modules only need to be stored once, thereby greatly reducing hardware resource consumption. At the same time, the real-time performance of the output signal is further improved through the parallelism of the modules. The collaboration and load balancing between modules optimize the processing efficiency of the overall system and achieve more efficient signal processing performance.

[0074] Step 5: splice the data frames generated by the lightweight submodule 22a, and then output the spliced continuous data frames across the clock domain via the second asynchronous data FIFO:

[0075] The time length of the data frame generated after frequency upscaling will be compressed. For real-time tasks, the input data is continuous and the output is usually continuous as well, so the compressed data frame time needs to be spliced. In this process, an asynchronous AXI-Stream data FIFO is connected for frequency downscaling. Both input and output use the AXI-Stream bus, but the clock at the output end is slower than the write port of the FIFO. We use this asynchronous data FIFO to achieve continuous waveform output of the output data frame. The technical details are described below. The output data frame of the integrated module is input into the asynchronous data FIFO through the AXI-Stream bus. If the output data frame length M is consistent with the acquisition data frame length N, the readout port is connected to the signal acquisition end clock. At this time, the frequency of the output data frame is consistent with the input frequency. If the output data frame lengths are different, the readout module is adjusted to use clock frequency f2:

[0076]

[0077] Among them, the clock of the write end is obviously faster than the read clock. Due to the discontinuity of the output result data frame of the write port, there is no result output in the time and space before the output of the next result data frame. At the same time, the time of outputting a data frame and the time of the next output data frame are exactly separated by the time of an input data frame. During this idle time of result output, the down-converting AXI-Stream data FIFO continuously outputs continuous result data waveforms, and finally achieves complete synchronization between the frequency of continuous output data frames and the frequency of input data frames of the integrated module. Therefore, in this case, the data written in the continuous data flow scenario will not be faster than the data read out, resulting in data accumulation and buffer overflow. Only a FIFO storage of the size of a data frame is required, which saves storage resources and ensures completely real-time output results. By delaying only one output result data frame, it is ensured that there is no idle time in the intermediate processing process, avoiding data accumulation and waiting. As shown in the attached Figure 5 As shown, in abnormal signal detection, abnormal bands can be detected in real time.

[0078] Step 6: Output the real-time signal of the processing result:

[0079] The oscilloscope outputs the integrated signal completely as a continuous waveform.

[0080] The above embodiments are preferred implementations of the present invention, but the implementation of the present invention is not limited to the embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be considered equivalent replacement methods and are included in the scope of protection of the present invention.

Claims

1. A cross-clock multi-module integrated FPGA real-time signal processing structure, characterized in that: The invention comprises a real-time acquisition module (1), a real-time processing module (2), an acquisition module main frequency clock (3), and a real-time output module (4). The real-time acquisition module (1) is used for real-time data acquisition. The real-time acquisition module (1) and the real-time output module (4) are both connected to the acquisition module main frequency clock (3) signal. The real-time processing module (2) comprises a first asynchronous data FIFO (21), an integration module (22), a frequency-increasing high-speed clock (23), and a second asynchronous data FIFO (24). The real-time acquisition module (1) can input data into the integration module (22) via the first asynchronous data FIFO (21), and the integration module (22) can output the processed data via the second asynchronous data FIFO (24). The data is output to a real-time output module (4); the input end of the first asynchronous data FIFO (21) and the output end of the second asynchronous data FIFO (24) are connected to the acquisition module main frequency clock (3) signal; the output end of the first asynchronous data FIFO (21) and the input end of the second asynchronous data FIFO (24) are connected to the high-speed clock (23) signal; the frequency of the high-speed clock (23) is higher than the acquisition module main frequency clock (3); a plurality of lightweight submodules (22a) are provided in the integrated module (22); each lightweight submodule (22a) processes a part of the data, and splices the processed data through the second asynchronous data FIFO (24) for continuous output.

2. The FPGA real-time signal processing structure with cross-clock multi-module integration according to claim 1 is characterized in that: Each lightweight submodule (22a) has the same processing structure and parameters, and the lightweight submodules realize coordinated data transmission and processing through a hardware bus.

3. A method for FPGA real-time signal processing with cross-clock multi-module integration, characterized by: Applying the cross-clock multi-module integrated FPGA real-time signal processing structure as described in claim 1 or 2 includes the following steps: Step 1: Perform lightweight processing on the real-time processing module (2), compressing the weights and parameters therein from high-precision floating-point representation to low-precision floating-point representation; Step 2: The real-time acquisition module (1) acquires data in real time at a frequency set by the acquisition module main frequency clock (3) and transmits the data to the real-time processing module (2). The real-time processing module (2) outputs the processed data and records the initial acquisition data frame output frequency and the result data frame output frequency; Step 3: increasing the clock frequency of the real-time processing module (2) by increasing the high-speed clock frequency (23), so that the output frequency of the result data frame of the real-time processing module (2) is synchronized with the acquisition data frame frequency of the k input real-time processing modules (2); Step 4: In the integrated module (22), the number of lightweight submodules (22a) is increased to k, each k data frames is a cycle, and each n*k+i data frames are input into the i-th lightweight submodule (22a) for calculation, where n is a natural number; Step 5: splicing the data frames generated by the lightweight submodule (22a) through the second asynchronous data FIFO (24), and then outputting the spliced continuous data frames across the clock domain; Step 6: The real-time output module (4) receives the spliced continuous data frames and outputs the processed result as an oscillographic real-time signal.

4. The FPGA real-time signal processing method with cross-clock multi-module integration according to claim 3 is characterized by: In step 1, the real-time processing module (2) is lightweighted, and the weights and parameters therein are compressed from 32-bit floating point numbers to 8-bit floating point numbers.

5. The FPGA real-time signal processing method with cross-clock multi-module integration according to claim 3 is characterized by: In step 2, the real-time acquisition module (1) operates at a main frequency f0. The real-time acquisition module (1) acquires and outputs N data as a collection data frame, and the real-time output module (4) outputs M data as a result data frame. The output frequency f1 of the collection data frame to be recorded is expressed as follows: The initial result data frame is generated at a frequency of f out , due to the complexity of model processing relative to data acquisition, f out <f1。 6. The FPGA real-time signal processing method with cross-clock multi-module integration according to claim 5 is characterized by: The specific method of step 3 is: within the limited range of onboard hardware resources, the real-time processing module (2) is frequency-upgraded, and the frequency-upgrade coefficient x is expressed as follows: f′ out =x*f out Among them, f′ out The frequency of the data frame output after the frequency up-conversion is increased so that the time when the real-time processing module (2) outputs the result is aligned with the time when the kth collected data frame is collected, thereby compressing the original data frame output time to k times the collected data frame output time.

7. The FPGA real-time signal processing method with cross-clock multi-module integration according to claim 6 is characterized by: In step 4, k lightweight submodules (22a) process data so that the data frame output frequency of the real-time processing module (2) is: f″ out =k*x*f out 。 8. The FPGA real-time signal processing method with cross-clock multi-module integration according to claim 3 is characterized by: In step 5, if the length of the spliced continuous data frame output by the second asynchronous data FIFO (24) is consistent with the length of the collected data frame, the output end of the second asynchronous data FIFO (24) is connected to the signal collection end clock; if the length of the spliced continuous data frame is inconsistent with the length of the collected data frame, the output end of the second asynchronous data FIFO (24) adopts the clock frequency f2: At this time, the length of the spliced continuous data frames is consistent with the length of the acquired data frames.

9. The FPGA real-time signal processing method with cross-clock multi-module integration according to claim 3 is characterized by: The first asynchronous data FIFO (21) and the second asynchronous data FIFO (24) are both AXI Stream Data FIFOs.

10. The FPGA real-time signal processing method with cross-clock multi-module integration according to claim 3 is characterized by: The first asynchronous data FIFO (21) and the second asynchronous data FIFO (24) are connected to the real-time acquisition module (1), the real-time output module (4) and the integration module (22) by using an AXI-Stream data bus.

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