Bus buffer driving circuit and integrated circuit chip

Abstract

The invention provides a bus buffer drive circuit and an integrated circuit chip, and relates to the technical field of semiconductors, and the bus buffer drive circuit comprises a bus signal anti-interference processing circuit, a hot plug and suspension processing circuit and a buffer drive circuit. Under the condition that a bus signal sent by an upper circuit is received, the on-off state of each switch tube in the anti-interference processing circuit is controlled based on the level change condition of the bus signal, so that anti-interference processing on the bus signal is realized by switching the on-off states of the switch tubes; and the hot plug and suspensible processing circuit is used for enabling the input end of the buffer driving circuit to keep a level in a determined state by utilizing a multi-stage phase inverter in the hot plug and suspensible processing circuit under the condition that a bus signal sent by the upper circuit is not received. According to the bus buffer driving circuit, the anti-interference, hot-plugging and suspending capabilities can be increased for the bus buffer driving circuit, so that the defects of larger PCB area, higher design difficulty, poor reliability, high failure rate and the like of a bus buffer driving integrated circuit chip are overcome.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a bus buffer driving circuit and an integrated circuit chip. Background Art

[0002] At present, traditional bus driver buffer integrated circuit chips have problems such as low transmission speed, poor anti-interference ability, poor signal compatibility, inability to implement hot plugging and floating, etc., which require the addition of matching resistors and capacitors in computer bus transmission design. This further causes traditional bus driver buffer integrated circuit chips to have many defects such as large PCB (Printed Circuit Board) board area, high design difficulty, poor reliability, and high failure rate. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a bus buffer driver circuit and an integrated circuit chip, which can increase the anti-interference, hot-swappable and floating capabilities of the bus buffer driver circuit, so as to improve the defects of the bus buffer driver integrated circuit chip, such as large PCB board area, high design difficulty, poor reliability and high failure rate.

[0004] In a first aspect, the present invention provides a bus buffer driving circuit, comprising: a bus signal anti-interference processing circuit, a hot-swappable and suspendable processing circuit, and a buffer driving circuit;

[0005] The input end of the bus signal anti-interference processing circuit is electrically connected to the output end of the upper circuit, and the output end of the bus signal anti-interference processing circuit is electrically connected to the input end of the buffer drive circuit. The bus signal anti-interference processing circuit is used to: when receiving a bus signal sent by the upper circuit, control the on-off state of each switch tube in the bus signal anti-interference processing circuit based on the level change of the bus signal, so as to realize anti-interference processing of the bus signal by switching the on-off state of the switch tube, and send the bus signal after anti-interference processing to the buffer drive circuit;

[0006] The input end of the hot-swappable and floatable processing circuit is electrically connected to the output end of the upper circuit, and the output end of the hot-swappable and floatable processing circuit is electrically connected to the input end of the buffer drive circuit. The hot-swappable and floatable processing circuit is used to: when not receiving a bus signal sent by the upper circuit, use the multi-stage inverter in the hot-swappable and floatable processing circuit to keep the input end of the buffer drive circuit at a certain state of electrical level.

[0007] In one embodiment, the bus signal anti-interference processing circuit includes a signal receiving subcircuit and an anti-interference subcircuit electrically connected in sequence:

[0008] The signal receiving subcircuit is used to: receive the bus signal sent by the upper circuit and reduce the voltage of the bus signal;

[0009] The anti-interference sub-circuit is used to control the on / off state of each MOS tube in the anti-interference sub-circuit based on the level change of the bus signal after the voltage is reduced.

[0010] In one embodiment, the signal receiving subcircuit is a MOS transistor, the gate and source of the MOS transistor in the signal receiving subcircuit are electrically connected to the output end of the upper circuit, and the drain of the MOS transistor in the signal receiving subcircuit is grounded.

[0011] In one embodiment, the anti-interference subcircuit includes a first switch tube group, a second switch tube group, and a positive feedback subcircuit, wherein the first switch tube group is connected to a power supply, and the second switch tube group is grounded;

[0012] When the bus signal after voltage reduction is at a high level, the first switch tube group is turned on and the second switch tube group is turned off, so as to provide a path from the power supply to the output end of the positive feedback sub-circuit;

[0013] When the bus signal after voltage reduction is at a low level, the first switch tube group is turned off and the second switch tube group is turned on to provide a path from the output end of the positive feedback sub-circuit to the ground.

[0014] In one embodiment, the first switch tube group includes a first MOS tube and a second MOS tube, the second switch tube group includes a third MOS tube and a fourth MOS tube, and the positive feedback sub-circuit includes a fifth MOS tube, a sixth MOS tube, and a seventh MOS tube;

[0015] The gates of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all electrically connected to the output end of the signal receiving sub-circuit;

[0016] The drain of the first MOS transistor and the source of the second MOS transistor are connected in series, and the source of the first MOS transistor and the source of the second MOS transistor are both connected to a power supply;

[0017] The source of the third MOS tube is connected in series with the drain of the fourth MOS tube, and the source of the third MOS tube and the source of the fourth MOS tube are both grounded;

[0018] The drain of the second MOS tube is connected to the drain of the third MOS tube, and the drain of the third MOS tube is connected to the gate of the fifth MOS tube, the gate of the sixth MOS tube, and the gate of the seventh MOS tube respectively;

[0019] The drain of the fifth MOS transistor is connected in series with the source of the sixth MOS transistor. The source of the fifth MOS transistor is connected to the drain of the first MOS transistor and the source of the second MOS transistor. The source of the fifth MOS transistor and the source of the sixth MOS transistor are both connected to another power supply.

[0020] The source of the seventh MOS transistor is grounded, and the drain of the seventh MOS transistor is connected to the source of the third MOS transistor and the drain of the fourth MOS transistor.

[0021] In one embodiment, the first MOS transistor, the second MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are all NMOS transistors, and the third MOS transistor, the fourth MOS transistor, and the seventh MOS transistor are all PMOS transistors.

[0022] In one embodiment, the hot-swappable and floating processing circuit includes a first-stage inverter and a second-stage inverter, and the first-stage inverter is complementary to the second-stage inverter.

[0023] In one embodiment, the first-stage inverter includes an NMOS transistor and a PMOS transistor;

[0024] The gate of the NMOS tube in the first-stage inverter is connected to the gate of the PMOS tube, the drain of the NMOS tube in the first-stage inverter is connected to the power supply, the source of the NMOS tube in the first-stage inverter is connected to the drain of the PMOS tube, and the source of the PMOS tube in the first-stage inverter is grounded.

[0025] In one embodiment, the second-stage inverter includes an NMOS transistor, a PMOS transistor, a Schottky diode, and two ordinary diodes;

[0026] The gate of the NMOS tube in the second-stage inverter is connected to the gate of the PMOS tube, the drain of the NMOS tube in the second-stage inverter is connected to another power supply, the source of the NMOS tube in the second-stage inverter, the Schottky diode, and the drain of the PMOS tube are connected in series, the source of the PMOS tube in the second-stage inverter is grounded, and the source and drain of the NMOS tube in the second-stage inverter are connected to two ordinary diodes respectively.

[0027] In a second aspect, the present invention further provides a bus buffer driver integrated circuit chip, which includes the bus buffer driver circuit provided in the first aspect.

[0028] The present invention provides a bus buffer drive circuit and an integrated circuit chip, comprising: a bus signal anti-interference processing circuit, a hot-swappable and suspendable processing circuit, and a buffer drive circuit; wherein the input end of the bus signal anti-interference processing circuit is electrically connected to the output end of the upper circuit, and the output end of the bus signal anti-interference processing circuit is electrically connected to the input end of the buffer drive circuit; the input end of the hot-swappable and suspendable processing circuit is electrically connected to the output end of the upper circuit, and the output end of the hot-swappable and suspendable processing circuit is electrically connected to the input end of the buffer drive circuit. When the bus signal sent by the upper circuit is received, the above method can control the on-off state of each switch tube in the bus signal anti-interference processing circuit based on the level change of the bus signal, so as to realize anti-interference processing of the bus signal by switching the on-off state of the switch tube; when the bus signal sent by the upper circuit is not received, the multi-stage inverter in the hot-swappable and floating processing circuit can be used to keep the input end of the buffer drive circuit at a certain state of level, thereby increasing the anti-interference, hot-swappable and floating capabilities of the bus buffer drive circuit, so as to improve the defects of the bus buffer drive integrated circuit chip such as large PCB board area, high design difficulty, poor reliability and high failure rate.

[0029] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 An application circuit diagram of a bus drive buffer circuit device provided by an embodiment of the present invention;

[0033] Figure 2 A circuit diagram of a conventional bus driver buffer integrated circuit chip provided by an embodiment of the present invention;

[0034] Figure 3 A logic block diagram of a bus buffer driving circuit provided by an embodiment of the present invention;

[0035] Figure 4 A bus signal anti-interference processing circuit diagram of a bus buffer driving circuit provided by an embodiment of the present invention;

[0036] Figure 5 A bus signal anti-interference processing circuit diagram of a bus buffer driving circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0038] When designing a computer system, Figure 1 The application circuit diagram of a bus driver buffer circuit shown in the figure usually uses a bus driver and buffer chip. Figure 2 The circuit diagram of a traditional bus driver buffer integrated circuit chip is shown. Traditional bus driver buffer integrated circuit chips have problems such as low transmission speed, poor anti-interference ability, poor signal compatibility, inability to hot plug and unplug, and inability to float. Therefore, matching resistors and capacitors need to be added in the computer bus transmission design to prevent abnormal changes in the signal when it is transmitted through the cable. This increases the area of the PCB board and increases the difficulty of design and debugging. At the same time, the reliability is poor and the failure rate is high.

[0039] Based on this, the present invention provides a bus buffer driving circuit and integrated circuit chip, which can increase the anti-interference, hot-swappable and floating capabilities of the bus buffer driving circuit, so as to improve the defects of the bus buffer driving integrated circuit chip such as large PCB board area, high design difficulty, poor reliability and high failure rate.

[0040] To facilitate understanding of this embodiment, a bus buffer driving circuit disclosed in an embodiment of the present invention is first introduced in detail.

[0041] An embodiment of the present invention provides a bus buffer driver circuit. Its bus control operation process is as follows: when the control terminal E = 1, the output = the input. At this time, the bus is driven by the device, and the data on the bus is determined by the input data. When the control terminal E = 0, the output terminal is in a high-impedance state, and the device has no effect on the bus. When the register output is connected to a tri-state gate, and the tri-state gate output is then connected to the bus, a three-state output buffer register is formed. A unidirectional tri-state gate is used, so data can only be output from the register to the data bus. For bidirectional transmission, a bidirectional tri-state gate can be used.

[0042] Based on the above bus control working process, see Figure 3 The bus buffer driving circuit shown is a logic block diagram of a bus buffer driving circuit. The bus buffer driving circuit can be applied to various types of bus driving buffer integrated circuit chips. The bus buffer driving circuit includes: a bus signal anti-interference processing circuit 1, a hot-swappable and floating processing circuit 2 and a buffer driving circuit 3.

[0043] In one example, the input end of the bus signal anti-interference processing circuit 1 is electrically connected to the output end of the upper circuit, and the output end of the bus signal anti-interference processing circuit 1 is electrically connected to the input end of the buffer driving circuit 3. The bus signal anti-interference processing circuit 1 is configured to: upon receiving a bus signal sent by the upper circuit, control the on / off state of each switch tube in the bus signal anti-interference processing circuit 1 based on the level change of the bus signal, so as to implement anti-interference processing of the bus signal by switching the on / off state of the switch tube, and send the bus signal after anti-interference processing to the buffer driving circuit 3;

[0044] In one example, the input end of the hot-swappable and floatable processing circuit 2 is electrically connected to the output end of the upper circuit, and the output end of the hot-swappable and floatable processing circuit 2 is electrically connected to the input end of the buffer driving circuit 3. The hot-swappable and floatable processing circuit 2 is configured to maintain the input end of the buffer driving circuit at a certain level by utilizing the multi-stage inverter within the hot-swappable and floatable processing circuit 2 when the hot-swappable and floatable processing circuit 2 does not receive a bus signal sent by the upper circuit.

[0045] The bus buffer driving circuit provided in the embodiment of the present invention adopts multiple circuit structures, including: bus signal anti-interference processing circuit, hot pluggable and floating processing circuit, and through circuit feedback and reducing the start-up time of internal components of the device, it can achieve improved transmission speed and increased anti-interference, hot pluggable and floating capabilities.

[0046] For ease of understanding, the embodiments of the present invention provide more detailed explanations of the aforementioned bus signal anti-interference processing circuit, hot-swappable and floating processing circuits.

[0047] (1) Bus signal anti-interference processing circuit: The embodiment of the present invention utilizes a bus signal anti-interference processing circuit to address the signal attenuation and deformation problems encountered during long-distance transmission of computer bus signals, thereby playing an anti-interference role. The circuit includes a signal receiving subcircuit and an anti-interference subcircuit electrically connected in sequence. The signal receiving subcircuit is used to receive the bus signal sent by the upper circuit and reduce the voltage of the bus signal; the anti-interference subcircuit is used to control the on / off state of each MOS tube in the anti-interference subcircuit based on the level change of the bus signal after the voltage reduction.

[0048] See also Figure 4 The figure shows a bus signal anti-interference processing circuit diagram of a bus buffer driving circuit.

[0049] In one embodiment, Figure 4 The signal receiving subcircuit is shown as a MOS transistor N1. Both its gate and source are electrically connected to the output of the upper circuit, and its drain is grounded. In practical applications, a MOS transistor N1 with significant capacitance is connected to the output of the upper circuit. When a high-voltage bus signal enters, it reduces the voltage to facilitate signal reception at the back end.

[0050] In one embodiment, the anti-interference subcircuit includes a first switch tube group, a second switch tube group and a positive feedback subcircuit, the first switch tube group is connected to the power supply, and the second switch tube group is grounded; when the bus signal after the voltage is stepped down is at a high level, the first switch tube group is turned on and the second switch tube group is turned off to provide a path from the power supply to the output end of the positive feedback subcircuit; when the bus signal after the voltage is stepped down is at a low level, the first switch tube group is turned off and the second switch tube group is turned on to provide a path from the output end of the positive feedback subcircuit to the ground.

[0051] Please continue to see Figure 4 , Figure 4 The diagram shows that the first switching transistor group includes a first MOS transistor D1 and a second MOS transistor D2, the second switching transistor group includes a third MOS transistor D3 and a fourth MOS transistor D4, and the positive feedback subcircuit includes a fifth MOS transistor D5, a sixth MOS transistor D6, and a seventh MOS transistor D7. In a specific implementation, the first MOS transistor D1, the second MOS transistor D2, the fifth MOS transistor D5, and the sixth MOS transistor D6 are all NMOS transistors, and the third MOS transistor D3, the fourth MOS transistor D4, and the seventh MOS transistor D7 are all PMOS transistors.

[0052] In one example, the gates of the first MOS transistor D1, the second MOS transistor D2, the third MOS transistor D3, and the fourth MOS transistor D4 are all electrically connected to the output terminal of the signal receiving sub-circuit. In actual applications, after the bus signal passes through the MOS transistor N1 with obvious capacitance characteristics, the gates of the first MOS transistor D1, the second MOS transistor D2, the third MOS transistor D3, and the fourth MOS transistor D4 are electrically connected to the output terminal of the signal receiving sub-circuit.

[0053] In one example, the drain of the first MOS transistor D1 is connected in series with the source of the second MOS transistor D2, and both the source of the first MOS transistor D1 and the source of the second MOS transistor D2 are connected to a power supply. The source of the third MOS transistor D3 is connected in series with the drain of the fourth MOS transistor D4, and both the source of the third MOS transistor D3 and the source of the fourth MOS transistor D4 are grounded. The drain of the second MOS transistor D2 is connected to the drain of the third MOS transistor D3, and the drain of the third MOS transistor D3 is connected to the gate of the fifth MOS transistor D5, the gate of the sixth MOS transistor D6, and the gate of the seventh MOS transistor D7, respectively. In actual applications, the drain and source of the NMOS transistors D1 and D2 are connected in series, and the sources of the NMOS transistors D1 and D2 are connected to a power supply. The drain and source of the PMOS transistors D3 and D4 are connected in series, and the sources of the PMOS transistors D3 and D4 are grounded. The drain of the PMOS transistor D3 enters the positive feedback sub-circuit.

[0054] In one example, the drain of the fifth MOS transistor D5 is connected in series with the source of the sixth MOS transistor D6. The source of the fifth MOS transistor D5 is connected to the drain of the first MOS transistor D1 and the source of the second MOS transistor D2. The sources of the fifth MOS transistor D5 and the sixth MOS transistor D6 are both connected to another power supply. The source of the seventh MOS transistor D7 is grounded, and the drain of the seventh MOS transistor D7 is connected to the source of the third MOS transistor D3 and the drain of the fourth MOS transistor D4. In actual applications, the drain of the PMOS transistor D3, which receives the bus signal, is connected to the gate of the NMOS transistor D5, which outputs the signal. At the same time, the sources and drains of the two NMOS transistors D5 and D6 are connected, forming a positive feedback structure.

[0055] The fundamental principle of bus signal processing in this circuit structure is hysteresis, which is implemented using D5, D6, and D7. When the output is high, D1, D2, D5, and D6 are on, while D3, D4, and D7 are off, providing a path from VCC to the output of the positive feedback subcircuit. When the output is low, D3, D4, and D7 are on, while D1, D2, D5, and D7 are off, providing a path from the output of the positive feedback subcircuit to ground.

[0056] When the input is 0 and the output is high, D3 and D4 are off, D5 and D6 are on, and the OUT voltage is equal to the voltage at D5's source terminal, that is, VOUT = VCC - Vth3. When the input Vin increases from 0 to VCC, VPUT remains at VCC - Vth3 until Vin falls below D4's threshold voltage, Vth1. When Vin increases above Vth1, D4 turns on, and the OUT voltage begins to decrease due to D4's conduction. Since the voltage at D3's source terminal, OUT, is not 0V, D3 turns on after D4, which is the source of hysteresis. When Vin increases until Vin-VA=Vth2, Vth2 is the threshold voltage of D3, and D3 is turned on. Once D3 is turned on, the output begins to decrease, causing D6 to slowly turn off, causing the OUT point to drop further, and the OUT point voltage drops. At the same time, the input Vin increases, causing D3 to turn on faster, the output to drop faster, causing D6 to turn off faster, and finally D3 and D4 to be fully turned on. This is a positive feedback process, which realizes the anti-interference design of the bus signal.

[0057] (2) Hot-swappable and floatable processing circuits: Hot-swappable and floatable processing circuits are used to deal with the situation where the computer bus signal is in the debugging state and needs to be floated and hot-swapped, without affecting any performance of the computer. The core principle is to use an inverter to feed back the signal at the output end to its input end, thereby forming a bistable circuit (locked). This ensures that when the bus is in the invalid state, the input end of the buffer drive circuit still has a certain state level, thereby realizing the function of computer bus signal buffering and allowing the driver integrated circuit chip to be floated.

[0058] See also Figure 5 The bus signal anti-interference processing circuit diagram of a bus buffer driving circuit shown in the figure includes a hot plug and a floating processing circuit including a first-stage inverter and a second-stage inverter, the first-stage inverter and the second-stage inverter are complementary, and also includes a diode M1.

[0059] In one example, the first-stage inverter includes an NMOS transistor Q1 and a PMOS transistor Q2. The gate of the NMOS transistor Q1 is connected to the gate of the PMOS transistor Q2, the drain of the NMOS transistor Q1 is connected to a power supply, the source of the NMOS transistor Q1 is connected to the drain of the PMOS transistor Q2, and the source of the PMOS transistor Q2 is grounded. In a specific implementation, the first-stage inverter comprises a pair of complementary NMOS transistors Q1 and PMOS transistors Q2. The gates of the NMOS transistors Q1 and PMOS transistors Q2 are connected to each other, the drain of the NMOS transistor Q1 is connected to a power supply, the source of the NMOS transistor Q1 is connected to the drain of the PMOS transistor Q2, and the source of the PMOS transistor Q2 is grounded.

[0060] In one example, the second-stage inverter includes an NMOS transistor Q3, a PMOS transistor Q4, a Schottky diode D2, and two conventional diodes D3 and D4. The gate of NMOS transistor Q3 is connected to the gate of PMOS transistor Q4, the drain of NMOS transistor Q3 is connected to another power supply, the source of NMOS transistor Q3, the Schottky diode D2, and the drain of PMOS transistor Q4 are connected in series, the source of PMOS transistor Q4 is grounded, and the source of NMOS transistor Q3 and the drain of PMOS transistor Q4 are connected to two conventional diodes D3 and D4, respectively. In a specific implementation, the output signal of the first pair of inverters is connected to the gate of the second pair of inverters, the gates of NMOS transistor Q3 and PMOS transistor Q4 are connected to each other, the drain of NMOS transistor Q3 is connected to the power supply, the source of NMOS transistor Q3 is connected in series with Schottky diode D2 and the drain of PMOS transistor Q4, the source of PMOS transistor Q4 is grounded, and the source and drain of NMOS transistor Q3 and PMOS transistor Q4 are connected to conventional diodes D3 and D4, respectively, for freewheeling.

[0061] The basic principle of the above circuit is that hot-swappable and floatable circuitry eliminates the need to connect floating inputs high or low by maintaining the last known input state until the next input signal appears. The hot-swappable and floatable circuitry consists of two complementary inverters. The second-stage inverter generates a relatively small positive feedback current back to the device input. This effectively increases the input current during the transient period, allowing the circuit to quickly return to the normal input level. The feedback then maintains this input level, essentially locking the last known input level to prevent it from changing in the opposite direction until the next level is reached. This hot-swappable and floatable circuitry eliminates output oscillation, reduces input power, reduces bus loading, improves output signal hold time, and enhances circuit reliability and stability, thus achieving hot-swappable and floatable capabilities.

[0062] Based on the aforementioned embodiments, an embodiment of the present invention provides a bus buffer driver integrated circuit chip, which includes the bus buffer driver circuit provided in the aforementioned embodiments. When receiving a bus signal sent by an upper circuit, the integrated circuit chip can control the on / off state of each switch tube in the bus signal anti-interference processing circuit based on the level change of the bus signal, so as to implement anti-interference processing of the bus signal by switching the on / off states of the switch tubes. When not receiving a bus signal sent by the upper circuit, the multi-stage inverter in the hot-swappable and floating processing circuit can be used to maintain the input end of the buffer driver circuit at a certain level, thereby enhancing the anti-interference, hot-swappable, and floating capabilities of the bus buffer driver circuit, thereby improving the defects of the bus buffer driver integrated circuit chip, such as a large PCB board area, high design difficulty, poor reliability, and high failure rate.

[0063] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working process of the bus buffer driver integrated circuit chip described above can refer to the corresponding process in the aforementioned embodiment and will not be repeated here.

[0064] In the description of the embodiments of the present invention, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0065] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0066] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A bus buffer driving circuit, characterized in that: include: Bus signal anti-interference processing circuit, hot-swappable and floating processing circuit and buffer drive circuit; The input end of the bus signal anti-interference processing circuit is electrically connected to the output end of the upper circuit, and the output end of the bus signal anti-interference processing circuit is electrically connected to the input end of the buffer driving circuit. The bus signal anti-interference processing circuit is configured to: upon receiving a bus signal sent by the upper circuit, control the on / off state of each switch tube in the bus signal anti-interference processing circuit based on a level change of the bus signal, so as to implement anti-interference processing of the bus signal by switching the on / off states of the switch tubes, and send the bus signal after anti-interference processing to the buffer driving circuit; The input end of the hot-swappable and floatable processing circuit is electrically connected to the output end of the upper circuit, and the output end of the hot-swappable and floatable processing circuit is electrically connected to the input end of the buffer drive circuit. The hot-swappable and floatable processing circuit is configured to maintain the input end of the buffer drive circuit at a certain level by utilizing a multi-stage inverter within the hot-swappable and floatable processing circuit when the circuit does not receive a bus signal sent by the upper circuit.

2. The bus buffer driving circuit according to claim 1, wherein: The bus signal anti-interference processing circuit includes a signal receiving subcircuit and an anti-interference subcircuit electrically connected in sequence: The signal receiving sub-circuit is used to: receive the bus signal sent by the upper circuit and reduce the voltage of the bus signal; The anti-interference sub-circuit is used to control the on / off state of each MOS tube in the anti-interference sub-circuit based on the level change of the bus signal after voltage reduction.

3. The bus buffer driving circuit according to claim 2, wherein: The signal receiving subcircuit is a MOS transistor, the gate and source of the MOS transistor in the signal receiving subcircuit are electrically connected to the output end of the upper circuit, and the drain of the MOS transistor in the signal receiving subcircuit is grounded.

4. The bus buffer driving circuit according to claim 2, wherein: The anti-interference subcircuit includes a first switch tube group, a second switch tube group and a positive feedback subcircuit, wherein the first switch tube group is connected to the power supply and the second switch tube group is grounded; When the bus signal after voltage reduction is at a high level, the first switch tube group is turned on and the second switch tube group is turned off, so as to provide a path from the power supply to the output end of the positive feedback sub-circuit; When the bus signal after voltage reduction is at a low level, the first switch tube group is turned off, and the second switch tube group is turned on to provide a path from the output end of the positive feedback sub-circuit to the ground.

5. The bus buffer driving circuit according to claim 4, wherein: The first switch tube group includes a first MOS tube and a second MOS tube, the second switch tube group includes a third MOS tube and a fourth MOS tube, and the positive feedback sub-circuit includes a fifth MOS tube, a sixth MOS tube and a seventh MOS tube; The gates of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all electrically connected to the output end of the signal receiving sub-circuit; The drain of the first MOS transistor is connected in series with the source of the second MOS transistor, and the source of the first MOS transistor and the source of the second MOS transistor are both connected to a power supply; The source of the third MOS transistor is connected in series with the drain of the fourth MOS transistor, and the source of the third MOS transistor and the source of the fourth MOS transistor are both grounded; The drain of the second MOS transistor is connected to the drain of the third MOS transistor, and the drain of the third MOS transistor is connected to the gate of the fifth MOS transistor, the gate of the sixth MOS transistor, and the gate of the seventh MOS transistor respectively; The drain of the fifth MOS transistor is connected in series with the source of the sixth MOS transistor, the source of the fifth MOS transistor is connected to the drain of the first MOS transistor and the source of the second MOS transistor, and the source of the fifth MOS transistor and the source of the sixth MOS transistor are both connected to another power supply; The source of the seventh MOS transistor is grounded, and the drain of the seventh MOS transistor is connected to the source of the third MOS transistor and the drain of the fourth MOS transistor.

6. The bus buffer driving circuit according to claim 5, wherein: The first MOS transistor, the second MOS transistor, the fifth MOS transistor and the sixth MOS transistor are all NMOS transistors, and the third MOS transistor, the fourth MOS transistor and the seventh MOS transistor are all PMOS transistors.

7. The bus buffer driving circuit according to claim 1, wherein: The hot-swappable and floating processing circuit includes a first-stage inverter and a second-stage inverter, wherein the first-stage inverter and the second-stage inverter are complementary.

8. The bus buffer driving circuit according to claim 7, wherein: The first-stage inverter includes an NMOS tube and a PMOS tube; The gate of the NMOS tube in the first-stage inverter is connected to the gate of the PMOS tube, the drain of the NMOS tube in the first-stage inverter is connected to a power supply, the source of the NMOS tube in the first-stage inverter is connected to the drain of the PMOS tube, and the source of the PMOS tube in the first-stage inverter is grounded.

9. The bus buffer driving circuit according to claim 8, wherein: The second-stage inverter includes an NMOS transistor, a PMOS transistor, a Schottky diode and two ordinary diodes; The gate of the NMOS tube in the second-stage inverter is connected to the gate of the PMOS tube, the drain of the NMOS tube in the second-stage inverter is connected to another power supply, the source of the NMOS tube in the second-stage inverter, the Schottky diode, and the drain of the PMOS tube are connected in series, the source of the PMOS tube in the second-stage inverter is grounded, and the source and drain of the NMOS tube in the second-stage inverter are respectively connected to the two ordinary diodes.

10. A bus buffer driver integrated circuit chip, characterized in that: The bus driver buffer integrated circuit chip includes the bus buffer driver circuit according to any one of claims 1 to 9.

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