Method and device for optimizing digital logic circuit layout and storage medium

Abstract

The invention provides a method and device for optimizing the layout of a digital logic circuit and a storage medium, and the method comprises the steps: determining a first layout of the digital logic circuit, the first layout comprises a plurality of macro cells and a plurality of standard cells, determining channels formed between the adjacent macro cells, and optimizing the layout of the digital logic circuit based on an optimization target of the digital logic circuit, according to the positions of the standard unit and the channel, the target step length parameter of the standard unit is determined, the optimization target comprises at least one of a line length target, a density target and a time sequence target, and the standard unit is adjusted based on the target step length parameter so as to optimize the layout of the digital logic circuit. By means of the method, automatic layout optimization of the digital logic circuit can be achieved, the influence of a channel on layout optimization is reduced, and the performance of a chip is further improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, device, and storage medium for optimizing the layout of digital logic circuits. Background Art

[0002] Electronic design automation (EDA) software is widely used in chip design. With various EDA software, engineers can easily perform chip design, including architecture design and register-transfer-level (RTL) code design, synthesis, design for test (DFT), physical development, and signoff.

[0003] When using EDA software to design chips, high-quality circuit layout and routing is a prerequisite for successful chip design. Complex and time-consuming layout planning is key to achieving this quality. As modern digital logic circuits grow larger and more complex, users are placing increasingly stringent requirements on circuit timing, power consumption, and performance-power-area (PPA). Only by properly placing every component in the chip can the desired timing, power consumption, and area be achieved. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a method, device and storage medium for optimizing the layout of digital logic circuits to solve or partially solve the above-mentioned problems.

[0005] Based on the above objectives, in a first aspect, the present application provides a method for optimizing the layout of a digital logic circuit, the method comprising: determining a first layout of the digital logic circuit; wherein the first layout includes a plurality of macro cells and a plurality of standard cells; determining channels formed between adjacent macro cells; Determining a target step size parameter of the standard cell based on an optimization target of the digital logic circuit and according to positions of the standard cell and the channel; wherein the optimization target includes at least one of a line length target, a density target, and a timing target; Based on the target step size parameter, the standard cell is adjusted to optimize the layout of the digital logic circuit.

[0006] In a second aspect of the present application, a computer device is provided, comprising: One or more processors, memory; and one or more programs; The one or more programs are stored in the memory and executed by the one or more processors, the programs including instructions for executing the method according to the first aspect.

[0007] In a third aspect of the present application, a non-volatile computer-readable storage medium containing a computer program is provided. When the computer program is executed by one or more processors, the processors are caused to execute the method according to the first aspect.

[0008] As can be seen from the above, the present application provides a method, device, and storage medium for optimizing the layout of a digital logic circuit. By determining a first layout of the digital logic circuit, the first layout includes multiple macro cells and multiple standard cells, determining the channels formed between adjacent macro cells, and based on the optimization goal of the digital logic circuit, determining the target step size parameters of the standard cells according to the positions of the standard cells and the channels, the optimization goal includes at least one of a line length target, a density target, and a timing target. Based on the target step size parameters, the standard cells are adjusted to optimize the layout of the digital logic circuit. The method of the present application can achieve automatic layout optimization of digital logic circuits, reduce the impact of channels on layout optimization, and further improve chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1 A schematic diagram of an exemplary computer device according to an embodiment of the present application is shown.

[0011] Figure 2 A basic structural diagram of a simulation tool according to an embodiment of the present application is shown.

[0012] Figure 3 A flowchart of a design and manufacturing process of an exemplary chip according to an embodiment of the present application is shown.

[0013] Figure 4 A schematic diagram showing an exemplary application scenario according to an embodiment of the present application is shown.

[0014] Figure 5 A schematic diagram showing an exemplary first layout according to an embodiment of the present application is shown.

[0015] Figure 6AA schematic diagram of an exemplary first region according to an embodiment of the present application is shown.

[0016] Figure 6B A schematic diagram illustrating an exemplary method of determining a target area based on the area ratio of a channel according to an embodiment of the present application is shown.

[0017] Figure 6C A schematic diagram illustrating an exemplary method of determining a target area based on the number of channels according to an embodiment of the present application is shown.

[0018] Figure 7 A flowchart of an exemplary method for optimizing digital logic circuit layout according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0020] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] In the related art, in integrated circuit design, macro cells usually occupy a large area, and during the layout process, there is often a certain gap area between macro cells, which is called a trench. The existence of these trenches has a significant impact on the layout of standard cells. On the one hand, the macro cells around the trench occupy a large area, and on the other hand, standard cells cannot overlap with macro cells. Therefore, during the layout process, many standard cells will be placed in the trench, resulting in poor layout effect.

[0022] In the related art, the number of standard cells falling into the channel can be controlled by setting an upper limit on the allowable density of the channel. However, when there are many channels stacked and the standard cell density is high, this method often cannot effectively prevent a large number of standard cells from being placed in the channel. Especially for cells located in deeper channel areas (far away from the center of the chip), since they are surrounded and blocked by surrounding macro cells, subsequent layout optimization is difficult to migrate them to other locations, resulting in an aggravation of the problem of cell aggregation in the channel. In addition, the position of the cell can be adjusted by adopting a forced movement strategy, but this strategy also has limitations. Although the strategy of forcibly moving standard cells can reduce the number of cells in the channel, it cannot ensure that the new position can meet the optimization goals, and this method cannot optimally select which cells to move.

[0023] To at least address the aforementioned issues, the present application provides a method, device, and storage medium for optimizing the layout of a digital logic circuit. The method comprises determining a first layout of the digital logic circuit, the first layout including multiple macrocells and multiple standard cells, determining the channels formed between adjacent macrocells, and determining target step parameters for the standard cells based on the positions of the standard cells and the channels, based on the optimization objectives of the digital logic circuit. The optimization objectives include at least one of a line length target, a density target, and a timing target. Based on the target step parameters, the standard cells are adjusted to optimize the layout of the digital logic circuit. The method of the present application enables automatic layout optimization of digital logic circuits, reduces the impact of channels on layout optimization, and further improves chip performance.

[0024] Figure 1 A schematic diagram of an exemplary computer device 100 according to an embodiment of the present application is shown. The computer device 100 may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are communicatively connected to each other within the device via the bus 1050.

[0025] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0026] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage devices, dynamic storage devices, etc. The memory 1020 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0027] The input / output interface 1030 is used to connect to an input / output module to enable information input and output. The input / output module can be configured as a component within the device (not shown) or can be externally connected to the device to provide corresponding functions. Input devices may include a keyboard, mouse, touch screen, microphone, various sensors, etc. Output devices may include a display, speaker, vibrator, indicator light, etc.

[0028] The communication interface 1040 is used to connect to a communication module (not shown) to enable communication between the device and other devices. The communication module can communicate via wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, Wi-Fi, Bluetooth, etc.).

[0029] The bus 1050 comprises a pathway for transmitting information between various components of the device, such as the processor 1010 , the memory 1020 , the input / output interface 1030 , and the communication interface 1040 .

[0030] It should be noted that although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040, and the bus 1050, in a specific implementation, the device may also include other components necessary for normal operation. In addition, it will be understood by those skilled in the art that the above device may only include the components necessary to implement the embodiments of this specification, and does not necessarily include all the components shown in the figure.

[0031] Figure 2 A basic structural diagram of a simulation tool 200 according to an embodiment of the present application is shown.

[0032] like Figure 2 As shown, the part above the dotted line is the user part; the part below the dotted line is the simulation tool 200, which can be Figure 1The computer device 100 shown is implemented. The simulation tool 200 may include a Tcl command module 204 (or a graphical / window interface module), various calculation modules (e.g., a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210), etc.), and a database system 212. A user 202 may operate the simulation tool 200 by entering commands in the Tcl command module 204 (or the graphical / window interface module). In some embodiments, the simulation tool 200 may be any EDA (Electronic Design Automation) software.

[0033] The Tcl command module 204 mainly performs the function of message transmission or command transmission. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and transmit the instructions to the corresponding computing modules to perform specific tasks according to the specific content of the instructions.

[0034] Depending on the calculation task, each calculation module can be divided into, for example, a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc. The Place calculation module 206 can be used to calculate a reasonable placement position for all components, the Route calculation module 208 can be used to calculate a reasonable wire connection method between each component, and the Optimization calculation module 210 can be used to optimize the placement position and wire connection method between each component. The calculation process of these calculation modules can be, for example, Figure 1 is performed in the processor 1010.

[0035] The database system 212 can be used to completely and comprehensively record and store all information of the chip being simulated or designed (such as position, direction, size, structure, wire connection method, etc.), for example, stored in Figure 1 The database system 212 may include database systems from different perspectives, for example, Figure 2 As shown, database system (schematic perspective) 2122 and database system (memory perspective) 2124.

[0036] Figure 3 A flow chart of a design and manufacturing process 300 of an exemplary chip according to an embodiment of the present application is shown.

[0037] like Figure 3As shown, the design and manufacturing process 300 begins with specification development 302. During specification development 302, the functional and performance requirements for the integrated circuit (i.e., digital logic circuit) are determined. During the chip design phase, circuit design is performed using EDA software to obtain, for example, a layout file for chip manufacturing. Design 304 may include different design steps depending on the circuit type (e.g., digital or analog). During manufacturing 306, the integrated circuit is formed on a wafer through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. During packaging 308, the wafer is diced to obtain bare dies, which are then packaged through processes such as bonding, soldering, and molding to produce chips. The resulting chips are tested during testing 310 to ensure that the performance of the finished chips meets the requirements determined in specification development 302. Chips that pass the tests 312 can be delivered to customers. It should be understood that the above process is merely illustrative and does not limit the scope of this application. In some cases, the chip design and manufacturing process may vary. For example, tape-out may be performed before manufacturing 306. A small number of chips from the tapeout can be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates a tapeout failure and the chip design may need to be adjusted or redesigned.

[0038] In some embodiments, the design of digital logic circuits 304 may illustratively include architecture design 322, RTL design 324, functional simulation 326, synthesis 328, timing analysis 330, DFT 332, verification 334, place and route 336, DRC 338 (design rule checking), and layout generation 340. Architecture design 322, for example, includes designing the chip architecture. For example, EDA software may be used to determine the types and number of components or subcircuits included in the chip system, as well as the functions, connections, and interactions of each component or subcircuit. During the RTL design 324 stage, the determined chip architecture may be described in code at the RTL level using a hardware programming language such as Verilog or VHDL. Functional simulation 326, also known as RTL-level behavioral simulation or front-end simulation, aims to analyze the correctness of the logical relationships in the designed circuit. Synthesis 328 may convert the RTL into a gate-level netlist. Synthesis 328 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis may first convert the RTL code into general Boolean equations and compile them. The netlist may be optimized based on designer-imposed constraints such as delay and area, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.

[0039] Timing analysis 330 is typically static timing analysis, primarily involving the calculation and estimation of timing for digital circuits. Timing analysis of paths within digital circuits determines whether timing closure has been achieved, thereby ensuring that the timing of various circuits meets various timing requirements. This type of digital circuit verification is typically performed statically and does not require simulation of digital logic. During the DFT 332 stage, various hardware logic can be embedded in the design to improve chip testability (including controllability and observability). This logic can be used to generate test vectors for testing large-scale digital circuits. DFT can, for example, include scan chain-based testing methods or built-in self-test (BIST). During the verification check 334 stage, the circuit can be formally verified and / or subjected to equivalence checking. Formal verification can use mathematical methods to prove correctness or incorrectness based on one or more formal specifications or properties. Formal verification can include, for example, abstract interpretation, formal model checking (also known as property checking), and theorem proving. Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate-level netlist, and between gate-level netlists.

[0040] During the layout and routing 336 stage, the chip circuit can be placed and routed. The layout can reasonably arrange the gate-level netlist generated by logic synthesis 328 within a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet timing requirements, and to comply with process routing rules (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of this application. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.

[0041] At the DRC 338 stage, the layout can be checked for potential open circuits, short circuits, or adverse effects caused by violations of design rules. After passing DRC, a file representing the layout, such as a GDSII file, can be generated by the EDA software. It will be understood that the above steps are merely exemplary and do not limit the scope of this application. In the actual design process, the above steps can be added, deleted, or modified according to design needs. In addition, some of the above steps can be implemented by different EDA software or integrated into one or more EDA software. This application does not impose any restrictions on this.

[0042] The scheme for optimizing digital logic circuit layout of the present application can be applied to the physical synthesis stage of the synthesis 328 stage. The components of circuit layout planning include the layout of macro cells and standard cells. Macro cells primarily include memory cells and various custom cells and are the main functional modules of digital logic circuits. Standard cells are modules of low-level electronic logic functions, such as various gate devices, flip-flops, latches, and buffers.

[0043] After the macrocells are placed in the circuit layout, the performance, power consumption, and area required by the circuit are achieved according to the circuit's design constraints, such as layout rules and routing rules. It is understood that the solution of this application can also be applied to other scenarios of optimizing other circuits, and this application does not limit this.

[0044] It will be appreciated that, although each operation has been described in a specific order above, this should be understood as not being limited to requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details have been included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in a plurality of implementations individually or in any suitable sub-combination.

[0045] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

[0046] Figure 4 A schematic diagram of an exemplary application scenario 400 according to an embodiment of the present application is shown.

[0047] like Figure 4As shown, application scenario 400 may include a computer device 100. In some embodiments, computer device 100 may be a device with computing capabilities, such as a personal computer, workstation, or server. The process described in this application may be implemented by EDA tool software in an electronic device with computing capabilities, such as a personal computer, workstation, or server. Computer device 100 may be installed with EDA software. During the EDA design process of a chip, a user (not shown) may input configurations into the EDA software, and the EDA software automatically generates digital logic circuits. EDA software includes, but is not limited to, chip design assistance software, programmable chip assistance software, and system design assistance software. The scope of this application is not limited in this respect.

[0048] The computer device 100 can obtain a first layout 402 of a digital logic circuit. The first layout 402 of the circuit may include relative positions of devices (eg, macro cells and standard cells) in the circuit.

[0049] After obtaining the first layout 402, the computer device 100 can determine a target step size parameter for the standard cell based on the locations of the standard cell and the channel in the first layout 402 and a specific optimization goal. In some embodiments, the computer device 100 can determine the target step size parameter for the standard cell based on at least one of a timing goal, a line length goal, or a density goal.

[0050] After determining the target step size parameters of the standard cells, the computer device 100 can adjust the positions of the standard cells according to the target step size parameters to obtain the second circuit layout 404. In some embodiments, the computer device 100 can change the movement step size or movement direction of the standard cells based on the target step size parameters to obtain the second circuit layout 404.

[0051] Figure 5 A schematic diagram of an exemplary first layout 402 according to an embodiment of the present application is shown.

[0052] like Figure 5 As shown, in some embodiments, for circuits with a large number of macrocells, a certain amount of space, called a trench, is often left between the macrocells in the first layout 402. After the macrocell layout is completed, that is, when the macrocell layout positions are determined, the remaining space can be used to layout standard cells. In addition to the large blank areas, the trenches between the macrocells can also be used to layout standard cells.

[0053] As previously mentioned, when optimizing the layout, it is difficult to effectively prevent a large number of standard cells from being placed in trenches. Therefore, after obtaining the first layout 402, it is possible to first determine whether trenches are formed between macro cells and find these trenches for further processing.

[0054] In some embodiments, the interval between two adjacent macro units can be determined first, and in response to the width of the interval being less than a width threshold, the interval can be determined to be a channel. Alternatively, the width threshold can be calculated based on the size of the macro unit, for example, the width threshold can be determined based on the width of the macro unit. Here, the width of the macro unit can be the size in the same direction as the width of the interval. For example, Figure 5 The figure is for reference only. Assuming the spacing between two macrocells is formed between two macrocells arranged horizontally, the width of a macrocell refers to its horizontal dimension. Alternatively, the width threshold can be set as a certain percentage of the macrocell width. This determines the channel size, which has a greater impact on the optimization results and requires more targeted processing.

[0055] For example, if two adjacent macro units have the same size, a gap whose width is smaller than a predetermined proportion (e.g., 1 / 5, 1 / 10, etc.) of the width of any of the macro units can be regarded as a channel; if two adjacent macro units have different sizes, the average of the widths of the two adjacent macro units is calculated, and a gap whose width is smaller than a predetermined proportion of the average is regarded as a channel.

[0056] The above method may be used to determine channels in the first layout 402 , for example, the channel 500 .

[0057] After determining the channels in the first layout 402, in some embodiments, a target step size parameter for the standard cell can be determined based on the optimization goal of the digital logic circuit and the positions of the standard cell and the channel. The target step size parameter can be used to adjust the standard cell to achieve the optimization goal.

[0058] In some embodiments, the computer device 100 may determine an initial step size parameter of the standard cell based on an optimization target of the digital logic circuit, wherein the initial step size parameter represents an initial amplitude of the standard cell position adjustment at the beginning of layout optimization.

[0059] Specifically, the optimization goal is expressed as an objective function, and the goal of the optimization algorithm is to find a solution that makes the objective function optimal. For example, the objective function satisfies the following expression:

[0060] in: Represents a single wire length objective function, used to measure wiring length; Represents a single density objective function, which can reflect the density of standard units in the region. Represents a single timing objective function, associated with circuit timing performance, ensuring signal transmission within the specified time. Then, based on the first layout 402, the location information of all standard cells is substituted into the objective function, and the function value of the objective function is calculated. In response to the function value not meeting the optimization target, that is, the calculated function value does not meet the preset optimization target, such as the desired upper limit of timing delay, upper limit of density, lower limit of total line length, etc., an initial step size parameter is calculated based on the objective function. It should be understood that if the function value meets the optimization target, it means that the standard cell does not need to be optimized again. Introducing an objective function to evaluate whether the current layout meets the optimization target and calculating the function value for judgment provides a quantitative and objective evaluation method that can clearly reflect the gap between the layout and the optimization target, providing a strong basis for subsequent step size parameter adjustment. When the function value does not meet the optimization target, the initial step size parameter is calculated based on the objective function. This allows for determining a more optimal initial step size parameter based on the different states of the circuit layout and optimization requirements, laying the foundation for subsequent precise adjustment and improving the efficiency of the entire optimization process.

[0061] In some embodiments, the initial step size parameter is derived by deriving the objective function based on the conjugate gradient algorithm. The conjugate gradient algorithm is a highly efficient iterative optimization algorithm that derives the fastest descent direction of the objective function under the current layout state, rapidly approximating the optimal solution and obtaining the initial step size parameter. The conjugate gradient algorithm has a fast convergence rate and high computational efficiency, enabling rapid and accurate determination of the initial step size parameter, saving computational time and resources and improving the overall efficiency of layout optimization.

[0062] Next, a step size coefficient is determined based on the position of the standard cell and channel 500, as well as the initial step size parameters. The step size coefficient is a factor used to adjust the initial step size parameters, reflecting the impact of the specific positional characteristics of the standard cell within channel 500 on layout adjustments. When the step size coefficient is less than 1, the initial step size is reduced, while when it is greater than 1, the adjustment range is amplified. By determining the step size coefficient, the initial step size parameters can be fine-tuned based on the local position conditions, improving the accuracy of layout optimization.

[0063] Figure 6A A schematic diagram of an exemplary first region 600 according to an embodiment of the present application is shown.

[0064] like Figure 6AAs shown, in some embodiments, a sliding window is used to scan the first layout 402 to identify a target region within the first layout 402. A sliding window is a dynamic scanning technique that enables local analysis of the distribution of components and channels 500 by sliding a fixed-size window across the digital logic circuit layout. Specifically, the area covered by the sliding window at its current position is defined as a first region 600. For example, the sliding window size is set to 1 / 10 of the chip area, and the sliding step size is 1 / 4 of the sliding window size. Furthermore, the area ratio of the channels 500 in the first region 600 and / or the number of channels 500 in the first region 600 are determined. In response to determining that the area ratio is greater than a ratio threshold and / or the number of channels 500 is greater than a number threshold, the first region 600 is determined to be a target region. For example, if the area ratio is greater than 0.5 or the number of channels 500 is greater than 5, the first region 600 is considered a target region, meaning that the first region 600 is the region where the standard cell is affected by the channels 500.

[0065] Figure 6B A schematic diagram illustrating an exemplary method of determining a target area 602 based on an area ratio of a channel 500 according to an embodiment of the present application is shown.

[0066] like Figure 6B As shown, when determining the target region 602 based on the area ratio of the channel 500, in some embodiments, in each first region 600, the computer device 100 can calculate the area ratio of the channel 500 by measuring the actual area of the channel 500 and dividing it by the total area of the first region 600. The area ratio of the channel 500 refers to the proportion of the area occupied by the channel 500 in the area covered by the sliding window. If the area ratio of the channel 500 exceeds a preset ratio threshold (e.g., 0.5), the first region 600 is determined as the target region 602, indicating that the standard cells in the region will be affected by the channel 500 during the layout optimization process and require further optimization.

[0067] Figure 6C FIG. 6 is a schematic diagram showing an exemplary method of determining a target area 602 based on the number of channels 500 according to an embodiment of the present application.

[0068] like Figure 6C As shown, when determining the target area 602 by the number of channels 500, in some embodiments, the computer device 100 can identify the number of channels 500 in the first area 600. If the number of channels 500 exceeds a preset threshold (e.g., 5), the first area 600 is determined as the target area 602. Figure 6CIn the example, the number of the channels 500 in the first region 600 is 6, and the first region 600 is determined to be the target region 602. The standard cells in the target region 602 will also be affected by the channels 500 during the layout optimization process, and further optimization processing is required.

[0069] In some embodiments, within the determined target region 602, the number of target channels 604 in the target region 602 and the standard cells located in the target region 602, i.e., the standard cells affected by the channel 500, are counted, and information such as the position, movement step, and movement direction of the standard cells is recorded based on the initial step size parameter. Furthermore, the relative position of the target channel 604 with respect to the center of the first layout 402 is determined. For example, a coordinate system is established with the center of the first layout 402 as the origin. Based on the coordinates of the target channel 604 and the coordinates of the center of the first layout 402, parameters such as coordinate difference, distance, and angle are calculated to determine the relative positional relationship between them.

[0070] It should be noted that the center of the first layout 402 can be regarded as the geometric center of the chip. Taking the center of the first layout 402 as the origin, the trench 500 farther away from the origin is defined as a deep trench. For standard cells close to the deep trench and with dense surrounding macro cells, the degree of impact is higher, indicating that the wiring pressure in this area is very high and the step size needs to be reduced to avoid wiring congestion caused by moving the standard cells. On the contrary, the step size can be appropriately increased. Through differentiated step size adjustment, the movement speed of the standard cells in the deep trench area is slowed down, and priority is given to optimization to other low-density areas.

[0071] In some embodiments, a step coefficient of the standard cell located in the target region 602 is determined based on the moving step size and moving direction of the standard cell and the relative position and / or number of the target channels 604 .

[0072] For each standard cell located in the target area 602, its movement direction is used to determine whether it is moving away from or toward the center of the first layout 402. If the standard cell's movement direction is away from the center of the first layout 402, a step coefficient is determined based on the relative distance of the target channel 604 from the center and the number of target channels 604. The step coefficient is set to less than 1 and is negatively correlated with the relative distance and the number of target channels 604. For example, the farther the target channel 604 is from the center of the layout, or the greater the number of target channels 604, the smaller the step coefficient. This can reduce the outward movement of the standard cell and prevent excessive diffusion of the layout. If the standard cell's movement direction is toward the center of the first layout 402, the step coefficient is set to greater than or equal to 1. By clustering the standard cells toward the center, this helps reduce wiring pressure. When determining the step coefficient, multiple factors are taken into consideration, including the standard cell's movement step length, movement direction, relative position of the target channel 604, and number of target channels 604. The step size coefficient is determined to ensure that the standard cell's position is adjusted according to the optimization direction during the movement process, while also allowing for appropriate step size adjustments based on the layout environment (such as distance from the center and number of channels), thereby achieving more reasonable layout optimization. Furthermore, step size adjustments do not change the original objective function, ensuring simultaneous optimization of line length, density, and timing.

[0073] Furthermore, the target step length parameter is determined based on the initial step length parameter and the step length coefficient.

[0074] The initial step length parameters include the moving step length and the moving direction.

[0075] In some embodiments, the step size coefficient is multiplied by the moving step size to obtain the target step size. Indicates the target step size of a single element, calculated as:

[0076] in, is the step coefficient, within the channel 500 range, , in other areas, ; is the moving step size, which is also the global initial step size value.

[0077] In some embodiments, a target step size parameter is determined based on the target step size and the movement direction. The target step size parameter can be combined with the target step size (step size) and the movement direction to obtain a complete movement description. For example, the target step size parameter can be expressed as a vector, target step size parameter = (target step size_x, target step size_y), which represents the displacement vector of the standard unit on the two-dimensional plane, including the size and direction of the movement.

[0078] Specifically, after taking the gradient derivative of the above objective function, the moving direction of each element can be obtained: . Combined 、 and the step size coefficient ,After multiple iterations through the conjugate gradient algorithm, the target step size parameter can be obtained.

[0079] The calculation formula of the target step length parameter is: .

[0080] Finally, the calculated target step size is combined with the movement direction to form a complete target step size parameter. Based on the movement direction in the target step size parameter, the standard cell is moved according to the movement distance corresponding to the target step size to adjust the standard cell, thereby achieving layout optimization.

[0081] The new layout after adjusting the standard cells is used as the second layout 404 .

[0082] In some embodiments, the parameters of the second layout 404 are input into an objective function to calculate the function value of the objective function. The specific expression of the objective function is as described above. Its optimization targets include line length, density, timing, etc., and then the overall quality of the layout is reflected through a specific weight combination.

[0083] In response to the function value of the objective function reaching the target value, the layout optimization of the digital logic circuit is terminated and the current layout is output as the optimal solution. In response to the function value of the objective function not reaching the target value, the above steps of optimizing the layout of the digital logic circuit based on the optimization target of the digital logic circuit are repeatedly performed, determining the target step size parameters of the standard cells according to the positions of the standard cells and the channels 500, and adjusting the standard cells based on the target step size parameters to generate a new layout (i.e., enter the next iteration) to optimize the layout of the digital logic circuit until the optimization target is met or the number of iterations reaches a predetermined number.

[0084] It should be understood that the above-described iterative optimization method for digital logic circuit layout optimizes and adjusts the step size of standard cells affected by channel 500, thereby adjusting the number of components that fall within channel 500. Furthermore, this method can also optimize the step size of all cells in the circuit. By optimizing different step sizes for cells with different positional constraints, step size optimization can be used to meet component positional constraints.

[0085] Figure 7 FIG. 7 is a flow chart of an exemplary method 700 for optimizing digital logic circuit layout according to an embodiment of the present application. The method 700 may be performed as follows: Figure 1 The computer device 100 shown performs and may include the following steps.

[0086] In step 702, a first layout of the digital logic circuit is determined (eg, Figure 4 a first layout 402 in the embodiment); wherein the first layout includes a plurality of macro cells and a plurality of standard cells.

[0087] In step 704, determine the channels (eg, Figure 5 channel 500 in the embodiment of the present invention).

[0088] In some embodiments, the method further includes: determining a spacing between two adjacent macrocells; and determining that the spacing is a channel in response to a width of the spacing being less than a width threshold, wherein the width threshold is calculated based on the size of the macrocell. The width threshold is calculated based on the size of the macrocell, and the judgment criteria can be dynamically adjusted based on the size characteristics of different macrocells, adapting to the combination of macrocells of different types and sizes, enhancing the versatility and flexibility of the method, and improving the accuracy of channel identification.

[0089] In step 706 , based on the optimization target of the digital logic circuit and according to the positions of the standard cell and the channel, a target step size parameter of the standard cell is determined; wherein the optimization target includes at least one of a line length target, a density target, and a timing target.

[0090] In some embodiments, the method further includes: determining an initial step size parameter for the standard cell based on an optimization goal for the digital logic circuit; determining a step size coefficient based on the locations of the standard cell and the channel and the initial step size parameter; and determining the target step size parameter based on the initial step size parameter and the step size coefficient. Based on the specific locations of the standard cell and the channel, dynamic adjustments are made to the initial step size parameter to allow different standard cells to be assigned independent step size coefficients according to their locations, thereby avoiding problems such as unreasonable layout adjustments or slow optimization caused by excessively large or small step sizes, and better meeting optimization goals.

[0091] In some embodiments, determining the initial step size parameters of the standard cells based on the optimization objective of the digital logic circuit further includes: determining an objective function; calculating a function value of the objective function based on the first layout; and, in response to the function value not meeting the optimization objective, calculating the initial step size parameters based on the objective function. When the function value does not meet the optimization objective, calculating the initial step size parameters based on the objective function allows for determining the initial step size based on the different states of the circuit layout and optimization requirements, laying the foundation for subsequent optimization and improving the efficiency and specificity of the entire optimization process.

[0092] In some embodiments, calculating the initial step size parameter based on the objective function further includes: deriving the objective function using a conjugate gradient algorithm to obtain the initial step size parameter. The conjugate gradient algorithm has a fast convergence rate and high computational efficiency, and can quickly and accurately obtain the initial step size parameter, thereby saving computational time and resources and improving the overall efficiency of layout optimization.

[0093] In some embodiments, the initial step size parameters include a moving step size and a moving direction; determining a step size coefficient according to the positions of the standard cell and the channel and the initial step size parameters further includes: scanning the first layout using a sliding window to determine a target area in the first layout (for example, Figure 6B Target region 602 in the target region); determining a target channel in the target region (eg, Figure 6C The number of target channels 604 in the target area and the standard cells located in the target area; determining the relative position of the target channel to the center of the first layout; and determining the step coefficient of the standard cells located in the target area based on the moving step and the moving direction of the standard cells and the relative position and / or the number of target channels. By scanning the first layout with a sliding window to determine the target area, a detailed local analysis of the layout can be performed to accurately identify those areas that require focus and adjustment, namely the target areas, thereby avoiding blind adjustment of the entire layout and improving the targetedness and efficiency of the optimization. In addition, the step coefficient is determined by taking into account multiple factors such as the number of target channels in the target area, the relative position of the standard cells to the center of the layout, and the initial step parameters (moving step and moving direction), so that the step coefficient can comprehensively reflect the position and adjustment requirements of the standard cells, further improving the accuracy and rationality of the adjustment.

[0094] In some embodiments, scanning the first layout using a sliding window to determine a target area in the first layout further includes: determining a first area defined by the sliding window at a current position (for example, Figure 6A The method further comprises: determining a first region 600 in the first region; determining an area ratio of the channels in the first region and / or the number of channels in the first region; and determining that the area ratio is greater than a ratio threshold and / or the number of channels is greater than a number threshold, determining that the first region is the target region. Optimization resources (such as computation time and step size adjustment) are concentrated on high-channel density regions, reducing ineffective optimization of non-critical regions and significantly shortening overall convergence time. Furthermore, regions with high channel area ratios and dense channel areas often correspond to routing congestion risks. Prioritizing optimization of such regions can effectively reduce global routing lengths.

[0095] In some embodiments, determining the step coefficient of the standard cell located in the target area based on the moving step size and moving direction of the standard cell as well as the relative position and / or the number of target channels further includes: determining whether the moving direction is away from the center of the first layout; in response to the moving direction being away from the center of the first layout, setting the step coefficient to less than 1; wherein the step coefficient is negatively correlated with the distance of the relative position and / or the number of target channels; and in response to the moving direction being close to the center of the first layout, setting the step coefficient to be greater than or equal to 1. Dynamically adjusting the step coefficient based on factors such as relative position and number of channels meets the actual needs of layout optimization and helps adjust the standard cell to a position that is more conducive to achieving the optimization goal.

[0096] In some embodiments, determining the target step length parameter based on the initial step length parameter and the step length coefficient further includes: multiplying the step length coefficient by the moving step length to obtain a target step length; and determining the target step length parameter based on the target step length and the moving direction. The step length coefficient is determined so that the standard cell can adjust its position according to the optimization direction during the movement process, and can also make appropriate step length adjustments based on the layout environment in which it is located, thereby achieving more reasonable layout optimization. At the same time, the step length adjustment does not change the original objective function, ensuring that the line length, density, and timing results are optimized simultaneously.

[0097] In step 708 , the standard cells are adjusted based on the target step size parameter to optimize the layout of the digital logic circuit.

[0098] In some embodiments, the method further includes adjusting the standard cell by moving the standard cell in a direction corresponding to the target step size. In combination with the direction of movement (e.g., the direction of gradient descent), the standard cell can be adjusted toward a low-density area, avoiding movement toward deeper channels, thereby improving layout optimization.

[0099] In some embodiments, after adjusting the standard cell based on the target step size parameter, the method further includes: determining a second layout after adjusting the standard cell (eg, Figure 4a second layout 404 in the circuit); according to the second layout, calculating the function value of the objective function; in response to the function value of the objective function reaching the target value, ending the layout optimization of the digital logic circuit; in response to the function value of the objective function not reaching the target value, repeatedly executing the steps of optimizing the layout of the digital logic circuit based on the optimization target of the digital logic circuit, determining the target step size parameter of the standard cell according to the positions of the standard cell and the channel, and adjusting the standard cell based on the target step size parameter, until the optimization target is met or the number of iterations reaches a predetermined number. When the function value does not reach the target value, repeating the relevant optimization steps until the optimization target is met or the predetermined number of iterations is reached. This cyclic iterative mechanism ensures that the optimization process can continue until it is as close to the optimization target as possible, avoids the problem of insufficient optimization due to insufficient adjustment times or early termination, and improves the integrity and effectiveness of layout optimization.

[0100] The present application provides a method, device and storage medium for optimizing the layout of a digital logic circuit. The method comprises determining a first layout of the digital logic circuit, wherein the first layout includes a plurality of macro cells and a plurality of standard cells, determining the channel formed between adjacent macro cells, and determining the target step length parameter of the standard cell based on the optimization target of the digital logic circuit and the position of the standard cell and the channel. The optimization target includes at least one of a line length target, a density target and a timing target. Based on the target step length parameter, the standard cell is adjusted to optimize the layout of the digital logic circuit. The method of the present application can realize automatic layout optimization of the digital logic circuit, reduce the influence of the channel on the layout optimization, and further improve the performance of the chip. At the same time, corresponding layout features can be extracted for different optimization targets, thereby obtaining a more targeted density function value for optimizing the component layout.

[0101] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied in a distributed scenario and performed by multiple devices working together. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the method.

[0102] It should be noted that the above description is limited to some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in an order different from that described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0103] Based on the same technical concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute method 700 as described in any of the above embodiments.

[0104] The computer-readable media of this embodiment includes permanent and non-permanent, removable and non-removable media, and can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0105] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute method 700 as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0106] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. Within the scope of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0107] In addition, to simplify the description and discussion, and to avoid obscuring the understanding of the embodiments of the present application, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. Furthermore, devices may be shown in block diagram form to avoid obscuring the understanding of the embodiments of the present application, and this also takes into account the fact that the implementation details of these block diagram devices are highly dependent on the platform on which the embodiments of the present application will be implemented (i.e., these details should be fully understood by those skilled in the art). Where specific details (e.g., circuits) are set forth to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with variations therefrom. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0108] Although the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the discussed embodiments.

[0109] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A method for optimizing digital logic circuit layout, characterized in that: include: Determining a first layout of the digital logic circuit; wherein the first layout includes a plurality of macro cells and a plurality of standard cells; determining channels formed between adjacent macro cells; Determining a target step size parameter of the standard cell based on an optimization target of the digital logic circuit and according to positions of the standard cell and the channel; wherein the optimization target includes at least one of a line length target, a density target, and a timing target; Based on the target step size parameter, the standard cell is adjusted to optimize the layout of the digital logic circuit.

2. The method according to claim 1, characterized in that Determining a target step size parameter of the standard cell based on an optimization target of the digital logic circuit and according to positions of the standard cell and the channel includes: Determining an initial step size parameter of the standard cell based on an optimization goal of the digital logic circuit; Determining a step coefficient according to the positions of the standard cell and the channel and the initial step parameter; The target step length parameter is determined according to the initial step length parameter and the step length coefficient.

3. The method according to claim 2, characterized in that Determining an initial step size parameter of the standard cell based on an optimization goal of the digital logic circuit includes: Determine the objective function; Calculating a function value of the objective function according to the first layout; In response to the function value not satisfying the optimization objective, the initial step size parameter is calculated according to the objective function.

4. The method according to claim 3, characterized in that Calculating the initial step size parameter according to the objective function includes: The objective function is derived based on a conjugate gradient algorithm to obtain the initial step size parameter.

5. The method according to claim 2, characterized in that The initial step length parameters include moving step length and moving direction; Determining a step coefficient according to the positions of the standard cell and the channel and the initial step parameter includes: Scanning the first layout using a sliding window to determine a target area in the first layout; determining the number of target channels in the target area and the standard cells located in the target area; determining a relative position of the target channel to a center of the first layout; The step coefficient of the standard cell located in the target area is determined based on the moving step size and the moving direction of the standard cell as well as the relative position and / or the number of the target channels.

6. The method according to claim 5, characterized in that Scanning the first layout using a sliding window to determine a target area in the first layout includes: Determining a first area defined by the sliding window at a current position; determining an area ratio of the channels in the first region and / or the number of channels in the first region; In response to determining that the area ratio is greater than a ratio threshold and / or the number of channels is greater than a number threshold, the first region is determined to be the target region.

7. The method according to claim 5, characterized in that Determining the step coefficient of the standard cell located in the target area based on the moving step size and the moving direction of the standard cell as well as the relative position and / or the number of the target channels includes: determining whether the moving direction is away from the center of the first layout; In response to the movement direction being away from the center of the first layout, the step coefficient is set to be less than 1; wherein the step coefficient is negatively correlated with the distance of the relative position and / or the number of the target channels; In response to the moving direction being close to the center of the first layout, the step coefficient is set to be greater than or equal to 1.

8. The method according to claim 5, characterized in that Determining the target step length parameter according to the initial step length parameter and the step length coefficient includes: Multiplying the step length coefficient by the moving step length to obtain a target step length; The target step length parameter is determined according to the target step length and the moving direction.

9. The method according to claim 8, characterized in that Adjusting the standard cell based on the target step size parameter includes: The standard unit is moved according to the moving direction and by a moving distance corresponding to the target step length to adjust the standard unit.

10. The method according to claim 1, characterized in that Determining a channel formed between adjacent macro cells includes: determining the interval between two adjacent macro units; In response to a width of the space being smaller than a width threshold, determining the space to be a channel; The width threshold is calculated according to the size of the macro unit.

11. The method according to claim 1, wherein After adjusting the standard cell based on the target step size parameter, the method further includes: determining a second layout after adjusting the standard cells; According to the second arrangement, calculating a function value of the objective function; In response to the function value of the objective function reaching a target value, ending the layout optimization of the digital logic circuit; In response to the function value of the objective function not reaching the target value, repeatedly executing the steps of optimizing the layout of the digital logic circuit based on the optimization target of the digital logic circuit, determining the target step size parameter of the standard cell according to the positions of the standard cell and the channel, and adjusting the standard cell based on the target step size parameter until the optimization target is met or the number of iterations reaches a predetermined number.

12. A computer device, characterized in that: include: One or more processors, memory; as well as one or more programs; The one or more programs are stored in the memory and executed by the one or more processors, the programs including instructions for executing the method according to any one of claims 1 to 11.

13. A non-volatile computer-readable storage medium containing a computer program, characterized in that When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 11.

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